drivers/media/rc/ite-cir.h

   1 /*
   2  * Driver for ITE Tech Inc. IT8712F/IT8512F CIR
   3  *
   4  * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of the
   9  * License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14  * General Public License for more details.
  15  */
  16
  17 /* platform driver name to register */
  18 #define ITE_DRIVER_NAME "ite-cir"
  19
  20 /* logging macros */
  21 #define ite_pr(level, text, ...) \
  22         printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
  23 #define ite_dbg(text, ...) do { \
  24         if (debug) \
  25                 printk(KERN_DEBUG \
  26                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \
  27 } while (0)
  28
  29 #define ite_dbg_verbose(text, ...) do {\
  30         if (debug > 1) \
  31                 printk(KERN_DEBUG \
  32                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \
  33 } while (0)
  34
  35 /* FIFO sizes */
  36 #define ITE_TX_FIFO_LEN 32
  37 #define ITE_RX_FIFO_LEN 32
  38
  39 /* interrupt types */
  40 #define ITE_IRQ_TX_FIFO        1
  41 #define ITE_IRQ_RX_FIFO        2
  42 #define ITE_IRQ_RX_FIFO_OVERRUN    4
  43
  44 /* forward declaration */
  45 struct ite_dev;
  46
  47 /* struct for storing the parameters of different recognized devices */
  48 struct ite_dev_params {
  49         /* model of the device */
  50         const char *model;
  51
  52         /* size of the I/O region */
  53         int io_region_size;
  54
  55         /* IR pnp I/O resource number */
  56         int io_rsrc_no;
  57
  58         /* true if the hardware supports transmission */
  59         bool hw_tx_capable;
  60
  61         /* base sampling period, in ns */
  62         u32 sample_period;
  63
  64         /* rx low carrier frequency, in Hz, 0 means no demodulation */
  65         unsigned int rx_low_carrier_freq;
  66
  67         /* tx high carrier frequency, in Hz, 0 means no demodulation */
  68         unsigned int rx_high_carrier_freq;
  69
  70         /* tx carrier frequency, in Hz */
  71         unsigned int tx_carrier_freq;
  72
  73         /* duty cycle, 0-100 */
  74         int tx_duty_cycle;
  75
  76         /* hw-specific operation function pointers; most of these must be
  77          * called while holding the spin lock, except for the TX FIFO length
  78          * one */
  79         /* get pending interrupt causes */
  80         int (*get_irq_causes) (struct ite_dev *dev);
  81
  82         /* enable rx */
  83         void (*enable_rx) (struct ite_dev *dev);
  84
  85         /* make rx enter the idle state; keep listening for a pulse, but stop
  86          * streaming space bytes */
  87         void (*idle_rx) (struct ite_dev *dev);
  88
  89         /* disable rx completely */
  90         void (*disable_rx) (struct ite_dev *dev);
  91
  92         /* read bytes from RX FIFO; return read count */
  93         int (*get_rx_bytes) (struct ite_dev *dev, u8 *buf, int buf_size);
  94
  95         /* enable tx FIFO space available interrupt */
  96         void (*enable_tx_interrupt) (struct ite_dev *dev);
  97
  98         /* disable tx FIFO space available interrupt */
  99         void (*disable_tx_interrupt) (struct ite_dev *dev);
 100
 101         /* get number of full TX FIFO slots */
 102         int (*get_tx_used_slots) (struct ite_dev *dev);
 103
 104         /* put a byte to the TX FIFO */
 105         void (*put_tx_byte) (struct ite_dev *dev, u8 value);
 106
 107         /* disable hardware completely */
 108         void (*disable) (struct ite_dev *dev);
 109
 110         /* initialize the hardware */
 111         void (*init_hardware) (struct ite_dev *dev);
 112
 113         /* set the carrier parameters */
 114         void (*set_carrier_params) (struct ite_dev *dev, bool high_freq,
 115                                     bool use_demodulator, u8 carrier_freq_bits,
 116                                     u8 allowance_bits, u8 pulse_width_bits);
 117 };
 118
 119 /* ITE CIR device structure */
 120 struct ite_dev {
 121         struct pnp_dev *pdev;
 122         struct rc_dev *rdev;
 123         struct ir_raw_event rawir;
 124
 125         /* sync data */
 126         spinlock_t lock;
 127         bool in_use, transmitting;
 128
 129         /* transmit support */
 130         int tx_fifo_allowance;
 131         wait_queue_head_t tx_queue, tx_ended;
 132
 133         /* hardware I/O settings */
 134         unsigned long cir_addr;
 135         int cir_irq;
 136
 137         /* overridable copy of model parameters */
 138         struct ite_dev_params params;
 139 };
 140
 141 /* common values for all kinds of hardware */
 142
 143 /* baud rate divisor default */
 144 #define ITE_BAUDRATE_DIVISOR            1
 145
 146 /* low-speed carrier frequency limits (Hz) */
 147 #define ITE_LCF_MIN_CARRIER_FREQ        27000
 148 #define ITE_LCF_MAX_CARRIER_FREQ        58000
 149
 150 /* high-speed carrier frequency limits (Hz) */
 151 #define ITE_HCF_MIN_CARRIER_FREQ        400000
 152 #define ITE_HCF_MAX_CARRIER_FREQ        500000
 153
 154 /* default carrier freq for when demodulator is off (Hz) */
 155 #define ITE_DEFAULT_CARRIER_FREQ        38000
 156
 157 /* convert bits to us */
 158 #define ITE_BITS_TO_NS(bits, sample_period) \
 159 ((u32) ((bits) * ITE_BAUDRATE_DIVISOR * sample_period))
 160
 161 /*
 162  * n in RDCR produces a tolerance of +/- n * 6.25% around the center
 163  * carrier frequency...
 164  *
 165  * From two limit frequencies, L (low) and H (high), we can get both the
 166  * center frequency F = (L + H) / 2 and the variation from the center
 167  * frequency A = (H - L) / (H + L). We can use this in order to honor the
 168  * s_rx_carrier_range() call in ir-core. We'll suppose that any request
 169  * setting L=0 means we must shut down the demodulator.
 170  */
 171 #define ITE_RXDCR_PER_10000_STEP 625
 172
 173 /* high speed carrier freq values */
 174 #define ITE_CFQ_400             0x03
 175 #define ITE_CFQ_450             0x08
 176 #define ITE_CFQ_480             0x0b
 177 #define ITE_CFQ_500             0x0d
 178
 179 /* values for pulse widths */
 180 #define ITE_TXMPW_A             0x02
 181 #define ITE_TXMPW_B             0x03
 182 #define ITE_TXMPW_C             0x04
 183 #define ITE_TXMPW_D             0x05
 184 #define ITE_TXMPW_E             0x06
 185
 186 /* values for demodulator carrier range allowance */
 187 #define ITE_RXDCR_DEFAULT       0x01    /* default carrier range */
 188 #define ITE_RXDCR_MAX           0x07    /* default carrier range */
 189
 190 /* DR TX bits */
 191 #define ITE_TX_PULSE            0x00
 192 #define ITE_TX_SPACE            0x80
 193 #define ITE_TX_MAX_RLE          0x80
 194 #define ITE_TX_RLE_MASK         0x7f
 195
 196 /*
 197  * IT8712F
 198  *
 199  * hardware data obtained from:
 200  *
 201  * IT8712F
 202  * Environment Control – Low Pin Count Input / Output
 203  * (EC - LPC I/O)
 204  * Preliminary Specification V0. 81
 205  */
 206
 207 /* register offsets */
 208 #define IT87_DR         0x00    /* data register */
 209 #define IT87_IER        0x01    /* interrupt enable register */
 210 #define IT87_RCR        0x02    /* receiver control register */
 211 #define IT87_TCR1       0x03    /* transmitter control register 1 */
 212 #define IT87_TCR2       0x04    /* transmitter control register 2 */
 213 #define IT87_TSR        0x05    /* transmitter status register */
 214 #define IT87_RSR        0x06    /* receiver status register */
 215 #define IT87_BDLR       0x05    /* baud rate divisor low byte register */
 216 #define IT87_BDHR       0x06    /* baud rate divisor high byte register */
 217 #define IT87_IIR        0x07    /* interrupt identification register */
 218
 219 #define IT87_IOREG_LENGTH 0x08  /* length of register file */
 220
 221 /* IER bits */
 222 #define IT87_TLDLIE     0x01    /* transmitter low data interrupt enable */
 223 #define IT87_RDAIE      0x02    /* receiver data available interrupt enable */
 224 #define IT87_RFOIE      0x04    /* receiver FIFO overrun interrupt enable */
 225 #define IT87_IEC        0x08    /* interrupt enable control */
 226 #define IT87_BR         0x10    /* baud rate register enable */
 227 #define IT87_RESET      0x20    /* reset */
 228
 229 /* RCR bits */
 230 #define IT87_RXDCR      0x07    /* receiver demodulation carrier range mask */
 231 #define IT87_RXACT      0x08    /* receiver active */
 232 #define IT87_RXEND      0x10    /* receiver demodulation enable */
 233 #define IT87_RXEN       0x20    /* receiver enable */
 234 #define IT87_HCFS       0x40    /* high-speed carrier frequency select */
 235 #define IT87_RDWOS      0x80    /* receiver data without sync */
 236
 237 /* TCR1 bits */
 238 #define IT87_TXMPM      0x03    /* transmitter modulation pulse mode mask */
 239 #define IT87_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
 240 #define IT87_TXENDF     0x04    /* transmitter deferral */
 241 #define IT87_TXRLE      0x08    /* transmitter run length enable */
 242 #define IT87_FIFOTL     0x30    /* FIFO level threshold mask */
 243 #define IT87_FIFOTL_DEFAULT 0x20        /* FIFO level threshold default
 244                                          * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
 245                                          * 0x30 -> 25 */
 246 #define IT87_ILE        0x40    /* internal loopback enable */
 247 #define IT87_FIFOCLR    0x80    /* FIFO clear bit */
 248
 249 /* TCR2 bits */
 250 #define IT87_TXMPW      0x07    /* transmitter modulation pulse width mask */
 251 #define IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
 252 #define IT87_CFQ        0xf8    /* carrier frequency mask */
 253 #define IT87_CFQ_SHIFT  3       /* carrier frequency bit shift */
 254
 255 /* TSR bits */
 256 #define IT87_TXFBC      0x3f    /* transmitter FIFO byte count mask */
 257
 258 /* RSR bits */
 259 #define IT87_RXFBC      0x3f    /* receiver FIFO byte count mask */
 260 #define IT87_RXFTO      0x80    /* receiver FIFO time-out */
 261
 262 /* IIR bits */
 263 #define IT87_IP         0x01    /* interrupt pending */
 264 #define IT87_II         0x06    /* interrupt identification mask */
 265 #define IT87_II_NOINT   0x00    /* no interrupt */
 266 #define IT87_II_TXLDL   0x02    /* transmitter low data level */
 267 #define IT87_II_RXDS    0x04    /* receiver data stored */
 268 #define IT87_II_RXFO    0x06    /* receiver FIFO overrun */
 269
 270 /*
 271  * IT8512E/F
 272  *
 273  * Hardware data obtained from:
 274  *
 275  * IT8512E/F
 276  * Embedded Controller
 277  * Preliminary Specification V0.4.1
 278  *
 279  * Note that the CIR registers are not directly available to the host, because
 280  * they only are accessible to the integrated microcontroller. Thus, in order
 281  * use it, some kind of bridging is required. As the bridging may depend on
 282  * the controller firmware in use, we are going to use the PNP ID in order to
 283  * determine the strategy and ports available. See after these generic
 284  * IT8512E/F register definitions for register definitions for those
 285  * strategies.
 286  */
 287
 288 /* register offsets */
 289 #define IT85_C0DR       0x00    /* data register */
 290 #define IT85_C0MSTCR    0x01    /* master control register */
 291 #define IT85_C0IER      0x02    /* interrupt enable register */
 292 #define IT85_C0IIR      0x03    /* interrupt identification register */
 293 #define IT85_C0CFR      0x04    /* carrier frequency register */
 294 #define IT85_C0RCR      0x05    /* receiver control register */
 295 #define IT85_C0TCR      0x06    /* transmitter control register */
 296 #define IT85_C0SCK      0x07    /* slow clock control register */
 297 #define IT85_C0BDLR     0x08    /* baud rate divisor low byte register */
 298 #define IT85_C0BDHR     0x09    /* baud rate divisor high byte register */
 299 #define IT85_C0TFSR     0x0a    /* transmitter FIFO status register */
 300 #define IT85_C0RFSR     0x0b    /* receiver FIFO status register */
 301 #define IT85_C0WCL      0x0d    /* wakeup code length register */
 302 #define IT85_C0WCR      0x0e    /* wakeup code read/write register */
 303 #define IT85_C0WPS      0x0f    /* wakeup power control/status register */
 304
 305 #define IT85_IOREG_LENGTH 0x10  /* length of register file */
 306
 307 /* C0MSTCR bits */
 308 #define IT85_RESET      0x01    /* reset */
 309 #define IT85_FIFOCLR    0x02    /* FIFO clear bit */
 310 #define IT85_FIFOTL     0x0c    /* FIFO level threshold mask */
 311 #define IT85_FIFOTL_DEFAULT 0x08        /* FIFO level threshold default
 312                                          * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
 313                                          * 0x0c -> 25 */
 314 #define IT85_ILE        0x10    /* internal loopback enable */
 315 #define IT85_ILSEL      0x20    /* internal loopback select */
 316
 317 /* C0IER bits */
 318 #define IT85_TLDLIE     0x01    /* TX low data level interrupt enable */
 319 #define IT85_RDAIE      0x02    /* RX data available interrupt enable */
 320 #define IT85_RFOIE      0x04    /* RX FIFO overrun interrupt enable */
 321 #define IT85_IEC        0x80    /* interrupt enable function control */
 322
 323 /* C0IIR bits */
 324 #define IT85_TLDLI      0x01    /* transmitter low data level interrupt */
 325 #define IT85_RDAI       0x02    /* receiver data available interrupt */
 326 #define IT85_RFOI       0x04    /* receiver FIFO overrun interrupt */
 327 #define IT85_NIP        0x80    /* no interrupt pending */
 328
 329 /* C0CFR bits */
 330 #define IT85_CFQ        0x1f    /* carrier frequency mask */
 331 #define IT85_HCFS       0x20    /* high speed carrier frequency select */
 332
 333 /* C0RCR bits */
 334 #define IT85_RXDCR      0x07    /* receiver demodulation carrier range mask */
 335 #define IT85_RXACT      0x08    /* receiver active */
 336 #define IT85_RXEND      0x10    /* receiver demodulation enable */
 337 #define IT85_RDWOS      0x20    /* receiver data without sync */
 338 #define IT85_RXEN       0x80    /* receiver enable */
 339
 340 /* C0TCR bits */
 341 #define IT85_TXMPW      0x07    /* transmitter modulation pulse width mask */
 342 #define IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
 343 #define IT85_TXMPM      0x18    /* transmitter modulation pulse mode mask */
 344 #define IT85_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
 345 #define IT85_TXENDF     0x20    /* transmitter deferral */
 346 #define IT85_TXRLE      0x40    /* transmitter run length enable */
 347
 348 /* C0SCK bits */
 349 #define IT85_SCKS       0x01    /* slow clock select */
 350 #define IT85_TXDCKG     0x02    /* TXD clock gating */
 351 #define IT85_DLL1P8E    0x04    /* DLL 1.8432M enable */
 352 #define IT85_DLLTE      0x08    /* DLL test enable */
 353 #define IT85_BRCM       0x70    /* baud rate count mode */
 354 #define IT85_DLLOCK     0x80    /* DLL lock */
 355
 356 /* C0TFSR bits */
 357 #define IT85_TXFBC      0x3f    /* transmitter FIFO count mask */
 358
 359 /* C0RFSR bits */
 360 #define IT85_RXFBC      0x3f    /* receiver FIFO count mask */
 361 #define IT85_RXFTO      0x80    /* receiver FIFO time-out */
 362
 363 /* C0WCL bits */
 364 #define IT85_WCL        0x3f    /* wakeup code length mask */
 365
 366 /* C0WPS bits */
 367 #define IT85_CIRPOSIE   0x01    /* power on/off status interrupt enable */
 368 #define IT85_CIRPOIS    0x02    /* power on/off interrupt status */
 369 #define IT85_CIRPOII    0x04    /* power on/off interrupt identification */
 370 #define IT85_RCRST      0x10    /* wakeup code reading counter reset bit */
 371 #define IT85_WCRST      0x20    /* wakeup code writing counter reset bit */
 372
 373 /*
 374  * ITE8708
 375  *
 376  * Hardware data obtained from hacked driver for IT8512 in this forum post:
 377  *
 378  *  http://ubuntuforums.org/showthread.php?t=1028640
 379  *
 380  * Although there's no official documentation for that driver, analysis would
 381  * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
 382  * selectable by a single bank-select bit that's mapped onto both banks. The
 383  * IT8512 registers are mapped in a different order, so that the first bank
 384  * maps the ones that are used more often, and two registers that share a
 385  * reserved high-order bit are placed at the same offset in both banks in
 386  * order to reuse the reserved bit as the bank select bit.
 387  */
 388
 389 /* register offsets */
 390
 391 /* mapped onto both banks */
 392 #define IT8708_BANKSEL  0x07    /* bank select register */
 393 #define IT8708_HRAE     0x80    /* high registers access enable */
 394
 395 /* mapped onto the low bank */
 396 #define IT8708_C0DR     0x00    /* data register */
 397 #define IT8708_C0MSTCR  0x01    /* master control register */
 398 #define IT8708_C0IER    0x02    /* interrupt enable register */
 399 #define IT8708_C0IIR    0x03    /* interrupt identification register */
 400 #define IT8708_C0RFSR   0x04    /* receiver FIFO status register */
 401 #define IT8708_C0RCR    0x05    /* receiver control register */
 402 #define IT8708_C0TFSR   0x06    /* transmitter FIFO status register */
 403 #define IT8708_C0TCR    0x07    /* transmitter control register */
 404
 405 /* mapped onto the high bank */
 406 #define IT8708_C0BDLR   0x01    /* baud rate divisor low byte register */
 407 #define IT8708_C0BDHR   0x02    /* baud rate divisor high byte register */
 408 #define IT8708_C0CFR    0x04    /* carrier frequency register */
 409
 410 /* registers whose bank mapping we don't know, since they weren't being used
 411  * in the hacked driver... most probably they belong to the high bank too,
 412  * since they fit in the holes the other registers leave */
 413 #define IT8708_C0SCK    0x03    /* slow clock control register */
 414 #define IT8708_C0WCL    0x05    /* wakeup code length register */
 415 #define IT8708_C0WCR    0x06    /* wakeup code read/write register */
 416 #define IT8708_C0WPS    0x07    /* wakeup power control/status register */
 417
 418 #define IT8708_IOREG_LENGTH 0x08        /* length of register file */
 419
 420 /* two more registers that are defined in the hacked driver, but can't be
 421  * found in the data sheets; no idea what they are or how they are accessed,
 422  * since the hacked driver doesn't seem to use them */
 423 #define IT8708_CSCRR    0x00
 424 #define IT8708_CGPINTR  0x01
 425
 426 /* CSCRR bits */
 427 #define IT8708_CSCRR_SCRB 0x3f
 428 #define IT8708_CSCRR_PM 0x80
 429
 430 /* CGPINTR bits */
 431 #define IT8708_CGPINT   0x01
 432
 433 /*
 434  * ITE8709
 435  *
 436  * Hardware interfacing data obtained from the original lirc_ite8709 driver.
 437  * Verbatim from its sources:
 438  *
 439  * The ITE8709 device seems to be the combination of IT8512 superIO chip and
 440  * a specific firmware running on the IT8512's embedded micro-controller.
 441  * In addition of the embedded micro-controller, the IT8512 chip contains a
 442  * CIR module and several other modules. A few modules are directly accessible
 443  * by the host CPU, but most of them are only accessible by the
 444  * micro-controller. The CIR module is only accessible by the
 445  * micro-controller.
 446  *
 447  * The battery-backed SRAM module is accessible by the host CPU and the
 448  * micro-controller. So one of the MC's firmware role is to act as a bridge
 449  * between the host CPU and the CIR module. The firmware implements a kind of
 450  * communication protocol using the SRAM module as a shared memory. The IT8512
 451  * specification is publicly available on ITE's web site, but the
 452  * communication protocol is not, so it was reverse-engineered.
 453  */
 454
 455 /* register offsets */
 456 #define IT8709_RAM_IDX  0x00    /* index into the SRAM module bytes */
 457 #define IT8709_RAM_VAL  0x01    /* read/write data to the indexed byte */
 458
 459 #define IT8709_IOREG_LENGTH 0x02        /* length of register file */
 460
 461 /* register offsets inside the SRAM module */
 462 #define IT8709_MODE     0x1a    /* request/ack byte */
 463 #define IT8709_REG_IDX  0x1b    /* index of the CIR register to access */
 464 #define IT8709_REG_VAL  0x1c    /* value read/to be written */
 465 #define IT8709_IIR      0x1e    /* interrupt identification register */
 466 #define IT8709_RFSR     0x1f    /* receiver FIFO status register */
 467 #define IT8709_FIFO     0x20    /* start of in RAM RX FIFO copy */
 468
 469 /* MODE values */
 470 #define IT8709_IDLE     0x00
 471 #define IT8709_WRITE    0x01
 472 #define IT8709_READ     0x02