drivers/media/rc/sunxi-cir.c

   1 /*
   2  * Driver for Allwinner sunXi IR controller
   3  *
   4  * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
   5  * Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>
   6  *
   7  * Based on sun5i-ir.c:
   8  * Copyright (C) 2007-2012 Daniel Wang
   9  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/clk.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/reset.h>
  27 #include <media/rc-core.h>
  28
  29 #define SUNXI_IR_DEV "sunxi-ir"
  30
  31 /* Registers */
  32 /* IR Control */
  33 #define SUNXI_IR_CTL_REG      0x00
  34 /* Global Enable */
  35 #define REG_CTL_GEN                     BIT(0)
  36 /* RX block enable */
  37 #define REG_CTL_RXEN                    BIT(1)
  38 /* CIR mode */
  39 #define REG_CTL_MD                      (BIT(4) | BIT(5))
  40
  41 /* Rx Config */
  42 #define SUNXI_IR_RXCTL_REG    0x10
  43 /* Pulse Polarity Invert flag */
  44 #define REG_RXCTL_RPPI                  BIT(2)
  45
  46 /* Rx Data */
  47 #define SUNXI_IR_RXFIFO_REG   0x20
  48
  49 /* Rx Interrupt Enable */
  50 #define SUNXI_IR_RXINT_REG    0x2C
  51 /* Rx FIFO Overflow */
  52 #define REG_RXINT_ROI_EN                BIT(0)
  53 /* Rx Packet End */
  54 #define REG_RXINT_RPEI_EN               BIT(1)
  55 /* Rx FIFO Data Available */
  56 #define REG_RXINT_RAI_EN                BIT(4)
  57
  58 /* Rx FIFO available byte level */
  59 #define REG_RXINT_RAL(val)    ((val) << 8)
  60
  61 /* Rx Interrupt Status */
  62 #define SUNXI_IR_RXSTA_REG    0x30
  63 /* RX FIFO Get Available Counter */
  64 #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
  65 /* Clear all interrupt status value */
  66 #define REG_RXSTA_CLEARALL    0xff
  67
  68 /* IR Sample Config */
  69 #define SUNXI_IR_CIR_REG      0x34
  70 /* CIR_REG register noise threshold */
  71 #define REG_CIR_NTHR(val)    (((val) << 2) & (GENMASK(7, 2)))
  72 /* CIR_REG register idle threshold */
  73 #define REG_CIR_ITHR(val)    (((val) << 8) & (GENMASK(15, 8)))
  74
  75 /* Required frequency for IR0 or IR1 clock in CIR mode (default) */
  76 #define SUNXI_IR_BASE_CLK     8000000
  77 /* Noise threshold in samples  */
  78 #define SUNXI_IR_RXNOISE      1
  79 /* Idle Threshold in samples */
  80 #define SUNXI_IR_RXIDLE       20
  81 /* Time after which device stops sending data in ms */
  82 #define SUNXI_IR_TIMEOUT      120
  83
  84 struct sunxi_ir {
  85         spinlock_t      ir_lock;
  86         struct rc_dev   *rc;
  87         void __iomem    *base;
  88         int             irq;
  89         int             fifo_size;
  90         struct clk      *clk;
  91         struct clk      *apb_clk;
  92         struct reset_control *rst;
  93         const char      *map_name;
  94 };
  95
  96 static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
  97 {
  98         unsigned long status;
  99         unsigned char dt;
 100         unsigned int cnt, rc;
 101         struct sunxi_ir *ir = dev_id;
 102         DEFINE_IR_RAW_EVENT(rawir);
 103
 104         spin_lock(&ir->ir_lock);
 105
 106         status = readl(ir->base + SUNXI_IR_RXSTA_REG);
 107
 108         /* clean all pending statuses */
 109         writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
 110
 111         if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) {
 112                 /* How many messages in fifo */
 113                 rc  = REG_RXSTA_GET_AC(status);
 114                 /* Sanity check */
 115                 rc = rc > ir->fifo_size ? ir->fifo_size : rc;
 116                 /* If we have data */
 117                 for (cnt = 0; cnt < rc; cnt++) {
 118                         /* for each bit in fifo */
 119                         dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
 120                         rawir.pulse = (dt & 0x80) != 0;
 121                         rawir.duration = ((dt & 0x7f) + 1) *
 122                                          ir->rc->rx_resolution;
 123                         ir_raw_event_store_with_filter(ir->rc, &rawir);
 124                 }
 125         }
 126
 127         if (status & REG_RXINT_ROI_EN) {
 128                 ir_raw_event_reset(ir->rc);
 129         } else if (status & REG_RXINT_RPEI_EN) {
 130                 ir_raw_event_set_idle(ir->rc, true);
 131                 ir_raw_event_handle(ir->rc);
 132         }
 133
 134         spin_unlock(&ir->ir_lock);
 135
 136         return IRQ_HANDLED;
 137 }
 138
 139 static int sunxi_ir_probe(struct platform_device *pdev)
 140 {
 141         int ret = 0;
 142         unsigned long tmp = 0;
 143
 144         struct device *dev = &pdev->dev;
 145         struct device_node *dn = dev->of_node;
 146         struct resource *res;
 147         struct sunxi_ir *ir;
 148         u32 b_clk_freq = SUNXI_IR_BASE_CLK;
 149
 150         ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
 151         if (!ir)
 152                 return -ENOMEM;
 153
 154         spin_lock_init(&ir->ir_lock);
 155
 156         if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
 157                 ir->fifo_size = 64;
 158         else
 159                 ir->fifo_size = 16;
 160
 161         /* Clock */
 162         ir->apb_clk = devm_clk_get(dev, "apb");
 163         if (IS_ERR(ir->apb_clk)) {
 164                 dev_err(dev, "failed to get a apb clock.\n");
 165                 return PTR_ERR(ir->apb_clk);
 166         }
 167         ir->clk = devm_clk_get(dev, "ir");
 168         if (IS_ERR(ir->clk)) {
 169                 dev_err(dev, "failed to get a ir clock.\n");
 170                 return PTR_ERR(ir->clk);
 171         }
 172
 173         /* Base clock frequency (optional) */
 174         of_property_read_u32(dn, "clock-frequency", &b_clk_freq);
 175
 176         /* Reset (optional) */
 177         ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
 178         if (IS_ERR(ir->rst))
 179                 return PTR_ERR(ir->rst);
 180         ret = reset_control_deassert(ir->rst);
 181         if (ret)
 182                 return ret;
 183
 184         ret = clk_set_rate(ir->clk, b_clk_freq);
 185         if (ret) {
 186                 dev_err(dev, "set ir base clock failed!\n");
 187                 goto exit_reset_assert;
 188         }
 189         dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
 190
 191         if (clk_prepare_enable(ir->apb_clk)) {
 192                 dev_err(dev, "try to enable apb_ir_clk failed\n");
 193                 ret = -EINVAL;
 194                 goto exit_reset_assert;
 195         }
 196
 197         if (clk_prepare_enable(ir->clk)) {
 198                 dev_err(dev, "try to enable ir_clk failed\n");
 199                 ret = -EINVAL;
 200                 goto exit_clkdisable_apb_clk;
 201         }
 202
 203         /* IO */
 204         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 205         ir->base = devm_ioremap_resource(dev, res);
 206         if (IS_ERR(ir->base)) {
 207                 dev_err(dev, "failed to map registers\n");
 208                 ret = PTR_ERR(ir->base);
 209                 goto exit_clkdisable_clk;
 210         }
 211
 212         ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);
 213         if (!ir->rc) {
 214                 dev_err(dev, "failed to allocate device\n");
 215                 ret = -ENOMEM;
 216                 goto exit_clkdisable_clk;
 217         }
 218
 219         ir->rc->priv = ir;
 220         ir->rc->device_name = SUNXI_IR_DEV;
 221         ir->rc->input_phys = "sunxi-ir/input0";
 222         ir->rc->input_id.bustype = BUS_HOST;
 223         ir->rc->input_id.vendor = 0x0001;
 224         ir->rc->input_id.product = 0x0001;
 225         ir->rc->input_id.version = 0x0100;
 226         ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
 227         ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
 228         ir->rc->dev.parent = dev;
 229         ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
 230         /* Frequency after IR internal divider with sample period in ns */
 231         ir->rc->rx_resolution = (1000000000ul / (b_clk_freq / 64));
 232         ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
 233         ir->rc->driver_name = SUNXI_IR_DEV;
 234
 235         ret = rc_register_device(ir->rc);
 236         if (ret) {
 237                 dev_err(dev, "failed to register rc device\n");
 238                 goto exit_free_dev;
 239         }
 240
 241         platform_set_drvdata(pdev, ir);
 242
 243         /* IRQ */
 244         ir->irq = platform_get_irq(pdev, 0);
 245         if (ir->irq < 0) {
 246                 dev_err(dev, "no irq resource\n");
 247                 ret = ir->irq;
 248                 goto exit_free_dev;
 249         }
 250
 251         ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
 252         if (ret) {
 253                 dev_err(dev, "failed request irq\n");
 254                 goto exit_free_dev;
 255         }
 256
 257         /* Enable CIR Mode */
 258         writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG);
 259
 260         /* Set noise threshold and idle threshold */
 261         writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE),
 262                ir->base + SUNXI_IR_CIR_REG);
 263
 264         /* Invert Input Signal */
 265         writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
 266
 267         /* Clear All Rx Interrupt Status */
 268         writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
 269
 270         /*
 271          * Enable IRQ on overflow, packet end, FIFO available with trigger
 272          * level
 273          */
 274         writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
 275                REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
 276                ir->base + SUNXI_IR_RXINT_REG);
 277
 278         /* Enable IR Module */
 279         tmp = readl(ir->base + SUNXI_IR_CTL_REG);
 280         writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
 281
 282         dev_info(dev, "initialized sunXi IR driver\n");
 283         return 0;
 284
 285 exit_free_dev:
 286         rc_free_device(ir->rc);
 287 exit_clkdisable_clk:
 288         clk_disable_unprepare(ir->clk);
 289 exit_clkdisable_apb_clk:
 290         clk_disable_unprepare(ir->apb_clk);
 291 exit_reset_assert:
 292         reset_control_assert(ir->rst);
 293
 294         return ret;
 295 }
 296
 297 static int sunxi_ir_remove(struct platform_device *pdev)
 298 {
 299         unsigned long flags;
 300         struct sunxi_ir *ir = platform_get_drvdata(pdev);
 301
 302         clk_disable_unprepare(ir->clk);
 303         clk_disable_unprepare(ir->apb_clk);
 304         reset_control_assert(ir->rst);
 305
 306         spin_lock_irqsave(&ir->ir_lock, flags);
 307         /* disable IR IRQ */
 308         writel(0, ir->base + SUNXI_IR_RXINT_REG);
 309         /* clear All Rx Interrupt Status */
 310         writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
 311         /* disable IR */
 312         writel(0, ir->base + SUNXI_IR_CTL_REG);
 313         spin_unlock_irqrestore(&ir->ir_lock, flags);
 314
 315         rc_unregister_device(ir->rc);
 316         return 0;
 317 }
 318
 319 static const struct of_device_id sunxi_ir_match[] = {
 320         { .compatible = "allwinner,sun4i-a10-ir", },
 321         { .compatible = "allwinner,sun5i-a13-ir", },
 322         {},
 323 };
 324 MODULE_DEVICE_TABLE(of, sunxi_ir_match);
 325
 326 static struct platform_driver sunxi_ir_driver = {
 327         .probe          = sunxi_ir_probe,
 328         .remove         = sunxi_ir_remove,
 329         .driver = {
 330                 .name = SUNXI_IR_DEV,
 331                 .of_match_table = sunxi_ir_match,
 332         },
 333 };
 334
 335 module_platform_driver(sunxi_ir_driver);
 336
 337 MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");
 338 MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");
 339 MODULE_LICENSE("GPL");