1 // SPDX-License-Identifier: GPL-2.0
3 * Sharp QM1D1C0042 8PSK tuner driver
5 * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
10 * As the disclosed information on the chip is very limited,
11 * this driver lacks some features, including chip config like IF freq.
12 * It assumes that users of this driver (such as a PCI bridge of
13 * DTV receiver cards) know the relevant info and
14 * configure the chip via I2C if necessary.
16 * Currently, PT3 driver is the only one that uses this driver,
17 * and contains init/config code in its firmware.
18 * Thus some part of the code might be dependent on PT3 specific config.
21 #include <linux/kernel.h>
22 #include <linux/math64.h>
23 #include "qm1d1c0042.h"
25 #define QM1D1C0042_NUM_REGS 0x20
26 #define QM1D1C0042_NUM_REG_ROWS 2
29 reg_initval
[QM1D1C0042_NUM_REG_ROWS
][QM1D1C0042_NUM_REGS
] = { {
30 0x48, 0x1c, 0xa0, 0x10, 0xbc, 0xc5, 0x20, 0x33,
31 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
32 0x00, 0xff, 0xf3, 0x00, 0x2a, 0x64, 0xa6, 0x86,
33 0x8c, 0xcf, 0xb8, 0xf1, 0xa8, 0xf2, 0x89, 0x00
35 0x68, 0x1c, 0xc0, 0x10, 0xbc, 0xc1, 0x11, 0x33,
36 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
37 0x00, 0xff, 0xf3, 0x00, 0x3f, 0x25, 0x5c, 0xd6,
38 0x55, 0xcf, 0x95, 0xf6, 0x36, 0xf2, 0x09, 0x00
44 static const struct qm1d1c0042_config default_cfg
= {
50 .normal_srch_wait
= 15,
53 struct qm1d1c0042_state
{
54 struct qm1d1c0042_config cfg
;
55 struct i2c_client
*i2c
;
56 u8 regs
[QM1D1C0042_NUM_REGS
];
59 static struct qm1d1c0042_state
*cfg_to_state(struct qm1d1c0042_config
*c
)
61 return container_of(c
, struct qm1d1c0042_state
, cfg
);
64 static int reg_write(struct qm1d1c0042_state
*state
, u8 reg
, u8 val
)
66 u8 wbuf
[2] = { reg
, val
};
69 ret
= i2c_master_send(state
->i2c
, wbuf
, sizeof(wbuf
));
70 if (ret
>= 0 && ret
< sizeof(wbuf
))
72 return (ret
== sizeof(wbuf
)) ? 0 : ret
;
75 static int reg_read(struct qm1d1c0042_state
*state
, u8 reg
, u8
*val
)
77 struct i2c_msg msgs
[2] = {
79 .addr
= state
->i2c
->addr
,
85 .addr
= state
->i2c
->addr
,
93 ret
= i2c_transfer(state
->i2c
->adapter
, msgs
, ARRAY_SIZE(msgs
));
94 if (ret
>= 0 && ret
< ARRAY_SIZE(msgs
))
96 return (ret
== ARRAY_SIZE(msgs
)) ? 0 : ret
;
100 static int qm1d1c0042_set_srch_mode(struct qm1d1c0042_state
*state
, bool fast
)
103 state
->regs
[0x03] |= 0x01; /* set fast search mode */
105 state
->regs
[0x03] &= ~0x01 & 0xff;
107 return reg_write(state
, 0x03, state
->regs
[0x03]);
110 static int qm1d1c0042_wakeup(struct qm1d1c0042_state
*state
)
114 state
->regs
[0x01] |= 1 << 3; /* BB_Reg_enable */
115 state
->regs
[0x01] &= (~(1 << 0)) & 0xff; /* NORMAL (wake-up) */
116 state
->regs
[0x05] &= (~(1 << 3)) & 0xff; /* pfd_rst NORMAL */
117 ret
= reg_write(state
, 0x01, state
->regs
[0x01]);
119 ret
= reg_write(state
, 0x05, state
->regs
[0x05]);
122 dev_warn(&state
->i2c
->dev
, "(%s) failed. [adap%d-fe%d]\n",
123 __func__
, state
->cfg
.fe
->dvb
->num
, state
->cfg
.fe
->id
);
129 static int qm1d1c0042_set_config(struct dvb_frontend
*fe
, void *priv_cfg
)
131 struct qm1d1c0042_state
*state
;
132 struct qm1d1c0042_config
*cfg
;
134 state
= fe
->tuner_priv
;
138 state
->cfg
.fe
= cfg
->fe
;
140 if (cfg
->xtal_freq
!= QM1D1C0042_CFG_XTAL_DFLT
)
141 dev_warn(&state
->i2c
->dev
,
142 "(%s) changing xtal_freq not supported. ", __func__
);
143 state
->cfg
.xtal_freq
= default_cfg
.xtal_freq
;
145 state
->cfg
.lpf
= cfg
->lpf
;
146 state
->cfg
.fast_srch
= cfg
->fast_srch
;
148 if (cfg
->lpf_wait
!= QM1D1C0042_CFG_WAIT_DFLT
)
149 state
->cfg
.lpf_wait
= cfg
->lpf_wait
;
151 state
->cfg
.lpf_wait
= default_cfg
.lpf_wait
;
153 if (cfg
->fast_srch_wait
!= QM1D1C0042_CFG_WAIT_DFLT
)
154 state
->cfg
.fast_srch_wait
= cfg
->fast_srch_wait
;
156 state
->cfg
.fast_srch_wait
= default_cfg
.fast_srch_wait
;
158 if (cfg
->normal_srch_wait
!= QM1D1C0042_CFG_WAIT_DFLT
)
159 state
->cfg
.normal_srch_wait
= cfg
->normal_srch_wait
;
161 state
->cfg
.normal_srch_wait
= default_cfg
.normal_srch_wait
;
165 /* divisor, vco_band parameters */
166 /* {maxfreq, param1(band?), param2(div?) */
167 static const u32 conv_table
[9][3] = {
179 static int qm1d1c0042_set_params(struct dvb_frontend
*fe
)
181 struct qm1d1c0042_state
*state
;
188 state
= fe
->tuner_priv
;
189 freq
= fe
->dtv_property_cache
.frequency
;
191 state
->regs
[0x08] &= 0xf0;
192 state
->regs
[0x08] |= 0x09;
194 state
->regs
[0x13] &= 0x9f;
195 state
->regs
[0x13] |= 0x20;
198 val
= state
->regs
[0x02] & 0x0f;
199 for (i
= 0; i
< 8; i
++)
200 if (freq
< conv_table
[i
][0] && freq
>= conv_table
[i
+ 1][0]) {
201 val
|= conv_table
[i
][1] << 7;
202 val
|= conv_table
[i
][2] << 4;
205 ret
= reg_write(state
, 0x02, val
);
209 a
= (freq
+ state
->cfg
.xtal_freq
/ 2) / state
->cfg
.xtal_freq
;
211 state
->regs
[0x06] &= 0x40;
212 state
->regs
[0x06] |= (a
- 12) / 4;
213 ret
= reg_write(state
, 0x06, state
->regs
[0x06]);
217 state
->regs
[0x07] &= 0xf0;
218 state
->regs
[0x07] |= (a
- 4 * ((a
- 12) / 4 + 1) - 5) & 0x0f;
219 ret
= reg_write(state
, 0x07, state
->regs
[0x07]);
224 val
= state
->regs
[0x08];
225 if (state
->cfg
.lpf
) {
226 /* LPF_CLK, LPF_FC */
230 ret
= reg_write(state
, 0x08, val
);
235 * b = (freq / state->cfg.xtal_freq - a) << 20;
239 b
= (s32
)div64_s64(((s64
) freq
) << 20, state
->cfg
.xtal_freq
)
247 state
->regs
[0x09] &= 0xc0;
248 state
->regs
[0x09] |= (sd
>> 16) & 0x3f;
249 state
->regs
[0x0a] = (sd
>> 8) & 0xff;
250 state
->regs
[0x0b] = sd
& 0xff;
251 ret
= reg_write(state
, 0x09, state
->regs
[0x09]);
253 ret
= reg_write(state
, 0x0a, state
->regs
[0x0a]);
255 ret
= reg_write(state
, 0x0b, state
->regs
[0x0b]);
259 if (!state
->cfg
.lpf
) {
261 ret
= reg_write(state
, 0x13, state
->regs
[0x13]);
267 mask
= state
->cfg
.lpf
? 0x3f : 0x7f;
268 val
= state
->regs
[0x0c] & mask
;
269 ret
= reg_write(state
, 0x0c, val
);
272 usleep_range(2000, 3000);
273 val
= state
->regs
[0x0c] | ~mask
;
274 ret
= reg_write(state
, 0x0c, val
);
279 msleep(state
->cfg
.lpf_wait
);
280 else if (state
->regs
[0x03] & 0x01)
281 msleep(state
->cfg
.fast_srch_wait
);
283 msleep(state
->cfg
.normal_srch_wait
);
285 if (state
->cfg
.lpf
) {
287 ret
= reg_write(state
, 0x08, 0x09);
292 ret
= reg_write(state
, 0x13, state
->regs
[0x13]);
299 static int qm1d1c0042_sleep(struct dvb_frontend
*fe
)
301 struct qm1d1c0042_state
*state
;
304 state
= fe
->tuner_priv
;
305 state
->regs
[0x01] &= (~(1 << 3)) & 0xff; /* BB_Reg_disable */
306 state
->regs
[0x01] |= 1 << 0; /* STDBY */
307 state
->regs
[0x05] |= 1 << 3; /* pfd_rst STANDBY */
308 ret
= reg_write(state
, 0x05, state
->regs
[0x05]);
310 ret
= reg_write(state
, 0x01, state
->regs
[0x01]);
312 dev_warn(&state
->i2c
->dev
, "(%s) failed. [adap%d-fe%d]\n",
313 __func__
, fe
->dvb
->num
, fe
->id
);
317 static int qm1d1c0042_init(struct dvb_frontend
*fe
)
319 struct qm1d1c0042_state
*state
;
323 state
= fe
->tuner_priv
;
325 reg_write(state
, 0x01, 0x0c);
326 reg_write(state
, 0x01, 0x0c);
328 ret
= reg_write(state
, 0x01, 0x0c); /* soft reset on */
331 usleep_range(2000, 3000);
333 ret
= reg_write(state
, 0x01, 0x1c); /* soft reset off */
337 /* check ID and choose initial registers corresponding ID */
338 ret
= reg_read(state
, 0x00, &val
);
341 for (reg_index
= 0; reg_index
< QM1D1C0042_NUM_REG_ROWS
;
343 if (val
== reg_initval
[reg_index
][0x00])
346 if (reg_index
>= QM1D1C0042_NUM_REG_ROWS
)
348 memcpy(state
->regs
, reg_initval
[reg_index
], QM1D1C0042_NUM_REGS
);
349 usleep_range(2000, 3000);
351 state
->regs
[0x0c] |= 0x40;
352 ret
= reg_write(state
, 0x0c, state
->regs
[0x0c]);
355 msleep(state
->cfg
.lpf_wait
);
357 /* set all writable registers */
358 for (i
= 1; i
<= 0x0c ; i
++) {
359 ret
= reg_write(state
, i
, state
->regs
[i
]);
363 for (i
= 0x11; i
< QM1D1C0042_NUM_REGS
; i
++) {
364 ret
= reg_write(state
, i
, state
->regs
[i
]);
369 ret
= qm1d1c0042_wakeup(state
);
373 ret
= qm1d1c0042_set_srch_mode(state
, state
->cfg
.fast_srch
);
380 dev_warn(&state
->i2c
->dev
, "(%s) failed. [adap%d-fe%d]\n",
381 __func__
, fe
->dvb
->num
, fe
->id
);
385 /* I2C driver functions */
387 static const struct dvb_tuner_ops qm1d1c0042_ops
= {
389 .name
= "Sharp QM1D1C0042",
391 .frequency_min_hz
= 950 * MHz
,
392 .frequency_max_hz
= 2150 * MHz
,
395 .init
= qm1d1c0042_init
,
396 .sleep
= qm1d1c0042_sleep
,
397 .set_config
= qm1d1c0042_set_config
,
398 .set_params
= qm1d1c0042_set_params
,
402 static int qm1d1c0042_probe(struct i2c_client
*client
,
403 const struct i2c_device_id
*id
)
405 struct qm1d1c0042_state
*state
;
406 struct qm1d1c0042_config
*cfg
;
407 struct dvb_frontend
*fe
;
409 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
414 cfg
= client
->dev
.platform_data
;
416 fe
->tuner_priv
= state
;
417 qm1d1c0042_set_config(fe
, cfg
);
418 memcpy(&fe
->ops
.tuner_ops
, &qm1d1c0042_ops
, sizeof(qm1d1c0042_ops
));
420 i2c_set_clientdata(client
, &state
->cfg
);
421 dev_info(&client
->dev
, "Sharp QM1D1C0042 attached.\n");
425 static int qm1d1c0042_remove(struct i2c_client
*client
)
427 struct qm1d1c0042_state
*state
;
429 state
= cfg_to_state(i2c_get_clientdata(client
));
430 state
->cfg
.fe
->tuner_priv
= NULL
;
436 static const struct i2c_device_id qm1d1c0042_id
[] = {
440 MODULE_DEVICE_TABLE(i2c
, qm1d1c0042_id
);
442 static struct i2c_driver qm1d1c0042_driver
= {
444 .name
= "qm1d1c0042",
446 .probe
= qm1d1c0042_probe
,
447 .remove
= qm1d1c0042_remove
,
448 .id_table
= qm1d1c0042_id
,
451 module_i2c_driver(qm1d1c0042_driver
);
453 MODULE_DESCRIPTION("Sharp QM1D1C0042 tuner");
454 MODULE_AUTHOR("Akihiro TSUKADA");
455 MODULE_LICENSE("GPL");