Linux 4.19.133
[linux/fpc-iii.git] / drivers / mfd / intel-lpss.c
blob7577afd4284280ad001e245087d908b5d5f46989
1 /*
2 * Intel Sunrisepoint LPSS core support.
4 * Copyright (C) 2015, Intel Corporation
6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * Heikki Krogerus <heikki.krogerus@linux.intel.com>
9 * Jarkko Nikula <jarkko.nikula@linux.intel.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/clk.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk-provider.h>
19 #include <linux/debugfs.h>
20 #include <linux/idr.h>
21 #include <linux/ioport.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mfd/core.h>
25 #include <linux/pm_qos.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/property.h>
28 #include <linux/seq_file.h>
29 #include <linux/io-64-nonatomic-lo-hi.h>
31 #include "intel-lpss.h"
33 #define LPSS_DEV_OFFSET 0x000
34 #define LPSS_DEV_SIZE 0x200
35 #define LPSS_PRIV_OFFSET 0x200
36 #define LPSS_PRIV_SIZE 0x100
37 #define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
38 #define LPSS_IDMA64_OFFSET 0x800
39 #define LPSS_IDMA64_SIZE 0x800
41 /* Offsets from lpss->priv */
42 #define LPSS_PRIV_RESETS 0x04
43 #define LPSS_PRIV_RESETS_IDMA BIT(2)
44 #define LPSS_PRIV_RESETS_FUNC 0x3
46 #define LPSS_PRIV_ACTIVELTR 0x10
47 #define LPSS_PRIV_IDLELTR 0x14
49 #define LPSS_PRIV_LTR_REQ BIT(15)
50 #define LPSS_PRIV_LTR_SCALE_MASK 0xc00
51 #define LPSS_PRIV_LTR_SCALE_1US 0x800
52 #define LPSS_PRIV_LTR_SCALE_32US 0xc00
53 #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff
55 #define LPSS_PRIV_SSP_REG 0x20
56 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
58 #define LPSS_PRIV_REMAP_ADDR 0x40
60 #define LPSS_PRIV_CAPS 0xfc
61 #define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
62 #define LPSS_PRIV_CAPS_TYPE_SHIFT 4
63 #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
65 /* This matches the type field in CAPS register */
66 enum intel_lpss_dev_type {
67 LPSS_DEV_I2C = 0,
68 LPSS_DEV_UART,
69 LPSS_DEV_SPI,
72 struct intel_lpss {
73 const struct intel_lpss_platform_info *info;
74 enum intel_lpss_dev_type type;
75 struct clk *clk;
76 struct clk_lookup *clock;
77 struct mfd_cell *cell;
78 struct device *dev;
79 void __iomem *priv;
80 u32 priv_ctx[LPSS_PRIV_REG_COUNT];
81 int devid;
82 u32 caps;
83 u32 active_ltr;
84 u32 idle_ltr;
85 struct dentry *debugfs;
88 static const struct resource intel_lpss_dev_resources[] = {
89 DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
90 DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
91 DEFINE_RES_IRQ(0),
94 static const struct resource intel_lpss_idma64_resources[] = {
95 DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
96 DEFINE_RES_IRQ(0),
99 #define LPSS_IDMA64_DRIVER_NAME "idma64"
102 * Cells needs to be ordered so that the iDMA is created first. This is
103 * because we need to be sure the DMA is available when the host controller
104 * driver is probed.
106 static const struct mfd_cell intel_lpss_idma64_cell = {
107 .name = LPSS_IDMA64_DRIVER_NAME,
108 .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
109 .resources = intel_lpss_idma64_resources,
112 static const struct mfd_cell intel_lpss_i2c_cell = {
113 .name = "i2c_designware",
114 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
115 .resources = intel_lpss_dev_resources,
118 static const struct mfd_cell intel_lpss_uart_cell = {
119 .name = "dw-apb-uart",
120 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
121 .resources = intel_lpss_dev_resources,
124 static const struct mfd_cell intel_lpss_spi_cell = {
125 .name = "pxa2xx-spi",
126 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
127 .resources = intel_lpss_dev_resources,
130 static DEFINE_IDA(intel_lpss_devid_ida);
131 static struct dentry *intel_lpss_debugfs;
133 static int intel_lpss_request_dma_module(const char *name)
135 static bool intel_lpss_dma_requested;
137 if (intel_lpss_dma_requested)
138 return 0;
140 intel_lpss_dma_requested = true;
141 return request_module("%s", name);
144 static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
146 lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
147 lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
150 static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
152 struct dentry *dir;
154 dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
155 if (IS_ERR(dir))
156 return PTR_ERR(dir);
158 /* Cache the values into lpss structure */
159 intel_lpss_cache_ltr(lpss);
161 debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
162 debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
163 debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
165 lpss->debugfs = dir;
166 return 0;
169 static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
171 debugfs_remove_recursive(lpss->debugfs);
174 static void intel_lpss_ltr_set(struct device *dev, s32 val)
176 struct intel_lpss *lpss = dev_get_drvdata(dev);
177 u32 ltr;
180 * Program latency tolerance (LTR) accordingly what has been asked
181 * by the PM QoS layer or disable it in case we were passed
182 * negative value or PM_QOS_LATENCY_ANY.
184 ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
186 if (val == PM_QOS_LATENCY_ANY || val < 0) {
187 ltr &= ~LPSS_PRIV_LTR_REQ;
188 } else {
189 ltr |= LPSS_PRIV_LTR_REQ;
190 ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
191 ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
193 if (val > LPSS_PRIV_LTR_VALUE_MASK)
194 ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
195 else
196 ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
199 if (ltr == lpss->active_ltr)
200 return;
202 writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
203 writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
205 /* Cache the values into lpss structure */
206 intel_lpss_cache_ltr(lpss);
209 static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
211 lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
212 dev_pm_qos_expose_latency_tolerance(lpss->dev);
215 static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
217 dev_pm_qos_hide_latency_tolerance(lpss->dev);
218 lpss->dev->power.set_latency_tolerance = NULL;
221 static int intel_lpss_assign_devs(struct intel_lpss *lpss)
223 const struct mfd_cell *cell;
224 unsigned int type;
226 type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
227 type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
229 switch (type) {
230 case LPSS_DEV_I2C:
231 cell = &intel_lpss_i2c_cell;
232 break;
233 case LPSS_DEV_UART:
234 cell = &intel_lpss_uart_cell;
235 break;
236 case LPSS_DEV_SPI:
237 cell = &intel_lpss_spi_cell;
238 break;
239 default:
240 return -ENODEV;
243 lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
244 if (!lpss->cell)
245 return -ENOMEM;
247 lpss->type = type;
249 return 0;
252 static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
254 return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
257 static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
259 resource_size_t addr = lpss->info->mem->start;
261 lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
264 static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
266 u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
268 /* Bring out the device from reset */
269 writel(value, lpss->priv + LPSS_PRIV_RESETS);
272 static void intel_lpss_init_dev(const struct intel_lpss *lpss)
274 u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
276 /* Set the device in reset state */
277 writel(0, lpss->priv + LPSS_PRIV_RESETS);
279 intel_lpss_deassert_reset(lpss);
281 intel_lpss_set_remap_addr(lpss);
283 if (!intel_lpss_has_idma(lpss))
284 return;
286 /* Make sure that SPI multiblock DMA transfers are re-enabled */
287 if (lpss->type == LPSS_DEV_SPI)
288 writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
291 static void intel_lpss_unregister_clock_tree(struct clk *clk)
293 struct clk *parent;
295 while (clk) {
296 parent = clk_get_parent(clk);
297 clk_unregister(clk);
298 clk = parent;
302 static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
303 const char *devname,
304 struct clk **clk)
306 char name[32];
307 struct clk *tmp = *clk;
309 snprintf(name, sizeof(name), "%s-enable", devname);
310 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
311 lpss->priv, 0, 0, NULL);
312 if (IS_ERR(tmp))
313 return PTR_ERR(tmp);
315 snprintf(name, sizeof(name), "%s-div", devname);
316 tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
317 0, lpss->priv, 1, 15, 16, 15, 0,
318 NULL);
319 if (IS_ERR(tmp))
320 return PTR_ERR(tmp);
321 *clk = tmp;
323 snprintf(name, sizeof(name), "%s-update", devname);
324 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
325 CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
326 if (IS_ERR(tmp))
327 return PTR_ERR(tmp);
328 *clk = tmp;
330 return 0;
333 static int intel_lpss_register_clock(struct intel_lpss *lpss)
335 const struct mfd_cell *cell = lpss->cell;
336 struct clk *clk;
337 char devname[24];
338 int ret;
340 if (!lpss->info->clk_rate)
341 return 0;
343 /* Root clock */
344 clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
345 lpss->info->clk_rate);
346 if (IS_ERR(clk))
347 return PTR_ERR(clk);
349 snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
352 * Support for clock divider only if it has some preset value.
353 * Otherwise we assume that the divider is not used.
355 if (lpss->type != LPSS_DEV_I2C) {
356 ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
357 if (ret)
358 goto err_clk_register;
361 ret = -ENOMEM;
363 /* Clock for the host controller */
364 lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
365 if (!lpss->clock)
366 goto err_clk_register;
368 lpss->clk = clk;
370 return 0;
372 err_clk_register:
373 intel_lpss_unregister_clock_tree(clk);
375 return ret;
378 static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
380 if (IS_ERR_OR_NULL(lpss->clk))
381 return;
383 clkdev_drop(lpss->clock);
384 intel_lpss_unregister_clock_tree(lpss->clk);
387 int intel_lpss_probe(struct device *dev,
388 const struct intel_lpss_platform_info *info)
390 struct intel_lpss *lpss;
391 int ret;
393 if (!info || !info->mem || info->irq <= 0)
394 return -EINVAL;
396 lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
397 if (!lpss)
398 return -ENOMEM;
400 lpss->priv = devm_ioremap_uc(dev, info->mem->start + LPSS_PRIV_OFFSET,
401 LPSS_PRIV_SIZE);
402 if (!lpss->priv)
403 return -ENOMEM;
405 lpss->info = info;
406 lpss->dev = dev;
407 lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
409 dev_set_drvdata(dev, lpss);
411 ret = intel_lpss_assign_devs(lpss);
412 if (ret)
413 return ret;
415 lpss->cell->properties = info->properties;
417 intel_lpss_init_dev(lpss);
419 lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
420 if (lpss->devid < 0)
421 return lpss->devid;
423 ret = intel_lpss_register_clock(lpss);
424 if (ret)
425 goto err_clk_register;
427 intel_lpss_ltr_expose(lpss);
429 ret = intel_lpss_debugfs_add(lpss);
430 if (ret)
431 dev_warn(dev, "Failed to create debugfs entries\n");
433 if (intel_lpss_has_idma(lpss)) {
435 * Ensure the DMA driver is loaded before the host
436 * controller device appears, so that the host controller
437 * driver can request its DMA channels as early as
438 * possible.
440 * If the DMA module is not there that's OK as well.
442 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
444 ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
445 1, info->mem, info->irq, NULL);
446 if (ret)
447 dev_warn(dev, "Failed to add %s, fallback to PIO\n",
448 LPSS_IDMA64_DRIVER_NAME);
451 ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
452 1, info->mem, info->irq, NULL);
453 if (ret)
454 goto err_remove_ltr;
456 dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
458 return 0;
460 err_remove_ltr:
461 intel_lpss_debugfs_remove(lpss);
462 intel_lpss_ltr_hide(lpss);
463 intel_lpss_unregister_clock(lpss);
465 err_clk_register:
466 ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
468 return ret;
470 EXPORT_SYMBOL_GPL(intel_lpss_probe);
472 void intel_lpss_remove(struct device *dev)
474 struct intel_lpss *lpss = dev_get_drvdata(dev);
476 mfd_remove_devices(dev);
477 intel_lpss_debugfs_remove(lpss);
478 intel_lpss_ltr_hide(lpss);
479 intel_lpss_unregister_clock(lpss);
480 ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
482 EXPORT_SYMBOL_GPL(intel_lpss_remove);
484 static int resume_lpss_device(struct device *dev, void *data)
486 if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
487 pm_runtime_resume(dev);
489 return 0;
492 int intel_lpss_prepare(struct device *dev)
495 * Resume both child devices before entering system sleep. This
496 * ensures that they are in proper state before they get suspended.
498 device_for_each_child_reverse(dev, NULL, resume_lpss_device);
499 return 0;
501 EXPORT_SYMBOL_GPL(intel_lpss_prepare);
503 int intel_lpss_suspend(struct device *dev)
505 struct intel_lpss *lpss = dev_get_drvdata(dev);
506 unsigned int i;
508 /* Save device context */
509 for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
510 lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
513 * If the device type is not UART, then put the controller into
514 * reset. UART cannot be put into reset since S3/S0ix fail when
515 * no_console_suspend flag is enabled.
517 if (lpss->type != LPSS_DEV_UART)
518 writel(0, lpss->priv + LPSS_PRIV_RESETS);
520 return 0;
522 EXPORT_SYMBOL_GPL(intel_lpss_suspend);
524 int intel_lpss_resume(struct device *dev)
526 struct intel_lpss *lpss = dev_get_drvdata(dev);
527 unsigned int i;
529 intel_lpss_deassert_reset(lpss);
531 /* Restore device context */
532 for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
533 writel(lpss->priv_ctx[i], lpss->priv + i * 4);
535 return 0;
537 EXPORT_SYMBOL_GPL(intel_lpss_resume);
539 static int __init intel_lpss_init(void)
541 intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
542 return 0;
544 module_init(intel_lpss_init);
546 static void __exit intel_lpss_exit(void)
548 ida_destroy(&intel_lpss_devid_ida);
549 debugfs_remove(intel_lpss_debugfs);
551 module_exit(intel_lpss_exit);
553 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
554 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
555 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
556 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
557 MODULE_DESCRIPTION("Intel LPSS core driver");
558 MODULE_LICENSE("GPL v2");