?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / misc / genwqe / card_dev.c
blobd2098b4d29451e759d1e9a6a1ccd215a36c25c03
1 /**
2 * IBM Accelerator Family 'GenWQE'
3 *
4 * (C) Copyright IBM Corp. 2013
5 *
6 * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
7 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
8 * Author: Michael Jung <mijung@gmx.net>
9 * Author: Michael Ruettger <michael@ibmra.de>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License (version 2 only)
13 * as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 /*
22 * Character device representation of the GenWQE device. This allows
23 * user-space applications to communicate with the card.
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/string.h>
31 #include <linux/fs.h>
32 #include <linux/sched/signal.h>
33 #include <linux/wait.h>
34 #include <linux/delay.h>
35 #include <linux/atomic.h>
36
37 #include "card_base.h"
38 #include "card_ddcb.h"
39
40 static int genwqe_open_files(struct genwqe_dev *cd)
41 {
42 int rc;
43 unsigned long flags;
44
45 spin_lock_irqsave(&cd->file_lock, flags);
46 rc = list_empty(&cd->file_list);
47 spin_unlock_irqrestore(&cd->file_lock, flags);
48 return !rc;
49 }
50
51 static void genwqe_add_file(struct genwqe_dev *cd, struct genwqe_file *cfile)
52 {
53 unsigned long flags;
54
55 cfile->opener = get_pid(task_tgid(current));
56 spin_lock_irqsave(&cd->file_lock, flags);
57 list_add(&cfile->list, &cd->file_list);
58 spin_unlock_irqrestore(&cd->file_lock, flags);
59 }
60
61 static int genwqe_del_file(struct genwqe_dev *cd, struct genwqe_file *cfile)
62 {
63 unsigned long flags;
64
65 spin_lock_irqsave(&cd->file_lock, flags);
66 list_del(&cfile->list);
67 spin_unlock_irqrestore(&cd->file_lock, flags);
68 put_pid(cfile->opener);
69
70 return 0;
71 }
72
73 static void genwqe_add_pin(struct genwqe_file *cfile, struct dma_mapping *m)
74 {
75 unsigned long flags;
76
77 spin_lock_irqsave(&cfile->pin_lock, flags);
78 list_add(&m->pin_list, &cfile->pin_list);
79 spin_unlock_irqrestore(&cfile->pin_lock, flags);
80 }
81
82 static int genwqe_del_pin(struct genwqe_file *cfile, struct dma_mapping *m)
83 {
84 unsigned long flags;
85
86 spin_lock_irqsave(&cfile->pin_lock, flags);
87 list_del(&m->pin_list);
88 spin_unlock_irqrestore(&cfile->pin_lock, flags);
89
90 return 0;
91 }
92
93 /**
94 * genwqe_search_pin() - Search for the mapping for a userspace address
95 * @cfile: Descriptor of opened file
96 * @u_addr: User virtual address
97 * @size: Size of buffer
98 * @dma_addr: DMA address to be updated
99 *
100 * Return: Pointer to the corresponding mapping NULL if not found
101 */
102 static struct dma_mapping *genwqe_search_pin(struct genwqe_file *cfile,
103 unsigned long u_addr,
104 unsigned int size,
105 void **virt_addr)
106 {
107 unsigned long flags;
108 struct dma_mapping *m;
109
110 spin_lock_irqsave(&cfile->pin_lock, flags);
111
112 list_for_each_entry(m, &cfile->pin_list, pin_list) {
113 if ((((u64)m->u_vaddr) <= (u_addr)) &&
114 (((u64)m->u_vaddr + m->size) >= (u_addr + size))) {
115
116 if (virt_addr)
117 *virt_addr = m->k_vaddr +
118 (u_addr - (u64)m->u_vaddr);
119
120 spin_unlock_irqrestore(&cfile->pin_lock, flags);
121 return m;
122 }
123 }
124 spin_unlock_irqrestore(&cfile->pin_lock, flags);
125 return NULL;
126 }
127
128 static void __genwqe_add_mapping(struct genwqe_file *cfile,
129 struct dma_mapping *dma_map)
130 {
131 unsigned long flags;
132
133 spin_lock_irqsave(&cfile->map_lock, flags);
134 list_add(&dma_map->card_list, &cfile->map_list);
135 spin_unlock_irqrestore(&cfile->map_lock, flags);
136 }
137
138 static void __genwqe_del_mapping(struct genwqe_file *cfile,
139 struct dma_mapping *dma_map)
140 {
141 unsigned long flags;
142
143 spin_lock_irqsave(&cfile->map_lock, flags);
144 list_del(&dma_map->card_list);
145 spin_unlock_irqrestore(&cfile->map_lock, flags);
146 }
147
148
149 /**
150 * __genwqe_search_mapping() - Search for the mapping for a userspace address
151 * @cfile: descriptor of opened file
152 * @u_addr: user virtual address
153 * @size: size of buffer
154 * @dma_addr: DMA address to be updated
155 * Return: Pointer to the corresponding mapping NULL if not found
156 */
157 static struct dma_mapping *__genwqe_search_mapping(struct genwqe_file *cfile,
158 unsigned long u_addr,
159 unsigned int size,
160 dma_addr_t *dma_addr,
161 void **virt_addr)
162 {
163 unsigned long flags;
164 struct dma_mapping *m;
165 struct pci_dev *pci_dev = cfile->cd->pci_dev;
166
167 spin_lock_irqsave(&cfile->map_lock, flags);
168 list_for_each_entry(m, &cfile->map_list, card_list) {
169
170 if ((((u64)m->u_vaddr) <= (u_addr)) &&
171 (((u64)m->u_vaddr + m->size) >= (u_addr + size))) {
172
173 /* match found: current is as expected and
174 addr is in range */
175 if (dma_addr)
176 *dma_addr = m->dma_addr +
177 (u_addr - (u64)m->u_vaddr);
178
179 if (virt_addr)
180 *virt_addr = m->k_vaddr +
181 (u_addr - (u64)m->u_vaddr);
182
183 spin_unlock_irqrestore(&cfile->map_lock, flags);
184 return m;
185 }
186 }
187 spin_unlock_irqrestore(&cfile->map_lock, flags);
188
189 dev_err(&pci_dev->dev,
190 "[%s] Entry not found: u_addr=%lx, size=%x\n",
191 __func__, u_addr, size);
192
193 return NULL;
194 }
195
196 static void genwqe_remove_mappings(struct genwqe_file *cfile)
197 {
198 int i = 0;
199 struct list_head *node, *next;
200 struct dma_mapping *dma_map;
201 struct genwqe_dev *cd = cfile->cd;
202 struct pci_dev *pci_dev = cfile->cd->pci_dev;
203
204 list_for_each_safe(node, next, &cfile->map_list) {
205 dma_map = list_entry(node, struct dma_mapping, card_list);
206
207 list_del_init(&dma_map->card_list);
208
209 /*
210 * This is really a bug, because those things should
211 * have been already tidied up.
212 *
213 * GENWQE_MAPPING_RAW should have been removed via mmunmap().
214 * GENWQE_MAPPING_SGL_TEMP should be removed by tidy up code.
215 */
216 dev_err(&pci_dev->dev,
217 "[%s] %d. cleanup mapping: u_vaddr=%p u_kaddr=%016lx dma_addr=%lx\n",
218 __func__, i++, dma_map->u_vaddr,
219 (unsigned long)dma_map->k_vaddr,
220 (unsigned long)dma_map->dma_addr);
221
222 if (dma_map->type == GENWQE_MAPPING_RAW) {
223 /* we allocated this dynamically */
224 __genwqe_free_consistent(cd, dma_map->size,
225 dma_map->k_vaddr,
226 dma_map->dma_addr);
227 kfree(dma_map);
228 } else if (dma_map->type == GENWQE_MAPPING_SGL_TEMP) {
229 /* we use dma_map statically from the request */
230 genwqe_user_vunmap(cd, dma_map);
231 }
232 }
233 }
234
235 static void genwqe_remove_pinnings(struct genwqe_file *cfile)
236 {
237 struct list_head *node, *next;
238 struct dma_mapping *dma_map;
239 struct genwqe_dev *cd = cfile->cd;
240
241 list_for_each_safe(node, next, &cfile->pin_list) {
242 dma_map = list_entry(node, struct dma_mapping, pin_list);
243
244 /*
245 * This is not a bug, because a killed processed might
246 * not call the unpin ioctl, which is supposed to free
247 * the resources.
248 *
249 * Pinnings are dymically allocated and need to be
250 * deleted.
251 */
252 list_del_init(&dma_map->pin_list);
253 genwqe_user_vunmap(cd, dma_map);
254 kfree(dma_map);
255 }
256 }
257
258 /**
259 * genwqe_kill_fasync() - Send signal to all processes with open GenWQE files
260 *
261 * E.g. genwqe_send_signal(cd, SIGIO);
262 */
263 static int genwqe_kill_fasync(struct genwqe_dev *cd, int sig)
264 {
265 unsigned int files = 0;
266 unsigned long flags;
267 struct genwqe_file *cfile;
268
269 spin_lock_irqsave(&cd->file_lock, flags);
270 list_for_each_entry(cfile, &cd->file_list, list) {
271 if (cfile->async_queue)
272 kill_fasync(&cfile->async_queue, sig, POLL_HUP);
273 files++;
274 }
275 spin_unlock_irqrestore(&cd->file_lock, flags);
276 return files;
277 }
278
279 static int genwqe_terminate(struct genwqe_dev *cd)
280 {
281 unsigned int files = 0;
282 unsigned long flags;
283 struct genwqe_file *cfile;
284
285 spin_lock_irqsave(&cd->file_lock, flags);
286 list_for_each_entry(cfile, &cd->file_list, list) {
287 kill_pid(cfile->opener, SIGKILL, 1);
288 files++;
289 }
290 spin_unlock_irqrestore(&cd->file_lock, flags);
291 return files;
292 }
293
294 /**
295 * genwqe_open() - file open
296 * @inode: file system information
297 * @filp: file handle
298 *
299 * This function is executed whenever an application calls
300 * open("/dev/genwqe",..).
301 *
302 * Return: 0 if successful or <0 if errors
303 */
304 static int genwqe_open(struct inode *inode, struct file *filp)
305 {
306 struct genwqe_dev *cd;
307 struct genwqe_file *cfile;
308
309 cfile = kzalloc(sizeof(*cfile), GFP_KERNEL);
310 if (cfile == NULL)
311 return -ENOMEM;
312
313 cd = container_of(inode->i_cdev, struct genwqe_dev, cdev_genwqe);
314 cfile->cd = cd;
315 cfile->filp = filp;
316 cfile->client = NULL;
317
318 spin_lock_init(&cfile->map_lock); /* list of raw memory allocations */
319 INIT_LIST_HEAD(&cfile->map_list);
320
321 spin_lock_init(&cfile->pin_lock); /* list of user pinned memory */
322 INIT_LIST_HEAD(&cfile->pin_list);
323
324 filp->private_data = cfile;
325
326 genwqe_add_file(cd, cfile);
327 return 0;
328 }
329
330 /**
331 * genwqe_fasync() - Setup process to receive SIGIO.
332 * @fd: file descriptor
333 * @filp: file handle
334 * @mode: file mode
335 *
336 * Sending a signal is working as following:
337 *
338 * if (cdev->async_queue)
339 * kill_fasync(&cdev->async_queue, SIGIO, POLL_IN);
340 *
341 * Some devices also implement asynchronous notification to indicate
342 * when the device can be written; in this case, of course,
343 * kill_fasync must be called with a mode of POLL_OUT.
344 */
345 static int genwqe_fasync(int fd, struct file *filp, int mode)
346 {
347 struct genwqe_file *cdev = (struct genwqe_file *)filp->private_data;
348
349 return fasync_helper(fd, filp, mode, &cdev->async_queue);
350 }
351
352
353 /**
354 * genwqe_release() - file close
355 * @inode: file system information
356 * @filp: file handle
357 *
358 * This function is executed whenever an application calls 'close(fd_genwqe)'
359 *
360 * Return: always 0
361 */
362 static int genwqe_release(struct inode *inode, struct file *filp)
363 {
364 struct genwqe_file *cfile = (struct genwqe_file *)filp->private_data;
365 struct genwqe_dev *cd = cfile->cd;
366
367 /* there must be no entries in these lists! */
368 genwqe_remove_mappings(cfile);
369 genwqe_remove_pinnings(cfile);
370
371 /* remove this filp from the asynchronously notified filp's */
372 genwqe_fasync(-1, filp, 0);
373
374 /*
375 * For this to work we must not release cd when this cfile is
376 * not yet released, otherwise the list entry is invalid,
377 * because the list itself gets reinstantiated!
378 */
379 genwqe_del_file(cd, cfile);
380 kfree(cfile);
381 return 0;
382 }
383
384 static void genwqe_vma_open(struct vm_area_struct *vma)
385 {
386 /* nothing ... */
387 }
388
389 /**
390 * genwqe_vma_close() - Called each time when vma is unmapped
391 *
392 * Free memory which got allocated by GenWQE mmap().
393 */
394 static void genwqe_vma_close(struct vm_area_struct *vma)
395 {
396 unsigned long vsize = vma->vm_end - vma->vm_start;
397 struct inode *inode = file_inode(vma->vm_file);
398 struct dma_mapping *dma_map;
399 struct genwqe_dev *cd = container_of(inode->i_cdev, struct genwqe_dev,
400 cdev_genwqe);
401 struct pci_dev *pci_dev = cd->pci_dev;
402 dma_addr_t d_addr = 0;
403 struct genwqe_file *cfile = vma->vm_private_data;
404
405 dma_map = __genwqe_search_mapping(cfile, vma->vm_start, vsize,
406 &d_addr, NULL);
407 if (dma_map == NULL) {
408 dev_err(&pci_dev->dev,
409 " [%s] err: mapping not found: v=%lx, p=%lx s=%lx\n",
410 __func__, vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
411 vsize);
412 return;
413 }
414 __genwqe_del_mapping(cfile, dma_map);
415 __genwqe_free_consistent(cd, dma_map->size, dma_map->k_vaddr,
416 dma_map->dma_addr);
417 kfree(dma_map);
418 }
419
420 static const struct vm_operations_struct genwqe_vma_ops = {
421 .open = genwqe_vma_open,
422 .close = genwqe_vma_close,
423 };
424
425 /**
426 * genwqe_mmap() - Provide contignous buffers to userspace
427 *
428 * We use mmap() to allocate contignous buffers used for DMA
429 * transfers. After the buffer is allocated we remap it to user-space
430 * and remember a reference to our dma_mapping data structure, where
431 * we store the associated DMA address and allocated size.
432 *
433 * When we receive a DDCB execution request with the ATS bits set to
434 * plain buffer, we lookup our dma_mapping list to find the
435 * corresponding DMA address for the associated user-space address.
436 */
437 static int genwqe_mmap(struct file *filp, struct vm_area_struct *vma)
438 {
439 int rc;
440 unsigned long pfn, vsize = vma->vm_end - vma->vm_start;
441 struct genwqe_file *cfile = (struct genwqe_file *)filp->private_data;
442 struct genwqe_dev *cd = cfile->cd;
443 struct dma_mapping *dma_map;
444
445 if (vsize == 0)
446 return -EINVAL;
447
448 if (get_order(vsize) > MAX_ORDER)
449 return -ENOMEM;
450
451 dma_map = kzalloc(sizeof(struct dma_mapping), GFP_KERNEL);
452 if (dma_map == NULL)
453 return -ENOMEM;
454
455 genwqe_mapping_init(dma_map, GENWQE_MAPPING_RAW);
456 dma_map->u_vaddr = (void *)vma->vm_start;
457 dma_map->size = vsize;
458 dma_map->nr_pages = DIV_ROUND_UP(vsize, PAGE_SIZE);
459 dma_map->k_vaddr = __genwqe_alloc_consistent(cd, vsize,
460 &dma_map->dma_addr);
461 if (dma_map->k_vaddr == NULL) {
462 rc = -ENOMEM;
463 goto free_dma_map;
464 }
465
466 if (capable(CAP_SYS_ADMIN) && (vsize > sizeof(dma_addr_t)))
467 *(dma_addr_t *)dma_map->k_vaddr = dma_map->dma_addr;
468
469 pfn = virt_to_phys(dma_map->k_vaddr) >> PAGE_SHIFT;
470 rc = remap_pfn_range(vma,
471 vma->vm_start,
472 pfn,
473 vsize,
474 vma->vm_page_prot);
475 if (rc != 0) {
476 rc = -EFAULT;
477 goto free_dma_mem;
478 }
479
480 vma->vm_private_data = cfile;
481 vma->vm_ops = &genwqe_vma_ops;
482 __genwqe_add_mapping(cfile, dma_map);
483
484 return 0;
485
486 free_dma_mem:
487 __genwqe_free_consistent(cd, dma_map->size,
488 dma_map->k_vaddr,
489 dma_map->dma_addr);
490 free_dma_map:
491 kfree(dma_map);
492 return rc;
493 }
494
495 /**
496 * do_flash_update() - Excute flash update (write image or CVPD)
497 * @cd: genwqe device
498 * @load: details about image load
499 *
500 * Return: 0 if successful
501 */
502
503 #define FLASH_BLOCK 0x40000 /* we use 256k blocks */
504
505 static int do_flash_update(struct genwqe_file *cfile,
506 struct genwqe_bitstream *load)
507 {
508 int rc = 0;
509 int blocks_to_flash;
510 dma_addr_t dma_addr;
511 u64 flash = 0;
512 size_t tocopy = 0;
513 u8 __user *buf;
514 u8 *xbuf;
515 u32 crc;
516 u8 cmdopts;
517 struct genwqe_dev *cd = cfile->cd;
518 struct file *filp = cfile->filp;
519 struct pci_dev *pci_dev = cd->pci_dev;
520
521 if ((load->size & 0x3) != 0)
522 return -EINVAL;
523
524 if (((unsigned long)(load->data_addr) & ~PAGE_MASK) != 0)
525 return -EINVAL;
526
527 /* FIXME Bits have changed for new service layer! */
528 switch ((char)load->partition) {
529 case '0':
530 cmdopts = 0x14;
531 break; /* download/erase_first/part_0 */
532 case '1':
533 cmdopts = 0x1C;
534 break; /* download/erase_first/part_1 */
535 case 'v':
536 cmdopts = 0x0C;
537 break; /* download/erase_first/vpd */
538 default:
539 return -EINVAL;
540 }
541
542 buf = (u8 __user *)load->data_addr;
543 xbuf = __genwqe_alloc_consistent(cd, FLASH_BLOCK, &dma_addr);
544 if (xbuf == NULL)
545 return -ENOMEM;
546
547 blocks_to_flash = load->size / FLASH_BLOCK;
548 while (load->size) {
549 struct genwqe_ddcb_cmd *req;
550
551 /*
552 * We must be 4 byte aligned. Buffer must be 0 appened
553 * to have defined values when calculating CRC.
554 */
555 tocopy = min_t(size_t, load->size, FLASH_BLOCK);
556
557 rc = copy_from_user(xbuf, buf, tocopy);
558 if (rc) {
559 rc = -EFAULT;
560 goto free_buffer;
561 }
562 crc = genwqe_crc32(xbuf, tocopy, 0xffffffff);
563
564 dev_dbg(&pci_dev->dev,
565 "[%s] DMA: %lx CRC: %08x SZ: %ld %d\n",
566 __func__, (unsigned long)dma_addr, crc, tocopy,
567 blocks_to_flash);
568
569 /* prepare DDCB for SLU process */
570 req = ddcb_requ_alloc();
571 if (req == NULL) {
572 rc = -ENOMEM;
573 goto free_buffer;
574 }
575
576 req->cmd = SLCMD_MOVE_FLASH;
577 req->cmdopts = cmdopts;
578
579 /* prepare invariant values */
580 if (genwqe_get_slu_id(cd) <= 0x2) {
581 *(__be64 *)&req->__asiv[0] = cpu_to_be64(dma_addr);
582 *(__be64 *)&req->__asiv[8] = cpu_to_be64(tocopy);
583 *(__be64 *)&req->__asiv[16] = cpu_to_be64(flash);
584 *(__be32 *)&req->__asiv[24] = cpu_to_be32(0);
585 req->__asiv[24] = load->uid;
586 *(__be32 *)&req->__asiv[28] = cpu_to_be32(crc);
587
588 /* for simulation only */
589 *(__be64 *)&req->__asiv[88] = cpu_to_be64(load->slu_id);
590 *(__be64 *)&req->__asiv[96] = cpu_to_be64(load->app_id);
591 req->asiv_length = 32; /* bytes included in crc calc */
592 } else { /* setup DDCB for ATS architecture */
593 *(__be64 *)&req->asiv[0] = cpu_to_be64(dma_addr);
594 *(__be32 *)&req->asiv[8] = cpu_to_be32(tocopy);
595 *(__be32 *)&req->asiv[12] = cpu_to_be32(0); /* resvd */
596 *(__be64 *)&req->asiv[16] = cpu_to_be64(flash);
597 *(__be32 *)&req->asiv[24] = cpu_to_be32(load->uid<<24);
598 *(__be32 *)&req->asiv[28] = cpu_to_be32(crc);
599
600 /* for simulation only */
601 *(__be64 *)&req->asiv[80] = cpu_to_be64(load->slu_id);
602 *(__be64 *)&req->asiv[88] = cpu_to_be64(load->app_id);
603
604 /* Rd only */
605 req->ats = 0x4ULL << 44;
606 req->asiv_length = 40; /* bytes included in crc calc */
607 }
608 req->asv_length = 8;
609
610 /* For Genwqe5 we get back the calculated CRC */
611 *(u64 *)&req->asv[0] = 0ULL; /* 0x80 */
612
613 rc = __genwqe_execute_raw_ddcb(cd, req, filp->f_flags);
614
615 load->retc = req->retc;
616 load->attn = req->attn;
617 load->progress = req->progress;
618
619 if (rc < 0) {
620 ddcb_requ_free(req);
621 goto free_buffer;
622 }
623
624 if (req->retc != DDCB_RETC_COMPLETE) {
625 rc = -EIO;
626 ddcb_requ_free(req);
627 goto free_buffer;
628 }
629
630 load->size -= tocopy;
631 flash += tocopy;
632 buf += tocopy;
633 blocks_to_flash--;
634 ddcb_requ_free(req);
635 }
636
637 free_buffer:
638 __genwqe_free_consistent(cd, FLASH_BLOCK, xbuf, dma_addr);
639 return rc;
640 }
641
642 static int do_flash_read(struct genwqe_file *cfile,
643 struct genwqe_bitstream *load)
644 {
645 int rc, blocks_to_flash;
646 dma_addr_t dma_addr;
647 u64 flash = 0;
648 size_t tocopy = 0;
649 u8 __user *buf;
650 u8 *xbuf;
651 u8 cmdopts;
652 struct genwqe_dev *cd = cfile->cd;
653 struct file *filp = cfile->filp;
654 struct pci_dev *pci_dev = cd->pci_dev;
655 struct genwqe_ddcb_cmd *cmd;
656
657 if ((load->size & 0x3) != 0)
658 return -EINVAL;
659
660 if (((unsigned long)(load->data_addr) & ~PAGE_MASK) != 0)
661 return -EINVAL;
662
663 /* FIXME Bits have changed for new service layer! */
664 switch ((char)load->partition) {
665 case '0':
666 cmdopts = 0x12;
667 break; /* upload/part_0 */
668 case '1':
669 cmdopts = 0x1A;
670 break; /* upload/part_1 */
671 case 'v':
672 cmdopts = 0x0A;
673 break; /* upload/vpd */
674 default:
675 return -EINVAL;
676 }
677
678 buf = (u8 __user *)load->data_addr;
679 xbuf = __genwqe_alloc_consistent(cd, FLASH_BLOCK, &dma_addr);
680 if (xbuf == NULL)
681 return -ENOMEM;
682
683 blocks_to_flash = load->size / FLASH_BLOCK;
684 while (load->size) {
685 /*
686 * We must be 4 byte aligned. Buffer must be 0 appened
687 * to have defined values when calculating CRC.
688 */
689 tocopy = min_t(size_t, load->size, FLASH_BLOCK);
690
691 dev_dbg(&pci_dev->dev,
692 "[%s] DMA: %lx SZ: %ld %d\n",
693 __func__, (unsigned long)dma_addr, tocopy,
694 blocks_to_flash);
695
696 /* prepare DDCB for SLU process */
697 cmd = ddcb_requ_alloc();
698 if (cmd == NULL) {
699 rc = -ENOMEM;
700 goto free_buffer;
701 }
702 cmd->cmd = SLCMD_MOVE_FLASH;
703 cmd->cmdopts = cmdopts;
704
705 /* prepare invariant values */
706 if (genwqe_get_slu_id(cd) <= 0x2) {
707 *(__be64 *)&cmd->__asiv[0] = cpu_to_be64(dma_addr);
708 *(__be64 *)&cmd->__asiv[8] = cpu_to_be64(tocopy);
709 *(__be64 *)&cmd->__asiv[16] = cpu_to_be64(flash);
710 *(__be32 *)&cmd->__asiv[24] = cpu_to_be32(0);
711 cmd->__asiv[24] = load->uid;
712 *(__be32 *)&cmd->__asiv[28] = cpu_to_be32(0) /* CRC */;
713 cmd->asiv_length = 32; /* bytes included in crc calc */
714 } else { /* setup DDCB for ATS architecture */
715 *(__be64 *)&cmd->asiv[0] = cpu_to_be64(dma_addr);
716 *(__be32 *)&cmd->asiv[8] = cpu_to_be32(tocopy);
717 *(__be32 *)&cmd->asiv[12] = cpu_to_be32(0); /* resvd */
718 *(__be64 *)&cmd->asiv[16] = cpu_to_be64(flash);
719 *(__be32 *)&cmd->asiv[24] = cpu_to_be32(load->uid<<24);
720 *(__be32 *)&cmd->asiv[28] = cpu_to_be32(0); /* CRC */
721
722 /* rd/wr */
723 cmd->ats = 0x5ULL << 44;
724 cmd->asiv_length = 40; /* bytes included in crc calc */
725 }
726 cmd->asv_length = 8;
727
728 /* we only get back the calculated CRC */
729 *(u64 *)&cmd->asv[0] = 0ULL; /* 0x80 */
730
731 rc = __genwqe_execute_raw_ddcb(cd, cmd, filp->f_flags);
732
733 load->retc = cmd->retc;
734 load->attn = cmd->attn;
735 load->progress = cmd->progress;
736
737 if ((rc < 0) && (rc != -EBADMSG)) {
738 ddcb_requ_free(cmd);
739 goto free_buffer;
740 }
741
742 rc = copy_to_user(buf, xbuf, tocopy);
743 if (rc) {
744 rc = -EFAULT;
745 ddcb_requ_free(cmd);
746 goto free_buffer;
747 }
748
749 /* We know that we can get retc 0x104 with CRC err */
750 if (((cmd->retc == DDCB_RETC_FAULT) &&
751 (cmd->attn != 0x02)) || /* Normally ignore CRC error */
752 ((cmd->retc == DDCB_RETC_COMPLETE) &&
753 (cmd->attn != 0x00))) { /* Everything was fine */
754 rc = -EIO;
755 ddcb_requ_free(cmd);
756 goto free_buffer;
757 }
758
759 load->size -= tocopy;
760 flash += tocopy;
761 buf += tocopy;
762 blocks_to_flash--;
763 ddcb_requ_free(cmd);
764 }
765 rc = 0;
766
767 free_buffer:
768 __genwqe_free_consistent(cd, FLASH_BLOCK, xbuf, dma_addr);
769 return rc;
770 }
771
772 static int genwqe_pin_mem(struct genwqe_file *cfile, struct genwqe_mem *m)
773 {
774 int rc;
775 struct genwqe_dev *cd = cfile->cd;
776 struct pci_dev *pci_dev = cfile->cd->pci_dev;
777 struct dma_mapping *dma_map;
778 unsigned long map_addr;
779 unsigned long map_size;
780
781 if ((m->addr == 0x0) || (m->size == 0))
782 return -EINVAL;
783 if (m->size > ULONG_MAX - PAGE_SIZE - (m->addr & ~PAGE_MASK))
784 return -EINVAL;
785
786 map_addr = (m->addr & PAGE_MASK);
787 map_size = round_up(m->size + (m->addr & ~PAGE_MASK), PAGE_SIZE);
788
789 dma_map = kzalloc(sizeof(struct dma_mapping), GFP_KERNEL);
790 if (dma_map == NULL)
791 return -ENOMEM;
792
793 genwqe_mapping_init(dma_map, GENWQE_MAPPING_SGL_PINNED);
794 rc = genwqe_user_vmap(cd, dma_map, (void *)map_addr, map_size);
795 if (rc != 0) {
796 dev_err(&pci_dev->dev,
797 "[%s] genwqe_user_vmap rc=%d\n", __func__, rc);
798 kfree(dma_map);
799 return rc;
800 }
801
802 genwqe_add_pin(cfile, dma_map);
803 return 0;
804 }
805
806 static int genwqe_unpin_mem(struct genwqe_file *cfile, struct genwqe_mem *m)
807 {
808 struct genwqe_dev *cd = cfile->cd;
809 struct dma_mapping *dma_map;
810 unsigned long map_addr;
811 unsigned long map_size;
812
813 if (m->addr == 0x0)
814 return -EINVAL;
815
816 map_addr = (m->addr & PAGE_MASK);
817 map_size = round_up(m->size + (m->addr & ~PAGE_MASK), PAGE_SIZE);
818
819 dma_map = genwqe_search_pin(cfile, map_addr, map_size, NULL);
820 if (dma_map == NULL)
821 return -ENOENT;
822
823 genwqe_del_pin(cfile, dma_map);
824 genwqe_user_vunmap(cd, dma_map);
825 kfree(dma_map);
826 return 0;
827 }
828
829 /**
830 * ddcb_cmd_cleanup() - Remove dynamically created fixup entries
831 *
832 * Only if there are any. Pinnings are not removed.
833 */
834 static int ddcb_cmd_cleanup(struct genwqe_file *cfile, struct ddcb_requ *req)
835 {
836 unsigned int i;
837 struct dma_mapping *dma_map;
838 struct genwqe_dev *cd = cfile->cd;
839
840 for (i = 0; i < DDCB_FIXUPS; i++) {
841 dma_map = &req->dma_mappings[i];
842
843 if (dma_mapping_used(dma_map)) {
844 __genwqe_del_mapping(cfile, dma_map);
845 genwqe_user_vunmap(cd, dma_map);
846 }
847 if (req->sgls[i].sgl != NULL)
848 genwqe_free_sync_sgl(cd, &req->sgls[i]);
849 }
850 return 0;
851 }
852
853 /**
854 * ddcb_cmd_fixups() - Establish DMA fixups/sglists for user memory references
855 *
856 * Before the DDCB gets executed we need to handle the fixups. We
857 * replace the user-space addresses with DMA addresses or do
858 * additional setup work e.g. generating a scatter-gather list which
859 * is used to describe the memory referred to in the fixup.
860 */
861 static int ddcb_cmd_fixups(struct genwqe_file *cfile, struct ddcb_requ *req)
862 {
863 int rc;
864 unsigned int asiv_offs, i;
865 struct genwqe_dev *cd = cfile->cd;
866 struct genwqe_ddcb_cmd *cmd = &req->cmd;
867 struct dma_mapping *m;
868
869 for (i = 0, asiv_offs = 0x00; asiv_offs <= 0x58;
870 i++, asiv_offs += 0x08) {
871
872 u64 u_addr;
873 dma_addr_t d_addr;
874 u32 u_size = 0;
875 u64 ats_flags;
876
877 ats_flags = ATS_GET_FLAGS(cmd->ats, asiv_offs);
878
879 switch (ats_flags) {
880
881 case ATS_TYPE_DATA:
882 break; /* nothing to do here */
883
884 case ATS_TYPE_FLAT_RDWR:
885 case ATS_TYPE_FLAT_RD: {
886 u_addr = be64_to_cpu(*((__be64 *)&cmd->
887 asiv[asiv_offs]));
888 u_size = be32_to_cpu(*((__be32 *)&cmd->
889 asiv[asiv_offs + 0x08]));
890
891 /*
892 * No data available. Ignore u_addr in this
893 * case and set addr to 0. Hardware must not
894 * fetch the buffer.
895 */
896 if (u_size == 0x0) {
897 *((__be64 *)&cmd->asiv[asiv_offs]) =
898 cpu_to_be64(0x0);
899 break;
900 }
901
902 m = __genwqe_search_mapping(cfile, u_addr, u_size,
903 &d_addr, NULL);
904 if (m == NULL) {
905 rc = -EFAULT;
906 goto err_out;
907 }
908
909 *((__be64 *)&cmd->asiv[asiv_offs]) =
910 cpu_to_be64(d_addr);
911 break;
912 }
913
914 case ATS_TYPE_SGL_RDWR:
915 case ATS_TYPE_SGL_RD: {
916 int page_offs;
917
918 u_addr = be64_to_cpu(*((__be64 *)
919 &cmd->asiv[asiv_offs]));
920 u_size = be32_to_cpu(*((__be32 *)
921 &cmd->asiv[asiv_offs + 0x08]));
922
923 /*
924 * No data available. Ignore u_addr in this
925 * case and set addr to 0. Hardware must not
926 * fetch the empty sgl.
927 */
928 if (u_size == 0x0) {
929 *((__be64 *)&cmd->asiv[asiv_offs]) =
930 cpu_to_be64(0x0);
931 break;
932 }
933
934 m = genwqe_search_pin(cfile, u_addr, u_size, NULL);
935 if (m != NULL) {
936 page_offs = (u_addr -
937 (u64)m->u_vaddr)/PAGE_SIZE;
938 } else {
939 m = &req->dma_mappings[i];
940
941 genwqe_mapping_init(m,
942 GENWQE_MAPPING_SGL_TEMP);
943
944 if (ats_flags == ATS_TYPE_SGL_RD)
945 m->write = 0;
946
947 rc = genwqe_user_vmap(cd, m, (void *)u_addr,
948 u_size);
949 if (rc != 0)
950 goto err_out;
951
952 __genwqe_add_mapping(cfile, m);
953 page_offs = 0;
954 }
955
956 /* create genwqe style scatter gather list */
957 rc = genwqe_alloc_sync_sgl(cd, &req->sgls[i],
958 (void __user *)u_addr,
959 u_size, m->write);
960 if (rc != 0)
961 goto err_out;
962
963 genwqe_setup_sgl(cd, &req->sgls[i],
964 &m->dma_list[page_offs]);
965
966 *((__be64 *)&cmd->asiv[asiv_offs]) =
967 cpu_to_be64(req->sgls[i].sgl_dma_addr);
968
969 break;
970 }
971 default:
972 rc = -EINVAL;
973 goto err_out;
974 }
975 }
976 return 0;
977
978 err_out:
979 ddcb_cmd_cleanup(cfile, req);
980 return rc;
981 }
982
983 /**
984 * genwqe_execute_ddcb() - Execute DDCB using userspace address fixups
985 *
986 * The code will build up the translation tables or lookup the
987 * contignous memory allocation table to find the right translations
988 * and DMA addresses.
989 */
990 static int genwqe_execute_ddcb(struct genwqe_file *cfile,
991 struct genwqe_ddcb_cmd *cmd)
992 {
993 int rc;
994 struct genwqe_dev *cd = cfile->cd;
995 struct file *filp = cfile->filp;
996 struct ddcb_requ *req = container_of(cmd, struct ddcb_requ, cmd);
997
998 rc = ddcb_cmd_fixups(cfile, req);
999 if (rc != 0)
1000 return rc;
1001
1002 rc = __genwqe_execute_raw_ddcb(cd, cmd, filp->f_flags);
1003 ddcb_cmd_cleanup(cfile, req);
1004 return rc;
1005 }
1006
1007 static int do_execute_ddcb(struct genwqe_file *cfile,
1008 unsigned long arg, int raw)
1009 {
1010 int rc;
1011 struct genwqe_ddcb_cmd *cmd;
1012 struct genwqe_dev *cd = cfile->cd;
1013 struct file *filp = cfile->filp;
1014
1015 cmd = ddcb_requ_alloc();
1016 if (cmd == NULL)
1017 return -ENOMEM;
1018
1019 if (copy_from_user(cmd, (void __user *)arg, sizeof(*cmd))) {
1020 ddcb_requ_free(cmd);
1021 return -EFAULT;
1022 }
1023
1024 if (!raw)
1025 rc = genwqe_execute_ddcb(cfile, cmd);
1026 else
1027 rc = __genwqe_execute_raw_ddcb(cd, cmd, filp->f_flags);
1028
1029 /* Copy back only the modifed fields. Do not copy ASIV
1030 back since the copy got modified by the driver. */
1031 if (copy_to_user((void __user *)arg, cmd,
1032 sizeof(*cmd) - DDCB_ASIV_LENGTH)) {
1033 ddcb_requ_free(cmd);
1034 return -EFAULT;
1035 }
1036
1037 ddcb_requ_free(cmd);
1038 return rc;
1039 }
1040
1041 /**
1042 * genwqe_ioctl() - IO control
1043 * @filp: file handle
1044 * @cmd: command identifier (passed from user)
1045 * @arg: argument (passed from user)
1046 *
1047 * Return: 0 success
1048 */
1049 static long genwqe_ioctl(struct file *filp, unsigned int cmd,
1050 unsigned long arg)
1051 {
1052 int rc = 0;
1053 struct genwqe_file *cfile = (struct genwqe_file *)filp->private_data;
1054 struct genwqe_dev *cd = cfile->cd;
1055 struct pci_dev *pci_dev = cd->pci_dev;
1056 struct genwqe_reg_io __user *io;
1057 u64 val;
1058 u32 reg_offs;
1059
1060 /* Return -EIO if card hit EEH */
1061 if (pci_channel_offline(pci_dev))
1062 return -EIO;
1063
1064 if (_IOC_TYPE(cmd) != GENWQE_IOC_CODE)
1065 return -EINVAL;
1066
1067 switch (cmd) {
1068
1069 case GENWQE_GET_CARD_STATE:
1070 put_user(cd->card_state, (enum genwqe_card_state __user *)arg);
1071 return 0;
1072
1073 /* Register access */
1074 case GENWQE_READ_REG64: {
1075 io = (struct genwqe_reg_io __user *)arg;
1076
1077 if (get_user(reg_offs, &io->num))
1078 return -EFAULT;
1079
1080 if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x7))
1081 return -EINVAL;
1082
1083 val = __genwqe_readq(cd, reg_offs);
1084 put_user(val, &io->val64);
1085 return 0;
1086 }
1087
1088 case GENWQE_WRITE_REG64: {
1089 io = (struct genwqe_reg_io __user *)arg;
1090
1091 if (!capable(CAP_SYS_ADMIN))
1092 return -EPERM;
1093
1094 if ((filp->f_flags & O_ACCMODE) == O_RDONLY)
1095 return -EPERM;
1096
1097 if (get_user(reg_offs, &io->num))
1098 return -EFAULT;
1099
1100 if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x7))
1101 return -EINVAL;
1102
1103 if (get_user(val, &io->val64))
1104 return -EFAULT;
1105
1106 __genwqe_writeq(cd, reg_offs, val);
1107 return 0;
1108 }
1109
1110 case GENWQE_READ_REG32: {
1111 io = (struct genwqe_reg_io __user *)arg;
1112
1113 if (get_user(reg_offs, &io->num))
1114 return -EFAULT;
1115
1116 if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x3))
1117 return -EINVAL;
1118
1119 val = __genwqe_readl(cd, reg_offs);
1120 put_user(val, &io->val64);
1121 return 0;
1122 }
1123
1124 case GENWQE_WRITE_REG32: {
1125 io = (struct genwqe_reg_io __user *)arg;
1126
1127 if (!capable(CAP_SYS_ADMIN))
1128 return -EPERM;
1129
1130 if ((filp->f_flags & O_ACCMODE) == O_RDONLY)
1131 return -EPERM;
1132
1133 if (get_user(reg_offs, &io->num))
1134 return -EFAULT;
1135
1136 if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x3))
1137 return -EINVAL;
1138
1139 if (get_user(val, &io->val64))
1140 return -EFAULT;
1141
1142 __genwqe_writel(cd, reg_offs, val);
1143 return 0;
1144 }
1145
1146 /* Flash update/reading */
1147 case GENWQE_SLU_UPDATE: {
1148 struct genwqe_bitstream load;
1149
1150 if (!genwqe_is_privileged(cd))
1151 return -EPERM;
1152
1153 if ((filp->f_flags & O_ACCMODE) == O_RDONLY)
1154 return -EPERM;
1155
1156 if (copy_from_user(&load, (void __user *)arg,
1157 sizeof(load)))
1158 return -EFAULT;
1159
1160 rc = do_flash_update(cfile, &load);
1161
1162 if (copy_to_user((void __user *)arg, &load, sizeof(load)))
1163 return -EFAULT;
1164
1165 return rc;
1166 }
1167
1168 case GENWQE_SLU_READ: {
1169 struct genwqe_bitstream load;
1170
1171 if (!genwqe_is_privileged(cd))
1172 return -EPERM;
1173
1174 if (genwqe_flash_readback_fails(cd))
1175 return -ENOSPC; /* known to fail for old versions */
1176
1177 if (copy_from_user(&load, (void __user *)arg, sizeof(load)))
1178 return -EFAULT;
1179
1180 rc = do_flash_read(cfile, &load);
1181
1182 if (copy_to_user((void __user *)arg, &load, sizeof(load)))
1183 return -EFAULT;
1184
1185 return rc;
1186 }
1187
1188 /* memory pinning and unpinning */
1189 case GENWQE_PIN_MEM: {
1190 struct genwqe_mem m;
1191
1192 if (copy_from_user(&m, (void __user *)arg, sizeof(m)))
1193 return -EFAULT;
1194
1195 return genwqe_pin_mem(cfile, &m);
1196 }
1197
1198 case GENWQE_UNPIN_MEM: {
1199 struct genwqe_mem m;
1200
1201 if (copy_from_user(&m, (void __user *)arg, sizeof(m)))
1202 return -EFAULT;
1203
1204 return genwqe_unpin_mem(cfile, &m);
1205 }
1206
1207 /* launch an DDCB and wait for completion */
1208 case GENWQE_EXECUTE_DDCB:
1209 return do_execute_ddcb(cfile, arg, 0);
1210
1211 case GENWQE_EXECUTE_RAW_DDCB: {
1212
1213 if (!capable(CAP_SYS_ADMIN))
1214 return -EPERM;
1215
1216 return do_execute_ddcb(cfile, arg, 1);
1217 }
1218
1219 default:
1220 return -EINVAL;
1221 }
1222
1223 return rc;
1224 }
1225
1226 #if defined(CONFIG_COMPAT)
1227 /**
1228 * genwqe_compat_ioctl() - Compatibility ioctl
1229 *
1230 * Called whenever a 32-bit process running under a 64-bit kernel
1231 * performs an ioctl on /dev/genwqe<n>_card.
1232 *
1233 * @filp: file pointer.
1234 * @cmd: command.
1235 * @arg: user argument.
1236 * Return: zero on success or negative number on failure.
1237 */
1238 static long genwqe_compat_ioctl(struct file *filp, unsigned int cmd,
1239 unsigned long arg)
1240 {
1241 return genwqe_ioctl(filp, cmd, arg);
1242 }
1243 #endif /* defined(CONFIG_COMPAT) */
1244
1245 static const struct file_operations genwqe_fops = {
1246 .owner = THIS_MODULE,
1247 .open = genwqe_open,
1248 .fasync = genwqe_fasync,
1249 .mmap = genwqe_mmap,
1250 .unlocked_ioctl = genwqe_ioctl,
1251 #if defined(CONFIG_COMPAT)
1252 .compat_ioctl = genwqe_compat_ioctl,
1253 #endif
1254 .release = genwqe_release,
1255 };
1256
1257 static int genwqe_device_initialized(struct genwqe_dev *cd)
1258 {
1259 return cd->dev != NULL;
1260 }
1261
1262 /**
1263 * genwqe_device_create() - Create and configure genwqe char device
1264 * @cd: genwqe device descriptor
1265 *
1266 * This function must be called before we create any more genwqe
1267 * character devices, because it is allocating the major and minor
1268 * number which are supposed to be used by the client drivers.
1269 */
1270 int genwqe_device_create(struct genwqe_dev *cd)
1271 {
1272 int rc;
1273 struct pci_dev *pci_dev = cd->pci_dev;
1274
1275 /*
1276 * Here starts the individual setup per client. It must
1277 * initialize its own cdev data structure with its own fops.
1278 * The appropriate devnum needs to be created. The ranges must
1279 * not overlap.
1280 */
1281 rc = alloc_chrdev_region(&cd->devnum_genwqe, 0,
1282 GENWQE_MAX_MINOR, GENWQE_DEVNAME);
1283 if (rc < 0) {
1284 dev_err(&pci_dev->dev, "err: alloc_chrdev_region failed\n");
1285 goto err_dev;
1286 }
1287
1288 cdev_init(&cd->cdev_genwqe, &genwqe_fops);
1289 cd->cdev_genwqe.owner = THIS_MODULE;
1290
1291 rc = cdev_add(&cd->cdev_genwqe, cd->devnum_genwqe, 1);
1292 if (rc < 0) {
1293 dev_err(&pci_dev->dev, "err: cdev_add failed\n");
1294 goto err_add;
1295 }
1296
1297 /*
1298 * Finally the device in /dev/... must be created. The rule is
1299 * to use card%d_clientname for each created device.
1300 */
1301 cd->dev = device_create_with_groups(cd->class_genwqe,
1302 &cd->pci_dev->dev,
1303 cd->devnum_genwqe, cd,
1304 genwqe_attribute_groups,
1305 GENWQE_DEVNAME "%u_card",
1306 cd->card_idx);
1307 if (IS_ERR(cd->dev)) {
1308 rc = PTR_ERR(cd->dev);
1309 goto err_cdev;
1310 }
1311
1312 rc = genwqe_init_debugfs(cd);
1313 if (rc != 0)
1314 goto err_debugfs;
1315
1316 return 0;
1317
1318 err_debugfs:
1319 device_destroy(cd->class_genwqe, cd->devnum_genwqe);
1320 err_cdev:
1321 cdev_del(&cd->cdev_genwqe);
1322 err_add:
1323 unregister_chrdev_region(cd->devnum_genwqe, GENWQE_MAX_MINOR);
1324 err_dev:
1325 cd->dev = NULL;
1326 return rc;
1327 }
1328
1329 static int genwqe_inform_and_stop_processes(struct genwqe_dev *cd)
1330 {
1331 int rc;
1332 unsigned int i;
1333 struct pci_dev *pci_dev = cd->pci_dev;
1334
1335 if (!genwqe_open_files(cd))
1336 return 0;
1337
1338 dev_warn(&pci_dev->dev, "[%s] send SIGIO and wait ...\n", __func__);
1339
1340 rc = genwqe_kill_fasync(cd, SIGIO);
1341 if (rc > 0) {
1342 /* give kill_timeout seconds to close file descriptors ... */
1343 for (i = 0; (i < GENWQE_KILL_TIMEOUT) &&
1344 genwqe_open_files(cd); i++) {
1345 dev_info(&pci_dev->dev, " %d sec ...", i);
1346
1347 cond_resched();
1348 msleep(1000);
1349 }
1350
1351 /* if no open files we can safely continue, else ... */
1352 if (!genwqe_open_files(cd))
1353 return 0;
1354
1355 dev_warn(&pci_dev->dev,
1356 "[%s] send SIGKILL and wait ...\n", __func__);
1357
1358 rc = genwqe_terminate(cd);
1359 if (rc) {
1360 /* Give kill_timout more seconds to end processes */
1361 for (i = 0; (i < GENWQE_KILL_TIMEOUT) &&
1362 genwqe_open_files(cd); i++) {
1363 dev_warn(&pci_dev->dev, " %d sec ...", i);
1364
1365 cond_resched();
1366 msleep(1000);
1367 }
1368 }
1369 }
1370 return 0;
1371 }
1372
1373 /**
1374 * genwqe_device_remove() - Remove genwqe's char device
1375 *
1376 * This function must be called after the client devices are removed
1377 * because it will free the major/minor number range for the genwqe
1378 * drivers.
1379 *
1380 * This function must be robust enough to be called twice.
1381 */
1382 int genwqe_device_remove(struct genwqe_dev *cd)
1383 {
1384 int rc;
1385 struct pci_dev *pci_dev = cd->pci_dev;
1386
1387 if (!genwqe_device_initialized(cd))
1388 return 1;
1389
1390 genwqe_inform_and_stop_processes(cd);
1391
1392 /*
1393 * We currently do wait until all filedescriptors are
1394 * closed. This leads to a problem when we abort the
1395 * application which will decrease this reference from
1396 * 1/unused to 0/illegal and not from 2/used 1/empty.
1397 */
1398 rc = kref_read(&cd->cdev_genwqe.kobj.kref);
1399 if (rc != 1) {
1400 dev_err(&pci_dev->dev,
1401 "[%s] err: cdev_genwqe...refcount=%d\n", __func__, rc);
1402 panic("Fatal err: cannot free resources with pending references!");
1403 }
1404
1405 genqwe_exit_debugfs(cd);
1406 device_destroy(cd->class_genwqe, cd->devnum_genwqe);
1407 cdev_del(&cd->cdev_genwqe);
1408 unregister_chrdev_region(cd->devnum_genwqe, GENWQE_MAX_MINOR);
1409 cd->dev = NULL;
1410
1411 return 0;
1412 }
Linux with added FPC-III support