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Linux 4.19.133
[linux/fpc-iii.git] / drivers / misc / pci_endpoint_test.c
blob7d166f57f624227a90db4e5d18eeecb012d095bc
1 /**
2 * Host side test driver to test endpoint functionality
3 *
4 * Copyright (C) 2017 Texas Instruments
5 * Author: Kishon Vijay Abraham I <kishon@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/crc32.h>
21 #include <linux/delay.h>
22 #include <linux/fs.h>
23 #include <linux/io.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/miscdevice.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/random.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/pci_ids.h>
33
34 #include <linux/pci_regs.h>
35
36 #include <uapi/linux/pcitest.h>
37
38 #define DRV_MODULE_NAME "pci-endpoint-test"
39
40 #define IRQ_TYPE_UNDEFINED -1
41 #define IRQ_TYPE_LEGACY 0
42 #define IRQ_TYPE_MSI 1
43 #define IRQ_TYPE_MSIX 2
44
45 #define PCI_ENDPOINT_TEST_MAGIC 0x0
46
47 #define PCI_ENDPOINT_TEST_COMMAND 0x4
48 #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
49 #define COMMAND_RAISE_MSI_IRQ BIT(1)
50 #define COMMAND_RAISE_MSIX_IRQ BIT(2)
51 #define COMMAND_READ BIT(3)
52 #define COMMAND_WRITE BIT(4)
53 #define COMMAND_COPY BIT(5)
54
55 #define PCI_ENDPOINT_TEST_STATUS 0x8
56 #define STATUS_READ_SUCCESS BIT(0)
57 #define STATUS_READ_FAIL BIT(1)
58 #define STATUS_WRITE_SUCCESS BIT(2)
59 #define STATUS_WRITE_FAIL BIT(3)
60 #define STATUS_COPY_SUCCESS BIT(4)
61 #define STATUS_COPY_FAIL BIT(5)
62 #define STATUS_IRQ_RAISED BIT(6)
63 #define STATUS_SRC_ADDR_INVALID BIT(7)
64 #define STATUS_DST_ADDR_INVALID BIT(8)
65
66 #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
67 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
68
69 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
70 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
71
72 #define PCI_ENDPOINT_TEST_SIZE 0x1c
73 #define PCI_ENDPOINT_TEST_CHECKSUM 0x20
74
75 #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
76 #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
77
78 #define PCI_DEVICE_ID_TI_AM654 0xb00c
79
80 #define is_am654_pci_dev(pdev) \
81 ((pdev)->device == PCI_DEVICE_ID_TI_AM654)
82
83 static DEFINE_IDA(pci_endpoint_test_ida);
84
85 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
86 miscdev)
87
88 static bool no_msi;
89 module_param(no_msi, bool, 0444);
90 MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
91
92 static int irq_type = IRQ_TYPE_MSI;
93 module_param(irq_type, int, 0444);
94 MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
95
96 enum pci_barno {
97 BAR_0,
98 BAR_1,
99 BAR_2,
100 BAR_3,
101 BAR_4,
102 BAR_5,
103 };
104
105 struct pci_endpoint_test {
106 struct pci_dev *pdev;
107 void __iomem *base;
108 void __iomem *bar[6];
109 struct completion irq_raised;
110 int last_irq;
111 int num_irqs;
112 int irq_type;
113 /* mutex to protect the ioctls */
114 struct mutex mutex;
115 struct miscdevice miscdev;
116 enum pci_barno test_reg_bar;
117 size_t alignment;
118 };
119
120 struct pci_endpoint_test_data {
121 enum pci_barno test_reg_bar;
122 size_t alignment;
123 int irq_type;
124 };
125
126 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
127 u32 offset)
128 {
129 return readl(test->base + offset);
130 }
131
132 static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
133 u32 offset, u32 value)
134 {
135 writel(value, test->base + offset);
136 }
137
138 static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
139 int bar, int offset)
140 {
141 return readl(test->bar[bar] + offset);
142 }
143
144 static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
145 int bar, u32 offset, u32 value)
146 {
147 writel(value, test->bar[bar] + offset);
148 }
149
150 static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
151 {
152 struct pci_endpoint_test *test = dev_id;
153 u32 reg;
154
155 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
156 if (reg & STATUS_IRQ_RAISED) {
157 test->last_irq = irq;
158 complete(&test->irq_raised);
159 reg &= ~STATUS_IRQ_RAISED;
160 }
161 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
162 reg);
163
164 return IRQ_HANDLED;
165 }
166
167 static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
168 {
169 struct pci_dev *pdev = test->pdev;
170
171 pci_free_irq_vectors(pdev);
172 test->irq_type = IRQ_TYPE_UNDEFINED;
173 }
174
175 static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
176 int type)
177 {
178 int irq = -1;
179 struct pci_dev *pdev = test->pdev;
180 struct device *dev = &pdev->dev;
181 bool res = true;
182
183 switch (type) {
184 case IRQ_TYPE_LEGACY:
185 irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
186 if (irq < 0)
187 dev_err(dev, "Failed to get Legacy interrupt\n");
188 break;
189 case IRQ_TYPE_MSI:
190 irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
191 if (irq < 0)
192 dev_err(dev, "Failed to get MSI interrupts\n");
193 break;
194 case IRQ_TYPE_MSIX:
195 irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
196 if (irq < 0)
197 dev_err(dev, "Failed to get MSI-X interrupts\n");
198 break;
199 default:
200 dev_err(dev, "Invalid IRQ type selected\n");
201 }
202
203 if (irq < 0) {
204 irq = 0;
205 res = false;
206 }
207
208 test->irq_type = type;
209 test->num_irqs = irq;
210
211 return res;
212 }
213
214 static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
215 {
216 int i;
217 struct pci_dev *pdev = test->pdev;
218 struct device *dev = &pdev->dev;
219
220 for (i = 0; i < test->num_irqs; i++)
221 devm_free_irq(dev, pci_irq_vector(pdev, i), test);
222
223 test->num_irqs = 0;
224 }
225
226 static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
227 {
228 int i;
229 int err;
230 struct pci_dev *pdev = test->pdev;
231 struct device *dev = &pdev->dev;
232
233 for (i = 0; i < test->num_irqs; i++) {
234 err = devm_request_irq(dev, pci_irq_vector(pdev, i),
235 pci_endpoint_test_irqhandler,
236 IRQF_SHARED, DRV_MODULE_NAME, test);
237 if (err)
238 goto fail;
239 }
240
241 return true;
242
243 fail:
244 switch (irq_type) {
245 case IRQ_TYPE_LEGACY:
246 dev_err(dev, "Failed to request IRQ %d for Legacy\n",
247 pci_irq_vector(pdev, i));
248 break;
249 case IRQ_TYPE_MSI:
250 dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
251 pci_irq_vector(pdev, i),
252 i + 1);
253 break;
254 case IRQ_TYPE_MSIX:
255 dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
256 pci_irq_vector(pdev, i),
257 i + 1);
258 break;
259 }
260
261 return false;
262 }
263
264 static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
265 enum pci_barno barno)
266 {
267 int j;
268 u32 val;
269 int size;
270 struct pci_dev *pdev = test->pdev;
271
272 if (!test->bar[barno])
273 return false;
274
275 size = pci_resource_len(pdev, barno);
276
277 if (barno == test->test_reg_bar)
278 size = 0x4;
279
280 for (j = 0; j < size; j += 4)
281 pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
282
283 for (j = 0; j < size; j += 4) {
284 val = pci_endpoint_test_bar_readl(test, barno, j);
285 if (val != 0xA0A0A0A0)
286 return false;
287 }
288
289 return true;
290 }
291
292 static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
293 {
294 u32 val;
295
296 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
297 IRQ_TYPE_LEGACY);
298 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
299 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
300 COMMAND_RAISE_LEGACY_IRQ);
301 val = wait_for_completion_timeout(&test->irq_raised,
302 msecs_to_jiffies(1000));
303 if (!val)
304 return false;
305
306 return true;
307 }
308
309 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
310 u16 msi_num, bool msix)
311 {
312 u32 val;
313 struct pci_dev *pdev = test->pdev;
314
315 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
316 msix == false ? IRQ_TYPE_MSI :
317 IRQ_TYPE_MSIX);
318 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
319 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
320 msix == false ? COMMAND_RAISE_MSI_IRQ :
321 COMMAND_RAISE_MSIX_IRQ);
322 val = wait_for_completion_timeout(&test->irq_raised,
323 msecs_to_jiffies(1000));
324 if (!val)
325 return false;
326
327 if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
328 return true;
329
330 return false;
331 }
332
333 static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
334 {
335 bool ret = false;
336 void *src_addr;
337 void *dst_addr;
338 dma_addr_t src_phys_addr;
339 dma_addr_t dst_phys_addr;
340 struct pci_dev *pdev = test->pdev;
341 struct device *dev = &pdev->dev;
342 void *orig_src_addr;
343 dma_addr_t orig_src_phys_addr;
344 void *orig_dst_addr;
345 dma_addr_t orig_dst_phys_addr;
346 size_t offset;
347 size_t alignment = test->alignment;
348 int irq_type = test->irq_type;
349 u32 src_crc32;
350 u32 dst_crc32;
351
352 if (size > SIZE_MAX - alignment)
353 goto err;
354
355 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
356 dev_err(dev, "Invalid IRQ type option\n");
357 goto err;
358 }
359
360 orig_src_addr = dma_alloc_coherent(dev, size + alignment,
361 &orig_src_phys_addr, GFP_KERNEL);
362 if (!orig_src_addr) {
363 dev_err(dev, "Failed to allocate source buffer\n");
364 ret = false;
365 goto err;
366 }
367
368 if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
369 src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
370 offset = src_phys_addr - orig_src_phys_addr;
371 src_addr = orig_src_addr + offset;
372 } else {
373 src_phys_addr = orig_src_phys_addr;
374 src_addr = orig_src_addr;
375 }
376
377 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
378 lower_32_bits(src_phys_addr));
379
380 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
381 upper_32_bits(src_phys_addr));
382
383 get_random_bytes(src_addr, size);
384 src_crc32 = crc32_le(~0, src_addr, size);
385
386 orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
387 &orig_dst_phys_addr, GFP_KERNEL);
388 if (!orig_dst_addr) {
389 dev_err(dev, "Failed to allocate destination address\n");
390 ret = false;
391 goto err_orig_src_addr;
392 }
393
394 if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
395 dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
396 offset = dst_phys_addr - orig_dst_phys_addr;
397 dst_addr = orig_dst_addr + offset;
398 } else {
399 dst_phys_addr = orig_dst_phys_addr;
400 dst_addr = orig_dst_addr;
401 }
402
403 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
404 lower_32_bits(dst_phys_addr));
405 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
406 upper_32_bits(dst_phys_addr));
407
408 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
409 size);
410
411 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
412 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
413 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
414 COMMAND_COPY);
415
416 wait_for_completion(&test->irq_raised);
417
418 dst_crc32 = crc32_le(~0, dst_addr, size);
419 if (dst_crc32 == src_crc32)
420 ret = true;
421
422 dma_free_coherent(dev, size + alignment, orig_dst_addr,
423 orig_dst_phys_addr);
424
425 err_orig_src_addr:
426 dma_free_coherent(dev, size + alignment, orig_src_addr,
427 orig_src_phys_addr);
428
429 err:
430 return ret;
431 }
432
433 static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
434 {
435 bool ret = false;
436 u32 reg;
437 void *addr;
438 dma_addr_t phys_addr;
439 struct pci_dev *pdev = test->pdev;
440 struct device *dev = &pdev->dev;
441 void *orig_addr;
442 dma_addr_t orig_phys_addr;
443 size_t offset;
444 size_t alignment = test->alignment;
445 int irq_type = test->irq_type;
446 u32 crc32;
447
448 if (size > SIZE_MAX - alignment)
449 goto err;
450
451 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
452 dev_err(dev, "Invalid IRQ type option\n");
453 goto err;
454 }
455
456 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
457 GFP_KERNEL);
458 if (!orig_addr) {
459 dev_err(dev, "Failed to allocate address\n");
460 ret = false;
461 goto err;
462 }
463
464 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
465 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
466 offset = phys_addr - orig_phys_addr;
467 addr = orig_addr + offset;
468 } else {
469 phys_addr = orig_phys_addr;
470 addr = orig_addr;
471 }
472
473 get_random_bytes(addr, size);
474
475 crc32 = crc32_le(~0, addr, size);
476 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
477 crc32);
478
479 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
480 lower_32_bits(phys_addr));
481 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
482 upper_32_bits(phys_addr));
483
484 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
485
486 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
487 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
488 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
489 COMMAND_READ);
490
491 wait_for_completion(&test->irq_raised);
492
493 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
494 if (reg & STATUS_READ_SUCCESS)
495 ret = true;
496
497 dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
498
499 err:
500 return ret;
501 }
502
503 static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
504 {
505 bool ret = false;
506 void *addr;
507 dma_addr_t phys_addr;
508 struct pci_dev *pdev = test->pdev;
509 struct device *dev = &pdev->dev;
510 void *orig_addr;
511 dma_addr_t orig_phys_addr;
512 size_t offset;
513 size_t alignment = test->alignment;
514 int irq_type = test->irq_type;
515 u32 crc32;
516
517 if (size > SIZE_MAX - alignment)
518 goto err;
519
520 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
521 dev_err(dev, "Invalid IRQ type option\n");
522 goto err;
523 }
524
525 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
526 GFP_KERNEL);
527 if (!orig_addr) {
528 dev_err(dev, "Failed to allocate destination address\n");
529 ret = false;
530 goto err;
531 }
532
533 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
534 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
535 offset = phys_addr - orig_phys_addr;
536 addr = orig_addr + offset;
537 } else {
538 phys_addr = orig_phys_addr;
539 addr = orig_addr;
540 }
541
542 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
543 lower_32_bits(phys_addr));
544 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
545 upper_32_bits(phys_addr));
546
547 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
548
549 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
550 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
551 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
552 COMMAND_WRITE);
553
554 wait_for_completion(&test->irq_raised);
555
556 crc32 = crc32_le(~0, addr, size);
557 if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
558 ret = true;
559
560 dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
561 err:
562 return ret;
563 }
564
565 static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
566 int req_irq_type)
567 {
568 struct pci_dev *pdev = test->pdev;
569 struct device *dev = &pdev->dev;
570
571 if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
572 dev_err(dev, "Invalid IRQ type option\n");
573 return false;
574 }
575
576 if (test->irq_type == req_irq_type)
577 return true;
578
579 pci_endpoint_test_release_irq(test);
580 pci_endpoint_test_free_irq_vectors(test);
581
582 if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
583 goto err;
584
585 if (!pci_endpoint_test_request_irq(test))
586 goto err;
587
588 return true;
589
590 err:
591 pci_endpoint_test_free_irq_vectors(test);
592 return false;
593 }
594
595 static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
596 unsigned long arg)
597 {
598 int ret = -EINVAL;
599 enum pci_barno bar;
600 struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
601 struct pci_dev *pdev = test->pdev;
602
603 mutex_lock(&test->mutex);
604 switch (cmd) {
605 case PCITEST_BAR:
606 bar = arg;
607 if (bar < 0 || bar > 5)
608 goto ret;
609 if (is_am654_pci_dev(pdev) && bar == BAR_0)
610 goto ret;
611 ret = pci_endpoint_test_bar(test, bar);
612 break;
613 case PCITEST_LEGACY_IRQ:
614 ret = pci_endpoint_test_legacy_irq(test);
615 break;
616 case PCITEST_MSI:
617 case PCITEST_MSIX:
618 ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
619 break;
620 case PCITEST_WRITE:
621 ret = pci_endpoint_test_write(test, arg);
622 break;
623 case PCITEST_READ:
624 ret = pci_endpoint_test_read(test, arg);
625 break;
626 case PCITEST_COPY:
627 ret = pci_endpoint_test_copy(test, arg);
628 break;
629 case PCITEST_SET_IRQTYPE:
630 ret = pci_endpoint_test_set_irq(test, arg);
631 break;
632 case PCITEST_GET_IRQTYPE:
633 ret = irq_type;
634 break;
635 }
636
637 ret:
638 mutex_unlock(&test->mutex);
639 return ret;
640 }
641
642 static const struct file_operations pci_endpoint_test_fops = {
643 .owner = THIS_MODULE,
644 .unlocked_ioctl = pci_endpoint_test_ioctl,
645 };
646
647 static int pci_endpoint_test_probe(struct pci_dev *pdev,
648 const struct pci_device_id *ent)
649 {
650 int err;
651 int id;
652 char name[24];
653 enum pci_barno bar;
654 void __iomem *base;
655 struct device *dev = &pdev->dev;
656 struct pci_endpoint_test *test;
657 struct pci_endpoint_test_data *data;
658 enum pci_barno test_reg_bar = BAR_0;
659 struct miscdevice *misc_device;
660
661 if (pci_is_bridge(pdev))
662 return -ENODEV;
663
664 test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
665 if (!test)
666 return -ENOMEM;
667
668 test->test_reg_bar = 0;
669 test->alignment = 0;
670 test->pdev = pdev;
671 test->irq_type = IRQ_TYPE_UNDEFINED;
672
673 if (no_msi)
674 irq_type = IRQ_TYPE_LEGACY;
675
676 data = (struct pci_endpoint_test_data *)ent->driver_data;
677 if (data) {
678 test_reg_bar = data->test_reg_bar;
679 test->test_reg_bar = test_reg_bar;
680 test->alignment = data->alignment;
681 irq_type = data->irq_type;
682 }
683
684 init_completion(&test->irq_raised);
685 mutex_init(&test->mutex);
686
687 err = pci_enable_device(pdev);
688 if (err) {
689 dev_err(dev, "Cannot enable PCI device\n");
690 return err;
691 }
692
693 err = pci_request_regions(pdev, DRV_MODULE_NAME);
694 if (err) {
695 dev_err(dev, "Cannot obtain PCI resources\n");
696 goto err_disable_pdev;
697 }
698
699 pci_set_master(pdev);
700
701 if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type))
702 goto err_disable_irq;
703
704 if (!pci_endpoint_test_request_irq(test))
705 goto err_disable_irq;
706
707 for (bar = BAR_0; bar <= BAR_5; bar++) {
708 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
709 base = pci_ioremap_bar(pdev, bar);
710 if (!base) {
711 dev_err(dev, "Failed to read BAR%d\n", bar);
712 WARN_ON(bar == test_reg_bar);
713 }
714 test->bar[bar] = base;
715 }
716 }
717
718 test->base = test->bar[test_reg_bar];
719 if (!test->base) {
720 err = -ENOMEM;
721 dev_err(dev, "Cannot perform PCI test without BAR%d\n",
722 test_reg_bar);
723 goto err_iounmap;
724 }
725
726 pci_set_drvdata(pdev, test);
727
728 id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
729 if (id < 0) {
730 err = id;
731 dev_err(dev, "Unable to get id\n");
732 goto err_iounmap;
733 }
734
735 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
736 misc_device = &test->miscdev;
737 misc_device->minor = MISC_DYNAMIC_MINOR;
738 misc_device->name = kstrdup(name, GFP_KERNEL);
739 if (!misc_device->name) {
740 err = -ENOMEM;
741 goto err_ida_remove;
742 }
743 misc_device->fops = &pci_endpoint_test_fops,
744
745 err = misc_register(misc_device);
746 if (err) {
747 dev_err(dev, "Failed to register device\n");
748 goto err_kfree_name;
749 }
750
751 return 0;
752
753 err_kfree_name:
754 kfree(misc_device->name);
755
756 err_ida_remove:
757 ida_simple_remove(&pci_endpoint_test_ida, id);
758
759 err_iounmap:
760 for (bar = BAR_0; bar <= BAR_5; bar++) {
761 if (test->bar[bar])
762 pci_iounmap(pdev, test->bar[bar]);
763 }
764 pci_endpoint_test_release_irq(test);
765
766 err_disable_irq:
767 pci_endpoint_test_free_irq_vectors(test);
768 pci_release_regions(pdev);
769
770 err_disable_pdev:
771 pci_disable_device(pdev);
772
773 return err;
774 }
775
776 static void pci_endpoint_test_remove(struct pci_dev *pdev)
777 {
778 int id;
779 enum pci_barno bar;
780 struct pci_endpoint_test *test = pci_get_drvdata(pdev);
781 struct miscdevice *misc_device = &test->miscdev;
782
783 if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
784 return;
785 if (id < 0)
786 return;
787
788 misc_deregister(&test->miscdev);
789 kfree(misc_device->name);
790 ida_simple_remove(&pci_endpoint_test_ida, id);
791 for (bar = BAR_0; bar <= BAR_5; bar++) {
792 if (test->bar[bar])
793 pci_iounmap(pdev, test->bar[bar]);
794 }
795
796 pci_endpoint_test_release_irq(test);
797 pci_endpoint_test_free_irq_vectors(test);
798
799 pci_release_regions(pdev);
800 pci_disable_device(pdev);
801 }
802
803 static const struct pci_endpoint_test_data am654_data = {
804 .test_reg_bar = BAR_2,
805 .alignment = SZ_64K,
806 .irq_type = IRQ_TYPE_MSI,
807 };
808
809 static const struct pci_device_id pci_endpoint_test_tbl[] = {
810 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
811 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
812 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },
813 { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
814 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
815 .driver_data = (kernel_ulong_t)&am654_data
816 },
817 { }
818 };
819 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
820
821 static struct pci_driver pci_endpoint_test_driver = {
822 .name = DRV_MODULE_NAME,
823 .id_table = pci_endpoint_test_tbl,
824 .probe = pci_endpoint_test_probe,
825 .remove = pci_endpoint_test_remove,
826 };
827 module_pci_driver(pci_endpoint_test_driver);
828
829 MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
830 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
831 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support