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Linux 4.19.133
[linux/fpc-iii.git] / drivers / mmc / host / atmel-mci.c
blobfbc56ee9968277634b7d8ede472070d89d486380
1 /*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/ioport.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_gpio.h>
26 #include <linux/platform_device.h>
27 #include <linux/scatterlist.h>
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <linux/stat.h>
31 #include <linux/types.h>
32
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/sdio.h>
35
36 #include <linux/atmel-mci.h>
37 #include <linux/atmel_pdc.h>
38 #include <linux/pm.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/pinctrl/consumer.h>
41
42 #include <asm/cacheflush.h>
43 #include <asm/io.h>
44 #include <asm/unaligned.h>
45
46 /*
47 * Superset of MCI IP registers integrated in Atmel AT91 Processor
48 * Registers and bitfields marked with [2] are only available in MCI2
49 */
50
51 /* MCI Register Definitions */
52 #define ATMCI_CR 0x0000 /* Control */
53 #define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
54 #define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
55 #define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
56 #define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
57 #define ATMCI_CR_SWRST BIT(7) /* Software Reset */
58 #define ATMCI_MR 0x0004 /* Mode */
59 #define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
60 #define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
61 #define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
62 #define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
63 #define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
64 #define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
65 #define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
66 #define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
67 #define ATMCI_DTOR 0x0008 /* Data Timeout */
68 #define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
69 #define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
70 #define ATMCI_SDCR 0x000c /* SD Card / SDIO */
71 #define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
72 #define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
73 #define ATMCI_SDCSEL_MASK (3 << 0)
74 #define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
75 #define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
76 #define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
77 #define ATMCI_SDCBUS_MASK (3 << 6)
78 #define ATMCI_ARGR 0x0010 /* Command Argument */
79 #define ATMCI_CMDR 0x0014 /* Command */
80 #define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
81 #define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
82 #define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
83 #define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
84 #define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
85 #define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
86 #define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
87 #define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
88 #define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
89 #define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
90 #define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
91 #define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
92 #define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
93 #define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
94 #define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
95 #define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
96 #define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
97 #define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
98 #define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
99 #define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
100 #define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
101 #define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
102 #define ATMCI_BLKR 0x0018 /* Block */
103 #define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
104 #define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
105 #define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
106 #define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
107 #define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
108 #define ATMCI_RSPR 0x0020 /* Response 0 */
109 #define ATMCI_RSPR1 0x0024 /* Response 1 */
110 #define ATMCI_RSPR2 0x0028 /* Response 2 */
111 #define ATMCI_RSPR3 0x002c /* Response 3 */
112 #define ATMCI_RDR 0x0030 /* Receive Data */
113 #define ATMCI_TDR 0x0034 /* Transmit Data */
114 #define ATMCI_SR 0x0040 /* Status */
115 #define ATMCI_IER 0x0044 /* Interrupt Enable */
116 #define ATMCI_IDR 0x0048 /* Interrupt Disable */
117 #define ATMCI_IMR 0x004c /* Interrupt Mask */
118 #define ATMCI_CMDRDY BIT(0) /* Command Ready */
119 #define ATMCI_RXRDY BIT(1) /* Receiver Ready */
120 #define ATMCI_TXRDY BIT(2) /* Transmitter Ready */
121 #define ATMCI_BLKE BIT(3) /* Data Block Ended */
122 #define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */
123 #define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */
124 #define ATMCI_ENDRX BIT(6) /* End of RX Buffer */
125 #define ATMCI_ENDTX BIT(7) /* End of TX Buffer */
126 #define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */
127 #define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */
128 #define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */
129 #define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */
130 #define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */
131 #define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */
132 #define ATMCI_RINDE BIT(16) /* Response Index Error */
133 #define ATMCI_RDIRE BIT(17) /* Response Direction Error */
134 #define ATMCI_RCRCE BIT(18) /* Response CRC Error */
135 #define ATMCI_RENDE BIT(19) /* Response End Bit Error */
136 #define ATMCI_RTOE BIT(20) /* Response Time-Out Error */
137 #define ATMCI_DCRCE BIT(21) /* Data CRC Error */
138 #define ATMCI_DTOE BIT(22) /* Data Time-Out Error */
139 #define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */
140 #define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */
141 #define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */
142 #define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */
143 #define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */
144 #define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */
145 #define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */
146 #define ATMCI_OVRE BIT(30) /* RX Overrun Error */
147 #define ATMCI_UNRE BIT(31) /* TX Underrun Error */
148 #define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
149 #define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
150 #define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
151 #define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */
152 #define ATMCI_CFG 0x0054 /* Configuration[2] */
153 #define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
154 #define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
155 #define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
156 #define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */
157 #define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
158 #define ATMCI_WP_EN BIT(0) /* WP Enable */
159 #define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
160 #define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
161 #define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
162 #define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
163 #define ATMCI_VERSION 0x00FC /* Version */
164 #define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
165
166 /* This is not including the FIFO Aperture on MCI2 */
167 #define ATMCI_REGS_SIZE 0x100
168
169 /* Register access macros */
170 #define atmci_readl(port, reg) \
171 __raw_readl((port)->regs + reg)
172 #define atmci_writel(port, reg, value) \
173 __raw_writel((value), (port)->regs + reg)
174
175 #define AUTOSUSPEND_DELAY 50
176
177 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
178 #define ATMCI_DMA_THRESHOLD 16
179
180 enum {
181 EVENT_CMD_RDY = 0,
182 EVENT_XFER_COMPLETE,
183 EVENT_NOTBUSY,
184 EVENT_DATA_ERROR,
185 };
186
187 enum atmel_mci_state {
188 STATE_IDLE = 0,
189 STATE_SENDING_CMD,
190 STATE_DATA_XFER,
191 STATE_WAITING_NOTBUSY,
192 STATE_SENDING_STOP,
193 STATE_END_REQUEST,
194 };
195
196 enum atmci_xfer_dir {
197 XFER_RECEIVE = 0,
198 XFER_TRANSMIT,
199 };
200
201 enum atmci_pdc_buf {
202 PDC_FIRST_BUF = 0,
203 PDC_SECOND_BUF,
204 };
205
206 struct atmel_mci_caps {
207 bool has_dma_conf_reg;
208 bool has_pdc;
209 bool has_cfg_reg;
210 bool has_cstor_reg;
211 bool has_highspeed;
212 bool has_rwproof;
213 bool has_odd_clk_div;
214 bool has_bad_data_ordering;
215 bool need_reset_after_xfer;
216 bool need_blksz_mul_4;
217 bool need_notbusy_for_read_ops;
218 };
219
220 struct atmel_mci_dma {
221 struct dma_chan *chan;
222 struct dma_async_tx_descriptor *data_desc;
223 };
224
225 /**
226 * struct atmel_mci - MMC controller state shared between all slots
227 * @lock: Spinlock protecting the queue and associated data.
228 * @regs: Pointer to MMIO registers.
229 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
230 * @pio_offset: Offset into the current scatterlist entry.
231 * @buffer: Buffer used if we don't have the r/w proof capability. We
232 * don't have the time to switch pdc buffers so we have to use only
233 * one buffer for the full transaction.
234 * @buf_size: size of the buffer.
235 * @phys_buf_addr: buffer address needed for pdc.
236 * @cur_slot: The slot which is currently using the controller.
237 * @mrq: The request currently being processed on @cur_slot,
238 * or NULL if the controller is idle.
239 * @cmd: The command currently being sent to the card, or NULL.
240 * @data: The data currently being transferred, or NULL if no data
241 * transfer is in progress.
242 * @data_size: just data->blocks * data->blksz.
243 * @dma: DMA client state.
244 * @data_chan: DMA channel being used for the current data transfer.
245 * @cmd_status: Snapshot of SR taken upon completion of the current
246 * command. Only valid when EVENT_CMD_COMPLETE is pending.
247 * @data_status: Snapshot of SR taken upon completion of the current
248 * data transfer. Only valid when EVENT_DATA_COMPLETE or
249 * EVENT_DATA_ERROR is pending.
250 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
251 * to be sent.
252 * @tasklet: Tasklet running the request state machine.
253 * @pending_events: Bitmask of events flagged by the interrupt handler
254 * to be processed by the tasklet.
255 * @completed_events: Bitmask of events which the state machine has
256 * processed.
257 * @state: Tasklet state.
258 * @queue: List of slots waiting for access to the controller.
259 * @need_clock_update: Update the clock rate before the next request.
260 * @need_reset: Reset controller before next request.
261 * @timer: Timer to balance the data timeout error flag which cannot rise.
262 * @mode_reg: Value of the MR register.
263 * @cfg_reg: Value of the CFG register.
264 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
265 * rate and timeout calculations.
266 * @mapbase: Physical address of the MMIO registers.
267 * @mck: The peripheral bus clock hooked up to the MMC controller.
268 * @pdev: Platform device associated with the MMC controller.
269 * @slot: Slots sharing this MMC controller.
270 * @caps: MCI capabilities depending on MCI version.
271 * @prepare_data: function to setup MCI before data transfer which
272 * depends on MCI capabilities.
273 * @submit_data: function to start data transfer which depends on MCI
274 * capabilities.
275 * @stop_transfer: function to stop data transfer which depends on MCI
276 * capabilities.
277 *
278 * Locking
279 * =======
280 *
281 * @lock is a softirq-safe spinlock protecting @queue as well as
282 * @cur_slot, @mrq and @state. These must always be updated
283 * at the same time while holding @lock.
284 *
285 * @lock also protects mode_reg and need_clock_update since these are
286 * used to synchronize mode register updates with the queue
287 * processing.
288 *
289 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
290 * and must always be written at the same time as the slot is added to
291 * @queue.
292 *
293 * @pending_events and @completed_events are accessed using atomic bit
294 * operations, so they don't need any locking.
295 *
296 * None of the fields touched by the interrupt handler need any
297 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
298 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
299 * interrupts must be disabled and @data_status updated with a
300 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
301 * CMDRDY interrupt must be disabled and @cmd_status updated with a
302 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
303 * bytes_xfered field of @data must be written. This is ensured by
304 * using barriers.
305 */
306 struct atmel_mci {
307 spinlock_t lock;
308 void __iomem *regs;
309
310 struct scatterlist *sg;
311 unsigned int sg_len;
312 unsigned int pio_offset;
313 unsigned int *buffer;
314 unsigned int buf_size;
315 dma_addr_t buf_phys_addr;
316
317 struct atmel_mci_slot *cur_slot;
318 struct mmc_request *mrq;
319 struct mmc_command *cmd;
320 struct mmc_data *data;
321 unsigned int data_size;
322
323 struct atmel_mci_dma dma;
324 struct dma_chan *data_chan;
325 struct dma_slave_config dma_conf;
326
327 u32 cmd_status;
328 u32 data_status;
329 u32 stop_cmdr;
330
331 struct tasklet_struct tasklet;
332 unsigned long pending_events;
333 unsigned long completed_events;
334 enum atmel_mci_state state;
335 struct list_head queue;
336
337 bool need_clock_update;
338 bool need_reset;
339 struct timer_list timer;
340 u32 mode_reg;
341 u32 cfg_reg;
342 unsigned long bus_hz;
343 unsigned long mapbase;
344 struct clk *mck;
345 struct platform_device *pdev;
346
347 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
348
349 struct atmel_mci_caps caps;
350
351 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
352 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
353 void (*stop_transfer)(struct atmel_mci *host);
354 };
355
356 /**
357 * struct atmel_mci_slot - MMC slot state
358 * @mmc: The mmc_host representing this slot.
359 * @host: The MMC controller this slot is using.
360 * @sdc_reg: Value of SDCR to be written before using this slot.
361 * @sdio_irq: SDIO irq mask for this slot.
362 * @mrq: mmc_request currently being processed or waiting to be
363 * processed, or NULL when the slot is idle.
364 * @queue_node: List node for placing this node in the @queue list of
365 * &struct atmel_mci.
366 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
367 * @flags: Random state bits associated with the slot.
368 * @detect_pin: GPIO pin used for card detection, or negative if not
369 * available.
370 * @wp_pin: GPIO pin used for card write protect sending, or negative
371 * if not available.
372 * @detect_is_active_high: The state of the detect pin when it is active.
373 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
374 */
375 struct atmel_mci_slot {
376 struct mmc_host *mmc;
377 struct atmel_mci *host;
378
379 u32 sdc_reg;
380 u32 sdio_irq;
381
382 struct mmc_request *mrq;
383 struct list_head queue_node;
384
385 unsigned int clock;
386 unsigned long flags;
387 #define ATMCI_CARD_PRESENT 0
388 #define ATMCI_CARD_NEED_INIT 1
389 #define ATMCI_SHUTDOWN 2
390
391 int detect_pin;
392 int wp_pin;
393 bool detect_is_active_high;
394
395 struct timer_list detect_timer;
396 };
397
398 #define atmci_test_and_clear_pending(host, event) \
399 test_and_clear_bit(event, &host->pending_events)
400 #define atmci_set_completed(host, event) \
401 set_bit(event, &host->completed_events)
402 #define atmci_set_pending(host, event) \
403 set_bit(event, &host->pending_events)
404
405 /*
406 * The debugfs stuff below is mostly optimized away when
407 * CONFIG_DEBUG_FS is not set.
408 */
409 static int atmci_req_show(struct seq_file *s, void *v)
410 {
411 struct atmel_mci_slot *slot = s->private;
412 struct mmc_request *mrq;
413 struct mmc_command *cmd;
414 struct mmc_command *stop;
415 struct mmc_data *data;
416
417 /* Make sure we get a consistent snapshot */
418 spin_lock_bh(&slot->host->lock);
419 mrq = slot->mrq;
420
421 if (mrq) {
422 cmd = mrq->cmd;
423 data = mrq->data;
424 stop = mrq->stop;
425
426 if (cmd)
427 seq_printf(s,
428 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
429 cmd->opcode, cmd->arg, cmd->flags,
430 cmd->resp[0], cmd->resp[1], cmd->resp[2],
431 cmd->resp[3], cmd->error);
432 if (data)
433 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
434 data->bytes_xfered, data->blocks,
435 data->blksz, data->flags, data->error);
436 if (stop)
437 seq_printf(s,
438 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
439 stop->opcode, stop->arg, stop->flags,
440 stop->resp[0], stop->resp[1], stop->resp[2],
441 stop->resp[3], stop->error);
442 }
443
444 spin_unlock_bh(&slot->host->lock);
445
446 return 0;
447 }
448
449 static int atmci_req_open(struct inode *inode, struct file *file)
450 {
451 return single_open(file, atmci_req_show, inode->i_private);
452 }
453
454 static const struct file_operations atmci_req_fops = {
455 .owner = THIS_MODULE,
456 .open = atmci_req_open,
457 .read = seq_read,
458 .llseek = seq_lseek,
459 .release = single_release,
460 };
461
462 static void atmci_show_status_reg(struct seq_file *s,
463 const char *regname, u32 value)
464 {
465 static const char *sr_bit[] = {
466 [0] = "CMDRDY",
467 [1] = "RXRDY",
468 [2] = "TXRDY",
469 [3] = "BLKE",
470 [4] = "DTIP",
471 [5] = "NOTBUSY",
472 [6] = "ENDRX",
473 [7] = "ENDTX",
474 [8] = "SDIOIRQA",
475 [9] = "SDIOIRQB",
476 [12] = "SDIOWAIT",
477 [14] = "RXBUFF",
478 [15] = "TXBUFE",
479 [16] = "RINDE",
480 [17] = "RDIRE",
481 [18] = "RCRCE",
482 [19] = "RENDE",
483 [20] = "RTOE",
484 [21] = "DCRCE",
485 [22] = "DTOE",
486 [23] = "CSTOE",
487 [24] = "BLKOVRE",
488 [25] = "DMADONE",
489 [26] = "FIFOEMPTY",
490 [27] = "XFRDONE",
491 [30] = "OVRE",
492 [31] = "UNRE",
493 };
494 unsigned int i;
495
496 seq_printf(s, "%s:\t0x%08x", regname, value);
497 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
498 if (value & (1 << i)) {
499 if (sr_bit[i])
500 seq_printf(s, " %s", sr_bit[i]);
501 else
502 seq_puts(s, " UNKNOWN");
503 }
504 }
505 seq_putc(s, '\n');
506 }
507
508 static int atmci_regs_show(struct seq_file *s, void *v)
509 {
510 struct atmel_mci *host = s->private;
511 u32 *buf;
512 int ret = 0;
513
514
515 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
516 if (!buf)
517 return -ENOMEM;
518
519 pm_runtime_get_sync(&host->pdev->dev);
520
521 /*
522 * Grab a more or less consistent snapshot. Note that we're
523 * not disabling interrupts, so IMR and SR may not be
524 * consistent.
525 */
526 spin_lock_bh(&host->lock);
527 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
528 spin_unlock_bh(&host->lock);
529
530 pm_runtime_mark_last_busy(&host->pdev->dev);
531 pm_runtime_put_autosuspend(&host->pdev->dev);
532
533 seq_printf(s, "MR:\t0x%08x%s%s ",
534 buf[ATMCI_MR / 4],
535 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
536 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
537 if (host->caps.has_odd_clk_div)
538 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
539 ((buf[ATMCI_MR / 4] & 0xff) << 1)
540 | ((buf[ATMCI_MR / 4] >> 16) & 1));
541 else
542 seq_printf(s, "CLKDIV=%u\n",
543 (buf[ATMCI_MR / 4] & 0xff));
544 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
545 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
546 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
547 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
548 buf[ATMCI_BLKR / 4],
549 buf[ATMCI_BLKR / 4] & 0xffff,
550 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
551 if (host->caps.has_cstor_reg)
552 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
553
554 /* Don't read RSPR and RDR; it will consume the data there */
555
556 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
557 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
558
559 if (host->caps.has_dma_conf_reg) {
560 u32 val;
561
562 val = buf[ATMCI_DMA / 4];
563 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
564 val, val & 3,
565 ((val >> 4) & 3) ?
566 1 << (((val >> 4) & 3) + 1) : 1,
567 val & ATMCI_DMAEN ? " DMAEN" : "");
568 }
569 if (host->caps.has_cfg_reg) {
570 u32 val;
571
572 val = buf[ATMCI_CFG / 4];
573 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
574 val,
575 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
576 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
577 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
578 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
579 }
580
581 kfree(buf);
582
583 return ret;
584 }
585
586 static int atmci_regs_open(struct inode *inode, struct file *file)
587 {
588 return single_open(file, atmci_regs_show, inode->i_private);
589 }
590
591 static const struct file_operations atmci_regs_fops = {
592 .owner = THIS_MODULE,
593 .open = atmci_regs_open,
594 .read = seq_read,
595 .llseek = seq_lseek,
596 .release = single_release,
597 };
598
599 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
600 {
601 struct mmc_host *mmc = slot->mmc;
602 struct atmel_mci *host = slot->host;
603 struct dentry *root;
604 struct dentry *node;
605
606 root = mmc->debugfs_root;
607 if (!root)
608 return;
609
610 node = debugfs_create_file("regs", S_IRUSR, root, host,
611 &atmci_regs_fops);
612 if (IS_ERR(node))
613 return;
614 if (!node)
615 goto err;
616
617 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
618 if (!node)
619 goto err;
620
621 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
622 if (!node)
623 goto err;
624
625 node = debugfs_create_x32("pending_events", S_IRUSR, root,
626 (u32 *)&host->pending_events);
627 if (!node)
628 goto err;
629
630 node = debugfs_create_x32("completed_events", S_IRUSR, root,
631 (u32 *)&host->completed_events);
632 if (!node)
633 goto err;
634
635 return;
636
637 err:
638 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
639 }
640
641 #if defined(CONFIG_OF)
642 static const struct of_device_id atmci_dt_ids[] = {
643 { .compatible = "atmel,hsmci" },
644 { /* sentinel */ }
645 };
646
647 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
648
649 static struct mci_platform_data*
650 atmci_of_init(struct platform_device *pdev)
651 {
652 struct device_node *np = pdev->dev.of_node;
653 struct device_node *cnp;
654 struct mci_platform_data *pdata;
655 u32 slot_id;
656
657 if (!np) {
658 dev_err(&pdev->dev, "device node not found\n");
659 return ERR_PTR(-EINVAL);
660 }
661
662 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
663 if (!pdata)
664 return ERR_PTR(-ENOMEM);
665
666 for_each_child_of_node(np, cnp) {
667 if (of_property_read_u32(cnp, "reg", &slot_id)) {
668 dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
669 cnp);
670 continue;
671 }
672
673 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
674 dev_warn(&pdev->dev, "can't have more than %d slots\n",
675 ATMCI_MAX_NR_SLOTS);
676 of_node_put(cnp);
677 break;
678 }
679
680 if (of_property_read_u32(cnp, "bus-width",
681 &pdata->slot[slot_id].bus_width))
682 pdata->slot[slot_id].bus_width = 1;
683
684 pdata->slot[slot_id].detect_pin =
685 of_get_named_gpio(cnp, "cd-gpios", 0);
686
687 pdata->slot[slot_id].detect_is_active_high =
688 of_property_read_bool(cnp, "cd-inverted");
689
690 pdata->slot[slot_id].non_removable =
691 of_property_read_bool(cnp, "non-removable");
692
693 pdata->slot[slot_id].wp_pin =
694 of_get_named_gpio(cnp, "wp-gpios", 0);
695 }
696
697 return pdata;
698 }
699 #else /* CONFIG_OF */
700 static inline struct mci_platform_data*
701 atmci_of_init(struct platform_device *dev)
702 {
703 return ERR_PTR(-EINVAL);
704 }
705 #endif
706
707 static inline unsigned int atmci_get_version(struct atmel_mci *host)
708 {
709 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
710 }
711
712 /*
713 * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
714 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
715 * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
716 * 8 -> 3, 16 -> 4.
717 *
718 * This can be done by finding most significant bit set.
719 */
720 static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
721 unsigned int maxburst)
722 {
723 unsigned int version = atmci_get_version(host);
724 unsigned int offset = 2;
725
726 if (version >= 0x600)
727 offset = 1;
728
729 if (maxburst > 1)
730 return fls(maxburst) - offset;
731 else
732 return 0;
733 }
734
735 static void atmci_timeout_timer(struct timer_list *t)
736 {
737 struct atmel_mci *host;
738
739 host = from_timer(host, t, timer);
740
741 dev_dbg(&host->pdev->dev, "software timeout\n");
742
743 if (host->mrq->cmd->data) {
744 host->mrq->cmd->data->error = -ETIMEDOUT;
745 host->data = NULL;
746 /*
747 * With some SDIO modules, sometimes DMA transfer hangs. If
748 * stop_transfer() is not called then the DMA request is not
749 * removed, following ones are queued and never computed.
750 */
751 if (host->state == STATE_DATA_XFER)
752 host->stop_transfer(host);
753 } else {
754 host->mrq->cmd->error = -ETIMEDOUT;
755 host->cmd = NULL;
756 }
757 host->need_reset = 1;
758 host->state = STATE_END_REQUEST;
759 smp_wmb();
760 tasklet_schedule(&host->tasklet);
761 }
762
763 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
764 unsigned int ns)
765 {
766 /*
767 * It is easier here to use us instead of ns for the timeout,
768 * it prevents from overflows during calculation.
769 */
770 unsigned int us = DIV_ROUND_UP(ns, 1000);
771
772 /* Maximum clock frequency is host->bus_hz/2 */
773 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
774 }
775
776 static void atmci_set_timeout(struct atmel_mci *host,
777 struct atmel_mci_slot *slot, struct mmc_data *data)
778 {
779 static unsigned dtomul_to_shift[] = {
780 0, 4, 7, 8, 10, 12, 16, 20
781 };
782 unsigned timeout;
783 unsigned dtocyc;
784 unsigned dtomul;
785
786 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
787 + data->timeout_clks;
788
789 for (dtomul = 0; dtomul < 8; dtomul++) {
790 unsigned shift = dtomul_to_shift[dtomul];
791 dtocyc = (timeout + (1 << shift) - 1) >> shift;
792 if (dtocyc < 15)
793 break;
794 }
795
796 if (dtomul >= 8) {
797 dtomul = 7;
798 dtocyc = 15;
799 }
800
801 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
802 dtocyc << dtomul_to_shift[dtomul]);
803 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
804 }
805
806 /*
807 * Return mask with command flags to be enabled for this command.
808 */
809 static u32 atmci_prepare_command(struct mmc_host *mmc,
810 struct mmc_command *cmd)
811 {
812 struct mmc_data *data;
813 u32 cmdr;
814
815 cmd->error = -EINPROGRESS;
816
817 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
818
819 if (cmd->flags & MMC_RSP_PRESENT) {
820 if (cmd->flags & MMC_RSP_136)
821 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
822 else
823 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
824 }
825
826 /*
827 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
828 * it's too difficult to determine whether this is an ACMD or
829 * not. Better make it 64.
830 */
831 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
832
833 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
834 cmdr |= ATMCI_CMDR_OPDCMD;
835
836 data = cmd->data;
837 if (data) {
838 cmdr |= ATMCI_CMDR_START_XFER;
839
840 if (cmd->opcode == SD_IO_RW_EXTENDED) {
841 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
842 } else {
843 if (data->blocks > 1)
844 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
845 else
846 cmdr |= ATMCI_CMDR_BLOCK;
847 }
848
849 if (data->flags & MMC_DATA_READ)
850 cmdr |= ATMCI_CMDR_TRDIR_READ;
851 }
852
853 return cmdr;
854 }
855
856 static void atmci_send_command(struct atmel_mci *host,
857 struct mmc_command *cmd, u32 cmd_flags)
858 {
859 WARN_ON(host->cmd);
860 host->cmd = cmd;
861
862 dev_vdbg(&host->pdev->dev,
863 "start command: ARGR=0x%08x CMDR=0x%08x\n",
864 cmd->arg, cmd_flags);
865
866 atmci_writel(host, ATMCI_ARGR, cmd->arg);
867 atmci_writel(host, ATMCI_CMDR, cmd_flags);
868 }
869
870 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
871 {
872 dev_dbg(&host->pdev->dev, "send stop command\n");
873 atmci_send_command(host, data->stop, host->stop_cmdr);
874 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
875 }
876
877 /*
878 * Configure given PDC buffer taking care of alignement issues.
879 * Update host->data_size and host->sg.
880 */
881 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
882 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
883 {
884 u32 pointer_reg, counter_reg;
885 unsigned int buf_size;
886
887 if (dir == XFER_RECEIVE) {
888 pointer_reg = ATMEL_PDC_RPR;
889 counter_reg = ATMEL_PDC_RCR;
890 } else {
891 pointer_reg = ATMEL_PDC_TPR;
892 counter_reg = ATMEL_PDC_TCR;
893 }
894
895 if (buf_nb == PDC_SECOND_BUF) {
896 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
897 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
898 }
899
900 if (!host->caps.has_rwproof) {
901 buf_size = host->buf_size;
902 atmci_writel(host, pointer_reg, host->buf_phys_addr);
903 } else {
904 buf_size = sg_dma_len(host->sg);
905 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
906 }
907
908 if (host->data_size <= buf_size) {
909 if (host->data_size & 0x3) {
910 /* If size is different from modulo 4, transfer bytes */
911 atmci_writel(host, counter_reg, host->data_size);
912 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
913 } else {
914 /* Else transfer 32-bits words */
915 atmci_writel(host, counter_reg, host->data_size / 4);
916 }
917 host->data_size = 0;
918 } else {
919 /* We assume the size of a page is 32-bits aligned */
920 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
921 host->data_size -= sg_dma_len(host->sg);
922 if (host->data_size)
923 host->sg = sg_next(host->sg);
924 }
925 }
926
927 /*
928 * Configure PDC buffer according to the data size ie configuring one or two
929 * buffers. Don't use this function if you want to configure only the second
930 * buffer. In this case, use atmci_pdc_set_single_buf.
931 */
932 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
933 {
934 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
935 if (host->data_size)
936 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
937 }
938
939 /*
940 * Unmap sg lists, called when transfer is finished.
941 */
942 static void atmci_pdc_cleanup(struct atmel_mci *host)
943 {
944 struct mmc_data *data = host->data;
945
946 if (data)
947 dma_unmap_sg(&host->pdev->dev,
948 data->sg, data->sg_len,
949 mmc_get_dma_dir(data));
950 }
951
952 /*
953 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
954 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
955 * interrupt needed for both transfer directions.
956 */
957 static void atmci_pdc_complete(struct atmel_mci *host)
958 {
959 int transfer_size = host->data->blocks * host->data->blksz;
960 int i;
961
962 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
963
964 if ((!host->caps.has_rwproof)
965 && (host->data->flags & MMC_DATA_READ)) {
966 if (host->caps.has_bad_data_ordering)
967 for (i = 0; i < transfer_size; i++)
968 host->buffer[i] = swab32(host->buffer[i]);
969 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
970 host->buffer, transfer_size);
971 }
972
973 atmci_pdc_cleanup(host);
974
975 dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
976 atmci_set_pending(host, EVENT_XFER_COMPLETE);
977 tasklet_schedule(&host->tasklet);
978 }
979
980 static void atmci_dma_cleanup(struct atmel_mci *host)
981 {
982 struct mmc_data *data = host->data;
983
984 if (data)
985 dma_unmap_sg(host->dma.chan->device->dev,
986 data->sg, data->sg_len,
987 mmc_get_dma_dir(data));
988 }
989
990 /*
991 * This function is called by the DMA driver from tasklet context.
992 */
993 static void atmci_dma_complete(void *arg)
994 {
995 struct atmel_mci *host = arg;
996 struct mmc_data *data = host->data;
997
998 dev_vdbg(&host->pdev->dev, "DMA complete\n");
999
1000 if (host->caps.has_dma_conf_reg)
1001 /* Disable DMA hardware handshaking on MCI */
1002 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
1003
1004 atmci_dma_cleanup(host);
1005
1006 /*
1007 * If the card was removed, data will be NULL. No point trying
1008 * to send the stop command or waiting for NBUSY in this case.
1009 */
1010 if (data) {
1011 dev_dbg(&host->pdev->dev,
1012 "(%s) set pending xfer complete\n", __func__);
1013 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1014 tasklet_schedule(&host->tasklet);
1015
1016 /*
1017 * Regardless of what the documentation says, we have
1018 * to wait for NOTBUSY even after block read
1019 * operations.
1020 *
1021 * When the DMA transfer is complete, the controller
1022 * may still be reading the CRC from the card, i.e.
1023 * the data transfer is still in progress and we
1024 * haven't seen all the potential error bits yet.
1025 *
1026 * The interrupt handler will schedule a different
1027 * tasklet to finish things up when the data transfer
1028 * is completely done.
1029 *
1030 * We may not complete the mmc request here anyway
1031 * because the mmc layer may call back and cause us to
1032 * violate the "don't submit new operations from the
1033 * completion callback" rule of the dma engine
1034 * framework.
1035 */
1036 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1037 }
1038 }
1039
1040 /*
1041 * Returns a mask of interrupt flags to be enabled after the whole
1042 * request has been prepared.
1043 */
1044 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1045 {
1046 u32 iflags;
1047
1048 data->error = -EINPROGRESS;
1049
1050 host->sg = data->sg;
1051 host->sg_len = data->sg_len;
1052 host->data = data;
1053 host->data_chan = NULL;
1054
1055 iflags = ATMCI_DATA_ERROR_FLAGS;
1056
1057 /*
1058 * Errata: MMC data write operation with less than 12
1059 * bytes is impossible.
1060 *
1061 * Errata: MCI Transmit Data Register (TDR) FIFO
1062 * corruption when length is not multiple of 4.
1063 */
1064 if (data->blocks * data->blksz < 12
1065 || (data->blocks * data->blksz) & 3)
1066 host->need_reset = true;
1067
1068 host->pio_offset = 0;
1069 if (data->flags & MMC_DATA_READ)
1070 iflags |= ATMCI_RXRDY;
1071 else
1072 iflags |= ATMCI_TXRDY;
1073
1074 return iflags;
1075 }
1076
1077 /*
1078 * Set interrupt flags and set block length into the MCI mode register even
1079 * if this value is also accessible in the MCI block register. It seems to be
1080 * necessary before the High Speed MCI version. It also map sg and configure
1081 * PDC registers.
1082 */
1083 static u32
1084 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1085 {
1086 u32 iflags, tmp;
1087 int i;
1088
1089 data->error = -EINPROGRESS;
1090
1091 host->data = data;
1092 host->sg = data->sg;
1093 iflags = ATMCI_DATA_ERROR_FLAGS;
1094
1095 /* Enable pdc mode */
1096 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1097
1098 if (data->flags & MMC_DATA_READ)
1099 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1100 else
1101 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1102
1103 /* Set BLKLEN */
1104 tmp = atmci_readl(host, ATMCI_MR);
1105 tmp &= 0x0000ffff;
1106 tmp |= ATMCI_BLKLEN(data->blksz);
1107 atmci_writel(host, ATMCI_MR, tmp);
1108
1109 /* Configure PDC */
1110 host->data_size = data->blocks * data->blksz;
1111 dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
1112 mmc_get_dma_dir(data));
1113
1114 if ((!host->caps.has_rwproof)
1115 && (host->data->flags & MMC_DATA_WRITE)) {
1116 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1117 host->buffer, host->data_size);
1118 if (host->caps.has_bad_data_ordering)
1119 for (i = 0; i < host->data_size; i++)
1120 host->buffer[i] = swab32(host->buffer[i]);
1121 }
1122
1123 if (host->data_size)
1124 atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
1125 XFER_RECEIVE : XFER_TRANSMIT);
1126 return iflags;
1127 }
1128
1129 static u32
1130 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1131 {
1132 struct dma_chan *chan;
1133 struct dma_async_tx_descriptor *desc;
1134 struct scatterlist *sg;
1135 unsigned int i;
1136 enum dma_transfer_direction slave_dirn;
1137 unsigned int sglen;
1138 u32 maxburst;
1139 u32 iflags;
1140
1141 data->error = -EINPROGRESS;
1142
1143 WARN_ON(host->data);
1144 host->sg = NULL;
1145 host->data = data;
1146
1147 iflags = ATMCI_DATA_ERROR_FLAGS;
1148
1149 /*
1150 * We don't do DMA on "complex" transfers, i.e. with
1151 * non-word-aligned buffers or lengths. Also, we don't bother
1152 * with all the DMA setup overhead for short transfers.
1153 */
1154 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1155 return atmci_prepare_data(host, data);
1156 if (data->blksz & 3)
1157 return atmci_prepare_data(host, data);
1158
1159 for_each_sg(data->sg, sg, data->sg_len, i) {
1160 if (sg->offset & 3 || sg->length & 3)
1161 return atmci_prepare_data(host, data);
1162 }
1163
1164 /* If we don't have a channel, we can't do DMA */
1165 chan = host->dma.chan;
1166 if (chan)
1167 host->data_chan = chan;
1168
1169 if (!chan)
1170 return -ENODEV;
1171
1172 if (data->flags & MMC_DATA_READ) {
1173 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1174 maxburst = atmci_convert_chksize(host,
1175 host->dma_conf.src_maxburst);
1176 } else {
1177 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1178 maxburst = atmci_convert_chksize(host,
1179 host->dma_conf.dst_maxburst);
1180 }
1181
1182 if (host->caps.has_dma_conf_reg)
1183 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1184 ATMCI_DMAEN);
1185
1186 sglen = dma_map_sg(chan->device->dev, data->sg,
1187 data->sg_len, mmc_get_dma_dir(data));
1188
1189 dmaengine_slave_config(chan, &host->dma_conf);
1190 desc = dmaengine_prep_slave_sg(chan,
1191 data->sg, sglen, slave_dirn,
1192 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1193 if (!desc)
1194 goto unmap_exit;
1195
1196 host->dma.data_desc = desc;
1197 desc->callback = atmci_dma_complete;
1198 desc->callback_param = host;
1199
1200 return iflags;
1201 unmap_exit:
1202 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
1203 mmc_get_dma_dir(data));
1204 return -ENOMEM;
1205 }
1206
1207 static void
1208 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1209 {
1210 return;
1211 }
1212
1213 /*
1214 * Start PDC according to transfer direction.
1215 */
1216 static void
1217 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1218 {
1219 if (data->flags & MMC_DATA_READ)
1220 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1221 else
1222 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1223 }
1224
1225 static void
1226 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1227 {
1228 struct dma_chan *chan = host->data_chan;
1229 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1230
1231 if (chan) {
1232 dmaengine_submit(desc);
1233 dma_async_issue_pending(chan);
1234 }
1235 }
1236
1237 static void atmci_stop_transfer(struct atmel_mci *host)
1238 {
1239 dev_dbg(&host->pdev->dev,
1240 "(%s) set pending xfer complete\n", __func__);
1241 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1242 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1243 }
1244
1245 /*
1246 * Stop data transfer because error(s) occurred.
1247 */
1248 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1249 {
1250 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1251 }
1252
1253 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1254 {
1255 struct dma_chan *chan = host->data_chan;
1256
1257 if (chan) {
1258 dmaengine_terminate_all(chan);
1259 atmci_dma_cleanup(host);
1260 } else {
1261 /* Data transfer was stopped by the interrupt handler */
1262 dev_dbg(&host->pdev->dev,
1263 "(%s) set pending xfer complete\n", __func__);
1264 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1265 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1266 }
1267 }
1268
1269 /*
1270 * Start a request: prepare data if needed, prepare the command and activate
1271 * interrupts.
1272 */
1273 static void atmci_start_request(struct atmel_mci *host,
1274 struct atmel_mci_slot *slot)
1275 {
1276 struct mmc_request *mrq;
1277 struct mmc_command *cmd;
1278 struct mmc_data *data;
1279 u32 iflags;
1280 u32 cmdflags;
1281
1282 mrq = slot->mrq;
1283 host->cur_slot = slot;
1284 host->mrq = mrq;
1285
1286 host->pending_events = 0;
1287 host->completed_events = 0;
1288 host->cmd_status = 0;
1289 host->data_status = 0;
1290
1291 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1292
1293 if (host->need_reset || host->caps.need_reset_after_xfer) {
1294 iflags = atmci_readl(host, ATMCI_IMR);
1295 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1296 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1297 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1298 atmci_writel(host, ATMCI_MR, host->mode_reg);
1299 if (host->caps.has_cfg_reg)
1300 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1301 atmci_writel(host, ATMCI_IER, iflags);
1302 host->need_reset = false;
1303 }
1304 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1305
1306 iflags = atmci_readl(host, ATMCI_IMR);
1307 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1308 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1309 iflags);
1310
1311 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1312 /* Send init sequence (74 clock cycles) */
1313 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1314 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1315 cpu_relax();
1316 }
1317 iflags = 0;
1318 data = mrq->data;
1319 if (data) {
1320 atmci_set_timeout(host, slot, data);
1321
1322 /* Must set block count/size before sending command */
1323 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1324 | ATMCI_BLKLEN(data->blksz));
1325 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1326 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1327
1328 iflags |= host->prepare_data(host, data);
1329 }
1330
1331 iflags |= ATMCI_CMDRDY;
1332 cmd = mrq->cmd;
1333 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1334
1335 /*
1336 * DMA transfer should be started before sending the command to avoid
1337 * unexpected errors especially for read operations in SDIO mode.
1338 * Unfortunately, in PDC mode, command has to be sent before starting
1339 * the transfer.
1340 */
1341 if (host->submit_data != &atmci_submit_data_dma)
1342 atmci_send_command(host, cmd, cmdflags);
1343
1344 if (data)
1345 host->submit_data(host, data);
1346
1347 if (host->submit_data == &atmci_submit_data_dma)
1348 atmci_send_command(host, cmd, cmdflags);
1349
1350 if (mrq->stop) {
1351 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1352 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1353 if (!(data->flags & MMC_DATA_WRITE))
1354 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1355 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1356 }
1357
1358 /*
1359 * We could have enabled interrupts earlier, but I suspect
1360 * that would open up a nice can of interesting race
1361 * conditions (e.g. command and data complete, but stop not
1362 * prepared yet.)
1363 */
1364 atmci_writel(host, ATMCI_IER, iflags);
1365
1366 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
1367 }
1368
1369 static void atmci_queue_request(struct atmel_mci *host,
1370 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1371 {
1372 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1373 host->state);
1374
1375 spin_lock_bh(&host->lock);
1376 slot->mrq = mrq;
1377 if (host->state == STATE_IDLE) {
1378 host->state = STATE_SENDING_CMD;
1379 atmci_start_request(host, slot);
1380 } else {
1381 dev_dbg(&host->pdev->dev, "queue request\n");
1382 list_add_tail(&slot->queue_node, &host->queue);
1383 }
1384 spin_unlock_bh(&host->lock);
1385 }
1386
1387 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1388 {
1389 struct atmel_mci_slot *slot = mmc_priv(mmc);
1390 struct atmel_mci *host = slot->host;
1391 struct mmc_data *data;
1392
1393 WARN_ON(slot->mrq);
1394 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1395
1396 /*
1397 * We may "know" the card is gone even though there's still an
1398 * electrical connection. If so, we really need to communicate
1399 * this to the MMC core since there won't be any more
1400 * interrupts as the card is completely removed. Otherwise,
1401 * the MMC core might believe the card is still there even
1402 * though the card was just removed very slowly.
1403 */
1404 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1405 mrq->cmd->error = -ENOMEDIUM;
1406 mmc_request_done(mmc, mrq);
1407 return;
1408 }
1409
1410 /* We don't support multiple blocks of weird lengths. */
1411 data = mrq->data;
1412 if (data && data->blocks > 1 && data->blksz & 3) {
1413 mrq->cmd->error = -EINVAL;
1414 mmc_request_done(mmc, mrq);
1415 }
1416
1417 atmci_queue_request(host, slot, mrq);
1418 }
1419
1420 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1421 {
1422 struct atmel_mci_slot *slot = mmc_priv(mmc);
1423 struct atmel_mci *host = slot->host;
1424 unsigned int i;
1425
1426 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1427 switch (ios->bus_width) {
1428 case MMC_BUS_WIDTH_1:
1429 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1430 break;
1431 case MMC_BUS_WIDTH_4:
1432 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1433 break;
1434 }
1435
1436 if (ios->clock) {
1437 unsigned int clock_min = ~0U;
1438 int clkdiv;
1439
1440 spin_lock_bh(&host->lock);
1441 if (!host->mode_reg) {
1442 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1443 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1444 if (host->caps.has_cfg_reg)
1445 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1446 }
1447
1448 /*
1449 * Use mirror of ios->clock to prevent race with mmc
1450 * core ios update when finding the minimum.
1451 */
1452 slot->clock = ios->clock;
1453 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1454 if (host->slot[i] && host->slot[i]->clock
1455 && host->slot[i]->clock < clock_min)
1456 clock_min = host->slot[i]->clock;
1457 }
1458
1459 /* Calculate clock divider */
1460 if (host->caps.has_odd_clk_div) {
1461 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1462 if (clkdiv < 0) {
1463 dev_warn(&mmc->class_dev,
1464 "clock %u too fast; using %lu\n",
1465 clock_min, host->bus_hz / 2);
1466 clkdiv = 0;
1467 } else if (clkdiv > 511) {
1468 dev_warn(&mmc->class_dev,
1469 "clock %u too slow; using %lu\n",
1470 clock_min, host->bus_hz / (511 + 2));
1471 clkdiv = 511;
1472 }
1473 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1474 | ATMCI_MR_CLKODD(clkdiv & 1);
1475 } else {
1476 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1477 if (clkdiv > 255) {
1478 dev_warn(&mmc->class_dev,
1479 "clock %u too slow; using %lu\n",
1480 clock_min, host->bus_hz / (2 * 256));
1481 clkdiv = 255;
1482 }
1483 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1484 }
1485
1486 /*
1487 * WRPROOF and RDPROOF prevent overruns/underruns by
1488 * stopping the clock when the FIFO is full/empty.
1489 * This state is not expected to last for long.
1490 */
1491 if (host->caps.has_rwproof)
1492 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1493
1494 if (host->caps.has_cfg_reg) {
1495 /* setup High Speed mode in relation with card capacity */
1496 if (ios->timing == MMC_TIMING_SD_HS)
1497 host->cfg_reg |= ATMCI_CFG_HSMODE;
1498 else
1499 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1500 }
1501
1502 if (list_empty(&host->queue)) {
1503 atmci_writel(host, ATMCI_MR, host->mode_reg);
1504 if (host->caps.has_cfg_reg)
1505 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1506 } else {
1507 host->need_clock_update = true;
1508 }
1509
1510 spin_unlock_bh(&host->lock);
1511 } else {
1512 bool any_slot_active = false;
1513
1514 spin_lock_bh(&host->lock);
1515 slot->clock = 0;
1516 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1517 if (host->slot[i] && host->slot[i]->clock) {
1518 any_slot_active = true;
1519 break;
1520 }
1521 }
1522 if (!any_slot_active) {
1523 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1524 if (host->mode_reg) {
1525 atmci_readl(host, ATMCI_MR);
1526 }
1527 host->mode_reg = 0;
1528 }
1529 spin_unlock_bh(&host->lock);
1530 }
1531
1532 switch (ios->power_mode) {
1533 case MMC_POWER_OFF:
1534 if (!IS_ERR(mmc->supply.vmmc))
1535 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1536 break;
1537 case MMC_POWER_UP:
1538 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1539 if (!IS_ERR(mmc->supply.vmmc))
1540 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1541 break;
1542 default:
1543 break;
1544 }
1545 }
1546
1547 static int atmci_get_ro(struct mmc_host *mmc)
1548 {
1549 int read_only = -ENOSYS;
1550 struct atmel_mci_slot *slot = mmc_priv(mmc);
1551
1552 if (gpio_is_valid(slot->wp_pin)) {
1553 read_only = gpio_get_value(slot->wp_pin);
1554 dev_dbg(&mmc->class_dev, "card is %s\n",
1555 read_only ? "read-only" : "read-write");
1556 }
1557
1558 return read_only;
1559 }
1560
1561 static int atmci_get_cd(struct mmc_host *mmc)
1562 {
1563 int present = -ENOSYS;
1564 struct atmel_mci_slot *slot = mmc_priv(mmc);
1565
1566 if (gpio_is_valid(slot->detect_pin)) {
1567 present = !(gpio_get_value(slot->detect_pin) ^
1568 slot->detect_is_active_high);
1569 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1570 present ? "" : "not ");
1571 }
1572
1573 return present;
1574 }
1575
1576 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1577 {
1578 struct atmel_mci_slot *slot = mmc_priv(mmc);
1579 struct atmel_mci *host = slot->host;
1580
1581 if (enable)
1582 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1583 else
1584 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1585 }
1586
1587 static const struct mmc_host_ops atmci_ops = {
1588 .request = atmci_request,
1589 .set_ios = atmci_set_ios,
1590 .get_ro = atmci_get_ro,
1591 .get_cd = atmci_get_cd,
1592 .enable_sdio_irq = atmci_enable_sdio_irq,
1593 };
1594
1595 /* Called with host->lock held */
1596 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1597 __releases(&host->lock)
1598 __acquires(&host->lock)
1599 {
1600 struct atmel_mci_slot *slot = NULL;
1601 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1602
1603 WARN_ON(host->cmd || host->data);
1604
1605 /*
1606 * Update the MMC clock rate if necessary. This may be
1607 * necessary if set_ios() is called when a different slot is
1608 * busy transferring data.
1609 */
1610 if (host->need_clock_update) {
1611 atmci_writel(host, ATMCI_MR, host->mode_reg);
1612 if (host->caps.has_cfg_reg)
1613 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1614 }
1615
1616 host->cur_slot->mrq = NULL;
1617 host->mrq = NULL;
1618 if (!list_empty(&host->queue)) {
1619 slot = list_entry(host->queue.next,
1620 struct atmel_mci_slot, queue_node);
1621 list_del(&slot->queue_node);
1622 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1623 mmc_hostname(slot->mmc));
1624 host->state = STATE_SENDING_CMD;
1625 atmci_start_request(host, slot);
1626 } else {
1627 dev_vdbg(&host->pdev->dev, "list empty\n");
1628 host->state = STATE_IDLE;
1629 }
1630
1631 del_timer(&host->timer);
1632
1633 spin_unlock(&host->lock);
1634 mmc_request_done(prev_mmc, mrq);
1635 spin_lock(&host->lock);
1636 }
1637
1638 static void atmci_command_complete(struct atmel_mci *host,
1639 struct mmc_command *cmd)
1640 {
1641 u32 status = host->cmd_status;
1642
1643 /* Read the response from the card (up to 16 bytes) */
1644 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1645 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1646 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1647 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1648
1649 if (status & ATMCI_RTOE)
1650 cmd->error = -ETIMEDOUT;
1651 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1652 cmd->error = -EILSEQ;
1653 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1654 cmd->error = -EIO;
1655 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1656 if (host->caps.need_blksz_mul_4) {
1657 cmd->error = -EINVAL;
1658 host->need_reset = 1;
1659 }
1660 } else
1661 cmd->error = 0;
1662 }
1663
1664 static void atmci_detect_change(struct timer_list *t)
1665 {
1666 struct atmel_mci_slot *slot = from_timer(slot, t, detect_timer);
1667 bool present;
1668 bool present_old;
1669
1670 /*
1671 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1672 * freeing the interrupt. We must not re-enable the interrupt
1673 * if it has been freed, and if we're shutting down, it
1674 * doesn't really matter whether the card is present or not.
1675 */
1676 smp_rmb();
1677 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1678 return;
1679
1680 enable_irq(gpio_to_irq(slot->detect_pin));
1681 present = !(gpio_get_value(slot->detect_pin) ^
1682 slot->detect_is_active_high);
1683 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1684
1685 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1686 present, present_old);
1687
1688 if (present != present_old) {
1689 struct atmel_mci *host = slot->host;
1690 struct mmc_request *mrq;
1691
1692 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1693 present ? "inserted" : "removed");
1694
1695 spin_lock(&host->lock);
1696
1697 if (!present)
1698 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1699 else
1700 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1701
1702 /* Clean up queue if present */
1703 mrq = slot->mrq;
1704 if (mrq) {
1705 if (mrq == host->mrq) {
1706 /*
1707 * Reset controller to terminate any ongoing
1708 * commands or data transfers.
1709 */
1710 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1711 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1712 atmci_writel(host, ATMCI_MR, host->mode_reg);
1713 if (host->caps.has_cfg_reg)
1714 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1715
1716 host->data = NULL;
1717 host->cmd = NULL;
1718
1719 switch (host->state) {
1720 case STATE_IDLE:
1721 break;
1722 case STATE_SENDING_CMD:
1723 mrq->cmd->error = -ENOMEDIUM;
1724 if (mrq->data)
1725 host->stop_transfer(host);
1726 break;
1727 case STATE_DATA_XFER:
1728 mrq->data->error = -ENOMEDIUM;
1729 host->stop_transfer(host);
1730 break;
1731 case STATE_WAITING_NOTBUSY:
1732 mrq->data->error = -ENOMEDIUM;
1733 break;
1734 case STATE_SENDING_STOP:
1735 mrq->stop->error = -ENOMEDIUM;
1736 break;
1737 case STATE_END_REQUEST:
1738 break;
1739 }
1740
1741 atmci_request_end(host, mrq);
1742 } else {
1743 list_del(&slot->queue_node);
1744 mrq->cmd->error = -ENOMEDIUM;
1745 if (mrq->data)
1746 mrq->data->error = -ENOMEDIUM;
1747 if (mrq->stop)
1748 mrq->stop->error = -ENOMEDIUM;
1749
1750 spin_unlock(&host->lock);
1751 mmc_request_done(slot->mmc, mrq);
1752 spin_lock(&host->lock);
1753 }
1754 }
1755 spin_unlock(&host->lock);
1756
1757 mmc_detect_change(slot->mmc, 0);
1758 }
1759 }
1760
1761 static void atmci_tasklet_func(unsigned long priv)
1762 {
1763 struct atmel_mci *host = (struct atmel_mci *)priv;
1764 struct mmc_request *mrq = host->mrq;
1765 struct mmc_data *data = host->data;
1766 enum atmel_mci_state state = host->state;
1767 enum atmel_mci_state prev_state;
1768 u32 status;
1769
1770 spin_lock(&host->lock);
1771
1772 state = host->state;
1773
1774 dev_vdbg(&host->pdev->dev,
1775 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1776 state, host->pending_events, host->completed_events,
1777 atmci_readl(host, ATMCI_IMR));
1778
1779 do {
1780 prev_state = state;
1781 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1782
1783 switch (state) {
1784 case STATE_IDLE:
1785 break;
1786
1787 case STATE_SENDING_CMD:
1788 /*
1789 * Command has been sent, we are waiting for command
1790 * ready. Then we have three next states possible:
1791 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1792 * command needing it or DATA_XFER if there is data.
1793 */
1794 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1795 if (!atmci_test_and_clear_pending(host,
1796 EVENT_CMD_RDY))
1797 break;
1798
1799 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1800 host->cmd = NULL;
1801 atmci_set_completed(host, EVENT_CMD_RDY);
1802 atmci_command_complete(host, mrq->cmd);
1803 if (mrq->data) {
1804 dev_dbg(&host->pdev->dev,
1805 "command with data transfer");
1806 /*
1807 * If there is a command error don't start
1808 * data transfer.
1809 */
1810 if (mrq->cmd->error) {
1811 host->stop_transfer(host);
1812 host->data = NULL;
1813 atmci_writel(host, ATMCI_IDR,
1814 ATMCI_TXRDY | ATMCI_RXRDY
1815 | ATMCI_DATA_ERROR_FLAGS);
1816 state = STATE_END_REQUEST;
1817 } else
1818 state = STATE_DATA_XFER;
1819 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1820 dev_dbg(&host->pdev->dev,
1821 "command response need waiting notbusy");
1822 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1823 state = STATE_WAITING_NOTBUSY;
1824 } else
1825 state = STATE_END_REQUEST;
1826
1827 break;
1828
1829 case STATE_DATA_XFER:
1830 if (atmci_test_and_clear_pending(host,
1831 EVENT_DATA_ERROR)) {
1832 dev_dbg(&host->pdev->dev, "set completed data error\n");
1833 atmci_set_completed(host, EVENT_DATA_ERROR);
1834 state = STATE_END_REQUEST;
1835 break;
1836 }
1837
1838 /*
1839 * A data transfer is in progress. The event expected
1840 * to move to the next state depends of data transfer
1841 * type (PDC or DMA). Once transfer done we can move
1842 * to the next step which is WAITING_NOTBUSY in write
1843 * case and directly SENDING_STOP in read case.
1844 */
1845 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1846 if (!atmci_test_and_clear_pending(host,
1847 EVENT_XFER_COMPLETE))
1848 break;
1849
1850 dev_dbg(&host->pdev->dev,
1851 "(%s) set completed xfer complete\n",
1852 __func__);
1853 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1854
1855 if (host->caps.need_notbusy_for_read_ops ||
1856 (host->data->flags & MMC_DATA_WRITE)) {
1857 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1858 state = STATE_WAITING_NOTBUSY;
1859 } else if (host->mrq->stop) {
1860 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1861 atmci_send_stop_cmd(host, data);
1862 state = STATE_SENDING_STOP;
1863 } else {
1864 host->data = NULL;
1865 data->bytes_xfered = data->blocks * data->blksz;
1866 data->error = 0;
1867 state = STATE_END_REQUEST;
1868 }
1869 break;
1870
1871 case STATE_WAITING_NOTBUSY:
1872 /*
1873 * We can be in the state for two reasons: a command
1874 * requiring waiting not busy signal (stop command
1875 * included) or a write operation. In the latest case,
1876 * we need to send a stop command.
1877 */
1878 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1879 if (!atmci_test_and_clear_pending(host,
1880 EVENT_NOTBUSY))
1881 break;
1882
1883 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1884 atmci_set_completed(host, EVENT_NOTBUSY);
1885
1886 if (host->data) {
1887 /*
1888 * For some commands such as CMD53, even if
1889 * there is data transfer, there is no stop
1890 * command to send.
1891 */
1892 if (host->mrq->stop) {
1893 atmci_writel(host, ATMCI_IER,
1894 ATMCI_CMDRDY);
1895 atmci_send_stop_cmd(host, data);
1896 state = STATE_SENDING_STOP;
1897 } else {
1898 host->data = NULL;
1899 data->bytes_xfered = data->blocks
1900 * data->blksz;
1901 data->error = 0;
1902 state = STATE_END_REQUEST;
1903 }
1904 } else
1905 state = STATE_END_REQUEST;
1906 break;
1907
1908 case STATE_SENDING_STOP:
1909 /*
1910 * In this state, it is important to set host->data to
1911 * NULL (which is tested in the waiting notbusy state)
1912 * in order to go to the end request state instead of
1913 * sending stop again.
1914 */
1915 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1916 if (!atmci_test_and_clear_pending(host,
1917 EVENT_CMD_RDY))
1918 break;
1919
1920 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1921 host->cmd = NULL;
1922 data->bytes_xfered = data->blocks * data->blksz;
1923 data->error = 0;
1924 atmci_command_complete(host, mrq->stop);
1925 if (mrq->stop->error) {
1926 host->stop_transfer(host);
1927 atmci_writel(host, ATMCI_IDR,
1928 ATMCI_TXRDY | ATMCI_RXRDY
1929 | ATMCI_DATA_ERROR_FLAGS);
1930 state = STATE_END_REQUEST;
1931 } else {
1932 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1933 state = STATE_WAITING_NOTBUSY;
1934 }
1935 host->data = NULL;
1936 break;
1937
1938 case STATE_END_REQUEST:
1939 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1940 | ATMCI_DATA_ERROR_FLAGS);
1941 status = host->data_status;
1942 if (unlikely(status)) {
1943 host->stop_transfer(host);
1944 host->data = NULL;
1945 if (data) {
1946 if (status & ATMCI_DTOE) {
1947 data->error = -ETIMEDOUT;
1948 } else if (status & ATMCI_DCRCE) {
1949 data->error = -EILSEQ;
1950 } else {
1951 data->error = -EIO;
1952 }
1953 }
1954 }
1955
1956 atmci_request_end(host, host->mrq);
1957 goto unlock; /* atmci_request_end() sets host->state */
1958 break;
1959 }
1960 } while (state != prev_state);
1961
1962 host->state = state;
1963
1964 unlock:
1965 spin_unlock(&host->lock);
1966 }
1967
1968 static void atmci_read_data_pio(struct atmel_mci *host)
1969 {
1970 struct scatterlist *sg = host->sg;
1971 unsigned int offset = host->pio_offset;
1972 struct mmc_data *data = host->data;
1973 u32 value;
1974 u32 status;
1975 unsigned int nbytes = 0;
1976
1977 do {
1978 value = atmci_readl(host, ATMCI_RDR);
1979 if (likely(offset + 4 <= sg->length)) {
1980 sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset);
1981
1982 offset += 4;
1983 nbytes += 4;
1984
1985 if (offset == sg->length) {
1986 flush_dcache_page(sg_page(sg));
1987 host->sg = sg = sg_next(sg);
1988 host->sg_len--;
1989 if (!sg || !host->sg_len)
1990 goto done;
1991
1992 offset = 0;
1993 }
1994 } else {
1995 unsigned int remaining = sg->length - offset;
1996
1997 sg_pcopy_from_buffer(sg, 1, &value, remaining, offset);
1998 nbytes += remaining;
1999
2000 flush_dcache_page(sg_page(sg));
2001 host->sg = sg = sg_next(sg);
2002 host->sg_len--;
2003 if (!sg || !host->sg_len)
2004 goto done;
2005
2006 offset = 4 - remaining;
2007 sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining,
2008 offset, 0);
2009 nbytes += offset;
2010 }
2011
2012 status = atmci_readl(host, ATMCI_SR);
2013 if (status & ATMCI_DATA_ERROR_FLAGS) {
2014 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
2015 | ATMCI_DATA_ERROR_FLAGS));
2016 host->data_status = status;
2017 data->bytes_xfered += nbytes;
2018 return;
2019 }
2020 } while (status & ATMCI_RXRDY);
2021
2022 host->pio_offset = offset;
2023 data->bytes_xfered += nbytes;
2024
2025 return;
2026
2027 done:
2028 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
2029 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2030 data->bytes_xfered += nbytes;
2031 smp_wmb();
2032 atmci_set_pending(host, EVENT_XFER_COMPLETE);
2033 }
2034
2035 static void atmci_write_data_pio(struct atmel_mci *host)
2036 {
2037 struct scatterlist *sg = host->sg;
2038 unsigned int offset = host->pio_offset;
2039 struct mmc_data *data = host->data;
2040 u32 value;
2041 u32 status;
2042 unsigned int nbytes = 0;
2043
2044 do {
2045 if (likely(offset + 4 <= sg->length)) {
2046 sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset);
2047 atmci_writel(host, ATMCI_TDR, value);
2048
2049 offset += 4;
2050 nbytes += 4;
2051 if (offset == sg->length) {
2052 host->sg = sg = sg_next(sg);
2053 host->sg_len--;
2054 if (!sg || !host->sg_len)
2055 goto done;
2056
2057 offset = 0;
2058 }
2059 } else {
2060 unsigned int remaining = sg->length - offset;
2061
2062 value = 0;
2063 sg_pcopy_to_buffer(sg, 1, &value, remaining, offset);
2064 nbytes += remaining;
2065
2066 host->sg = sg = sg_next(sg);
2067 host->sg_len--;
2068 if (!sg || !host->sg_len) {
2069 atmci_writel(host, ATMCI_TDR, value);
2070 goto done;
2071 }
2072
2073 offset = 4 - remaining;
2074 sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining,
2075 offset, 0);
2076 atmci_writel(host, ATMCI_TDR, value);
2077 nbytes += offset;
2078 }
2079
2080 status = atmci_readl(host, ATMCI_SR);
2081 if (status & ATMCI_DATA_ERROR_FLAGS) {
2082 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2083 | ATMCI_DATA_ERROR_FLAGS));
2084 host->data_status = status;
2085 data->bytes_xfered += nbytes;
2086 return;
2087 }
2088 } while (status & ATMCI_TXRDY);
2089
2090 host->pio_offset = offset;
2091 data->bytes_xfered += nbytes;
2092
2093 return;
2094
2095 done:
2096 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2097 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2098 data->bytes_xfered += nbytes;
2099 smp_wmb();
2100 atmci_set_pending(host, EVENT_XFER_COMPLETE);
2101 }
2102
2103 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2104 {
2105 int i;
2106
2107 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2108 struct atmel_mci_slot *slot = host->slot[i];
2109 if (slot && (status & slot->sdio_irq)) {
2110 mmc_signal_sdio_irq(slot->mmc);
2111 }
2112 }
2113 }
2114
2115
2116 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2117 {
2118 struct atmel_mci *host = dev_id;
2119 u32 status, mask, pending;
2120 unsigned int pass_count = 0;
2121
2122 do {
2123 status = atmci_readl(host, ATMCI_SR);
2124 mask = atmci_readl(host, ATMCI_IMR);
2125 pending = status & mask;
2126 if (!pending)
2127 break;
2128
2129 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2130 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2131 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2132 | ATMCI_RXRDY | ATMCI_TXRDY
2133 | ATMCI_ENDRX | ATMCI_ENDTX
2134 | ATMCI_RXBUFF | ATMCI_TXBUFE);
2135
2136 host->data_status = status;
2137 dev_dbg(&host->pdev->dev, "set pending data error\n");
2138 smp_wmb();
2139 atmci_set_pending(host, EVENT_DATA_ERROR);
2140 tasklet_schedule(&host->tasklet);
2141 }
2142
2143 if (pending & ATMCI_TXBUFE) {
2144 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2145 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2146 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2147 /*
2148 * We can receive this interruption before having configured
2149 * the second pdc buffer, so we need to reconfigure first and
2150 * second buffers again
2151 */
2152 if (host->data_size) {
2153 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2154 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2155 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2156 } else {
2157 atmci_pdc_complete(host);
2158 }
2159 } else if (pending & ATMCI_ENDTX) {
2160 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2161 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2162
2163 if (host->data_size) {
2164 atmci_pdc_set_single_buf(host,
2165 XFER_TRANSMIT, PDC_SECOND_BUF);
2166 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2167 }
2168 }
2169
2170 if (pending & ATMCI_RXBUFF) {
2171 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2172 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2173 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2174 /*
2175 * We can receive this interruption before having configured
2176 * the second pdc buffer, so we need to reconfigure first and
2177 * second buffers again
2178 */
2179 if (host->data_size) {
2180 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2181 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2182 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2183 } else {
2184 atmci_pdc_complete(host);
2185 }
2186 } else if (pending & ATMCI_ENDRX) {
2187 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2188 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2189
2190 if (host->data_size) {
2191 atmci_pdc_set_single_buf(host,
2192 XFER_RECEIVE, PDC_SECOND_BUF);
2193 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2194 }
2195 }
2196
2197 /*
2198 * First mci IPs, so mainly the ones having pdc, have some
2199 * issues with the notbusy signal. You can't get it after
2200 * data transmission if you have not sent a stop command.
2201 * The appropriate workaround is to use the BLKE signal.
2202 */
2203 if (pending & ATMCI_BLKE) {
2204 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2205 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2206 smp_wmb();
2207 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2208 atmci_set_pending(host, EVENT_NOTBUSY);
2209 tasklet_schedule(&host->tasklet);
2210 }
2211
2212 if (pending & ATMCI_NOTBUSY) {
2213 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2214 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2215 smp_wmb();
2216 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2217 atmci_set_pending(host, EVENT_NOTBUSY);
2218 tasklet_schedule(&host->tasklet);
2219 }
2220
2221 if (pending & ATMCI_RXRDY)
2222 atmci_read_data_pio(host);
2223 if (pending & ATMCI_TXRDY)
2224 atmci_write_data_pio(host);
2225
2226 if (pending & ATMCI_CMDRDY) {
2227 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2228 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2229 host->cmd_status = status;
2230 smp_wmb();
2231 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2232 atmci_set_pending(host, EVENT_CMD_RDY);
2233 tasklet_schedule(&host->tasklet);
2234 }
2235
2236 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2237 atmci_sdio_interrupt(host, status);
2238
2239 } while (pass_count++ < 5);
2240
2241 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2242 }
2243
2244 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2245 {
2246 struct atmel_mci_slot *slot = dev_id;
2247
2248 /*
2249 * Disable interrupts until the pin has stabilized and check
2250 * the state then. Use mod_timer() since we may be in the
2251 * middle of the timer routine when this interrupt triggers.
2252 */
2253 disable_irq_nosync(irq);
2254 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2255
2256 return IRQ_HANDLED;
2257 }
2258
2259 static int atmci_init_slot(struct atmel_mci *host,
2260 struct mci_slot_pdata *slot_data, unsigned int id,
2261 u32 sdc_reg, u32 sdio_irq)
2262 {
2263 struct mmc_host *mmc;
2264 struct atmel_mci_slot *slot;
2265
2266 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2267 if (!mmc)
2268 return -ENOMEM;
2269
2270 slot = mmc_priv(mmc);
2271 slot->mmc = mmc;
2272 slot->host = host;
2273 slot->detect_pin = slot_data->detect_pin;
2274 slot->wp_pin = slot_data->wp_pin;
2275 slot->detect_is_active_high = slot_data->detect_is_active_high;
2276 slot->sdc_reg = sdc_reg;
2277 slot->sdio_irq = sdio_irq;
2278
2279 dev_dbg(&mmc->class_dev,
2280 "slot[%u]: bus_width=%u, detect_pin=%d, "
2281 "detect_is_active_high=%s, wp_pin=%d\n",
2282 id, slot_data->bus_width, slot_data->detect_pin,
2283 slot_data->detect_is_active_high ? "true" : "false",
2284 slot_data->wp_pin);
2285
2286 mmc->ops = &atmci_ops;
2287 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2288 mmc->f_max = host->bus_hz / 2;
2289 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2290 if (sdio_irq)
2291 mmc->caps |= MMC_CAP_SDIO_IRQ;
2292 if (host->caps.has_highspeed)
2293 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2294 /*
2295 * Without the read/write proof capability, it is strongly suggested to
2296 * use only one bit for data to prevent fifo underruns and overruns
2297 * which will corrupt data.
2298 */
2299 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2300 mmc->caps |= MMC_CAP_4_BIT_DATA;
2301
2302 if (atmci_get_version(host) < 0x200) {
2303 mmc->max_segs = 256;
2304 mmc->max_blk_size = 4095;
2305 mmc->max_blk_count = 256;
2306 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2307 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2308 } else {
2309 mmc->max_segs = 64;
2310 mmc->max_req_size = 32768 * 512;
2311 mmc->max_blk_size = 32768;
2312 mmc->max_blk_count = 512;
2313 }
2314
2315 /* Assume card is present initially */
2316 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2317 if (gpio_is_valid(slot->detect_pin)) {
2318 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2319 "mmc_detect")) {
2320 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2321 slot->detect_pin = -EBUSY;
2322 } else if (gpio_get_value(slot->detect_pin) ^
2323 slot->detect_is_active_high) {
2324 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2325 }
2326 }
2327
2328 if (!gpio_is_valid(slot->detect_pin)) {
2329 if (slot_data->non_removable)
2330 mmc->caps |= MMC_CAP_NONREMOVABLE;
2331 else
2332 mmc->caps |= MMC_CAP_NEEDS_POLL;
2333 }
2334
2335 if (gpio_is_valid(slot->wp_pin)) {
2336 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2337 "mmc_wp")) {
2338 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2339 slot->wp_pin = -EBUSY;
2340 }
2341 }
2342
2343 host->slot[id] = slot;
2344 mmc_regulator_get_supply(mmc);
2345 mmc_add_host(mmc);
2346
2347 if (gpio_is_valid(slot->detect_pin)) {
2348 int ret;
2349
2350 timer_setup(&slot->detect_timer, atmci_detect_change, 0);
2351
2352 ret = request_irq(gpio_to_irq(slot->detect_pin),
2353 atmci_detect_interrupt,
2354 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2355 "mmc-detect", slot);
2356 if (ret) {
2357 dev_dbg(&mmc->class_dev,
2358 "could not request IRQ %d for detect pin\n",
2359 gpio_to_irq(slot->detect_pin));
2360 slot->detect_pin = -EBUSY;
2361 }
2362 }
2363
2364 atmci_init_debugfs(slot);
2365
2366 return 0;
2367 }
2368
2369 static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2370 unsigned int id)
2371 {
2372 /* Debugfs stuff is cleaned up by mmc core */
2373
2374 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2375 smp_wmb();
2376
2377 mmc_remove_host(slot->mmc);
2378
2379 if (gpio_is_valid(slot->detect_pin)) {
2380 int pin = slot->detect_pin;
2381
2382 free_irq(gpio_to_irq(pin), slot);
2383 del_timer_sync(&slot->detect_timer);
2384 }
2385
2386 slot->host->slot[id] = NULL;
2387 mmc_free_host(slot->mmc);
2388 }
2389
2390 static int atmci_configure_dma(struct atmel_mci *host)
2391 {
2392 host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev,
2393 "rxtx");
2394
2395 if (PTR_ERR(host->dma.chan) == -ENODEV) {
2396 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2397 dma_cap_mask_t mask;
2398
2399 if (!pdata || !pdata->dma_filter)
2400 return -ENODEV;
2401
2402 dma_cap_zero(mask);
2403 dma_cap_set(DMA_SLAVE, mask);
2404
2405 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2406 pdata->dma_slave);
2407 if (!host->dma.chan)
2408 host->dma.chan = ERR_PTR(-ENODEV);
2409 }
2410
2411 if (IS_ERR(host->dma.chan))
2412 return PTR_ERR(host->dma.chan);
2413
2414 dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2415 dma_chan_name(host->dma.chan));
2416
2417 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2418 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2419 host->dma_conf.src_maxburst = 1;
2420 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2421 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2422 host->dma_conf.dst_maxburst = 1;
2423 host->dma_conf.device_fc = false;
2424
2425 return 0;
2426 }
2427
2428 /*
2429 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2430 * HSMCI provides DMA support and a new config register but no more supports
2431 * PDC.
2432 */
2433 static void atmci_get_cap(struct atmel_mci *host)
2434 {
2435 unsigned int version;
2436
2437 version = atmci_get_version(host);
2438 dev_info(&host->pdev->dev,
2439 "version: 0x%x\n", version);
2440
2441 host->caps.has_dma_conf_reg = 0;
2442 host->caps.has_pdc = 1;
2443 host->caps.has_cfg_reg = 0;
2444 host->caps.has_cstor_reg = 0;
2445 host->caps.has_highspeed = 0;
2446 host->caps.has_rwproof = 0;
2447 host->caps.has_odd_clk_div = 0;
2448 host->caps.has_bad_data_ordering = 1;
2449 host->caps.need_reset_after_xfer = 1;
2450 host->caps.need_blksz_mul_4 = 1;
2451 host->caps.need_notbusy_for_read_ops = 0;
2452
2453 /* keep only major version number */
2454 switch (version & 0xf00) {
2455 case 0x600:
2456 case 0x500:
2457 host->caps.has_odd_clk_div = 1;
2458 case 0x400:
2459 case 0x300:
2460 host->caps.has_dma_conf_reg = 1;
2461 host->caps.has_pdc = 0;
2462 host->caps.has_cfg_reg = 1;
2463 host->caps.has_cstor_reg = 1;
2464 host->caps.has_highspeed = 1;
2465 case 0x200:
2466 host->caps.has_rwproof = 1;
2467 host->caps.need_blksz_mul_4 = 0;
2468 host->caps.need_notbusy_for_read_ops = 1;
2469 case 0x100:
2470 host->caps.has_bad_data_ordering = 0;
2471 host->caps.need_reset_after_xfer = 0;
2472 case 0x0:
2473 break;
2474 default:
2475 host->caps.has_pdc = 0;
2476 dev_warn(&host->pdev->dev,
2477 "Unmanaged mci version, set minimum capabilities\n");
2478 break;
2479 }
2480 }
2481
2482 static int atmci_probe(struct platform_device *pdev)
2483 {
2484 struct mci_platform_data *pdata;
2485 struct atmel_mci *host;
2486 struct resource *regs;
2487 unsigned int nr_slots;
2488 int irq;
2489 int ret, i;
2490
2491 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2492 if (!regs)
2493 return -ENXIO;
2494 pdata = pdev->dev.platform_data;
2495 if (!pdata) {
2496 pdata = atmci_of_init(pdev);
2497 if (IS_ERR(pdata)) {
2498 dev_err(&pdev->dev, "platform data not available\n");
2499 return PTR_ERR(pdata);
2500 }
2501 }
2502
2503 irq = platform_get_irq(pdev, 0);
2504 if (irq < 0)
2505 return irq;
2506
2507 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2508 if (!host)
2509 return -ENOMEM;
2510
2511 host->pdev = pdev;
2512 spin_lock_init(&host->lock);
2513 INIT_LIST_HEAD(&host->queue);
2514
2515 host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2516 if (IS_ERR(host->mck))
2517 return PTR_ERR(host->mck);
2518
2519 host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2520 if (!host->regs)
2521 return -ENOMEM;
2522
2523 ret = clk_prepare_enable(host->mck);
2524 if (ret)
2525 return ret;
2526
2527 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2528 host->bus_hz = clk_get_rate(host->mck);
2529
2530 host->mapbase = regs->start;
2531
2532 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2533
2534 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2535 if (ret) {
2536 clk_disable_unprepare(host->mck);
2537 return ret;
2538 }
2539
2540 /* Get MCI capabilities and set operations according to it */
2541 atmci_get_cap(host);
2542 ret = atmci_configure_dma(host);
2543 if (ret == -EPROBE_DEFER)
2544 goto err_dma_probe_defer;
2545 if (ret == 0) {
2546 host->prepare_data = &atmci_prepare_data_dma;
2547 host->submit_data = &atmci_submit_data_dma;
2548 host->stop_transfer = &atmci_stop_transfer_dma;
2549 } else if (host->caps.has_pdc) {
2550 dev_info(&pdev->dev, "using PDC\n");
2551 host->prepare_data = &atmci_prepare_data_pdc;
2552 host->submit_data = &atmci_submit_data_pdc;
2553 host->stop_transfer = &atmci_stop_transfer_pdc;
2554 } else {
2555 dev_info(&pdev->dev, "using PIO\n");
2556 host->prepare_data = &atmci_prepare_data;
2557 host->submit_data = &atmci_submit_data;
2558 host->stop_transfer = &atmci_stop_transfer;
2559 }
2560
2561 platform_set_drvdata(pdev, host);
2562
2563 timer_setup(&host->timer, atmci_timeout_timer, 0);
2564
2565 pm_runtime_get_noresume(&pdev->dev);
2566 pm_runtime_set_active(&pdev->dev);
2567 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2568 pm_runtime_use_autosuspend(&pdev->dev);
2569 pm_runtime_enable(&pdev->dev);
2570
2571 /* We need at least one slot to succeed */
2572 nr_slots = 0;
2573 ret = -ENODEV;
2574 if (pdata->slot[0].bus_width) {
2575 ret = atmci_init_slot(host, &pdata->slot[0],
2576 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2577 if (!ret) {
2578 nr_slots++;
2579 host->buf_size = host->slot[0]->mmc->max_req_size;
2580 }
2581 }
2582 if (pdata->slot[1].bus_width) {
2583 ret = atmci_init_slot(host, &pdata->slot[1],
2584 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2585 if (!ret) {
2586 nr_slots++;
2587 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2588 host->buf_size =
2589 host->slot[1]->mmc->max_req_size;
2590 }
2591 }
2592
2593 if (!nr_slots) {
2594 dev_err(&pdev->dev, "init failed: no slot defined\n");
2595 goto err_init_slot;
2596 }
2597
2598 if (!host->caps.has_rwproof) {
2599 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2600 &host->buf_phys_addr,
2601 GFP_KERNEL);
2602 if (!host->buffer) {
2603 ret = -ENOMEM;
2604 dev_err(&pdev->dev, "buffer allocation failed\n");
2605 goto err_dma_alloc;
2606 }
2607 }
2608
2609 dev_info(&pdev->dev,
2610 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2611 host->mapbase, irq, nr_slots);
2612
2613 pm_runtime_mark_last_busy(&host->pdev->dev);
2614 pm_runtime_put_autosuspend(&pdev->dev);
2615
2616 return 0;
2617
2618 err_dma_alloc:
2619 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2620 if (host->slot[i])
2621 atmci_cleanup_slot(host->slot[i], i);
2622 }
2623 err_init_slot:
2624 clk_disable_unprepare(host->mck);
2625
2626 pm_runtime_disable(&pdev->dev);
2627 pm_runtime_put_noidle(&pdev->dev);
2628
2629 del_timer_sync(&host->timer);
2630 if (!IS_ERR(host->dma.chan))
2631 dma_release_channel(host->dma.chan);
2632 err_dma_probe_defer:
2633 free_irq(irq, host);
2634 return ret;
2635 }
2636
2637 static int atmci_remove(struct platform_device *pdev)
2638 {
2639 struct atmel_mci *host = platform_get_drvdata(pdev);
2640 unsigned int i;
2641
2642 pm_runtime_get_sync(&pdev->dev);
2643
2644 if (host->buffer)
2645 dma_free_coherent(&pdev->dev, host->buf_size,
2646 host->buffer, host->buf_phys_addr);
2647
2648 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2649 if (host->slot[i])
2650 atmci_cleanup_slot(host->slot[i], i);
2651 }
2652
2653 atmci_writel(host, ATMCI_IDR, ~0UL);
2654 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2655 atmci_readl(host, ATMCI_SR);
2656
2657 del_timer_sync(&host->timer);
2658 if (!IS_ERR(host->dma.chan))
2659 dma_release_channel(host->dma.chan);
2660
2661 free_irq(platform_get_irq(pdev, 0), host);
2662
2663 clk_disable_unprepare(host->mck);
2664
2665 pm_runtime_disable(&pdev->dev);
2666 pm_runtime_put_noidle(&pdev->dev);
2667
2668 return 0;
2669 }
2670
2671 #ifdef CONFIG_PM
2672 static int atmci_runtime_suspend(struct device *dev)
2673 {
2674 struct atmel_mci *host = dev_get_drvdata(dev);
2675
2676 clk_disable_unprepare(host->mck);
2677
2678 pinctrl_pm_select_sleep_state(dev);
2679
2680 return 0;
2681 }
2682
2683 static int atmci_runtime_resume(struct device *dev)
2684 {
2685 struct atmel_mci *host = dev_get_drvdata(dev);
2686
2687 pinctrl_pm_select_default_state(dev);
2688
2689 return clk_prepare_enable(host->mck);
2690 }
2691 #endif
2692
2693 static const struct dev_pm_ops atmci_dev_pm_ops = {
2694 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2695 pm_runtime_force_resume)
2696 SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2697 };
2698
2699 static struct platform_driver atmci_driver = {
2700 .probe = atmci_probe,
2701 .remove = atmci_remove,
2702 .driver = {
2703 .name = "atmel_mci",
2704 .of_match_table = of_match_ptr(atmci_dt_ids),
2705 .pm = &atmci_dev_pm_ops,
2706 },
2707 };
2708 module_platform_driver(atmci_driver);
2709
2710 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2711 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2712 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support