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Linux 4.19.133
[linux/fpc-iii.git] / drivers / mmc / host / mxcmmc.c
blob2f604b312767d01b4d713bd46fd17b5ce83aa180
1 /*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/highmem.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/blkdev.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/delay.h>
32 #include <linux/clk.h>
33 #include <linux/io.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/dmaengine.h>
37 #include <linux/types.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/of_dma.h>
41 #include <linux/of_gpio.h>
42 #include <linux/mmc/slot-gpio.h>
43
44 #include <asm/dma.h>
45 #include <asm/irq.h>
46 #include <linux/platform_data/mmc-mxcmmc.h>
47
48 #include <linux/platform_data/dma-imx.h>
49
50 #define DRIVER_NAME "mxc-mmc"
51 #define MXCMCI_TIMEOUT_MS 10000
52
53 #define MMC_REG_STR_STP_CLK 0x00
54 #define MMC_REG_STATUS 0x04
55 #define MMC_REG_CLK_RATE 0x08
56 #define MMC_REG_CMD_DAT_CONT 0x0C
57 #define MMC_REG_RES_TO 0x10
58 #define MMC_REG_READ_TO 0x14
59 #define MMC_REG_BLK_LEN 0x18
60 #define MMC_REG_NOB 0x1C
61 #define MMC_REG_REV_NO 0x20
62 #define MMC_REG_INT_CNTR 0x24
63 #define MMC_REG_CMD 0x28
64 #define MMC_REG_ARG 0x2C
65 #define MMC_REG_RES_FIFO 0x34
66 #define MMC_REG_BUFFER_ACCESS 0x38
67
68 #define STR_STP_CLK_RESET (1 << 3)
69 #define STR_STP_CLK_START_CLK (1 << 1)
70 #define STR_STP_CLK_STOP_CLK (1 << 0)
71
72 #define STATUS_CARD_INSERTION (1 << 31)
73 #define STATUS_CARD_REMOVAL (1 << 30)
74 #define STATUS_YBUF_EMPTY (1 << 29)
75 #define STATUS_XBUF_EMPTY (1 << 28)
76 #define STATUS_YBUF_FULL (1 << 27)
77 #define STATUS_XBUF_FULL (1 << 26)
78 #define STATUS_BUF_UND_RUN (1 << 25)
79 #define STATUS_BUF_OVFL (1 << 24)
80 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
81 #define STATUS_END_CMD_RESP (1 << 13)
82 #define STATUS_WRITE_OP_DONE (1 << 12)
83 #define STATUS_DATA_TRANS_DONE (1 << 11)
84 #define STATUS_READ_OP_DONE (1 << 11)
85 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
86 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
87 #define STATUS_BUF_READ_RDY (1 << 7)
88 #define STATUS_BUF_WRITE_RDY (1 << 6)
89 #define STATUS_RESP_CRC_ERR (1 << 5)
90 #define STATUS_CRC_READ_ERR (1 << 3)
91 #define STATUS_CRC_WRITE_ERR (1 << 2)
92 #define STATUS_TIME_OUT_RESP (1 << 1)
93 #define STATUS_TIME_OUT_READ (1 << 0)
94 #define STATUS_ERR_MASK 0x2f
95
96 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
97 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
98 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
99 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
100 #define CMD_DAT_CONT_INIT (1 << 7)
101 #define CMD_DAT_CONT_WRITE (1 << 4)
102 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
103 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
104 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
105 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
106
107 #define INT_SDIO_INT_WKP_EN (1 << 18)
108 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
109 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
110 #define INT_CARD_INSERTION_EN (1 << 15)
111 #define INT_CARD_REMOVAL_EN (1 << 14)
112 #define INT_SDIO_IRQ_EN (1 << 13)
113 #define INT_DAT0_EN (1 << 12)
114 #define INT_BUF_READ_EN (1 << 4)
115 #define INT_BUF_WRITE_EN (1 << 3)
116 #define INT_END_CMD_RES_EN (1 << 2)
117 #define INT_WRITE_OP_DONE_EN (1 << 1)
118 #define INT_READ_OP_EN (1 << 0)
119
120 enum mxcmci_type {
121 IMX21_MMC,
122 IMX31_MMC,
123 MPC512X_MMC,
124 };
125
126 struct mxcmci_host {
127 struct mmc_host *mmc;
128 void __iomem *base;
129 dma_addr_t phys_base;
130 int detect_irq;
131 struct dma_chan *dma;
132 struct dma_async_tx_descriptor *desc;
133 int do_dma;
134 int default_irq_mask;
135 int use_sdio;
136 unsigned int power_mode;
137 struct imxmmc_platform_data *pdata;
138
139 struct mmc_request *req;
140 struct mmc_command *cmd;
141 struct mmc_data *data;
142
143 unsigned int datasize;
144 unsigned int dma_dir;
145
146 u16 rev_no;
147 unsigned int cmdat;
148
149 struct clk *clk_ipg;
150 struct clk *clk_per;
151
152 int clock;
153
154 struct work_struct datawork;
155 spinlock_t lock;
156
157 int burstlen;
158 int dmareq;
159 struct dma_slave_config dma_slave_config;
160 struct imx_dma_data dma_data;
161
162 struct timer_list watchdog;
163 enum mxcmci_type devtype;
164 };
165
166 static const struct platform_device_id mxcmci_devtype[] = {
167 {
168 .name = "imx21-mmc",
169 .driver_data = IMX21_MMC,
170 }, {
171 .name = "imx31-mmc",
172 .driver_data = IMX31_MMC,
173 }, {
174 .name = "mpc512x-sdhc",
175 .driver_data = MPC512X_MMC,
176 }, {
177 /* sentinel */
178 }
179 };
180 MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
181
182 static const struct of_device_id mxcmci_of_match[] = {
183 {
184 .compatible = "fsl,imx21-mmc",
185 .data = &mxcmci_devtype[IMX21_MMC],
186 }, {
187 .compatible = "fsl,imx31-mmc",
188 .data = &mxcmci_devtype[IMX31_MMC],
189 }, {
190 .compatible = "fsl,mpc5121-sdhc",
191 .data = &mxcmci_devtype[MPC512X_MMC],
192 }, {
193 /* sentinel */
194 }
195 };
196 MODULE_DEVICE_TABLE(of, mxcmci_of_match);
197
198 static inline int is_imx31_mmc(struct mxcmci_host *host)
199 {
200 return host->devtype == IMX31_MMC;
201 }
202
203 static inline int is_mpc512x_mmc(struct mxcmci_host *host)
204 {
205 return host->devtype == MPC512X_MMC;
206 }
207
208 static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
209 {
210 if (IS_ENABLED(CONFIG_PPC_MPC512x))
211 return ioread32be(host->base + reg);
212 else
213 return readl(host->base + reg);
214 }
215
216 static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
217 {
218 if (IS_ENABLED(CONFIG_PPC_MPC512x))
219 iowrite32be(val, host->base + reg);
220 else
221 writel(val, host->base + reg);
222 }
223
224 static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
225 {
226 if (IS_ENABLED(CONFIG_PPC_MPC512x))
227 return ioread32be(host->base + reg);
228 else
229 return readw(host->base + reg);
230 }
231
232 static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
233 {
234 if (IS_ENABLED(CONFIG_PPC_MPC512x))
235 iowrite32be(val, host->base + reg);
236 else
237 writew(val, host->base + reg);
238 }
239
240 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
241
242 static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
243 {
244 if (!IS_ERR(host->mmc->supply.vmmc)) {
245 if (host->power_mode == MMC_POWER_UP)
246 mmc_regulator_set_ocr(host->mmc,
247 host->mmc->supply.vmmc, vdd);
248 else if (host->power_mode == MMC_POWER_OFF)
249 mmc_regulator_set_ocr(host->mmc,
250 host->mmc->supply.vmmc, 0);
251 }
252
253 if (host->pdata && host->pdata->setpower)
254 host->pdata->setpower(mmc_dev(host->mmc), vdd);
255 }
256
257 static inline int mxcmci_use_dma(struct mxcmci_host *host)
258 {
259 return host->do_dma;
260 }
261
262 static void mxcmci_softreset(struct mxcmci_host *host)
263 {
264 int i;
265
266 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
267
268 /* reset sequence */
269 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
270 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
271 MMC_REG_STR_STP_CLK);
272
273 for (i = 0; i < 8; i++)
274 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
275
276 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
277 }
278
279 #if IS_ENABLED(CONFIG_PPC_MPC512x)
280 static inline void buffer_swap32(u32 *buf, int len)
281 {
282 int i;
283
284 for (i = 0; i < ((len + 3) / 4); i++) {
285 *buf = swab32(*buf);
286 buf++;
287 }
288 }
289
290 static void mxcmci_swap_buffers(struct mmc_data *data)
291 {
292 struct scatterlist *sg;
293 int i;
294
295 for_each_sg(data->sg, sg, data->sg_len, i)
296 buffer_swap32(sg_virt(sg), sg->length);
297 }
298 #else
299 static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
300 #endif
301
302 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
303 {
304 unsigned int nob = data->blocks;
305 unsigned int blksz = data->blksz;
306 unsigned int datasize = nob * blksz;
307 struct scatterlist *sg;
308 enum dma_transfer_direction slave_dirn;
309 int i, nents;
310
311 host->data = data;
312 data->bytes_xfered = 0;
313
314 mxcmci_writew(host, nob, MMC_REG_NOB);
315 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
316 host->datasize = datasize;
317
318 if (!mxcmci_use_dma(host))
319 return 0;
320
321 for_each_sg(data->sg, sg, data->sg_len, i) {
322 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
323 host->do_dma = 0;
324 return 0;
325 }
326 }
327
328 if (data->flags & MMC_DATA_READ) {
329 host->dma_dir = DMA_FROM_DEVICE;
330 slave_dirn = DMA_DEV_TO_MEM;
331 } else {
332 host->dma_dir = DMA_TO_DEVICE;
333 slave_dirn = DMA_MEM_TO_DEV;
334
335 mxcmci_swap_buffers(data);
336 }
337
338 nents = dma_map_sg(host->dma->device->dev, data->sg,
339 data->sg_len, host->dma_dir);
340 if (nents != data->sg_len)
341 return -EINVAL;
342
343 host->desc = dmaengine_prep_slave_sg(host->dma,
344 data->sg, data->sg_len, slave_dirn,
345 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
346
347 if (!host->desc) {
348 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
349 host->dma_dir);
350 host->do_dma = 0;
351 return 0; /* Fall back to PIO */
352 }
353 wmb();
354
355 dmaengine_submit(host->desc);
356 dma_async_issue_pending(host->dma);
357
358 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
359
360 return 0;
361 }
362
363 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
364 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
365
366 static void mxcmci_dma_callback(void *data)
367 {
368 struct mxcmci_host *host = data;
369 u32 stat;
370
371 del_timer(&host->watchdog);
372
373 stat = mxcmci_readl(host, MMC_REG_STATUS);
374
375 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
376
377 mxcmci_data_done(host, stat);
378 }
379
380 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
381 unsigned int cmdat)
382 {
383 u32 int_cntr = host->default_irq_mask;
384 unsigned long flags;
385
386 WARN_ON(host->cmd != NULL);
387 host->cmd = cmd;
388
389 switch (mmc_resp_type(cmd)) {
390 case MMC_RSP_R1: /* short CRC, OPCODE */
391 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
392 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
393 break;
394 case MMC_RSP_R2: /* long 136 bit + CRC */
395 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
396 break;
397 case MMC_RSP_R3: /* short */
398 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
399 break;
400 case MMC_RSP_NONE:
401 break;
402 default:
403 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
404 mmc_resp_type(cmd));
405 cmd->error = -EINVAL;
406 return -EINVAL;
407 }
408
409 int_cntr = INT_END_CMD_RES_EN;
410
411 if (mxcmci_use_dma(host)) {
412 if (host->dma_dir == DMA_FROM_DEVICE) {
413 host->desc->callback = mxcmci_dma_callback;
414 host->desc->callback_param = host;
415 } else {
416 int_cntr |= INT_WRITE_OP_DONE_EN;
417 }
418 }
419
420 spin_lock_irqsave(&host->lock, flags);
421 if (host->use_sdio)
422 int_cntr |= INT_SDIO_IRQ_EN;
423 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
424 spin_unlock_irqrestore(&host->lock, flags);
425
426 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
427 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
428 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
429
430 return 0;
431 }
432
433 static void mxcmci_finish_request(struct mxcmci_host *host,
434 struct mmc_request *req)
435 {
436 u32 int_cntr = host->default_irq_mask;
437 unsigned long flags;
438
439 spin_lock_irqsave(&host->lock, flags);
440 if (host->use_sdio)
441 int_cntr |= INT_SDIO_IRQ_EN;
442 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
443 spin_unlock_irqrestore(&host->lock, flags);
444
445 host->req = NULL;
446 host->cmd = NULL;
447 host->data = NULL;
448
449 mmc_request_done(host->mmc, req);
450 }
451
452 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
453 {
454 struct mmc_data *data = host->data;
455 int data_error;
456
457 if (mxcmci_use_dma(host)) {
458 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
459 host->dma_dir);
460 mxcmci_swap_buffers(data);
461 }
462
463 if (stat & STATUS_ERR_MASK) {
464 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
465 stat);
466 if (stat & STATUS_CRC_READ_ERR) {
467 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
468 data->error = -EILSEQ;
469 } else if (stat & STATUS_CRC_WRITE_ERR) {
470 u32 err_code = (stat >> 9) & 0x3;
471 if (err_code == 2) { /* No CRC response */
472 dev_err(mmc_dev(host->mmc),
473 "%s: No CRC -ETIMEDOUT\n", __func__);
474 data->error = -ETIMEDOUT;
475 } else {
476 dev_err(mmc_dev(host->mmc),
477 "%s: -EILSEQ\n", __func__);
478 data->error = -EILSEQ;
479 }
480 } else if (stat & STATUS_TIME_OUT_READ) {
481 dev_err(mmc_dev(host->mmc),
482 "%s: read -ETIMEDOUT\n", __func__);
483 data->error = -ETIMEDOUT;
484 } else {
485 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
486 data->error = -EIO;
487 }
488 } else {
489 data->bytes_xfered = host->datasize;
490 }
491
492 data_error = data->error;
493
494 host->data = NULL;
495
496 return data_error;
497 }
498
499 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
500 {
501 struct mmc_command *cmd = host->cmd;
502 int i;
503 u32 a, b, c;
504
505 if (!cmd)
506 return;
507
508 if (stat & STATUS_TIME_OUT_RESP) {
509 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
510 cmd->error = -ETIMEDOUT;
511 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
512 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
513 cmd->error = -EILSEQ;
514 }
515
516 if (cmd->flags & MMC_RSP_PRESENT) {
517 if (cmd->flags & MMC_RSP_136) {
518 for (i = 0; i < 4; i++) {
519 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
520 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
521 cmd->resp[i] = a << 16 | b;
522 }
523 } else {
524 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
525 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
526 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
527 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
528 }
529 }
530 }
531
532 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
533 {
534 u32 stat;
535 unsigned long timeout = jiffies + HZ;
536
537 do {
538 stat = mxcmci_readl(host, MMC_REG_STATUS);
539 if (stat & STATUS_ERR_MASK)
540 return stat;
541 if (time_after(jiffies, timeout)) {
542 mxcmci_softreset(host);
543 mxcmci_set_clk_rate(host, host->clock);
544 return STATUS_TIME_OUT_READ;
545 }
546 if (stat & mask)
547 return 0;
548 cpu_relax();
549 } while (1);
550 }
551
552 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
553 {
554 unsigned int stat;
555 u32 *buf = _buf;
556
557 while (bytes > 3) {
558 stat = mxcmci_poll_status(host,
559 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
560 if (stat)
561 return stat;
562 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
563 bytes -= 4;
564 }
565
566 if (bytes) {
567 u8 *b = (u8 *)buf;
568 u32 tmp;
569
570 stat = mxcmci_poll_status(host,
571 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
572 if (stat)
573 return stat;
574 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
575 memcpy(b, &tmp, bytes);
576 }
577
578 return 0;
579 }
580
581 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
582 {
583 unsigned int stat;
584 u32 *buf = _buf;
585
586 while (bytes > 3) {
587 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
588 if (stat)
589 return stat;
590 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
591 bytes -= 4;
592 }
593
594 if (bytes) {
595 u8 *b = (u8 *)buf;
596 u32 tmp;
597
598 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
599 if (stat)
600 return stat;
601
602 memcpy(&tmp, b, bytes);
603 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
604 }
605
606 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
607 }
608
609 static int mxcmci_transfer_data(struct mxcmci_host *host)
610 {
611 struct mmc_data *data = host->req->data;
612 struct scatterlist *sg;
613 int stat, i;
614
615 host->data = data;
616 host->datasize = 0;
617
618 if (data->flags & MMC_DATA_READ) {
619 for_each_sg(data->sg, sg, data->sg_len, i) {
620 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
621 if (stat)
622 return stat;
623 host->datasize += sg->length;
624 }
625 } else {
626 for_each_sg(data->sg, sg, data->sg_len, i) {
627 stat = mxcmci_push(host, sg_virt(sg), sg->length);
628 if (stat)
629 return stat;
630 host->datasize += sg->length;
631 }
632 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
633 if (stat)
634 return stat;
635 }
636 return 0;
637 }
638
639 static void mxcmci_datawork(struct work_struct *work)
640 {
641 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
642 datawork);
643 int datastat = mxcmci_transfer_data(host);
644
645 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
646 MMC_REG_STATUS);
647 mxcmci_finish_data(host, datastat);
648
649 if (host->req->stop) {
650 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
651 mxcmci_finish_request(host, host->req);
652 return;
653 }
654 } else {
655 mxcmci_finish_request(host, host->req);
656 }
657 }
658
659 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
660 {
661 struct mmc_request *req;
662 int data_error;
663 unsigned long flags;
664
665 spin_lock_irqsave(&host->lock, flags);
666
667 if (!host->data) {
668 spin_unlock_irqrestore(&host->lock, flags);
669 return;
670 }
671
672 if (!host->req) {
673 spin_unlock_irqrestore(&host->lock, flags);
674 return;
675 }
676
677 req = host->req;
678 if (!req->stop)
679 host->req = NULL; /* we will handle finish req below */
680
681 data_error = mxcmci_finish_data(host, stat);
682
683 spin_unlock_irqrestore(&host->lock, flags);
684
685 if (data_error)
686 return;
687
688 mxcmci_read_response(host, stat);
689 host->cmd = NULL;
690
691 if (req->stop) {
692 if (mxcmci_start_cmd(host, req->stop, 0)) {
693 mxcmci_finish_request(host, req);
694 return;
695 }
696 } else {
697 mxcmci_finish_request(host, req);
698 }
699 }
700
701 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
702 {
703 mxcmci_read_response(host, stat);
704 host->cmd = NULL;
705
706 if (!host->data && host->req) {
707 mxcmci_finish_request(host, host->req);
708 return;
709 }
710
711 /* For the DMA case the DMA engine handles the data transfer
712 * automatically. For non DMA we have to do it ourselves.
713 * Don't do it in interrupt context though.
714 */
715 if (!mxcmci_use_dma(host) && host->data)
716 schedule_work(&host->datawork);
717
718 }
719
720 static irqreturn_t mxcmci_irq(int irq, void *devid)
721 {
722 struct mxcmci_host *host = devid;
723 unsigned long flags;
724 bool sdio_irq;
725 u32 stat;
726
727 stat = mxcmci_readl(host, MMC_REG_STATUS);
728 mxcmci_writel(host,
729 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
730 STATUS_WRITE_OP_DONE),
731 MMC_REG_STATUS);
732
733 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
734
735 spin_lock_irqsave(&host->lock, flags);
736 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
737 spin_unlock_irqrestore(&host->lock, flags);
738
739 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
740 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
741
742 if (sdio_irq) {
743 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
744 mmc_signal_sdio_irq(host->mmc);
745 }
746
747 if (stat & STATUS_END_CMD_RESP)
748 mxcmci_cmd_done(host, stat);
749
750 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
751 del_timer(&host->watchdog);
752 mxcmci_data_done(host, stat);
753 }
754
755 if (host->default_irq_mask &&
756 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
757 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
758
759 return IRQ_HANDLED;
760 }
761
762 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
763 {
764 struct mxcmci_host *host = mmc_priv(mmc);
765 unsigned int cmdat = host->cmdat;
766 int error;
767
768 WARN_ON(host->req != NULL);
769
770 host->req = req;
771 host->cmdat &= ~CMD_DAT_CONT_INIT;
772
773 if (host->dma)
774 host->do_dma = 1;
775
776 if (req->data) {
777 error = mxcmci_setup_data(host, req->data);
778 if (error) {
779 req->cmd->error = error;
780 goto out;
781 }
782
783
784 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
785
786 if (req->data->flags & MMC_DATA_WRITE)
787 cmdat |= CMD_DAT_CONT_WRITE;
788 }
789
790 error = mxcmci_start_cmd(host, req->cmd, cmdat);
791
792 out:
793 if (error)
794 mxcmci_finish_request(host, req);
795 }
796
797 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
798 {
799 unsigned int divider;
800 int prescaler = 0;
801 unsigned int clk_in = clk_get_rate(host->clk_per);
802
803 while (prescaler <= 0x800) {
804 for (divider = 1; divider <= 0xF; divider++) {
805 int x;
806
807 x = (clk_in / (divider + 1));
808
809 if (prescaler)
810 x /= (prescaler * 2);
811
812 if (x <= clk_ios)
813 break;
814 }
815 if (divider < 0x10)
816 break;
817
818 if (prescaler == 0)
819 prescaler = 1;
820 else
821 prescaler <<= 1;
822 }
823
824 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
825
826 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
827 prescaler, divider, clk_in, clk_ios);
828 }
829
830 static int mxcmci_setup_dma(struct mmc_host *mmc)
831 {
832 struct mxcmci_host *host = mmc_priv(mmc);
833 struct dma_slave_config *config = &host->dma_slave_config;
834
835 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
836 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
837 config->dst_addr_width = 4;
838 config->src_addr_width = 4;
839 config->dst_maxburst = host->burstlen;
840 config->src_maxburst = host->burstlen;
841 config->device_fc = false;
842
843 return dmaengine_slave_config(host->dma, config);
844 }
845
846 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
847 {
848 struct mxcmci_host *host = mmc_priv(mmc);
849 int burstlen, ret;
850
851 /*
852 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
853 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
854 */
855 if (ios->bus_width == MMC_BUS_WIDTH_4)
856 burstlen = 16;
857 else
858 burstlen = 4;
859
860 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
861 host->burstlen = burstlen;
862 ret = mxcmci_setup_dma(mmc);
863 if (ret) {
864 dev_err(mmc_dev(host->mmc),
865 "failed to config DMA channel. Falling back to PIO\n");
866 dma_release_channel(host->dma);
867 host->do_dma = 0;
868 host->dma = NULL;
869 }
870 }
871
872 if (ios->bus_width == MMC_BUS_WIDTH_4)
873 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
874 else
875 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
876
877 if (host->power_mode != ios->power_mode) {
878 host->power_mode = ios->power_mode;
879 mxcmci_set_power(host, ios->vdd);
880
881 if (ios->power_mode == MMC_POWER_ON)
882 host->cmdat |= CMD_DAT_CONT_INIT;
883 }
884
885 if (ios->clock) {
886 mxcmci_set_clk_rate(host, ios->clock);
887 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
888 } else {
889 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
890 }
891
892 host->clock = ios->clock;
893 }
894
895 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
896 {
897 struct mmc_host *mmc = data;
898
899 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
900
901 mmc_detect_change(mmc, msecs_to_jiffies(250));
902 return IRQ_HANDLED;
903 }
904
905 static int mxcmci_get_ro(struct mmc_host *mmc)
906 {
907 struct mxcmci_host *host = mmc_priv(mmc);
908
909 if (host->pdata && host->pdata->get_ro)
910 return !!host->pdata->get_ro(mmc_dev(mmc));
911 /*
912 * If board doesn't support read only detection (no mmc_gpio
913 * context or gpio is invalid), then let the mmc core decide
914 * what to do.
915 */
916 return mmc_gpio_get_ro(mmc);
917 }
918
919 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
920 {
921 struct mxcmci_host *host = mmc_priv(mmc);
922 unsigned long flags;
923 u32 int_cntr;
924
925 spin_lock_irqsave(&host->lock, flags);
926 host->use_sdio = enable;
927 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
928
929 if (enable)
930 int_cntr |= INT_SDIO_IRQ_EN;
931 else
932 int_cntr &= ~INT_SDIO_IRQ_EN;
933
934 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
935 spin_unlock_irqrestore(&host->lock, flags);
936 }
937
938 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
939 {
940 struct mxcmci_host *mxcmci = mmc_priv(host);
941
942 /*
943 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
944 * multi-block transfers when connected SDIO peripheral doesn't
945 * drive the BUSY line as required by the specs.
946 * One way to prevent this is to only allow 1-bit transfers.
947 */
948
949 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
950 host->caps &= ~MMC_CAP_4_BIT_DATA;
951 else
952 host->caps |= MMC_CAP_4_BIT_DATA;
953 }
954
955 static bool filter(struct dma_chan *chan, void *param)
956 {
957 struct mxcmci_host *host = param;
958
959 if (!imx_dma_is_general_purpose(chan))
960 return false;
961
962 chan->private = &host->dma_data;
963
964 return true;
965 }
966
967 static void mxcmci_watchdog(struct timer_list *t)
968 {
969 struct mxcmci_host *host = from_timer(host, t, watchdog);
970 struct mmc_request *req = host->req;
971 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
972
973 if (host->dma_dir == DMA_FROM_DEVICE) {
974 dmaengine_terminate_all(host->dma);
975 dev_err(mmc_dev(host->mmc),
976 "%s: read time out (status = 0x%08x)\n",
977 __func__, stat);
978 } else {
979 dev_err(mmc_dev(host->mmc),
980 "%s: write time out (status = 0x%08x)\n",
981 __func__, stat);
982 mxcmci_softreset(host);
983 }
984
985 /* Mark transfer as erroneus and inform the upper layers */
986
987 if (host->data)
988 host->data->error = -ETIMEDOUT;
989 host->req = NULL;
990 host->cmd = NULL;
991 host->data = NULL;
992 mmc_request_done(host->mmc, req);
993 }
994
995 static const struct mmc_host_ops mxcmci_ops = {
996 .request = mxcmci_request,
997 .set_ios = mxcmci_set_ios,
998 .get_ro = mxcmci_get_ro,
999 .enable_sdio_irq = mxcmci_enable_sdio_irq,
1000 .init_card = mxcmci_init_card,
1001 };
1002
1003 static int mxcmci_probe(struct platform_device *pdev)
1004 {
1005 struct mmc_host *mmc;
1006 struct mxcmci_host *host;
1007 struct resource *res;
1008 int ret = 0, irq;
1009 bool dat3_card_detect = false;
1010 dma_cap_mask_t mask;
1011 const struct of_device_id *of_id;
1012 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
1013
1014 pr_info("i.MX/MPC512x SDHC driver\n");
1015
1016 of_id = of_match_device(mxcmci_of_match, &pdev->dev);
1017
1018 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1019 irq = platform_get_irq(pdev, 0);
1020 if (irq < 0) {
1021 dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq);
1022 return irq;
1023 }
1024
1025 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1026 if (!mmc)
1027 return -ENOMEM;
1028
1029 host = mmc_priv(mmc);
1030
1031 host->base = devm_ioremap_resource(&pdev->dev, res);
1032 if (IS_ERR(host->base)) {
1033 ret = PTR_ERR(host->base);
1034 goto out_free;
1035 }
1036
1037 host->phys_base = res->start;
1038
1039 ret = mmc_of_parse(mmc);
1040 if (ret)
1041 goto out_free;
1042 mmc->ops = &mxcmci_ops;
1043
1044 /* For devicetree parsing, the bus width is read from devicetree */
1045 if (pdata)
1046 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1047 else
1048 mmc->caps |= MMC_CAP_SDIO_IRQ;
1049
1050 /* MMC core transfer sizes tunable parameters */
1051 mmc->max_blk_size = 2048;
1052 mmc->max_blk_count = 65535;
1053 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1054 mmc->max_seg_size = mmc->max_req_size;
1055
1056 if (of_id) {
1057 const struct platform_device_id *id_entry = of_id->data;
1058 host->devtype = id_entry->driver_data;
1059 } else {
1060 host->devtype = pdev->id_entry->driver_data;
1061 }
1062
1063 /* adjust max_segs after devtype detection */
1064 if (!is_mpc512x_mmc(host))
1065 mmc->max_segs = 64;
1066
1067 host->mmc = mmc;
1068 host->pdata = pdata;
1069 spin_lock_init(&host->lock);
1070
1071 if (pdata)
1072 dat3_card_detect = pdata->dat3_card_detect;
1073 else if (mmc_card_is_removable(mmc)
1074 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1075 dat3_card_detect = true;
1076
1077 ret = mmc_regulator_get_supply(mmc);
1078 if (ret)
1079 goto out_free;
1080
1081 if (!mmc->ocr_avail) {
1082 if (pdata && pdata->ocr_avail)
1083 mmc->ocr_avail = pdata->ocr_avail;
1084 else
1085 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1086 }
1087
1088 if (dat3_card_detect)
1089 host->default_irq_mask =
1090 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1091 else
1092 host->default_irq_mask = 0;
1093
1094 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1095 if (IS_ERR(host->clk_ipg)) {
1096 ret = PTR_ERR(host->clk_ipg);
1097 goto out_free;
1098 }
1099
1100 host->clk_per = devm_clk_get(&pdev->dev, "per");
1101 if (IS_ERR(host->clk_per)) {
1102 ret = PTR_ERR(host->clk_per);
1103 goto out_free;
1104 }
1105
1106 ret = clk_prepare_enable(host->clk_per);
1107 if (ret)
1108 goto out_free;
1109
1110 ret = clk_prepare_enable(host->clk_ipg);
1111 if (ret)
1112 goto out_clk_per_put;
1113
1114 mxcmci_softreset(host);
1115
1116 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
1117 if (host->rev_no != 0x400) {
1118 ret = -ENODEV;
1119 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1120 host->rev_no);
1121 goto out_clk_put;
1122 }
1123
1124 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1125 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
1126
1127 /* recommended in data sheet */
1128 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
1129
1130 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
1131
1132 if (!host->pdata) {
1133 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx");
1134 } else {
1135 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1136 if (res) {
1137 host->dmareq = res->start;
1138 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1139 host->dma_data.priority = DMA_PRIO_LOW;
1140 host->dma_data.dma_request = host->dmareq;
1141 dma_cap_zero(mask);
1142 dma_cap_set(DMA_SLAVE, mask);
1143 host->dma = dma_request_channel(mask, filter, host);
1144 }
1145 }
1146 if (host->dma)
1147 mmc->max_seg_size = dma_get_max_seg_size(
1148 host->dma->device->dev);
1149 else
1150 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
1151
1152 INIT_WORK(&host->datawork, mxcmci_datawork);
1153
1154 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1155 dev_name(&pdev->dev), host);
1156 if (ret)
1157 goto out_free_dma;
1158
1159 platform_set_drvdata(pdev, mmc);
1160
1161 if (host->pdata && host->pdata->init) {
1162 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1163 host->mmc);
1164 if (ret)
1165 goto out_free_dma;
1166 }
1167
1168 timer_setup(&host->watchdog, mxcmci_watchdog, 0);
1169
1170 mmc_add_host(mmc);
1171
1172 return 0;
1173
1174 out_free_dma:
1175 if (host->dma)
1176 dma_release_channel(host->dma);
1177
1178 out_clk_put:
1179 clk_disable_unprepare(host->clk_ipg);
1180 out_clk_per_put:
1181 clk_disable_unprepare(host->clk_per);
1182
1183 out_free:
1184 mmc_free_host(mmc);
1185
1186 return ret;
1187 }
1188
1189 static int mxcmci_remove(struct platform_device *pdev)
1190 {
1191 struct mmc_host *mmc = platform_get_drvdata(pdev);
1192 struct mxcmci_host *host = mmc_priv(mmc);
1193
1194 mmc_remove_host(mmc);
1195
1196 if (host->pdata && host->pdata->exit)
1197 host->pdata->exit(&pdev->dev, mmc);
1198
1199 if (host->dma)
1200 dma_release_channel(host->dma);
1201
1202 clk_disable_unprepare(host->clk_per);
1203 clk_disable_unprepare(host->clk_ipg);
1204
1205 mmc_free_host(mmc);
1206
1207 return 0;
1208 }
1209
1210 #ifdef CONFIG_PM_SLEEP
1211 static int mxcmci_suspend(struct device *dev)
1212 {
1213 struct mmc_host *mmc = dev_get_drvdata(dev);
1214 struct mxcmci_host *host = mmc_priv(mmc);
1215
1216 clk_disable_unprepare(host->clk_per);
1217 clk_disable_unprepare(host->clk_ipg);
1218 return 0;
1219 }
1220
1221 static int mxcmci_resume(struct device *dev)
1222 {
1223 struct mmc_host *mmc = dev_get_drvdata(dev);
1224 struct mxcmci_host *host = mmc_priv(mmc);
1225 int ret;
1226
1227 ret = clk_prepare_enable(host->clk_per);
1228 if (ret)
1229 return ret;
1230
1231 ret = clk_prepare_enable(host->clk_ipg);
1232 if (ret)
1233 clk_disable_unprepare(host->clk_per);
1234
1235 return ret;
1236 }
1237 #endif
1238
1239 static SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
1240
1241 static struct platform_driver mxcmci_driver = {
1242 .probe = mxcmci_probe,
1243 .remove = mxcmci_remove,
1244 .id_table = mxcmci_devtype,
1245 .driver = {
1246 .name = DRIVER_NAME,
1247 .pm = &mxcmci_pm_ops,
1248 .of_match_table = mxcmci_of_match,
1249 }
1250 };
1251
1252 module_platform_driver(mxcmci_driver);
1253
1254 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1255 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1256 MODULE_LICENSE("GPL");
1257 MODULE_ALIAS("platform:mxc-mmc");
Linux with added FPC-III support