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Linux 4.19.133
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-msm.c
blob643fd1a1b88be26e7da9f66f1d1f9591845d7be3
1 /*
2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
3 *
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/delay.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/iopoll.h>
24 #include <linux/regulator/consumer.h>
25
26 #include "sdhci-pltfm.h"
27
28 #define CORE_MCI_VERSION 0x50
29 #define CORE_VERSION_MAJOR_SHIFT 28
30 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
31 #define CORE_VERSION_MINOR_MASK 0xff
32
33 #define CORE_MCI_GENERICS 0x70
34 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
35
36 #define HC_MODE_EN 0x1
37 #define CORE_POWER 0x0
38 #define CORE_SW_RST BIT(7)
39 #define FF_CLK_SW_RST_DIS BIT(13)
40
41 #define CORE_PWRCTL_BUS_OFF BIT(0)
42 #define CORE_PWRCTL_BUS_ON BIT(1)
43 #define CORE_PWRCTL_IO_LOW BIT(2)
44 #define CORE_PWRCTL_IO_HIGH BIT(3)
45 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
46 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
47 #define REQ_BUS_OFF BIT(0)
48 #define REQ_BUS_ON BIT(1)
49 #define REQ_IO_LOW BIT(2)
50 #define REQ_IO_HIGH BIT(3)
51 #define INT_MASK 0xf
52 #define MAX_PHASES 16
53 #define CORE_DLL_LOCK BIT(7)
54 #define CORE_DDR_DLL_LOCK BIT(11)
55 #define CORE_DLL_EN BIT(16)
56 #define CORE_CDR_EN BIT(17)
57 #define CORE_CK_OUT_EN BIT(18)
58 #define CORE_CDR_EXT_EN BIT(19)
59 #define CORE_DLL_PDN BIT(29)
60 #define CORE_DLL_RST BIT(30)
61 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
62
63 #define CORE_DDR_CAL_EN BIT(0)
64 #define CORE_FLL_CYCLE_CNT BIT(18)
65 #define CORE_DLL_CLOCK_DISABLE BIT(21)
66
67 #define CORE_VENDOR_SPEC_POR_VAL 0xa1c
68 #define CORE_CLK_PWRSAVE BIT(1)
69 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
70 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
71 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
72 #define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
73 #define CORE_IO_PAD_PWR_SWITCH (1 << 16)
74 #define CORE_HC_SELECT_IN_EN BIT(18)
75 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
76 #define CORE_HC_SELECT_IN_MASK (7 << 19)
77
78 #define CORE_3_0V_SUPPORT (1 << 25)
79 #define CORE_1_8V_SUPPORT (1 << 26)
80 #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
81
82 #define CORE_CSR_CDC_CTLR_CFG0 0x130
83 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
84 #define CORE_HW_AUTOCAL_ENA BIT(17)
85
86 #define CORE_CSR_CDC_CTLR_CFG1 0x134
87 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
88 #define CORE_TIMER_ENA BIT(16)
89
90 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
91 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
92 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
93 #define CORE_CDC_OFFSET_CFG 0x14C
94 #define CORE_CSR_CDC_DELAY_CFG 0x150
95 #define CORE_CDC_SLAVE_DDA_CFG 0x160
96 #define CORE_CSR_CDC_STATUS0 0x164
97 #define CORE_CALIBRATION_DONE BIT(0)
98
99 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
100
101 #define CORE_CSR_CDC_GEN_CFG 0x178
102 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
103 #define CORE_CDC_SWITCH_RC_EN BIT(1)
104
105 #define CORE_CDC_T4_DLY_SEL BIT(0)
106 #define CORE_CMDIN_RCLK_EN BIT(1)
107 #define CORE_START_CDC_TRAFFIC BIT(6)
108
109 #define CORE_PWRSAVE_DLL BIT(3)
110
111 #define DDR_CONFIG_POR_VAL 0x80040873
112
113
114 #define INVALID_TUNING_PHASE -1
115 #define SDHCI_MSM_MIN_CLOCK 400000
116 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
117
118 #define CDR_SELEXT_SHIFT 20
119 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
120 #define CMUX_SHIFT_PHASE_SHIFT 24
121 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
122
123 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
124
125 /* Timeout value to avoid infinite waiting for pwr_irq */
126 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
127
128 #define msm_host_readl(msm_host, host, offset) \
129 msm_host->var_ops->msm_readl_relaxed(host, offset)
130
131 #define msm_host_writel(msm_host, val, host, offset) \
132 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
133
134 struct sdhci_msm_offset {
135 u32 core_hc_mode;
136 u32 core_mci_data_cnt;
137 u32 core_mci_status;
138 u32 core_mci_fifo_cnt;
139 u32 core_mci_version;
140 u32 core_generics;
141 u32 core_testbus_config;
142 u32 core_testbus_sel2_bit;
143 u32 core_testbus_ena;
144 u32 core_testbus_sel2;
145 u32 core_pwrctl_status;
146 u32 core_pwrctl_mask;
147 u32 core_pwrctl_clear;
148 u32 core_pwrctl_ctl;
149 u32 core_sdcc_debug_reg;
150 u32 core_dll_config;
151 u32 core_dll_status;
152 u32 core_vendor_spec;
153 u32 core_vendor_spec_adma_err_addr0;
154 u32 core_vendor_spec_adma_err_addr1;
155 u32 core_vendor_spec_func2;
156 u32 core_vendor_spec_capabilities0;
157 u32 core_ddr_200_cfg;
158 u32 core_vendor_spec3;
159 u32 core_dll_config_2;
160 u32 core_dll_config_3;
161 u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
162 u32 core_ddr_config;
163 };
164
165 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
166 .core_mci_data_cnt = 0x35c,
167 .core_mci_status = 0x324,
168 .core_mci_fifo_cnt = 0x308,
169 .core_mci_version = 0x318,
170 .core_generics = 0x320,
171 .core_testbus_config = 0x32c,
172 .core_testbus_sel2_bit = 3,
173 .core_testbus_ena = (1 << 31),
174 .core_testbus_sel2 = (1 << 3),
175 .core_pwrctl_status = 0x240,
176 .core_pwrctl_mask = 0x244,
177 .core_pwrctl_clear = 0x248,
178 .core_pwrctl_ctl = 0x24c,
179 .core_sdcc_debug_reg = 0x358,
180 .core_dll_config = 0x200,
181 .core_dll_status = 0x208,
182 .core_vendor_spec = 0x20c,
183 .core_vendor_spec_adma_err_addr0 = 0x214,
184 .core_vendor_spec_adma_err_addr1 = 0x218,
185 .core_vendor_spec_func2 = 0x210,
186 .core_vendor_spec_capabilities0 = 0x21c,
187 .core_ddr_200_cfg = 0x224,
188 .core_vendor_spec3 = 0x250,
189 .core_dll_config_2 = 0x254,
190 .core_dll_config_3 = 0x258,
191 .core_ddr_config = 0x25c,
192 };
193
194 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
195 .core_hc_mode = 0x78,
196 .core_mci_data_cnt = 0x30,
197 .core_mci_status = 0x34,
198 .core_mci_fifo_cnt = 0x44,
199 .core_mci_version = 0x050,
200 .core_generics = 0x70,
201 .core_testbus_config = 0x0cc,
202 .core_testbus_sel2_bit = 4,
203 .core_testbus_ena = (1 << 3),
204 .core_testbus_sel2 = (1 << 4),
205 .core_pwrctl_status = 0xdc,
206 .core_pwrctl_mask = 0xe0,
207 .core_pwrctl_clear = 0xe4,
208 .core_pwrctl_ctl = 0xe8,
209 .core_sdcc_debug_reg = 0x124,
210 .core_dll_config = 0x100,
211 .core_dll_status = 0x108,
212 .core_vendor_spec = 0x10c,
213 .core_vendor_spec_adma_err_addr0 = 0x114,
214 .core_vendor_spec_adma_err_addr1 = 0x118,
215 .core_vendor_spec_func2 = 0x110,
216 .core_vendor_spec_capabilities0 = 0x11c,
217 .core_ddr_200_cfg = 0x184,
218 .core_vendor_spec3 = 0x1b0,
219 .core_dll_config_2 = 0x1b4,
220 .core_ddr_config_old = 0x1b8,
221 .core_ddr_config = 0x1bc,
222 };
223
224 struct sdhci_msm_variant_ops {
225 u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
226 void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
227 u32 offset);
228 };
229
230 /*
231 * From V5, register spaces have changed. Wrap this info in a structure
232 * and choose the data_structure based on version info mentioned in DT.
233 */
234 struct sdhci_msm_variant_info {
235 bool mci_removed;
236 const struct sdhci_msm_variant_ops *var_ops;
237 const struct sdhci_msm_offset *offset;
238 };
239
240 struct sdhci_msm_host {
241 struct platform_device *pdev;
242 void __iomem *core_mem; /* MSM SDCC mapped address */
243 int pwr_irq; /* power irq */
244 struct clk *bus_clk; /* SDHC bus voter clock */
245 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
246 struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
247 unsigned long clk_rate;
248 struct mmc_host *mmc;
249 bool use_14lpp_dll_reset;
250 bool tuning_done;
251 bool calibration_done;
252 u8 saved_tuning_phase;
253 bool use_cdclp533;
254 u32 curr_pwr_state;
255 u32 curr_io_level;
256 wait_queue_head_t pwr_irq_wait;
257 bool pwr_irq_flag;
258 u32 caps_0;
259 bool mci_removed;
260 const struct sdhci_msm_variant_ops *var_ops;
261 const struct sdhci_msm_offset *offset;
262 bool use_cdr;
263 u32 transfer_mode;
264 bool updated_ddr_cfg;
265 };
266
267 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
268 {
269 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
270 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
271
272 return msm_host->offset;
273 }
274
275 /*
276 * APIs to read/write to vendor specific registers which were there in the
277 * core_mem region before MCI was removed.
278 */
279 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
280 u32 offset)
281 {
282 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
283 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
284
285 return readl_relaxed(msm_host->core_mem + offset);
286 }
287
288 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
289 u32 offset)
290 {
291 return readl_relaxed(host->ioaddr + offset);
292 }
293
294 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
295 struct sdhci_host *host, u32 offset)
296 {
297 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
298 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
299
300 writel_relaxed(val, msm_host->core_mem + offset);
301 }
302
303 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
304 struct sdhci_host *host, u32 offset)
305 {
306 writel_relaxed(val, host->ioaddr + offset);
307 }
308
309 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
310 unsigned int clock)
311 {
312 struct mmc_ios ios = host->mmc->ios;
313 /*
314 * The SDHC requires internal clock frequency to be double the
315 * actual clock that will be set for DDR mode. The controller
316 * uses the faster clock(100/400MHz) for some of its parts and
317 * send the actual required clock (50/200MHz) to the card.
318 */
319 if (ios.timing == MMC_TIMING_UHS_DDR50 ||
320 ios.timing == MMC_TIMING_MMC_DDR52 ||
321 ios.timing == MMC_TIMING_MMC_HS400 ||
322 host->flags & SDHCI_HS400_TUNING)
323 clock *= 2;
324 return clock;
325 }
326
327 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
328 unsigned int clock)
329 {
330 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
331 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
332 struct mmc_ios curr_ios = host->mmc->ios;
333 struct clk *core_clk = msm_host->bulk_clks[0].clk;
334 int rc;
335
336 clock = msm_get_clock_rate_for_bus_mode(host, clock);
337 rc = clk_set_rate(core_clk, clock);
338 if (rc) {
339 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
340 mmc_hostname(host->mmc), clock,
341 curr_ios.timing);
342 return;
343 }
344 msm_host->clk_rate = clock;
345 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
346 mmc_hostname(host->mmc), clk_get_rate(core_clk),
347 curr_ios.timing);
348 }
349
350 /* Platform specific tuning */
351 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
352 {
353 u32 wait_cnt = 50;
354 u8 ck_out_en;
355 struct mmc_host *mmc = host->mmc;
356 const struct sdhci_msm_offset *msm_offset =
357 sdhci_priv_msm_offset(host);
358
359 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
360 ck_out_en = !!(readl_relaxed(host->ioaddr +
361 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
362
363 while (ck_out_en != poll) {
364 if (--wait_cnt == 0) {
365 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
366 mmc_hostname(mmc), poll);
367 return -ETIMEDOUT;
368 }
369 udelay(1);
370
371 ck_out_en = !!(readl_relaxed(host->ioaddr +
372 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
373 }
374
375 return 0;
376 }
377
378 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
379 {
380 int rc;
381 static const u8 grey_coded_phase_table[] = {
382 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
383 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
384 };
385 unsigned long flags;
386 u32 config;
387 struct mmc_host *mmc = host->mmc;
388 const struct sdhci_msm_offset *msm_offset =
389 sdhci_priv_msm_offset(host);
390
391 if (phase > 0xf)
392 return -EINVAL;
393
394 spin_lock_irqsave(&host->lock, flags);
395
396 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
397 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
398 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
399 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
400
401 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
402 rc = msm_dll_poll_ck_out_en(host, 0);
403 if (rc)
404 goto err_out;
405
406 /*
407 * Write the selected DLL clock output phase (0 ... 15)
408 * to CDR_SELEXT bit field of DLL_CONFIG register.
409 */
410 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
411 config &= ~CDR_SELEXT_MASK;
412 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
413 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
414
415 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
416 config |= CORE_CK_OUT_EN;
417 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
418
419 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
420 rc = msm_dll_poll_ck_out_en(host, 1);
421 if (rc)
422 goto err_out;
423
424 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
425 config |= CORE_CDR_EN;
426 config &= ~CORE_CDR_EXT_EN;
427 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
428 goto out;
429
430 err_out:
431 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
432 mmc_hostname(mmc), phase);
433 out:
434 spin_unlock_irqrestore(&host->lock, flags);
435 return rc;
436 }
437
438 /*
439 * Find out the greatest range of consecuitive selected
440 * DLL clock output phases that can be used as sampling
441 * setting for SD3.0 UHS-I card read operation (in SDR104
442 * timing mode) or for eMMC4.5 card read operation (in
443 * HS400/HS200 timing mode).
444 * Select the 3/4 of the range and configure the DLL with the
445 * selected DLL clock output phase.
446 */
447
448 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
449 u8 *phase_table, u8 total_phases)
450 {
451 int ret;
452 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
453 u8 phases_per_row[MAX_PHASES] = { 0 };
454 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
455 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
456 bool phase_0_found = false, phase_15_found = false;
457 struct mmc_host *mmc = host->mmc;
458
459 if (!total_phases || (total_phases > MAX_PHASES)) {
460 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
461 mmc_hostname(mmc), total_phases);
462 return -EINVAL;
463 }
464
465 for (cnt = 0; cnt < total_phases; cnt++) {
466 ranges[row_index][col_index] = phase_table[cnt];
467 phases_per_row[row_index] += 1;
468 col_index++;
469
470 if ((cnt + 1) == total_phases) {
471 continue;
472 /* check if next phase in phase_table is consecutive or not */
473 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
474 row_index++;
475 col_index = 0;
476 }
477 }
478
479 if (row_index >= MAX_PHASES)
480 return -EINVAL;
481
482 /* Check if phase-0 is present in first valid window? */
483 if (!ranges[0][0]) {
484 phase_0_found = true;
485 phase_0_raw_index = 0;
486 /* Check if cycle exist between 2 valid windows */
487 for (cnt = 1; cnt <= row_index; cnt++) {
488 if (phases_per_row[cnt]) {
489 for (i = 0; i < phases_per_row[cnt]; i++) {
490 if (ranges[cnt][i] == 15) {
491 phase_15_found = true;
492 phase_15_raw_index = cnt;
493 break;
494 }
495 }
496 }
497 }
498 }
499
500 /* If 2 valid windows form cycle then merge them as single window */
501 if (phase_0_found && phase_15_found) {
502 /* number of phases in raw where phase 0 is present */
503 u8 phases_0 = phases_per_row[phase_0_raw_index];
504 /* number of phases in raw where phase 15 is present */
505 u8 phases_15 = phases_per_row[phase_15_raw_index];
506
507 if (phases_0 + phases_15 >= MAX_PHASES)
508 /*
509 * If there are more than 1 phase windows then total
510 * number of phases in both the windows should not be
511 * more than or equal to MAX_PHASES.
512 */
513 return -EINVAL;
514
515 /* Merge 2 cyclic windows */
516 i = phases_15;
517 for (cnt = 0; cnt < phases_0; cnt++) {
518 ranges[phase_15_raw_index][i] =
519 ranges[phase_0_raw_index][cnt];
520 if (++i >= MAX_PHASES)
521 break;
522 }
523
524 phases_per_row[phase_0_raw_index] = 0;
525 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
526 }
527
528 for (cnt = 0; cnt <= row_index; cnt++) {
529 if (phases_per_row[cnt] > curr_max) {
530 curr_max = phases_per_row[cnt];
531 selected_row_index = cnt;
532 }
533 }
534
535 i = (curr_max * 3) / 4;
536 if (i)
537 i--;
538
539 ret = ranges[selected_row_index][i];
540
541 if (ret >= MAX_PHASES) {
542 ret = -EINVAL;
543 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
544 mmc_hostname(mmc), ret);
545 }
546
547 return ret;
548 }
549
550 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
551 {
552 u32 mclk_freq = 0, config;
553 const struct sdhci_msm_offset *msm_offset =
554 sdhci_priv_msm_offset(host);
555
556 /* Program the MCLK value to MCLK_FREQ bit field */
557 if (host->clock <= 112000000)
558 mclk_freq = 0;
559 else if (host->clock <= 125000000)
560 mclk_freq = 1;
561 else if (host->clock <= 137000000)
562 mclk_freq = 2;
563 else if (host->clock <= 150000000)
564 mclk_freq = 3;
565 else if (host->clock <= 162000000)
566 mclk_freq = 4;
567 else if (host->clock <= 175000000)
568 mclk_freq = 5;
569 else if (host->clock <= 187000000)
570 mclk_freq = 6;
571 else if (host->clock <= 200000000)
572 mclk_freq = 7;
573
574 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
575 config &= ~CMUX_SHIFT_PHASE_MASK;
576 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
577 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
578 }
579
580 /* Initialize the DLL (Programmable Delay Line) */
581 static int msm_init_cm_dll(struct sdhci_host *host)
582 {
583 struct mmc_host *mmc = host->mmc;
584 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
585 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
586 int wait_cnt = 50;
587 unsigned long flags, xo_clk = 0;
588 u32 config;
589 const struct sdhci_msm_offset *msm_offset =
590 msm_host->offset;
591
592 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
593 xo_clk = clk_get_rate(msm_host->xo_clk);
594
595 spin_lock_irqsave(&host->lock, flags);
596
597 /*
598 * Make sure that clock is always enabled when DLL
599 * tuning is in progress. Keeping PWRSAVE ON may
600 * turn off the clock.
601 */
602 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
603 config &= ~CORE_CLK_PWRSAVE;
604 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
605
606 if (msm_host->use_14lpp_dll_reset) {
607 config = readl_relaxed(host->ioaddr +
608 msm_offset->core_dll_config);
609 config &= ~CORE_CK_OUT_EN;
610 writel_relaxed(config, host->ioaddr +
611 msm_offset->core_dll_config);
612
613 config = readl_relaxed(host->ioaddr +
614 msm_offset->core_dll_config_2);
615 config |= CORE_DLL_CLOCK_DISABLE;
616 writel_relaxed(config, host->ioaddr +
617 msm_offset->core_dll_config_2);
618 }
619
620 config = readl_relaxed(host->ioaddr +
621 msm_offset->core_dll_config);
622 config |= CORE_DLL_RST;
623 writel_relaxed(config, host->ioaddr +
624 msm_offset->core_dll_config);
625
626 config = readl_relaxed(host->ioaddr +
627 msm_offset->core_dll_config);
628 config |= CORE_DLL_PDN;
629 writel_relaxed(config, host->ioaddr +
630 msm_offset->core_dll_config);
631 msm_cm_dll_set_freq(host);
632
633 if (msm_host->use_14lpp_dll_reset &&
634 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
635 u32 mclk_freq = 0;
636
637 config = readl_relaxed(host->ioaddr +
638 msm_offset->core_dll_config_2);
639 config &= CORE_FLL_CYCLE_CNT;
640 if (config)
641 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
642 xo_clk);
643 else
644 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
645 xo_clk);
646
647 config = readl_relaxed(host->ioaddr +
648 msm_offset->core_dll_config_2);
649 config &= ~(0xFF << 10);
650 config |= mclk_freq << 10;
651
652 writel_relaxed(config, host->ioaddr +
653 msm_offset->core_dll_config_2);
654 /* wait for 5us before enabling DLL clock */
655 udelay(5);
656 }
657
658 config = readl_relaxed(host->ioaddr +
659 msm_offset->core_dll_config);
660 config &= ~CORE_DLL_RST;
661 writel_relaxed(config, host->ioaddr +
662 msm_offset->core_dll_config);
663
664 config = readl_relaxed(host->ioaddr +
665 msm_offset->core_dll_config);
666 config &= ~CORE_DLL_PDN;
667 writel_relaxed(config, host->ioaddr +
668 msm_offset->core_dll_config);
669
670 if (msm_host->use_14lpp_dll_reset) {
671 msm_cm_dll_set_freq(host);
672 config = readl_relaxed(host->ioaddr +
673 msm_offset->core_dll_config_2);
674 config &= ~CORE_DLL_CLOCK_DISABLE;
675 writel_relaxed(config, host->ioaddr +
676 msm_offset->core_dll_config_2);
677 }
678
679 config = readl_relaxed(host->ioaddr +
680 msm_offset->core_dll_config);
681 config |= CORE_DLL_EN;
682 writel_relaxed(config, host->ioaddr +
683 msm_offset->core_dll_config);
684
685 config = readl_relaxed(host->ioaddr +
686 msm_offset->core_dll_config);
687 config |= CORE_CK_OUT_EN;
688 writel_relaxed(config, host->ioaddr +
689 msm_offset->core_dll_config);
690
691 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
692 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
693 CORE_DLL_LOCK)) {
694 /* max. wait for 50us sec for LOCK bit to be set */
695 if (--wait_cnt == 0) {
696 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
697 mmc_hostname(mmc));
698 spin_unlock_irqrestore(&host->lock, flags);
699 return -ETIMEDOUT;
700 }
701 udelay(1);
702 }
703
704 spin_unlock_irqrestore(&host->lock, flags);
705 return 0;
706 }
707
708 static void msm_hc_select_default(struct sdhci_host *host)
709 {
710 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
711 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
712 u32 config;
713 const struct sdhci_msm_offset *msm_offset =
714 msm_host->offset;
715
716 if (!msm_host->use_cdclp533) {
717 config = readl_relaxed(host->ioaddr +
718 msm_offset->core_vendor_spec3);
719 config &= ~CORE_PWRSAVE_DLL;
720 writel_relaxed(config, host->ioaddr +
721 msm_offset->core_vendor_spec3);
722 }
723
724 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
725 config &= ~CORE_HC_MCLK_SEL_MASK;
726 config |= CORE_HC_MCLK_SEL_DFLT;
727 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
728
729 /*
730 * Disable HC_SELECT_IN to be able to use the UHS mode select
731 * configuration from Host Control2 register for all other
732 * modes.
733 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
734 * in VENDOR_SPEC_FUNC
735 */
736 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
737 config &= ~CORE_HC_SELECT_IN_EN;
738 config &= ~CORE_HC_SELECT_IN_MASK;
739 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
740
741 /*
742 * Make sure above writes impacting free running MCLK are completed
743 * before changing the clk_rate at GCC.
744 */
745 wmb();
746 }
747
748 static void msm_hc_select_hs400(struct sdhci_host *host)
749 {
750 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
751 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
752 struct mmc_ios ios = host->mmc->ios;
753 u32 config, dll_lock;
754 int rc;
755 const struct sdhci_msm_offset *msm_offset =
756 msm_host->offset;
757
758 /* Select the divided clock (free running MCLK/2) */
759 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
760 config &= ~CORE_HC_MCLK_SEL_MASK;
761 config |= CORE_HC_MCLK_SEL_HS400;
762
763 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
764 /*
765 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
766 * register
767 */
768 if ((msm_host->tuning_done || ios.enhanced_strobe) &&
769 !msm_host->calibration_done) {
770 config = readl_relaxed(host->ioaddr +
771 msm_offset->core_vendor_spec);
772 config |= CORE_HC_SELECT_IN_HS400;
773 config |= CORE_HC_SELECT_IN_EN;
774 writel_relaxed(config, host->ioaddr +
775 msm_offset->core_vendor_spec);
776 }
777 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
778 /*
779 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
780 * core_dll_status to be set. This should get set
781 * within 15 us at 200 MHz.
782 */
783 rc = readl_relaxed_poll_timeout(host->ioaddr +
784 msm_offset->core_dll_status,
785 dll_lock,
786 (dll_lock &
787 (CORE_DLL_LOCK |
788 CORE_DDR_DLL_LOCK)), 10,
789 1000);
790 if (rc == -ETIMEDOUT)
791 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
792 mmc_hostname(host->mmc), dll_lock);
793 }
794 /*
795 * Make sure above writes impacting free running MCLK are completed
796 * before changing the clk_rate at GCC.
797 */
798 wmb();
799 }
800
801 /*
802 * sdhci_msm_hc_select_mode :- In general all timing modes are
803 * controlled via UHS mode select in Host Control2 register.
804 * eMMC specific HS200/HS400 doesn't have their respective modes
805 * defined here, hence we use these values.
806 *
807 * HS200 - SDR104 (Since they both are equivalent in functionality)
808 * HS400 - This involves multiple configurations
809 * Initially SDR104 - when tuning is required as HS200
810 * Then when switching to DDR @ 400MHz (HS400) we use
811 * the vendor specific HC_SELECT_IN to control the mode.
812 *
813 * In addition to controlling the modes we also need to select the
814 * correct input clock for DLL depending on the mode.
815 *
816 * HS400 - divided clock (free running MCLK/2)
817 * All other modes - default (free running MCLK)
818 */
819 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
820 {
821 struct mmc_ios ios = host->mmc->ios;
822
823 if (ios.timing == MMC_TIMING_MMC_HS400 ||
824 host->flags & SDHCI_HS400_TUNING)
825 msm_hc_select_hs400(host);
826 else
827 msm_hc_select_default(host);
828 }
829
830 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
831 {
832 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
833 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
834 u32 config, calib_done;
835 int ret;
836 const struct sdhci_msm_offset *msm_offset =
837 msm_host->offset;
838
839 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
840
841 /*
842 * Retuning in HS400 (DDR mode) will fail, just reset the
843 * tuning block and restore the saved tuning phase.
844 */
845 ret = msm_init_cm_dll(host);
846 if (ret)
847 goto out;
848
849 /* Set the selected phase in delay line hw block */
850 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
851 if (ret)
852 goto out;
853
854 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
855 config |= CORE_CMD_DAT_TRACK_SEL;
856 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
857
858 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
859 config &= ~CORE_CDC_T4_DLY_SEL;
860 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
861
862 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
863 config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
864 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
865
866 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
867 config |= CORE_CDC_SWITCH_RC_EN;
868 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
869
870 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
871 config &= ~CORE_START_CDC_TRAFFIC;
872 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
873
874 /* Perform CDC Register Initialization Sequence */
875
876 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
877 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
878 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
879 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
880 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
881 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
882 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
883 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
884 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
885
886 /* CDC HW Calibration */
887
888 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
889 config |= CORE_SW_TRIG_FULL_CALIB;
890 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
891
892 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
893 config &= ~CORE_SW_TRIG_FULL_CALIB;
894 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
895
896 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
897 config |= CORE_HW_AUTOCAL_ENA;
898 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
899
900 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
901 config |= CORE_TIMER_ENA;
902 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
903
904 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
905 calib_done,
906 (calib_done & CORE_CALIBRATION_DONE),
907 1, 50);
908
909 if (ret == -ETIMEDOUT) {
910 pr_err("%s: %s: CDC calibration was not completed\n",
911 mmc_hostname(host->mmc), __func__);
912 goto out;
913 }
914
915 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
916 & CORE_CDC_ERROR_CODE_MASK;
917 if (ret) {
918 pr_err("%s: %s: CDC error code %d\n",
919 mmc_hostname(host->mmc), __func__, ret);
920 ret = -EINVAL;
921 goto out;
922 }
923
924 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
925 config |= CORE_START_CDC_TRAFFIC;
926 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
927 out:
928 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
929 __func__, ret);
930 return ret;
931 }
932
933 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
934 {
935 struct mmc_host *mmc = host->mmc;
936 u32 dll_status, config, ddr_cfg_offset;
937 int ret;
938 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
939 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
940 const struct sdhci_msm_offset *msm_offset =
941 sdhci_priv_msm_offset(host);
942
943 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
944
945 /*
946 * Currently the core_ddr_config register defaults to desired
947 * configuration on reset. Currently reprogramming the power on
948 * reset (POR) value in case it might have been modified by
949 * bootloaders. In the future, if this changes, then the desired
950 * values will need to be programmed appropriately.
951 */
952 if (msm_host->updated_ddr_cfg)
953 ddr_cfg_offset = msm_offset->core_ddr_config;
954 else
955 ddr_cfg_offset = msm_offset->core_ddr_config_old;
956 writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + ddr_cfg_offset);
957
958 if (mmc->ios.enhanced_strobe) {
959 config = readl_relaxed(host->ioaddr +
960 msm_offset->core_ddr_200_cfg);
961 config |= CORE_CMDIN_RCLK_EN;
962 writel_relaxed(config, host->ioaddr +
963 msm_offset->core_ddr_200_cfg);
964 }
965
966 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
967 config |= CORE_DDR_CAL_EN;
968 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
969
970 ret = readl_relaxed_poll_timeout(host->ioaddr +
971 msm_offset->core_dll_status,
972 dll_status,
973 (dll_status & CORE_DDR_DLL_LOCK),
974 10, 1000);
975
976 if (ret == -ETIMEDOUT) {
977 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
978 mmc_hostname(host->mmc), __func__);
979 goto out;
980 }
981
982 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3);
983 config |= CORE_PWRSAVE_DLL;
984 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3);
985
986 /*
987 * Drain writebuffer to ensure above DLL calibration
988 * and PWRSAVE DLL is enabled.
989 */
990 wmb();
991 out:
992 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
993 __func__, ret);
994 return ret;
995 }
996
997 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
998 {
999 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1000 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1001 struct mmc_host *mmc = host->mmc;
1002 int ret;
1003 u32 config;
1004 const struct sdhci_msm_offset *msm_offset =
1005 msm_host->offset;
1006
1007 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1008
1009 /*
1010 * Retuning in HS400 (DDR mode) will fail, just reset the
1011 * tuning block and restore the saved tuning phase.
1012 */
1013 ret = msm_init_cm_dll(host);
1014 if (ret)
1015 goto out;
1016
1017 if (!mmc->ios.enhanced_strobe) {
1018 /* Set the selected phase in delay line hw block */
1019 ret = msm_config_cm_dll_phase(host,
1020 msm_host->saved_tuning_phase);
1021 if (ret)
1022 goto out;
1023 config = readl_relaxed(host->ioaddr +
1024 msm_offset->core_dll_config);
1025 config |= CORE_CMD_DAT_TRACK_SEL;
1026 writel_relaxed(config, host->ioaddr +
1027 msm_offset->core_dll_config);
1028 }
1029
1030 if (msm_host->use_cdclp533)
1031 ret = sdhci_msm_cdclp533_calibration(host);
1032 else
1033 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1034 out:
1035 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1036 __func__, ret);
1037 return ret;
1038 }
1039
1040 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1041 {
1042 const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1043 u32 config, oldconfig = readl_relaxed(host->ioaddr +
1044 msm_offset->core_dll_config);
1045
1046 config = oldconfig;
1047 if (enable) {
1048 config |= CORE_CDR_EN;
1049 config &= ~CORE_CDR_EXT_EN;
1050 } else {
1051 config &= ~CORE_CDR_EN;
1052 config |= CORE_CDR_EXT_EN;
1053 }
1054
1055 if (config != oldconfig)
1056 writel_relaxed(config, host->ioaddr +
1057 msm_offset->core_dll_config);
1058 }
1059
1060 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1061 {
1062 struct sdhci_host *host = mmc_priv(mmc);
1063 int tuning_seq_cnt = 3;
1064 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1065 int rc;
1066 struct mmc_ios ios = host->mmc->ios;
1067 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1068 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1069
1070 /*
1071 * Tuning is required for SDR104, HS200 and HS400 cards and
1072 * if clock frequency is greater than 100MHz in these modes.
1073 */
1074 if (host->clock <= CORE_FREQ_100MHZ ||
1075 !(ios.timing == MMC_TIMING_MMC_HS400 ||
1076 ios.timing == MMC_TIMING_MMC_HS200 ||
1077 ios.timing == MMC_TIMING_UHS_SDR104)) {
1078 msm_host->use_cdr = false;
1079 sdhci_msm_set_cdr(host, false);
1080 return 0;
1081 }
1082
1083 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1084 msm_host->use_cdr = true;
1085
1086 /*
1087 * Clear tuning_done flag before tuning to ensure proper
1088 * HS400 settings.
1089 */
1090 msm_host->tuning_done = 0;
1091
1092 /*
1093 * For HS400 tuning in HS200 timing requires:
1094 * - select MCLK/2 in VENDOR_SPEC
1095 * - program MCLK to 400MHz (or nearest supported) in GCC
1096 */
1097 if (host->flags & SDHCI_HS400_TUNING) {
1098 sdhci_msm_hc_select_mode(host);
1099 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1100 host->flags &= ~SDHCI_HS400_TUNING;
1101 }
1102
1103 retry:
1104 /* First of all reset the tuning block */
1105 rc = msm_init_cm_dll(host);
1106 if (rc)
1107 return rc;
1108
1109 phase = 0;
1110 do {
1111 /* Set the phase in delay line hw block */
1112 rc = msm_config_cm_dll_phase(host, phase);
1113 if (rc)
1114 return rc;
1115
1116 msm_host->saved_tuning_phase = phase;
1117 rc = mmc_send_tuning(mmc, opcode, NULL);
1118 if (!rc) {
1119 /* Tuning is successful at this tuning point */
1120 tuned_phases[tuned_phase_cnt++] = phase;
1121 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1122 mmc_hostname(mmc), phase);
1123 }
1124 } while (++phase < ARRAY_SIZE(tuned_phases));
1125
1126 if (tuned_phase_cnt) {
1127 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1128 tuned_phase_cnt);
1129 if (rc < 0)
1130 return rc;
1131 else
1132 phase = rc;
1133
1134 /*
1135 * Finally set the selected phase in delay
1136 * line hw block.
1137 */
1138 rc = msm_config_cm_dll_phase(host, phase);
1139 if (rc)
1140 return rc;
1141 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1142 mmc_hostname(mmc), phase);
1143 } else {
1144 if (--tuning_seq_cnt)
1145 goto retry;
1146 /* Tuning failed */
1147 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1148 mmc_hostname(mmc));
1149 rc = -EIO;
1150 }
1151
1152 if (!rc)
1153 msm_host->tuning_done = true;
1154 return rc;
1155 }
1156
1157 /*
1158 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1159 * This needs to be done for both tuning and enhanced_strobe mode.
1160 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1161 * fixed feedback clock is used.
1162 */
1163 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1164 {
1165 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1166 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1167 int ret;
1168
1169 if (host->clock > CORE_FREQ_100MHZ &&
1170 (msm_host->tuning_done || ios->enhanced_strobe) &&
1171 !msm_host->calibration_done) {
1172 ret = sdhci_msm_hs400_dll_calibration(host);
1173 if (!ret)
1174 msm_host->calibration_done = true;
1175 else
1176 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1177 mmc_hostname(host->mmc), ret);
1178 }
1179 }
1180
1181 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1182 unsigned int uhs)
1183 {
1184 struct mmc_host *mmc = host->mmc;
1185 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1186 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1187 u16 ctrl_2;
1188 u32 config;
1189 const struct sdhci_msm_offset *msm_offset =
1190 msm_host->offset;
1191
1192 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1193 /* Select Bus Speed Mode for host */
1194 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1195 switch (uhs) {
1196 case MMC_TIMING_UHS_SDR12:
1197 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1198 break;
1199 case MMC_TIMING_UHS_SDR25:
1200 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1201 break;
1202 case MMC_TIMING_UHS_SDR50:
1203 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1204 break;
1205 case MMC_TIMING_MMC_HS400:
1206 case MMC_TIMING_MMC_HS200:
1207 case MMC_TIMING_UHS_SDR104:
1208 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1209 break;
1210 case MMC_TIMING_UHS_DDR50:
1211 case MMC_TIMING_MMC_DDR52:
1212 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1213 break;
1214 }
1215
1216 /*
1217 * When clock frequency is less than 100MHz, the feedback clock must be
1218 * provided and DLL must not be used so that tuning can be skipped. To
1219 * provide feedback clock, the mode selection can be any value less
1220 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1221 */
1222 if (host->clock <= CORE_FREQ_100MHZ) {
1223 if (uhs == MMC_TIMING_MMC_HS400 ||
1224 uhs == MMC_TIMING_MMC_HS200 ||
1225 uhs == MMC_TIMING_UHS_SDR104)
1226 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1227 /*
1228 * DLL is not required for clock <= 100MHz
1229 * Thus, make sure DLL it is disabled when not required
1230 */
1231 config = readl_relaxed(host->ioaddr +
1232 msm_offset->core_dll_config);
1233 config |= CORE_DLL_RST;
1234 writel_relaxed(config, host->ioaddr +
1235 msm_offset->core_dll_config);
1236
1237 config = readl_relaxed(host->ioaddr +
1238 msm_offset->core_dll_config);
1239 config |= CORE_DLL_PDN;
1240 writel_relaxed(config, host->ioaddr +
1241 msm_offset->core_dll_config);
1242
1243 /*
1244 * The DLL needs to be restored and CDCLP533 recalibrated
1245 * when the clock frequency is set back to 400MHz.
1246 */
1247 msm_host->calibration_done = false;
1248 }
1249
1250 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1251 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1252 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1253
1254 if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1255 sdhci_msm_hs400(host, &mmc->ios);
1256 }
1257
1258 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1259 {
1260 init_waitqueue_head(&msm_host->pwr_irq_wait);
1261 }
1262
1263 static inline void sdhci_msm_complete_pwr_irq_wait(
1264 struct sdhci_msm_host *msm_host)
1265 {
1266 wake_up(&msm_host->pwr_irq_wait);
1267 }
1268
1269 /*
1270 * sdhci_msm_check_power_status API should be called when registers writes
1271 * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1272 * To what state the register writes will change the IO lines should be passed
1273 * as the argument req_type. This API will check whether the IO line's state
1274 * is already the expected state and will wait for power irq only if
1275 * power irq is expected to be trigerred based on the current IO line state
1276 * and expected IO line state.
1277 */
1278 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1279 {
1280 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1281 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1282 bool done = false;
1283 u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1284 const struct sdhci_msm_offset *msm_offset =
1285 msm_host->offset;
1286
1287 pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1288 mmc_hostname(host->mmc), __func__, req_type,
1289 msm_host->curr_pwr_state, msm_host->curr_io_level);
1290
1291 /*
1292 * The power interrupt will not be generated for signal voltage
1293 * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1294 * Since sdhci-msm-v5, this bit has been removed and SW must consider
1295 * it as always set.
1296 */
1297 if (!msm_host->mci_removed)
1298 val = msm_host_readl(msm_host, host,
1299 msm_offset->core_generics);
1300 if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1301 !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1302 return;
1303 }
1304
1305 /*
1306 * The IRQ for request type IO High/LOW will be generated when -
1307 * there is a state change in 1.8V enable bit (bit 3) of
1308 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1309 * which indicates 3.3V IO voltage. So, when MMC core layer tries
1310 * to set it to 3.3V before card detection happens, the
1311 * IRQ doesn't get triggered as there is no state change in this bit.
1312 * The driver already handles this case by changing the IO voltage
1313 * level to high as part of controller power up sequence. Hence, check
1314 * for host->pwr to handle a case where IO voltage high request is
1315 * issued even before controller power up.
1316 */
1317 if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1318 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1319 mmc_hostname(host->mmc), req_type);
1320 return;
1321 }
1322 if ((req_type & msm_host->curr_pwr_state) ||
1323 (req_type & msm_host->curr_io_level))
1324 done = true;
1325 /*
1326 * This is needed here to handle cases where register writes will
1327 * not change the current bus state or io level of the controller.
1328 * In this case, no power irq will be triggerred and we should
1329 * not wait.
1330 */
1331 if (!done) {
1332 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1333 msm_host->pwr_irq_flag,
1334 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1335 dev_warn(&msm_host->pdev->dev,
1336 "%s: pwr_irq for req: (%d) timed out\n",
1337 mmc_hostname(host->mmc), req_type);
1338 }
1339 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1340 __func__, req_type);
1341 }
1342
1343 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1344 {
1345 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1346 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1347 const struct sdhci_msm_offset *msm_offset =
1348 msm_host->offset;
1349
1350 pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1351 mmc_hostname(host->mmc),
1352 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1353 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1354 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1355 }
1356
1357 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1358 {
1359 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1360 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1361 u32 irq_status, irq_ack = 0;
1362 int retry = 10;
1363 u32 pwr_state = 0, io_level = 0;
1364 u32 config;
1365 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1366
1367 irq_status = msm_host_readl(msm_host, host,
1368 msm_offset->core_pwrctl_status);
1369 irq_status &= INT_MASK;
1370
1371 msm_host_writel(msm_host, irq_status, host,
1372 msm_offset->core_pwrctl_clear);
1373
1374 /*
1375 * There is a rare HW scenario where the first clear pulse could be
1376 * lost when actual reset and clear/read of status register is
1377 * happening at a time. Hence, retry for at least 10 times to make
1378 * sure status register is cleared. Otherwise, this will result in
1379 * a spurious power IRQ resulting in system instability.
1380 */
1381 while (irq_status & msm_host_readl(msm_host, host,
1382 msm_offset->core_pwrctl_status)) {
1383 if (retry == 0) {
1384 pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1385 mmc_hostname(host->mmc), irq_status);
1386 sdhci_msm_dump_pwr_ctrl_regs(host);
1387 WARN_ON(1);
1388 break;
1389 }
1390 msm_host_writel(msm_host, irq_status, host,
1391 msm_offset->core_pwrctl_clear);
1392 retry--;
1393 udelay(10);
1394 }
1395
1396 /* Handle BUS ON/OFF*/
1397 if (irq_status & CORE_PWRCTL_BUS_ON) {
1398 pwr_state = REQ_BUS_ON;
1399 io_level = REQ_IO_HIGH;
1400 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1401 }
1402 if (irq_status & CORE_PWRCTL_BUS_OFF) {
1403 pwr_state = REQ_BUS_OFF;
1404 io_level = REQ_IO_LOW;
1405 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1406 }
1407 /* Handle IO LOW/HIGH */
1408 if (irq_status & CORE_PWRCTL_IO_LOW) {
1409 io_level = REQ_IO_LOW;
1410 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1411 }
1412 if (irq_status & CORE_PWRCTL_IO_HIGH) {
1413 io_level = REQ_IO_HIGH;
1414 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1415 }
1416
1417 /*
1418 * The driver has to acknowledge the interrupt, switch voltages and
1419 * report back if it succeded or not to this register. The voltage
1420 * switches are handled by the sdhci core, so just report success.
1421 */
1422 msm_host_writel(msm_host, irq_ack, host,
1423 msm_offset->core_pwrctl_ctl);
1424
1425 /*
1426 * If we don't have info regarding the voltage levels supported by
1427 * regulators, don't change the IO PAD PWR SWITCH.
1428 */
1429 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1430 u32 new_config;
1431 /*
1432 * We should unset IO PAD PWR switch only if the register write
1433 * can set IO lines high and the regulator also switches to 3 V.
1434 * Else, we should keep the IO PAD PWR switch set.
1435 * This is applicable to certain targets where eMMC vccq supply
1436 * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1437 * IO PAD PWR switch must be kept set to reflect actual
1438 * regulator voltage. This way, during initialization of
1439 * controllers with only 1.8V, we will set the IO PAD bit
1440 * without waiting for a REQ_IO_LOW.
1441 */
1442 config = readl_relaxed(host->ioaddr +
1443 msm_offset->core_vendor_spec);
1444 new_config = config;
1445
1446 if ((io_level & REQ_IO_HIGH) &&
1447 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1448 new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1449 else if ((io_level & REQ_IO_LOW) ||
1450 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1451 new_config |= CORE_IO_PAD_PWR_SWITCH;
1452
1453 if (config ^ new_config)
1454 writel_relaxed(new_config, host->ioaddr +
1455 msm_offset->core_vendor_spec);
1456 }
1457
1458 if (pwr_state)
1459 msm_host->curr_pwr_state = pwr_state;
1460 if (io_level)
1461 msm_host->curr_io_level = io_level;
1462
1463 pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1464 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1465 irq_ack);
1466 }
1467
1468 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1469 {
1470 struct sdhci_host *host = (struct sdhci_host *)data;
1471 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1472 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1473
1474 sdhci_msm_handle_pwr_irq(host, irq);
1475 msm_host->pwr_irq_flag = 1;
1476 sdhci_msm_complete_pwr_irq_wait(msm_host);
1477
1478
1479 return IRQ_HANDLED;
1480 }
1481
1482 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1483 {
1484 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1485 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1486 struct clk *core_clk = msm_host->bulk_clks[0].clk;
1487
1488 return clk_round_rate(core_clk, ULONG_MAX);
1489 }
1490
1491 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1492 {
1493 return SDHCI_MSM_MIN_CLOCK;
1494 }
1495
1496 /**
1497 * __sdhci_msm_set_clock - sdhci_msm clock control.
1498 *
1499 * Description:
1500 * MSM controller does not use internal divider and
1501 * instead directly control the GCC clock as per
1502 * HW recommendation.
1503 **/
1504 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1505 {
1506 u16 clk;
1507 /*
1508 * Keep actual_clock as zero -
1509 * - since there is no divider used so no need of having actual_clock.
1510 * - MSM controller uses SDCLK for data timeout calculation. If
1511 * actual_clock is zero, host->clock is taken for calculation.
1512 */
1513 host->mmc->actual_clock = 0;
1514
1515 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1516
1517 if (clock == 0)
1518 return;
1519
1520 /*
1521 * MSM controller do not use clock divider.
1522 * Thus read SDHCI_CLOCK_CONTROL and only enable
1523 * clock with no divider value programmed.
1524 */
1525 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1526 sdhci_enable_clk(host, clk);
1527 }
1528
1529 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1530 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1531 {
1532 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1533 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1534
1535 if (!clock) {
1536 msm_host->clk_rate = clock;
1537 goto out;
1538 }
1539
1540 sdhci_msm_hc_select_mode(host);
1541
1542 msm_set_clock_rate_for_bus_mode(host, clock);
1543 out:
1544 __sdhci_msm_set_clock(host, clock);
1545 }
1546
1547 /*
1548 * Platform specific register write functions. This is so that, if any
1549 * register write needs to be followed up by platform specific actions,
1550 * they can be added here. These functions can go to sleep when writes
1551 * to certain registers are done.
1552 * These functions are relying on sdhci_set_ios not using spinlock.
1553 */
1554 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1555 {
1556 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1557 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1558 u32 req_type = 0;
1559
1560 switch (reg) {
1561 case SDHCI_HOST_CONTROL2:
1562 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1563 REQ_IO_HIGH;
1564 break;
1565 case SDHCI_SOFTWARE_RESET:
1566 if (host->pwr && (val & SDHCI_RESET_ALL))
1567 req_type = REQ_BUS_OFF;
1568 break;
1569 case SDHCI_POWER_CONTROL:
1570 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1571 break;
1572 case SDHCI_TRANSFER_MODE:
1573 msm_host->transfer_mode = val;
1574 break;
1575 case SDHCI_COMMAND:
1576 if (!msm_host->use_cdr)
1577 break;
1578 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
1579 SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 &&
1580 SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)
1581 sdhci_msm_set_cdr(host, true);
1582 else
1583 sdhci_msm_set_cdr(host, false);
1584 break;
1585 }
1586
1587 if (req_type) {
1588 msm_host->pwr_irq_flag = 0;
1589 /*
1590 * Since this register write may trigger a power irq, ensure
1591 * all previous register writes are complete by this point.
1592 */
1593 mb();
1594 }
1595 return req_type;
1596 }
1597
1598 /* This function may sleep*/
1599 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1600 {
1601 u32 req_type = 0;
1602
1603 req_type = __sdhci_msm_check_write(host, val, reg);
1604 writew_relaxed(val, host->ioaddr + reg);
1605
1606 if (req_type)
1607 sdhci_msm_check_power_status(host, req_type);
1608 }
1609
1610 /* This function may sleep*/
1611 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1612 {
1613 u32 req_type = 0;
1614
1615 req_type = __sdhci_msm_check_write(host, val, reg);
1616
1617 writeb_relaxed(val, host->ioaddr + reg);
1618
1619 if (req_type)
1620 sdhci_msm_check_power_status(host, req_type);
1621 }
1622
1623 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
1624 {
1625 struct mmc_host *mmc = msm_host->mmc;
1626 struct regulator *supply = mmc->supply.vqmmc;
1627 u32 caps = 0, config;
1628 struct sdhci_host *host = mmc_priv(mmc);
1629 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1630
1631 if (!IS_ERR(mmc->supply.vqmmc)) {
1632 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
1633 caps |= CORE_1_8V_SUPPORT;
1634 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
1635 caps |= CORE_3_0V_SUPPORT;
1636
1637 if (!caps)
1638 pr_warn("%s: 1.8/3V not supported for vqmmc\n",
1639 mmc_hostname(mmc));
1640 }
1641
1642 if (caps) {
1643 /*
1644 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
1645 * bit can be used as required later on.
1646 */
1647 u32 io_level = msm_host->curr_io_level;
1648
1649 config = readl_relaxed(host->ioaddr +
1650 msm_offset->core_vendor_spec);
1651 config |= CORE_IO_PAD_PWR_SWITCH_EN;
1652
1653 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
1654 config &= ~CORE_IO_PAD_PWR_SWITCH;
1655 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
1656 config |= CORE_IO_PAD_PWR_SWITCH;
1657
1658 writel_relaxed(config,
1659 host->ioaddr + msm_offset->core_vendor_spec);
1660 }
1661 msm_host->caps_0 |= caps;
1662 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
1663 }
1664
1665 static const struct sdhci_msm_variant_ops mci_var_ops = {
1666 .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
1667 .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
1668 };
1669
1670 static const struct sdhci_msm_variant_ops v5_var_ops = {
1671 .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
1672 .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
1673 };
1674
1675 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
1676 .mci_removed = false,
1677 .var_ops = &mci_var_ops,
1678 .offset = &sdhci_msm_mci_offset,
1679 };
1680
1681 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
1682 .mci_removed = true,
1683 .var_ops = &v5_var_ops,
1684 .offset = &sdhci_msm_v5_offset,
1685 };
1686
1687 static const struct of_device_id sdhci_msm_dt_match[] = {
1688 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
1689 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
1690 {},
1691 };
1692
1693 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1694
1695 static const struct sdhci_ops sdhci_msm_ops = {
1696 .reset = sdhci_reset,
1697 .set_clock = sdhci_msm_set_clock,
1698 .get_min_clock = sdhci_msm_get_min_clock,
1699 .get_max_clock = sdhci_msm_get_max_clock,
1700 .set_bus_width = sdhci_set_bus_width,
1701 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1702 .write_w = sdhci_msm_writew,
1703 .write_b = sdhci_msm_writeb,
1704 };
1705
1706 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1707 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1708 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1709 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1710 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
1711
1712 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1713 .ops = &sdhci_msm_ops,
1714 };
1715
1716 static int sdhci_msm_probe(struct platform_device *pdev)
1717 {
1718 struct sdhci_host *host;
1719 struct sdhci_pltfm_host *pltfm_host;
1720 struct sdhci_msm_host *msm_host;
1721 struct resource *core_memres;
1722 struct clk *clk;
1723 int ret;
1724 u16 host_version, core_minor;
1725 u32 core_version, config;
1726 u8 core_major;
1727 const struct sdhci_msm_offset *msm_offset;
1728 const struct sdhci_msm_variant_info *var_info;
1729
1730 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1731 if (IS_ERR(host))
1732 return PTR_ERR(host);
1733
1734 host->sdma_boundary = 0;
1735 pltfm_host = sdhci_priv(host);
1736 msm_host = sdhci_pltfm_priv(pltfm_host);
1737 msm_host->mmc = host->mmc;
1738 msm_host->pdev = pdev;
1739
1740 ret = mmc_of_parse(host->mmc);
1741 if (ret)
1742 goto pltfm_free;
1743
1744 /*
1745 * Based on the compatible string, load the required msm host info from
1746 * the data associated with the version info.
1747 */
1748 var_info = of_device_get_match_data(&pdev->dev);
1749
1750 msm_host->mci_removed = var_info->mci_removed;
1751 msm_host->var_ops = var_info->var_ops;
1752 msm_host->offset = var_info->offset;
1753
1754 msm_offset = msm_host->offset;
1755
1756 sdhci_get_of_property(pdev);
1757
1758 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1759
1760 /* Setup SDCC bus voter clock. */
1761 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1762 if (!IS_ERR(msm_host->bus_clk)) {
1763 /* Vote for max. clk rate for max. performance */
1764 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1765 if (ret)
1766 goto pltfm_free;
1767 ret = clk_prepare_enable(msm_host->bus_clk);
1768 if (ret)
1769 goto pltfm_free;
1770 }
1771
1772 /* Setup main peripheral bus clock */
1773 clk = devm_clk_get(&pdev->dev, "iface");
1774 if (IS_ERR(clk)) {
1775 ret = PTR_ERR(clk);
1776 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1777 goto bus_clk_disable;
1778 }
1779 msm_host->bulk_clks[1].clk = clk;
1780
1781 /* Setup SDC MMC clock */
1782 clk = devm_clk_get(&pdev->dev, "core");
1783 if (IS_ERR(clk)) {
1784 ret = PTR_ERR(clk);
1785 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1786 goto bus_clk_disable;
1787 }
1788 msm_host->bulk_clks[0].clk = clk;
1789
1790 /* Vote for maximum clock rate for maximum performance */
1791 ret = clk_set_rate(clk, INT_MAX);
1792 if (ret)
1793 dev_warn(&pdev->dev, "core clock boost failed\n");
1794
1795 clk = devm_clk_get(&pdev->dev, "cal");
1796 if (IS_ERR(clk))
1797 clk = NULL;
1798 msm_host->bulk_clks[2].clk = clk;
1799
1800 clk = devm_clk_get(&pdev->dev, "sleep");
1801 if (IS_ERR(clk))
1802 clk = NULL;
1803 msm_host->bulk_clks[3].clk = clk;
1804
1805 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1806 msm_host->bulk_clks);
1807 if (ret)
1808 goto bus_clk_disable;
1809
1810 /*
1811 * xo clock is needed for FLL feature of cm_dll.
1812 * In case if xo clock is not mentioned in DT, warn and proceed.
1813 */
1814 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1815 if (IS_ERR(msm_host->xo_clk)) {
1816 ret = PTR_ERR(msm_host->xo_clk);
1817 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1818 }
1819
1820 if (!msm_host->mci_removed) {
1821 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1822 msm_host->core_mem = devm_ioremap_resource(&pdev->dev,
1823 core_memres);
1824
1825 if (IS_ERR(msm_host->core_mem)) {
1826 ret = PTR_ERR(msm_host->core_mem);
1827 goto clk_disable;
1828 }
1829 }
1830
1831 /* Reset the vendor spec register to power on reset state */
1832 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
1833 host->ioaddr + msm_offset->core_vendor_spec);
1834
1835 if (!msm_host->mci_removed) {
1836 /* Set HC_MODE_EN bit in HC_MODE register */
1837 msm_host_writel(msm_host, HC_MODE_EN, host,
1838 msm_offset->core_hc_mode);
1839 config = msm_host_readl(msm_host, host,
1840 msm_offset->core_hc_mode);
1841 config |= FF_CLK_SW_RST_DIS;
1842 msm_host_writel(msm_host, config, host,
1843 msm_offset->core_hc_mode);
1844 }
1845
1846 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1847 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1848 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1849 SDHCI_VENDOR_VER_SHIFT));
1850
1851 core_version = msm_host_readl(msm_host, host,
1852 msm_offset->core_mci_version);
1853 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1854 CORE_VERSION_MAJOR_SHIFT;
1855 core_minor = core_version & CORE_VERSION_MINOR_MASK;
1856 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1857 core_version, core_major, core_minor);
1858
1859 if (core_major == 1 && core_minor >= 0x42)
1860 msm_host->use_14lpp_dll_reset = true;
1861
1862 /*
1863 * SDCC 5 controller with major version 1, minor version 0x34 and later
1864 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1865 */
1866 if (core_major == 1 && core_minor < 0x34)
1867 msm_host->use_cdclp533 = true;
1868
1869 /*
1870 * Support for some capabilities is not advertised by newer
1871 * controller versions and must be explicitly enabled.
1872 */
1873 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1874 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1875 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1876 writel_relaxed(config, host->ioaddr +
1877 msm_offset->core_vendor_spec_capabilities0);
1878 }
1879
1880 if (core_major == 1 && core_minor >= 0x49)
1881 msm_host->updated_ddr_cfg = true;
1882
1883 /*
1884 * Power on reset state may trigger power irq if previous status of
1885 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1886 * interrupt in GIC, any pending power irq interrupt should be
1887 * acknowledged. Otherwise power irq interrupt handler would be
1888 * fired prematurely.
1889 */
1890 sdhci_msm_handle_pwr_irq(host, 0);
1891
1892 /*
1893 * Ensure that above writes are propogated before interrupt enablement
1894 * in GIC.
1895 */
1896 mb();
1897
1898 /* Setup IRQ for handling power/voltage tasks with PMIC */
1899 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1900 if (msm_host->pwr_irq < 0) {
1901 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
1902 msm_host->pwr_irq);
1903 ret = msm_host->pwr_irq;
1904 goto clk_disable;
1905 }
1906
1907 sdhci_msm_init_pwr_irq_wait(msm_host);
1908 /* Enable pwr irq interrupts */
1909 msm_host_writel(msm_host, INT_MASK, host,
1910 msm_offset->core_pwrctl_mask);
1911
1912 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1913 sdhci_msm_pwr_irq, IRQF_ONESHOT,
1914 dev_name(&pdev->dev), host);
1915 if (ret) {
1916 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1917 goto clk_disable;
1918 }
1919
1920 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
1921
1922 pm_runtime_get_noresume(&pdev->dev);
1923 pm_runtime_set_active(&pdev->dev);
1924 pm_runtime_enable(&pdev->dev);
1925 pm_runtime_set_autosuspend_delay(&pdev->dev,
1926 MSM_MMC_AUTOSUSPEND_DELAY_MS);
1927 pm_runtime_use_autosuspend(&pdev->dev);
1928
1929 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
1930 ret = sdhci_add_host(host);
1931 if (ret)
1932 goto pm_runtime_disable;
1933 sdhci_msm_set_regulator_caps(msm_host);
1934
1935 pm_runtime_mark_last_busy(&pdev->dev);
1936 pm_runtime_put_autosuspend(&pdev->dev);
1937
1938 return 0;
1939
1940 pm_runtime_disable:
1941 pm_runtime_disable(&pdev->dev);
1942 pm_runtime_set_suspended(&pdev->dev);
1943 pm_runtime_put_noidle(&pdev->dev);
1944 clk_disable:
1945 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1946 msm_host->bulk_clks);
1947 bus_clk_disable:
1948 if (!IS_ERR(msm_host->bus_clk))
1949 clk_disable_unprepare(msm_host->bus_clk);
1950 pltfm_free:
1951 sdhci_pltfm_free(pdev);
1952 return ret;
1953 }
1954
1955 static int sdhci_msm_remove(struct platform_device *pdev)
1956 {
1957 struct sdhci_host *host = platform_get_drvdata(pdev);
1958 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1959 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1960 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1961 0xffffffff);
1962
1963 sdhci_remove_host(host, dead);
1964
1965 pm_runtime_get_sync(&pdev->dev);
1966 pm_runtime_disable(&pdev->dev);
1967 pm_runtime_put_noidle(&pdev->dev);
1968
1969 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1970 msm_host->bulk_clks);
1971 if (!IS_ERR(msm_host->bus_clk))
1972 clk_disable_unprepare(msm_host->bus_clk);
1973 sdhci_pltfm_free(pdev);
1974 return 0;
1975 }
1976
1977 #ifdef CONFIG_PM
1978 static int sdhci_msm_runtime_suspend(struct device *dev)
1979 {
1980 struct sdhci_host *host = dev_get_drvdata(dev);
1981 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1982 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1983
1984 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1985 msm_host->bulk_clks);
1986
1987 return 0;
1988 }
1989
1990 static int sdhci_msm_runtime_resume(struct device *dev)
1991 {
1992 struct sdhci_host *host = dev_get_drvdata(dev);
1993 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1994 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1995
1996 return clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1997 msm_host->bulk_clks);
1998 }
1999 #endif
2000
2001 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2002 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2003 pm_runtime_force_resume)
2004 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
2005 sdhci_msm_runtime_resume,
2006 NULL)
2007 };
2008
2009 static struct platform_driver sdhci_msm_driver = {
2010 .probe = sdhci_msm_probe,
2011 .remove = sdhci_msm_remove,
2012 .driver = {
2013 .name = "sdhci_msm",
2014 .of_match_table = sdhci_msm_dt_match,
2015 .pm = &sdhci_msm_pm_ops,
2016 },
2017 };
2018
2019 module_platform_driver(sdhci_msm_driver);
2020
2021 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2022 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support