drivers/mmc/host/sdhci.h

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
   3  *
   4  * Header file for Host Controller registers and I/O accessors.
   5  *
   6  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or (at
  11  * your option) any later version.
  12  */
  13 #ifndef __SDHCI_HW_H
  14 #define __SDHCI_HW_H
  15
  16 #include <linux/scatterlist.h>
  17 #include <linux/compiler.h>
  18 #include <linux/types.h>
  19 #include <linux/io.h>
  20 #include <linux/leds.h>
  21 #include <linux/interrupt.h>
  22
  23 #include <linux/mmc/host.h>
  24
  25 /*
  26  * Controller registers
  27  */
  28
  29 #define SDHCI_DMA_ADDRESS       0x00
  30 #define SDHCI_ARGUMENT2         SDHCI_DMA_ADDRESS
  31
  32 #define SDHCI_BLOCK_SIZE        0x04
  33 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  34
  35 #define SDHCI_BLOCK_COUNT       0x06
  36
  37 #define SDHCI_ARGUMENT          0x08
  38
  39 #define SDHCI_TRANSFER_MODE     0x0C
  40 #define  SDHCI_TRNS_DMA         0x01
  41 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
  42 #define  SDHCI_TRNS_AUTO_CMD12  0x04
  43 #define  SDHCI_TRNS_AUTO_CMD23  0x08
  44 #define  SDHCI_TRNS_READ        0x10
  45 #define  SDHCI_TRNS_MULTI       0x20
  46
  47 #define SDHCI_COMMAND           0x0E
  48 #define  SDHCI_CMD_RESP_MASK    0x03
  49 #define  SDHCI_CMD_CRC          0x08
  50 #define  SDHCI_CMD_INDEX        0x10
  51 #define  SDHCI_CMD_DATA         0x20
  52 #define  SDHCI_CMD_ABORTCMD     0xC0
  53
  54 #define  SDHCI_CMD_RESP_NONE    0x00
  55 #define  SDHCI_CMD_RESP_LONG    0x01
  56 #define  SDHCI_CMD_RESP_SHORT   0x02
  57 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
  58
  59 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  60 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  61
  62 #define SDHCI_RESPONSE          0x10
  63
  64 #define SDHCI_BUFFER            0x20
  65
  66 #define SDHCI_PRESENT_STATE     0x24
  67 #define  SDHCI_CMD_INHIBIT      0x00000001
  68 #define  SDHCI_DATA_INHIBIT     0x00000002
  69 #define  SDHCI_DOING_WRITE      0x00000100
  70 #define  SDHCI_DOING_READ       0x00000200
  71 #define  SDHCI_SPACE_AVAILABLE  0x00000400
  72 #define  SDHCI_DATA_AVAILABLE   0x00000800
  73 #define  SDHCI_CARD_PRESENT     0x00010000
  74 #define  SDHCI_WRITE_PROTECT    0x00080000
  75 #define  SDHCI_DATA_LVL_MASK    0x00F00000
  76 #define   SDHCI_DATA_LVL_SHIFT  20
  77 #define   SDHCI_DATA_0_LVL_MASK 0x00100000
  78 #define  SDHCI_CMD_LVL          0x01000000
  79
  80 #define SDHCI_HOST_CONTROL      0x28
  81 #define  SDHCI_CTRL_LED         0x01
  82 #define  SDHCI_CTRL_4BITBUS     0x02
  83 #define  SDHCI_CTRL_HISPD       0x04
  84 #define  SDHCI_CTRL_DMA_MASK    0x18
  85 #define   SDHCI_CTRL_SDMA       0x00
  86 #define   SDHCI_CTRL_ADMA1      0x08
  87 #define   SDHCI_CTRL_ADMA32     0x10
  88 #define   SDHCI_CTRL_ADMA64     0x18
  89 #define   SDHCI_CTRL_8BITBUS    0x20
  90 #define  SDHCI_CTRL_CDTEST_INS  0x40
  91 #define  SDHCI_CTRL_CDTEST_EN   0x80
  92
  93 #define SDHCI_POWER_CONTROL     0x29
  94 #define  SDHCI_POWER_ON         0x01
  95 #define  SDHCI_POWER_180        0x0A
  96 #define  SDHCI_POWER_300        0x0C
  97 #define  SDHCI_POWER_330        0x0E
  98
  99 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
 100
 101 #define SDHCI_WAKE_UP_CONTROL   0x2B
 102 #define  SDHCI_WAKE_ON_INT      0x01
 103 #define  SDHCI_WAKE_ON_INSERT   0x02
 104 #define  SDHCI_WAKE_ON_REMOVE   0x04
 105
 106 #define SDHCI_CLOCK_CONTROL     0x2C
 107 #define  SDHCI_DIVIDER_SHIFT    8
 108 #define  SDHCI_DIVIDER_HI_SHIFT 6
 109 #define  SDHCI_DIV_MASK 0xFF
 110 #define  SDHCI_DIV_MASK_LEN     8
 111 #define  SDHCI_DIV_HI_MASK      0x300
 112 #define  SDHCI_PROG_CLOCK_MODE  0x0020
 113 #define  SDHCI_CLOCK_CARD_EN    0x0004
 114 #define  SDHCI_CLOCK_INT_STABLE 0x0002
 115 #define  SDHCI_CLOCK_INT_EN     0x0001
 116
 117 #define SDHCI_TIMEOUT_CONTROL   0x2E
 118
 119 #define SDHCI_SOFTWARE_RESET    0x2F
 120 #define  SDHCI_RESET_ALL        0x01
 121 #define  SDHCI_RESET_CMD        0x02
 122 #define  SDHCI_RESET_DATA       0x04
 123
 124 #define SDHCI_INT_STATUS        0x30
 125 #define SDHCI_INT_ENABLE        0x34
 126 #define SDHCI_SIGNAL_ENABLE     0x38
 127 #define  SDHCI_INT_RESPONSE     0x00000001
 128 #define  SDHCI_INT_DATA_END     0x00000002
 129 #define  SDHCI_INT_BLK_GAP      0x00000004
 130 #define  SDHCI_INT_DMA_END      0x00000008
 131 #define  SDHCI_INT_SPACE_AVAIL  0x00000010
 132 #define  SDHCI_INT_DATA_AVAIL   0x00000020
 133 #define  SDHCI_INT_CARD_INSERT  0x00000040
 134 #define  SDHCI_INT_CARD_REMOVE  0x00000080
 135 #define  SDHCI_INT_CARD_INT     0x00000100
 136 #define  SDHCI_INT_RETUNE       0x00001000
 137 #define  SDHCI_INT_CQE          0x00004000
 138 #define  SDHCI_INT_ERROR        0x00008000
 139 #define  SDHCI_INT_TIMEOUT      0x00010000
 140 #define  SDHCI_INT_CRC          0x00020000
 141 #define  SDHCI_INT_END_BIT      0x00040000
 142 #define  SDHCI_INT_INDEX        0x00080000
 143 #define  SDHCI_INT_DATA_TIMEOUT 0x00100000
 144 #define  SDHCI_INT_DATA_CRC     0x00200000
 145 #define  SDHCI_INT_DATA_END_BIT 0x00400000
 146 #define  SDHCI_INT_BUS_POWER    0x00800000
 147 #define  SDHCI_INT_AUTO_CMD_ERR 0x01000000
 148 #define  SDHCI_INT_ADMA_ERROR   0x02000000
 149
 150 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 151 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 152
 153 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 154                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
 155                 SDHCI_INT_AUTO_CMD_ERR)
 156 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 157                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 158                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 159                 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
 160                 SDHCI_INT_BLK_GAP)
 161 #define SDHCI_INT_ALL_MASK      ((unsigned int)-1)
 162
 163 #define SDHCI_CQE_INT_ERR_MASK ( \
 164         SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \
 165         SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \
 166         SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
 167
 168 #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
 169
 170 #define SDHCI_AUTO_CMD_STATUS   0x3C
 171 #define  SDHCI_AUTO_CMD_TIMEOUT 0x00000002
 172 #define  SDHCI_AUTO_CMD_CRC     0x00000004
 173 #define  SDHCI_AUTO_CMD_END_BIT 0x00000008
 174 #define  SDHCI_AUTO_CMD_INDEX   0x00000010
 175
 176 #define SDHCI_HOST_CONTROL2             0x3E
 177 #define  SDHCI_CTRL_UHS_MASK            0x0007
 178 #define   SDHCI_CTRL_UHS_SDR12          0x0000
 179 #define   SDHCI_CTRL_UHS_SDR25          0x0001
 180 #define   SDHCI_CTRL_UHS_SDR50          0x0002
 181 #define   SDHCI_CTRL_UHS_SDR104         0x0003
 182 #define   SDHCI_CTRL_UHS_DDR50          0x0004
 183 #define   SDHCI_CTRL_HS400              0x0005 /* Non-standard */
 184 #define  SDHCI_CTRL_VDD_180             0x0008
 185 #define  SDHCI_CTRL_DRV_TYPE_MASK       0x0030
 186 #define   SDHCI_CTRL_DRV_TYPE_B         0x0000
 187 #define   SDHCI_CTRL_DRV_TYPE_A         0x0010
 188 #define   SDHCI_CTRL_DRV_TYPE_C         0x0020
 189 #define   SDHCI_CTRL_DRV_TYPE_D         0x0030
 190 #define  SDHCI_CTRL_EXEC_TUNING         0x0040
 191 #define  SDHCI_CTRL_TUNED_CLK           0x0080
 192 #define  SDHCI_CTRL_PRESET_VAL_ENABLE   0x8000
 193
 194 #define SDHCI_CAPABILITIES      0x40
 195 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 196 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 197 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 198 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 199 #define  SDHCI_CLOCK_V3_BASE_MASK       0x0000FF00
 200 #define  SDHCI_CLOCK_BASE_SHIFT 8
 201 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 202 #define  SDHCI_MAX_BLOCK_SHIFT  16
 203 #define  SDHCI_CAN_DO_8BIT      0x00040000
 204 #define  SDHCI_CAN_DO_ADMA2     0x00080000
 205 #define  SDHCI_CAN_DO_ADMA1     0x00100000
 206 #define  SDHCI_CAN_DO_HISPD     0x00200000
 207 #define  SDHCI_CAN_DO_SDMA      0x00400000
 208 #define  SDHCI_CAN_DO_SUSPEND   0x00800000
 209 #define  SDHCI_CAN_VDD_330      0x01000000
 210 #define  SDHCI_CAN_VDD_300      0x02000000
 211 #define  SDHCI_CAN_VDD_180      0x04000000
 212 #define  SDHCI_CAN_64BIT        0x10000000
 213
 214 #define  SDHCI_SUPPORT_SDR50    0x00000001
 215 #define  SDHCI_SUPPORT_SDR104   0x00000002
 216 #define  SDHCI_SUPPORT_DDR50    0x00000004
 217 #define  SDHCI_DRIVER_TYPE_A    0x00000010
 218 #define  SDHCI_DRIVER_TYPE_C    0x00000020
 219 #define  SDHCI_DRIVER_TYPE_D    0x00000040
 220 #define  SDHCI_RETUNING_TIMER_COUNT_MASK        0x00000F00
 221 #define  SDHCI_RETUNING_TIMER_COUNT_SHIFT       8
 222 #define  SDHCI_USE_SDR50_TUNING                 0x00002000
 223 #define  SDHCI_RETUNING_MODE_MASK               0x0000C000
 224 #define  SDHCI_RETUNING_MODE_SHIFT              14
 225 #define  SDHCI_CLOCK_MUL_MASK   0x00FF0000
 226 #define  SDHCI_CLOCK_MUL_SHIFT  16
 227 #define  SDHCI_SUPPORT_HS400    0x80000000 /* Non-standard */
 228
 229 #define SDHCI_CAPABILITIES_1    0x44
 230
 231 #define SDHCI_MAX_CURRENT               0x48
 232 #define  SDHCI_MAX_CURRENT_LIMIT        0xFF
 233 #define  SDHCI_MAX_CURRENT_330_MASK     0x0000FF
 234 #define  SDHCI_MAX_CURRENT_330_SHIFT    0
 235 #define  SDHCI_MAX_CURRENT_300_MASK     0x00FF00
 236 #define  SDHCI_MAX_CURRENT_300_SHIFT    8
 237 #define  SDHCI_MAX_CURRENT_180_MASK     0xFF0000
 238 #define  SDHCI_MAX_CURRENT_180_SHIFT    16
 239 #define   SDHCI_MAX_CURRENT_MULTIPLIER  4
 240
 241 /* 4C-4F reserved for more max current */
 242
 243 #define SDHCI_SET_ACMD12_ERROR  0x50
 244 #define SDHCI_SET_INT_ERROR     0x52
 245
 246 #define SDHCI_ADMA_ERROR        0x54
 247
 248 /* 55-57 reserved */
 249
 250 #define SDHCI_ADMA_ADDRESS      0x58
 251 #define SDHCI_ADMA_ADDRESS_HI   0x5C
 252
 253 /* 60-FB reserved */
 254
 255 #define SDHCI_PRESET_FOR_SDR12 0x66
 256 #define SDHCI_PRESET_FOR_SDR25 0x68
 257 #define SDHCI_PRESET_FOR_SDR50 0x6A
 258 #define SDHCI_PRESET_FOR_SDR104        0x6C
 259 #define SDHCI_PRESET_FOR_DDR50 0x6E
 260 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
 261 #define SDHCI_PRESET_DRV_MASK  0xC000
 262 #define SDHCI_PRESET_DRV_SHIFT  14
 263 #define SDHCI_PRESET_CLKGEN_SEL_MASK   0x400
 264 #define SDHCI_PRESET_CLKGEN_SEL_SHIFT   10
 265 #define SDHCI_PRESET_SDCLK_FREQ_MASK   0x3FF
 266 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT   0
 267
 268 #define SDHCI_SLOT_INT_STATUS   0xFC
 269
 270 #define SDHCI_HOST_VERSION      0xFE
 271 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 272 #define  SDHCI_VENDOR_VER_SHIFT 8
 273 #define  SDHCI_SPEC_VER_MASK    0x00FF
 274 #define  SDHCI_SPEC_VER_SHIFT   0
 275 #define   SDHCI_SPEC_100        0
 276 #define   SDHCI_SPEC_200        1
 277 #define   SDHCI_SPEC_300        2
 278
 279 /*
 280  * End of controller registers.
 281  */
 282
 283 #define SDHCI_MAX_DIV_SPEC_200  256
 284 #define SDHCI_MAX_DIV_SPEC_300  2046
 285
 286 /*
 287  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
 288  */
 289 #define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
 290 #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
 291
 292 /* ADMA2 32-bit DMA descriptor size */
 293 #define SDHCI_ADMA2_32_DESC_SZ  8
 294
 295 /* ADMA2 32-bit descriptor */
 296 struct sdhci_adma2_32_desc {
 297         __le16  cmd;
 298         __le16  len;
 299         __le32  addr;
 300 }  __packed __aligned(4);
 301
 302 /* ADMA2 data alignment */
 303 #define SDHCI_ADMA2_ALIGN       4
 304 #define SDHCI_ADMA2_MASK        (SDHCI_ADMA2_ALIGN - 1)
 305
 306 /*
 307  * ADMA2 descriptor alignment.  Some controllers (e.g. Intel) require 8 byte
 308  * alignment for the descriptor table even in 32-bit DMA mode.  Memory
 309  * allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
 310  */
 311 #define SDHCI_ADMA2_DESC_ALIGN  8
 312
 313 /* ADMA2 64-bit DMA descriptor size */
 314 #define SDHCI_ADMA2_64_DESC_SZ  12
 315
 316 /*
 317  * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
 318  * aligned.
 319  */
 320 struct sdhci_adma2_64_desc {
 321         __le16  cmd;
 322         __le16  len;
 323         __le32  addr_lo;
 324         __le32  addr_hi;
 325 }  __packed __aligned(4);
 326
 327 #define ADMA2_TRAN_VALID        0x21
 328 #define ADMA2_NOP_END_VALID     0x3
 329 #define ADMA2_END               0x2
 330
 331 /*
 332  * Maximum segments assuming a 512KiB maximum requisition size and a minimum
 333  * 4KiB page size.
 334  */
 335 #define SDHCI_MAX_SEGS          128
 336
 337 /* Allow for a a command request and a data request at the same time */
 338 #define SDHCI_MAX_MRQS          2
 339
 340 /*
 341  * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
 342  * However since the start time of the command, the time between
 343  * command and response, and the time between response and start of data is
 344  * not known, set the command transfer time to 10ms.
 345  */
 346 #define MMC_CMD_TRANSFER_TIME   (10 * NSEC_PER_MSEC) /* max 10 ms */
 347
 348 enum sdhci_cookie {
 349         COOKIE_UNMAPPED,
 350         COOKIE_PRE_MAPPED,      /* mapped by sdhci_pre_req() */
 351         COOKIE_MAPPED,          /* mapped by sdhci_prepare_data() */
 352 };
 353
 354 struct sdhci_host {
 355         /* Data set by hardware interface driver */
 356         const char *hw_name;    /* Hardware bus name */
 357
 358         unsigned int quirks;    /* Deviations from spec. */
 359
 360 /* Controller doesn't honor resets unless we touch the clock register */
 361 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
 362 /* Controller has bad caps bits, but really supports DMA */
 363 #define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
 364 /* Controller doesn't like to be reset when there is no card inserted. */
 365 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
 366 /* Controller doesn't like clearing the power reg before a change */
 367 #define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
 368 /* Controller has flaky internal state so reset it on each ios change */
 369 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
 370 /* Controller has an unusable DMA engine */
 371 #define SDHCI_QUIRK_BROKEN_DMA                          (1<<5)
 372 /* Controller has an unusable ADMA engine */
 373 #define SDHCI_QUIRK_BROKEN_ADMA                         (1<<6)
 374 /* Controller can only DMA from 32-bit aligned addresses */
 375 #define SDHCI_QUIRK_32BIT_DMA_ADDR                      (1<<7)
 376 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
 377 #define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1<<8)
 378 /* Controller can only ADMA chunks that are a multiple of 32 bits */
 379 #define SDHCI_QUIRK_32BIT_ADMA_SIZE                     (1<<9)
 380 /* Controller needs to be reset after each request to stay stable */
 381 #define SDHCI_QUIRK_RESET_AFTER_REQUEST                 (1<<10)
 382 /* Controller needs voltage and power writes to happen separately */
 383 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER             (1<<11)
 384 /* Controller provides an incorrect timeout value for transfers */
 385 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL                  (1<<12)
 386 /* Controller has an issue with buffer bits for small transfers */
 387 #define SDHCI_QUIRK_BROKEN_SMALL_PIO                    (1<<13)
 388 /* Controller does not provide transfer-complete interrupt when not busy */
 389 #define SDHCI_QUIRK_NO_BUSY_IRQ                         (1<<14)
 390 /* Controller has unreliable card detection */
 391 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION               (1<<15)
 392 /* Controller reports inverted write-protect state */
 393 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT              (1<<16)
 394 /* Controller has unusable command queue engine */
 395 #define SDHCI_QUIRK_BROKEN_CQE                          (1<<17)
 396 /* Controller does not like fast PIO transfers */
 397 #define SDHCI_QUIRK_PIO_NEEDS_DELAY                     (1<<18)
 398 /* Controller has to be forced to use block size of 2048 bytes */
 399 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048                   (1<<20)
 400 /* Controller cannot do multi-block transfers */
 401 #define SDHCI_QUIRK_NO_MULTIBLOCK                       (1<<21)
 402 /* Controller can only handle 1-bit data transfers */
 403 #define SDHCI_QUIRK_FORCE_1_BIT_DATA                    (1<<22)
 404 /* Controller needs 10ms delay between applying power and clock */
 405 #define SDHCI_QUIRK_DELAY_AFTER_POWER                   (1<<23)
 406 /* Controller uses SDCLK instead of TMCLK for data timeouts */
 407 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK             (1<<24)
 408 /* Controller reports wrong base clock capability */
 409 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN               (1<<25)
 410 /* Controller cannot support End Attribute in NOP ADMA descriptor */
 411 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC               (1<<26)
 412 /* Controller is missing device caps. Use caps provided by host */
 413 #define SDHCI_QUIRK_MISSING_CAPS                        (1<<27)
 414 /* Controller uses Auto CMD12 command to stop the transfer */
 415 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12              (1<<28)
 416 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
 417 #define SDHCI_QUIRK_NO_HISPD_BIT                        (1<<29)
 418 /* Controller treats ADMA descriptors with length 0000h incorrectly */
 419 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC            (1<<30)
 420 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
 421 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT                  (1<<31)
 422
 423         unsigned int quirks2;   /* More deviations from spec. */
 424
 425 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON                   (1<<0)
 426 #define SDHCI_QUIRK2_HOST_NO_CMD23                      (1<<1)
 427 /* The system physically doesn't support 1.8v, even if the host does */
 428 #define SDHCI_QUIRK2_NO_1_8_V                           (1<<2)
 429 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN                (1<<3)
 430 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON               (1<<4)
 431 /* Controller has a non-standard host control register */
 432 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL                (1<<5)
 433 /* Controller does not support HS200 */
 434 #define SDHCI_QUIRK2_BROKEN_HS200                       (1<<6)
 435 /* Controller does not support DDR50 */
 436 #define SDHCI_QUIRK2_BROKEN_DDR50                       (1<<7)
 437 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
 438 #define SDHCI_QUIRK2_STOP_WITH_TC                       (1<<8)
 439 /* Controller does not support 64-bit DMA */
 440 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA                  (1<<9)
 441 /* need clear transfer mode register before send cmd */
 442 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD  (1<<10)
 443 /* Capability register bit-63 indicates HS400 support */
 444 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400               (1<<11)
 445 /* forced tuned clock */
 446 #define SDHCI_QUIRK2_TUNING_WORK_AROUND                 (1<<12)
 447 /* disable the block count for single block transactions */
 448 #define SDHCI_QUIRK2_SUPPORT_SINGLE                     (1<<13)
 449 /* Controller broken with using ACMD23 */
 450 #define SDHCI_QUIRK2_ACMD23_BROKEN                      (1<<14)
 451 /* Broken Clock divider zero in controller */
 452 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN              (1<<15)
 453 /* Controller has CRC in 136 bit Command Response */
 454 #define SDHCI_QUIRK2_RSP_136_HAS_CRC                    (1<<16)
 455 /*
 456  * Disable HW timeout if the requested timeout is more than the maximum
 457  * obtainable timeout.
 458  */
 459 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT                 (1<<17)
 460
 461         int irq;                /* Device IRQ */
 462         void __iomem *ioaddr;   /* Mapped address */
 463         char *bounce_buffer;    /* For packing SDMA reads/writes */
 464         dma_addr_t bounce_addr;
 465         unsigned int bounce_buffer_size;
 466
 467         const struct sdhci_ops *ops;    /* Low level hw interface */
 468
 469         /* Internal data */
 470         struct mmc_host *mmc;   /* MMC structure */
 471         struct mmc_host_ops mmc_host_ops;       /* MMC host ops */
 472         u64 dma_mask;           /* custom DMA mask */
 473
 474 #if IS_ENABLED(CONFIG_LEDS_CLASS)
 475         struct led_classdev led;        /* LED control */
 476         char led_name[32];
 477 #endif
 478
 479         spinlock_t lock;        /* Mutex */
 480
 481         int flags;              /* Host attributes */
 482 #define SDHCI_USE_SDMA          (1<<0)  /* Host is SDMA capable */
 483 #define SDHCI_USE_ADMA          (1<<1)  /* Host is ADMA capable */
 484 #define SDHCI_REQ_USE_DMA       (1<<2)  /* Use DMA for this req. */
 485 #define SDHCI_DEVICE_DEAD       (1<<3)  /* Device unresponsive */
 486 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
 487 #define SDHCI_AUTO_CMD12        (1<<6)  /* Auto CMD12 support */
 488 #define SDHCI_AUTO_CMD23        (1<<7)  /* Auto CMD23 support */
 489 #define SDHCI_PV_ENABLED        (1<<8)  /* Preset value enabled */
 490 #define SDHCI_SDIO_IRQ_ENABLED  (1<<9)  /* SDIO irq enabled */
 491 #define SDHCI_USE_64_BIT_DMA    (1<<12) /* Use 64-bit DMA */
 492 #define SDHCI_HS400_TUNING      (1<<13) /* Tuning for HS400 */
 493 #define SDHCI_SIGNALING_330     (1<<14) /* Host is capable of 3.3V signaling */
 494 #define SDHCI_SIGNALING_180     (1<<15) /* Host is capable of 1.8V signaling */
 495 #define SDHCI_SIGNALING_120     (1<<16) /* Host is capable of 1.2V signaling */
 496
 497         unsigned int version;   /* SDHCI spec. version */
 498
 499         unsigned int max_clk;   /* Max possible freq (MHz) */
 500         unsigned int timeout_clk;       /* Timeout freq (KHz) */
 501         unsigned int clk_mul;   /* Clock Muliplier value */
 502
 503         unsigned int clock;     /* Current clock (MHz) */
 504         u8 pwr;                 /* Current voltage */
 505
 506         bool runtime_suspended; /* Host is runtime suspended */
 507         bool bus_on;            /* Bus power prevents runtime suspend */
 508         bool preset_enabled;    /* Preset is enabled */
 509         bool pending_reset;     /* Cmd/data reset is pending */
 510         bool irq_wake_enabled;  /* IRQ wakeup is enabled */
 511
 512         struct mmc_request *mrqs_done[SDHCI_MAX_MRQS];  /* Requests done */
 513         struct mmc_command *cmd;        /* Current command */
 514         struct mmc_command *data_cmd;   /* Current data command */
 515         struct mmc_data *data;  /* Current data request */
 516         unsigned int data_early:1;      /* Data finished before cmd */
 517
 518         struct sg_mapping_iter sg_miter;        /* SG state for PIO */
 519         unsigned int blocks;    /* remaining PIO blocks */
 520
 521         int sg_count;           /* Mapped sg entries */
 522
 523         void *adma_table;       /* ADMA descriptor table */
 524         void *align_buffer;     /* Bounce buffer */
 525
 526         size_t adma_table_sz;   /* ADMA descriptor table size */
 527         size_t align_buffer_sz; /* Bounce buffer size */
 528
 529         dma_addr_t adma_addr;   /* Mapped ADMA descr. table */
 530         dma_addr_t align_addr;  /* Mapped bounce buffer */
 531
 532         unsigned int desc_sz;   /* ADMA descriptor size */
 533
 534         struct tasklet_struct finish_tasklet;   /* Tasklet structures */
 535
 536         struct timer_list timer;        /* Timer for timeouts */
 537         struct timer_list data_timer;   /* Timer for data timeouts */
 538
 539         u32 caps;               /* CAPABILITY_0 */
 540         u32 caps1;              /* CAPABILITY_1 */
 541         bool read_caps;         /* Capability flags have been read */
 542
 543         unsigned int            ocr_avail_sdio; /* OCR bit masks */
 544         unsigned int            ocr_avail_sd;
 545         unsigned int            ocr_avail_mmc;
 546         u32 ocr_mask;           /* available voltages */
 547
 548         unsigned                timing;         /* Current timing */
 549
 550         u32                     thread_isr;
 551
 552         /* cached registers */
 553         u32                     ier;
 554
 555         bool                    cqe_on;         /* CQE is operating */
 556         u32                     cqe_ier;        /* CQE interrupt mask */
 557         u32                     cqe_err_ier;    /* CQE error interrupt mask */
 558
 559         wait_queue_head_t       buf_ready_int;  /* Waitqueue for Buffer Read Ready interrupt */
 560         unsigned int            tuning_done;    /* Condition flag set when CMD19 succeeds */
 561
 562         unsigned int            tuning_count;   /* Timer count for re-tuning */
 563         unsigned int            tuning_mode;    /* Re-tuning mode supported by host */
 564 #define SDHCI_TUNING_MODE_1     0
 565 #define SDHCI_TUNING_MODE_2     1
 566 #define SDHCI_TUNING_MODE_3     2
 567         /* Delay (ms) between tuning commands */
 568         int                     tuning_delay;
 569
 570         /* Host SDMA buffer boundary. */
 571         u32                     sdma_boundary;
 572
 573         u64                     data_timeout;
 574
 575         unsigned long private[0] ____cacheline_aligned;
 576 };
 577
 578 struct sdhci_ops {
 579 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 580         u32             (*read_l)(struct sdhci_host *host, int reg);
 581         u16             (*read_w)(struct sdhci_host *host, int reg);
 582         u8              (*read_b)(struct sdhci_host *host, int reg);
 583         void            (*write_l)(struct sdhci_host *host, u32 val, int reg);
 584         void            (*write_w)(struct sdhci_host *host, u16 val, int reg);
 585         void            (*write_b)(struct sdhci_host *host, u8 val, int reg);
 586 #endif
 587
 588         void    (*set_clock)(struct sdhci_host *host, unsigned int clock);
 589         void    (*set_power)(struct sdhci_host *host, unsigned char mode,
 590                              unsigned short vdd);
 591
 592         u32             (*irq)(struct sdhci_host *host, u32 intmask);
 593
 594         int             (*enable_dma)(struct sdhci_host *host);
 595         unsigned int    (*get_max_clock)(struct sdhci_host *host);
 596         unsigned int    (*get_min_clock)(struct sdhci_host *host);
 597         /* get_timeout_clock should return clk rate in unit of Hz */
 598         unsigned int    (*get_timeout_clock)(struct sdhci_host *host);
 599         unsigned int    (*get_max_timeout_count)(struct sdhci_host *host);
 600         void            (*set_timeout)(struct sdhci_host *host,
 601                                        struct mmc_command *cmd);
 602         void            (*set_bus_width)(struct sdhci_host *host, int width);
 603         void (*platform_send_init_74_clocks)(struct sdhci_host *host,
 604                                              u8 power_mode);
 605         unsigned int    (*get_ro)(struct sdhci_host *host);
 606         void            (*reset)(struct sdhci_host *host, u8 mask);
 607         int     (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
 608         void    (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
 609         void    (*hw_reset)(struct sdhci_host *host);
 610         void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
 611         void    (*card_event)(struct sdhci_host *host);
 612         void    (*voltage_switch)(struct sdhci_host *host);
 613 };
 614
 615 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 616
 617 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 618 {
 619         if (unlikely(host->ops->write_l))
 620                 host->ops->write_l(host, val, reg);
 621         else
 622                 writel(val, host->ioaddr + reg);
 623 }
 624
 625 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 626 {
 627         if (unlikely(host->ops->write_w))
 628                 host->ops->write_w(host, val, reg);
 629         else
 630                 writew(val, host->ioaddr + reg);
 631 }
 632
 633 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 634 {
 635         if (unlikely(host->ops->write_b))
 636                 host->ops->write_b(host, val, reg);
 637         else
 638                 writeb(val, host->ioaddr + reg);
 639 }
 640
 641 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 642 {
 643         if (unlikely(host->ops->read_l))
 644                 return host->ops->read_l(host, reg);
 645         else
 646                 return readl(host->ioaddr + reg);
 647 }
 648
 649 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 650 {
 651         if (unlikely(host->ops->read_w))
 652                 return host->ops->read_w(host, reg);
 653         else
 654                 return readw(host->ioaddr + reg);
 655 }
 656
 657 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 658 {
 659         if (unlikely(host->ops->read_b))
 660                 return host->ops->read_b(host, reg);
 661         else
 662                 return readb(host->ioaddr + reg);
 663 }
 664
 665 #else
 666
 667 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 668 {
 669         writel(val, host->ioaddr + reg);
 670 }
 671
 672 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 673 {
 674         writew(val, host->ioaddr + reg);
 675 }
 676
 677 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 678 {
 679         writeb(val, host->ioaddr + reg);
 680 }
 681
 682 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 683 {
 684         return readl(host->ioaddr + reg);
 685 }
 686
 687 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 688 {
 689         return readw(host->ioaddr + reg);
 690 }
 691
 692 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 693 {
 694         return readb(host->ioaddr + reg);
 695 }
 696
 697 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
 698
 699 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size);
 700 void sdhci_free_host(struct sdhci_host *host);
 701
 702 static inline void *sdhci_priv(struct sdhci_host *host)
 703 {
 704         return host->private;
 705 }
 706
 707 void sdhci_card_detect(struct sdhci_host *host);
 708 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps,
 709                        u32 *caps1);
 710 int sdhci_setup_host(struct sdhci_host *host);
 711 void sdhci_cleanup_host(struct sdhci_host *host);
 712 int __sdhci_add_host(struct sdhci_host *host);
 713 int sdhci_add_host(struct sdhci_host *host);
 714 void sdhci_remove_host(struct sdhci_host *host, int dead);
 715 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
 716
 717 static inline void sdhci_read_caps(struct sdhci_host *host)
 718 {
 719         __sdhci_read_caps(host, NULL, NULL, NULL);
 720 }
 721
 722 static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
 723 {
 724         return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
 725 }
 726
 727 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
 728                    unsigned int *actual_clock);
 729 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
 730 void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
 731 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
 732                      unsigned short vdd);
 733 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
 734                            unsigned short vdd);
 735 void sdhci_set_bus_width(struct sdhci_host *host, int width);
 736 void sdhci_reset(struct sdhci_host *host, u8 mask);
 737 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
 738 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
 739 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 740 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
 741                                       struct mmc_ios *ios);
 742 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
 743
 744 #ifdef CONFIG_PM
 745 int sdhci_suspend_host(struct sdhci_host *host);
 746 int sdhci_resume_host(struct sdhci_host *host);
 747 int sdhci_runtime_suspend_host(struct sdhci_host *host);
 748 int sdhci_runtime_resume_host(struct sdhci_host *host);
 749 #endif
 750
 751 void sdhci_cqe_enable(struct mmc_host *mmc);
 752 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery);
 753 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
 754                    int *data_error);
 755
 756 void sdhci_dumpregs(struct sdhci_host *host);
 757
 758 void sdhci_start_tuning(struct sdhci_host *host);
 759 void sdhci_end_tuning(struct sdhci_host *host);
 760 void sdhci_reset_tuning(struct sdhci_host *host);
 761 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
 762
 763 #endif /* __SDHCI_HW_H */