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Linux 4.19.133
[linux/fpc-iii.git] / drivers / mmc / host / via-sdmmc.c
blob246dc6255e696c6d5310f5620284454879b2297c
1 /*
2 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
3 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/module.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/highmem.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17
18 #include <linux/mmc/host.h>
19
20 #define DRV_NAME "via_sdmmc"
21
22 #define PCI_DEVICE_ID_VIA_9530 0x9530
23
24 #define VIA_CRDR_SDC_OFF 0x200
25 #define VIA_CRDR_DDMA_OFF 0x400
26 #define VIA_CRDR_PCICTRL_OFF 0x600
27
28 #define VIA_CRDR_MIN_CLOCK 375000
29 #define VIA_CRDR_MAX_CLOCK 48000000
30
31 /*
32 * PCI registers
33 */
34
35 #define VIA_CRDR_PCI_WORK_MODE 0x40
36 #define VIA_CRDR_PCI_DBG_MODE 0x41
37
38 /*
39 * SDC MMIO Registers
40 */
41
42 #define VIA_CRDR_SDCTRL 0x0
43 #define VIA_CRDR_SDCTRL_START 0x01
44 #define VIA_CRDR_SDCTRL_WRITE 0x04
45 #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
46 #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
47 #define VIA_CRDR_SDCTRL_MULTI_WR 0x30
48 #define VIA_CRDR_SDCTRL_MULTI_RD 0x40
49 #define VIA_CRDR_SDCTRL_STOP 0x70
50
51 #define VIA_CRDR_SDCTRL_RSP_NONE 0x0
52 #define VIA_CRDR_SDCTRL_RSP_R1 0x10000
53 #define VIA_CRDR_SDCTRL_RSP_R2 0x20000
54 #define VIA_CRDR_SDCTRL_RSP_R3 0x30000
55 #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
56
57 #define VIA_CRDR_SDCARG 0x4
58
59 #define VIA_CRDR_SDBUSMODE 0x8
60 #define VIA_CRDR_SDMODE_4BIT 0x02
61 #define VIA_CRDR_SDMODE_CLK_ON 0x40
62
63 #define VIA_CRDR_SDBLKLEN 0xc
64 /*
65 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
66 * Bit 11 - Bit 13 : Reserved.
67 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
68 * INTEN : Enable SD host interrupt.
69 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
70 */
71 #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
72 #define VIA_CRDR_SDBLKLEN_INTEN 0x8000
73 #define VIA_CRDR_MAX_BLOCK_COUNT 65536
74 #define VIA_CRDR_MAX_BLOCK_LENGTH 2048
75
76 #define VIA_CRDR_SDRESP0 0x10
77 #define VIA_CRDR_SDRESP1 0x14
78 #define VIA_CRDR_SDRESP2 0x18
79 #define VIA_CRDR_SDRESP3 0x1c
80
81 #define VIA_CRDR_SDCURBLKCNT 0x20
82
83 #define VIA_CRDR_SDINTMASK 0x24
84 /*
85 * MBDIE : Multiple Blocks transfer Done Interrupt Enable
86 * BDDIE : Block Data transfer Done Interrupt Enable
87 * CIRIE : Card Insertion or Removal Interrupt Enable
88 * CRDIE : Command-Response transfer Done Interrupt Enable
89 * CRTOIE : Command-Response response TimeOut Interrupt Enable
90 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
91 * DTIE : Data access Timeout Interrupt Enable
92 * SCIE : reSponse CRC error Interrupt Enable
93 * RCIE : Read data CRC error Interrupt Enable
94 * WCIE : Write data CRC error Interrupt Enable
95 */
96 #define VIA_CRDR_SDINTMASK_MBDIE 0x10
97 #define VIA_CRDR_SDINTMASK_BDDIE 0x20
98 #define VIA_CRDR_SDINTMASK_CIRIE 0x80
99 #define VIA_CRDR_SDINTMASK_CRDIE 0x200
100 #define VIA_CRDR_SDINTMASK_CRTOIE 0x400
101 #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
102 #define VIA_CRDR_SDINTMASK_DTIE 0x1000
103 #define VIA_CRDR_SDINTMASK_SCIE 0x2000
104 #define VIA_CRDR_SDINTMASK_RCIE 0x4000
105 #define VIA_CRDR_SDINTMASK_WCIE 0x8000
106
107 #define VIA_CRDR_SDACTIVE_INTMASK \
108 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
109 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
110 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
111 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
112
113 #define VIA_CRDR_SDSTATUS 0x28
114 /*
115 * CECC : Reserved
116 * WP : SD card Write Protect status
117 * SLOTD : Reserved
118 * SLOTG : SD SLOT status(Gpi pin status)
119 * MBD : Multiple Blocks transfer Done interrupt status
120 * BDD : Block Data transfer Done interrupt status
121 * CD : Reserved
122 * CIR : Card Insertion or Removal interrupt detected on GPI pin
123 * IO : Reserved
124 * CRD : Command-Response transfer Done interrupt status
125 * CRTO : Command-Response response TimeOut interrupt status
126 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
127 * DT : Data access Timeout interrupt status
128 * SC : reSponse CRC error interrupt status
129 * RC : Read data CRC error interrupt status
130 * WC : Write data CRC error interrupt status
131 */
132 #define VIA_CRDR_SDSTS_CECC 0x01
133 #define VIA_CRDR_SDSTS_WP 0x02
134 #define VIA_CRDR_SDSTS_SLOTD 0x04
135 #define VIA_CRDR_SDSTS_SLOTG 0x08
136 #define VIA_CRDR_SDSTS_MBD 0x10
137 #define VIA_CRDR_SDSTS_BDD 0x20
138 #define VIA_CRDR_SDSTS_CD 0x40
139 #define VIA_CRDR_SDSTS_CIR 0x80
140 #define VIA_CRDR_SDSTS_IO 0x100
141 #define VIA_CRDR_SDSTS_CRD 0x200
142 #define VIA_CRDR_SDSTS_CRTO 0x400
143 #define VIA_CRDR_SDSTS_ASCRDIE 0x800
144 #define VIA_CRDR_SDSTS_DT 0x1000
145 #define VIA_CRDR_SDSTS_SC 0x2000
146 #define VIA_CRDR_SDSTS_RC 0x4000
147 #define VIA_CRDR_SDSTS_WC 0x8000
148
149 #define VIA_CRDR_SDSTS_IGN_MASK\
150 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
151 #define VIA_CRDR_SDSTS_INT_MASK \
152 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
153 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
154 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
155 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
156 #define VIA_CRDR_SDSTS_W1C_MASK \
157 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
158 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
159 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
160 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
161 #define VIA_CRDR_SDSTS_CMD_MASK \
162 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
163 #define VIA_CRDR_SDSTS_DATA_MASK\
164 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
165 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
166
167 #define VIA_CRDR_SDSTATUS2 0x2a
168 /*
169 * CFE : Enable SD host automatic Clock FReezing
170 */
171 #define VIA_CRDR_SDSTS_CFE 0x80
172
173 #define VIA_CRDR_SDRSPTMO 0x2C
174
175 #define VIA_CRDR_SDCLKSEL 0x30
176
177 #define VIA_CRDR_SDEXTCTRL 0x34
178 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
179 #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
180 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
181 #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
182 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
183 #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
184 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
185 #define VIA_CRDR_SDEXTCTRL_HISPD 0x80
186 /* 0x38-0xFF reserved */
187
188 /*
189 * Data DMA Control Registers
190 */
191
192 #define VIA_CRDR_DMABASEADD 0x0
193 #define VIA_CRDR_DMACOUNTER 0x4
194
195 #define VIA_CRDR_DMACTRL 0x8
196 /*
197 * DIR :Transaction Direction
198 * 0 : From card to memory
199 * 1 : From memory to card
200 */
201 #define VIA_CRDR_DMACTRL_DIR 0x100
202 #define VIA_CRDR_DMACTRL_ENIRQ 0x10000
203 #define VIA_CRDR_DMACTRL_SFTRST 0x1000000
204
205 #define VIA_CRDR_DMASTS 0xc
206
207 #define VIA_CRDR_DMASTART 0x10
208 /*0x14-0xFF reserved*/
209
210 /*
211 * PCI Control Registers
212 */
213
214 /*0x0 - 0x1 reserved*/
215 #define VIA_CRDR_PCICLKGATT 0x2
216 /*
217 * SFTRST :
218 * 0 : Soft reset all the controller and it will be de-asserted automatically
219 * 1 : Soft reset is de-asserted
220 */
221 #define VIA_CRDR_PCICLKGATT_SFTRST 0x01
222 /*
223 * 3V3 : Pad power select
224 * 0 : 1.8V
225 * 1 : 3.3V
226 * NOTE : No mater what the actual value should be, this bit always
227 * read as 0. This is a hardware bug.
228 */
229 #define VIA_CRDR_PCICLKGATT_3V3 0x10
230 /*
231 * PAD_PWRON : Pad Power on/off select
232 * 0 : Power off
233 * 1 : Power on
234 * NOTE : No mater what the actual value should be, this bit always
235 * read as 0. This is a hardware bug.
236 */
237 #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
238
239 #define VIA_CRDR_PCISDCCLK 0x5
240
241 #define VIA_CRDR_PCIDMACLK 0x7
242 #define VIA_CRDR_PCIDMACLK_SDC 0x2
243
244 #define VIA_CRDR_PCIINTCTRL 0x8
245 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
246
247 #define VIA_CRDR_PCIINTSTATUS 0x9
248 #define VIA_CRDR_PCIINTSTATUS_SDC 0x04
249
250 #define VIA_CRDR_PCITMOCTRL 0xa
251 #define VIA_CRDR_PCITMOCTRL_NO 0x0
252 #define VIA_CRDR_PCITMOCTRL_32US 0x1
253 #define VIA_CRDR_PCITMOCTRL_256US 0x2
254 #define VIA_CRDR_PCITMOCTRL_1024US 0x3
255 #define VIA_CRDR_PCITMOCTRL_256MS 0x4
256 #define VIA_CRDR_PCITMOCTRL_512MS 0x5
257 #define VIA_CRDR_PCITMOCTRL_1024MS 0x6
258
259 /*0xB-0xFF reserved*/
260
261 enum PCI_HOST_CLK_CONTROL {
262 PCI_CLK_375K = 0x03,
263 PCI_CLK_8M = 0x04,
264 PCI_CLK_12M = 0x00,
265 PCI_CLK_16M = 0x05,
266 PCI_CLK_24M = 0x01,
267 PCI_CLK_33M = 0x06,
268 PCI_CLK_48M = 0x02
269 };
270
271 struct sdhcreg {
272 u32 sdcontrol_reg;
273 u32 sdcmdarg_reg;
274 u32 sdbusmode_reg;
275 u32 sdblklen_reg;
276 u32 sdresp_reg[4];
277 u32 sdcurblkcnt_reg;
278 u32 sdintmask_reg;
279 u32 sdstatus_reg;
280 u32 sdrsptmo_reg;
281 u32 sdclksel_reg;
282 u32 sdextctrl_reg;
283 };
284
285 struct pcictrlreg {
286 u8 reserve[2];
287 u8 pciclkgat_reg;
288 u8 pcinfcclk_reg;
289 u8 pcimscclk_reg;
290 u8 pcisdclk_reg;
291 u8 pcicaclk_reg;
292 u8 pcidmaclk_reg;
293 u8 pciintctrl_reg;
294 u8 pciintstatus_reg;
295 u8 pcitmoctrl_reg;
296 u8 Resv;
297 };
298
299 struct via_crdr_mmc_host {
300 struct mmc_host *mmc;
301 struct mmc_request *mrq;
302 struct mmc_command *cmd;
303 struct mmc_data *data;
304
305 void __iomem *mmiobase;
306 void __iomem *sdhc_mmiobase;
307 void __iomem *ddma_mmiobase;
308 void __iomem *pcictrl_mmiobase;
309
310 struct pcictrlreg pm_pcictrl_reg;
311 struct sdhcreg pm_sdhc_reg;
312
313 struct work_struct carddet_work;
314 struct tasklet_struct finish_tasklet;
315
316 struct timer_list timer;
317 spinlock_t lock;
318 u8 power;
319 int reject;
320 unsigned int quirks;
321 };
322
323 /* some devices need a very long delay for power to stabilize */
324 #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
325
326 #define VIA_CMD_TIMEOUT_MS 1000
327
328 static const struct pci_device_id via_ids[] = {
329 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
331 {0,}
332 };
333
334 MODULE_DEVICE_TABLE(pci, via_ids);
335
336 static void via_print_sdchc(struct via_crdr_mmc_host *host)
337 {
338 void __iomem *addrbase = host->sdhc_mmiobase;
339
340 pr_debug("SDC MMIO Registers:\n");
341 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
342 readl(addrbase + VIA_CRDR_SDCTRL),
343 readl(addrbase + VIA_CRDR_SDCARG),
344 readl(addrbase + VIA_CRDR_SDBUSMODE));
345 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
346 readl(addrbase + VIA_CRDR_SDBLKLEN),
347 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
348 readl(addrbase + VIA_CRDR_SDINTMASK));
349 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
350 readl(addrbase + VIA_CRDR_SDSTATUS),
351 readl(addrbase + VIA_CRDR_SDCLKSEL),
352 readl(addrbase + VIA_CRDR_SDEXTCTRL));
353 }
354
355 static void via_print_pcictrl(struct via_crdr_mmc_host *host)
356 {
357 void __iomem *addrbase = host->pcictrl_mmiobase;
358
359 pr_debug("PCI Control Registers:\n");
360 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
361 readb(addrbase + VIA_CRDR_PCICLKGATT),
362 readb(addrbase + VIA_CRDR_PCISDCCLK),
363 readb(addrbase + VIA_CRDR_PCIDMACLK));
364 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
365 readb(addrbase + VIA_CRDR_PCIINTCTRL),
366 readb(addrbase + VIA_CRDR_PCIINTSTATUS));
367 }
368
369 static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
370 {
371 struct pcictrlreg *pm_pcictrl_reg;
372 void __iomem *addrbase;
373
374 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
375 addrbase = host->pcictrl_mmiobase;
376
377 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
378 pm_pcictrl_reg->pciclkgat_reg |=
379 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
380 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
381 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
382 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
383 pm_pcictrl_reg->pciintstatus_reg =
384 readb(addrbase + VIA_CRDR_PCIINTSTATUS);
385 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
386 }
387
388 static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
389 {
390 struct pcictrlreg *pm_pcictrl_reg;
391 void __iomem *addrbase;
392
393 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
394 addrbase = host->pcictrl_mmiobase;
395
396 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
397 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
398 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
399 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
400 writeb(pm_pcictrl_reg->pciintstatus_reg,
401 addrbase + VIA_CRDR_PCIINTSTATUS);
402 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
403 }
404
405 static void via_save_sdcreg(struct via_crdr_mmc_host *host)
406 {
407 struct sdhcreg *pm_sdhc_reg;
408 void __iomem *addrbase;
409
410 pm_sdhc_reg = &(host->pm_sdhc_reg);
411 addrbase = host->sdhc_mmiobase;
412
413 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
414 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
415 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
416 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
417 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
418 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
419 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
420 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
421 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
422 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
423 }
424
425 static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
426 {
427 struct sdhcreg *pm_sdhc_reg;
428 void __iomem *addrbase;
429
430 pm_sdhc_reg = &(host->pm_sdhc_reg);
431 addrbase = host->sdhc_mmiobase;
432
433 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
434 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
435 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
436 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
437 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
438 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
439 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
440 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
441 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
442 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
443 }
444
445 static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
446 {
447 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
448 msleep(300);
449 else
450 msleep(3);
451 }
452
453 static void via_set_ddma(struct via_crdr_mmc_host *host,
454 dma_addr_t dmaaddr, u32 count, int dir, int enirq)
455 {
456 void __iomem *addrbase;
457 u32 ctrl_data = 0;
458
459 if (enirq)
460 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
461
462 if (dir)
463 ctrl_data |= VIA_CRDR_DMACTRL_DIR;
464
465 addrbase = host->ddma_mmiobase;
466
467 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
468 writel(count, addrbase + VIA_CRDR_DMACOUNTER);
469 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
470 writel(0x01, addrbase + VIA_CRDR_DMASTART);
471
472 /* It seems that our DMA can not work normally with 375kHz clock */
473 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
474 addrbase = host->pcictrl_mmiobase;
475 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
476 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
477 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
478 }
479 }
480
481 static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
482 struct mmc_data *data)
483 {
484 void __iomem *addrbase;
485 u32 blk_reg;
486 int count;
487
488 WARN_ON(host->data);
489
490 /* Sanity checks */
491 BUG_ON(data->blksz > host->mmc->max_blk_size);
492 BUG_ON(data->blocks > host->mmc->max_blk_count);
493
494 host->data = data;
495
496 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
497 ((data->flags & MMC_DATA_READ) ?
498 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
499 BUG_ON(count != 1);
500
501 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
502 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
503
504 addrbase = host->sdhc_mmiobase;
505
506 blk_reg = data->blksz - 1;
507 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
508 blk_reg |= (data->blocks) << 16;
509
510 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
511 }
512
513 static void via_sdc_get_response(struct via_crdr_mmc_host *host,
514 struct mmc_command *cmd)
515 {
516 void __iomem *addrbase = host->sdhc_mmiobase;
517 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
518 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
519 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
520 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
521
522 if (cmd->flags & MMC_RSP_136) {
523 cmd->resp[0] = ((u8) (dwdata1)) |
524 (((u8) (dwdata0 >> 24)) << 8) |
525 (((u8) (dwdata0 >> 16)) << 16) |
526 (((u8) (dwdata0 >> 8)) << 24);
527
528 cmd->resp[1] = ((u8) (dwdata2)) |
529 (((u8) (dwdata1 >> 24)) << 8) |
530 (((u8) (dwdata1 >> 16)) << 16) |
531 (((u8) (dwdata1 >> 8)) << 24);
532
533 cmd->resp[2] = ((u8) (dwdata3)) |
534 (((u8) (dwdata2 >> 24)) << 8) |
535 (((u8) (dwdata2 >> 16)) << 16) |
536 (((u8) (dwdata2 >> 8)) << 24);
537
538 cmd->resp[3] = 0xff |
539 ((((u8) (dwdata3 >> 24))) << 8) |
540 (((u8) (dwdata3 >> 16)) << 16) |
541 (((u8) (dwdata3 >> 8)) << 24);
542 } else {
543 dwdata0 >>= 8;
544 cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
545 (((dwdata0 >> 8) & 0xff) << 16) |
546 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
547
548 dwdata1 >>= 8;
549 cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
550 (((dwdata1 >> 8) & 0xff) << 16) |
551 (((dwdata1 >> 16) & 0xff) << 8);
552 }
553 }
554
555 static void via_sdc_send_command(struct via_crdr_mmc_host *host,
556 struct mmc_command *cmd)
557 {
558 void __iomem *addrbase;
559 struct mmc_data *data;
560 unsigned int timeout_ms;
561 u32 cmdctrl = 0;
562
563 WARN_ON(host->cmd);
564
565 data = cmd->data;
566 host->cmd = cmd;
567
568 timeout_ms = cmd->busy_timeout ? cmd->busy_timeout : VIA_CMD_TIMEOUT_MS;
569 mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms));
570
571 /*Command index*/
572 cmdctrl = cmd->opcode << 8;
573
574 /*Response type*/
575 switch (mmc_resp_type(cmd)) {
576 case MMC_RSP_NONE:
577 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
578 break;
579 case MMC_RSP_R1:
580 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
581 break;
582 case MMC_RSP_R1B:
583 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
584 break;
585 case MMC_RSP_R2:
586 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
587 break;
588 case MMC_RSP_R3:
589 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
590 break;
591 default:
592 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
593 break;
594 }
595
596 if (!(cmd->data))
597 goto nodata;
598
599 via_sdc_preparedata(host, data);
600
601 /*Command control*/
602 if (data->blocks > 1) {
603 if (data->flags & MMC_DATA_WRITE) {
604 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
605 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
606 } else {
607 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
608 }
609 } else {
610 if (data->flags & MMC_DATA_WRITE) {
611 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
612 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
613 } else {
614 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
615 }
616 }
617
618 nodata:
619 if (cmd == host->mrq->stop)
620 cmdctrl |= VIA_CRDR_SDCTRL_STOP;
621
622 cmdctrl |= VIA_CRDR_SDCTRL_START;
623
624 addrbase = host->sdhc_mmiobase;
625 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
626 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
627 }
628
629 static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
630 {
631 struct mmc_data *data;
632
633 BUG_ON(!host->data);
634
635 data = host->data;
636 host->data = NULL;
637
638 if (data->error)
639 data->bytes_xfered = 0;
640 else
641 data->bytes_xfered = data->blocks * data->blksz;
642
643 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
644 ((data->flags & MMC_DATA_READ) ?
645 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
646
647 if (data->stop)
648 via_sdc_send_command(host, data->stop);
649 else
650 tasklet_schedule(&host->finish_tasklet);
651 }
652
653 static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
654 {
655 via_sdc_get_response(host, host->cmd);
656
657 host->cmd->error = 0;
658
659 if (!host->cmd->data)
660 tasklet_schedule(&host->finish_tasklet);
661
662 host->cmd = NULL;
663 }
664
665 static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
666 {
667 void __iomem *addrbase;
668 struct via_crdr_mmc_host *host;
669 unsigned long flags;
670 u16 status;
671
672 host = mmc_priv(mmc);
673
674 spin_lock_irqsave(&host->lock, flags);
675
676 addrbase = host->pcictrl_mmiobase;
677 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
678
679 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
680 status &= VIA_CRDR_SDSTS_W1C_MASK;
681 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
682
683 WARN_ON(host->mrq != NULL);
684 host->mrq = mrq;
685
686 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
687 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
688 host->mrq->cmd->error = -ENOMEDIUM;
689 tasklet_schedule(&host->finish_tasklet);
690 } else {
691 via_sdc_send_command(host, mrq->cmd);
692 }
693
694 mmiowb();
695 spin_unlock_irqrestore(&host->lock, flags);
696 }
697
698 static void via_sdc_set_power(struct via_crdr_mmc_host *host,
699 unsigned short power, unsigned int on)
700 {
701 unsigned long flags;
702 u8 gatt;
703
704 spin_lock_irqsave(&host->lock, flags);
705
706 host->power = (1 << power);
707
708 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
709 if (host->power == MMC_VDD_165_195)
710 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
711 else
712 gatt |= VIA_CRDR_PCICLKGATT_3V3;
713 if (on)
714 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
715 else
716 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
717 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
718
719 mmiowb();
720 spin_unlock_irqrestore(&host->lock, flags);
721
722 via_pwron_sleep(host);
723 }
724
725 static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
726 {
727 struct via_crdr_mmc_host *host;
728 unsigned long flags;
729 void __iomem *addrbase;
730 u32 org_data, sdextctrl;
731 u8 clock;
732
733 host = mmc_priv(mmc);
734
735 spin_lock_irqsave(&host->lock, flags);
736
737 addrbase = host->sdhc_mmiobase;
738 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
739 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
740
741 if (ios->bus_width == MMC_BUS_WIDTH_1)
742 org_data &= ~VIA_CRDR_SDMODE_4BIT;
743 else
744 org_data |= VIA_CRDR_SDMODE_4BIT;
745
746 if (ios->power_mode == MMC_POWER_OFF)
747 org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
748 else
749 org_data |= VIA_CRDR_SDMODE_CLK_ON;
750
751 if (ios->timing == MMC_TIMING_SD_HS)
752 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
753 else
754 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
755
756 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
757 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
758
759 if (ios->clock >= 48000000)
760 clock = PCI_CLK_48M;
761 else if (ios->clock >= 33000000)
762 clock = PCI_CLK_33M;
763 else if (ios->clock >= 24000000)
764 clock = PCI_CLK_24M;
765 else if (ios->clock >= 16000000)
766 clock = PCI_CLK_16M;
767 else if (ios->clock >= 12000000)
768 clock = PCI_CLK_12M;
769 else if (ios->clock >= 8000000)
770 clock = PCI_CLK_8M;
771 else
772 clock = PCI_CLK_375K;
773
774 addrbase = host->pcictrl_mmiobase;
775 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
776 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
777
778 mmiowb();
779 spin_unlock_irqrestore(&host->lock, flags);
780
781 if (ios->power_mode != MMC_POWER_OFF)
782 via_sdc_set_power(host, ios->vdd, 1);
783 else
784 via_sdc_set_power(host, ios->vdd, 0);
785 }
786
787 static int via_sdc_get_ro(struct mmc_host *mmc)
788 {
789 struct via_crdr_mmc_host *host;
790 unsigned long flags;
791 u16 status;
792
793 host = mmc_priv(mmc);
794
795 spin_lock_irqsave(&host->lock, flags);
796
797 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
798
799 spin_unlock_irqrestore(&host->lock, flags);
800
801 return !(status & VIA_CRDR_SDSTS_WP);
802 }
803
804 static const struct mmc_host_ops via_sdc_ops = {
805 .request = via_sdc_request,
806 .set_ios = via_sdc_set_ios,
807 .get_ro = via_sdc_get_ro,
808 };
809
810 static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
811 {
812 unsigned long flags;
813 u8 gatt;
814
815 spin_lock_irqsave(&host->lock, flags);
816
817 via_save_pcictrlreg(host);
818 via_save_sdcreg(host);
819
820 spin_unlock_irqrestore(&host->lock, flags);
821
822 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
823 if (host->power == MMC_VDD_165_195)
824 gatt &= VIA_CRDR_PCICLKGATT_3V3;
825 else
826 gatt |= VIA_CRDR_PCICLKGATT_3V3;
827 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
828 via_pwron_sleep(host);
829 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
830 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
831 msleep(3);
832
833 spin_lock_irqsave(&host->lock, flags);
834
835 via_restore_pcictrlreg(host);
836 via_restore_sdcreg(host);
837
838 mmiowb();
839 spin_unlock_irqrestore(&host->lock, flags);
840 }
841
842 static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
843 {
844 BUG_ON(intmask == 0);
845
846 if (!host->cmd) {
847 pr_err("%s: Got command interrupt 0x%x even "
848 "though no command operation was in progress.\n",
849 mmc_hostname(host->mmc), intmask);
850 return;
851 }
852
853 if (intmask & VIA_CRDR_SDSTS_CRTO)
854 host->cmd->error = -ETIMEDOUT;
855 else if (intmask & VIA_CRDR_SDSTS_SC)
856 host->cmd->error = -EILSEQ;
857
858 if (host->cmd->error)
859 tasklet_schedule(&host->finish_tasklet);
860 else if (intmask & VIA_CRDR_SDSTS_CRD)
861 via_sdc_finish_command(host);
862 }
863
864 static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
865 {
866 BUG_ON(intmask == 0);
867
868 if (intmask & VIA_CRDR_SDSTS_DT)
869 host->data->error = -ETIMEDOUT;
870 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
871 host->data->error = -EILSEQ;
872
873 via_sdc_finish_data(host);
874 }
875
876 static irqreturn_t via_sdc_isr(int irq, void *dev_id)
877 {
878 struct via_crdr_mmc_host *sdhost = dev_id;
879 void __iomem *addrbase;
880 u8 pci_status;
881 u16 sd_status;
882 irqreturn_t result;
883
884 if (!sdhost)
885 return IRQ_NONE;
886
887 spin_lock(&sdhost->lock);
888
889 addrbase = sdhost->pcictrl_mmiobase;
890 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
891 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
892 result = IRQ_NONE;
893 goto out;
894 }
895
896 addrbase = sdhost->sdhc_mmiobase;
897 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
898 sd_status &= VIA_CRDR_SDSTS_INT_MASK;
899 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
900 if (!sd_status) {
901 result = IRQ_NONE;
902 goto out;
903 }
904
905 if (sd_status & VIA_CRDR_SDSTS_CIR) {
906 writew(sd_status & VIA_CRDR_SDSTS_CIR,
907 addrbase + VIA_CRDR_SDSTATUS);
908
909 schedule_work(&sdhost->carddet_work);
910 }
911
912 sd_status &= ~VIA_CRDR_SDSTS_CIR;
913 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
914 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
915 addrbase + VIA_CRDR_SDSTATUS);
916 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
917 }
918 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
919 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
920 addrbase + VIA_CRDR_SDSTATUS);
921 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
922 }
923
924 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
925 if (sd_status) {
926 pr_err("%s: Unexpected interrupt 0x%x\n",
927 mmc_hostname(sdhost->mmc), sd_status);
928 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
929 }
930
931 result = IRQ_HANDLED;
932
933 mmiowb();
934 out:
935 spin_unlock(&sdhost->lock);
936
937 return result;
938 }
939
940 static void via_sdc_timeout(struct timer_list *t)
941 {
942 struct via_crdr_mmc_host *sdhost;
943 unsigned long flags;
944
945 sdhost = from_timer(sdhost, t, timer);
946
947 spin_lock_irqsave(&sdhost->lock, flags);
948
949 if (sdhost->mrq) {
950 pr_err("%s: Timeout waiting for hardware interrupt."
951 "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
952 sdhost->mrq->cmd->opcode);
953
954 if (sdhost->data) {
955 writel(VIA_CRDR_DMACTRL_SFTRST,
956 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
957 sdhost->data->error = -ETIMEDOUT;
958 via_sdc_finish_data(sdhost);
959 } else {
960 if (sdhost->cmd)
961 sdhost->cmd->error = -ETIMEDOUT;
962 else
963 sdhost->mrq->cmd->error = -ETIMEDOUT;
964 tasklet_schedule(&sdhost->finish_tasklet);
965 }
966 }
967
968 mmiowb();
969 spin_unlock_irqrestore(&sdhost->lock, flags);
970 }
971
972 static void via_sdc_tasklet_finish(unsigned long param)
973 {
974 struct via_crdr_mmc_host *host;
975 unsigned long flags;
976 struct mmc_request *mrq;
977
978 host = (struct via_crdr_mmc_host *)param;
979
980 spin_lock_irqsave(&host->lock, flags);
981
982 del_timer(&host->timer);
983 mrq = host->mrq;
984 host->mrq = NULL;
985 host->cmd = NULL;
986 host->data = NULL;
987
988 spin_unlock_irqrestore(&host->lock, flags);
989
990 mmc_request_done(host->mmc, mrq);
991 }
992
993 static void via_sdc_card_detect(struct work_struct *work)
994 {
995 struct via_crdr_mmc_host *host;
996 void __iomem *addrbase;
997 unsigned long flags;
998 u16 status;
999
1000 host = container_of(work, struct via_crdr_mmc_host, carddet_work);
1001
1002 addrbase = host->ddma_mmiobase;
1003 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
1004
1005 spin_lock_irqsave(&host->lock, flags);
1006
1007 addrbase = host->pcictrl_mmiobase;
1008 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
1009
1010 addrbase = host->sdhc_mmiobase;
1011 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1012 if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
1013 if (host->mrq) {
1014 pr_err("%s: Card removed during transfer!\n",
1015 mmc_hostname(host->mmc));
1016 host->mrq->cmd->error = -ENOMEDIUM;
1017 tasklet_schedule(&host->finish_tasklet);
1018 }
1019
1020 mmiowb();
1021 spin_unlock_irqrestore(&host->lock, flags);
1022
1023 via_reset_pcictrl(host);
1024
1025 spin_lock_irqsave(&host->lock, flags);
1026 }
1027
1028 mmiowb();
1029 spin_unlock_irqrestore(&host->lock, flags);
1030
1031 via_print_pcictrl(host);
1032 via_print_sdchc(host);
1033
1034 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1035 }
1036
1037 static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1038 {
1039 struct mmc_host *mmc = host->mmc;
1040 void __iomem *addrbase;
1041 u32 lenreg;
1042 u32 status;
1043
1044 timer_setup(&host->timer, via_sdc_timeout, 0);
1045
1046 spin_lock_init(&host->lock);
1047
1048 mmc->f_min = VIA_CRDR_MIN_CLOCK;
1049 mmc->f_max = VIA_CRDR_MAX_CLOCK;
1050 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1051 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1052 mmc->ops = &via_sdc_ops;
1053
1054 /*Hardware cannot do scatter lists*/
1055 mmc->max_segs = 1;
1056
1057 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1058 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1059
1060 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1061 mmc->max_req_size = mmc->max_seg_size;
1062
1063 INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1064
1065 tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish,
1066 (unsigned long)host);
1067
1068 addrbase = host->sdhc_mmiobase;
1069 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1070 msleep(1);
1071
1072 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1073 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1074
1075 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1076 status &= VIA_CRDR_SDSTS_W1C_MASK;
1077 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1078
1079 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1080 status |= VIA_CRDR_SDSTS_CFE;
1081 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1082
1083 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1084
1085 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1086 msleep(1);
1087 }
1088
1089 static int via_sd_probe(struct pci_dev *pcidev,
1090 const struct pci_device_id *id)
1091 {
1092 struct mmc_host *mmc;
1093 struct via_crdr_mmc_host *sdhost;
1094 u32 base, len;
1095 u8 gatt;
1096 int ret;
1097
1098 pr_info(DRV_NAME
1099 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1100 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1101 (int)pcidev->revision);
1102
1103 ret = pci_enable_device(pcidev);
1104 if (ret)
1105 return ret;
1106
1107 ret = pci_request_regions(pcidev, DRV_NAME);
1108 if (ret)
1109 goto disable;
1110
1111 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1112 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1113
1114 mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1115 if (!mmc) {
1116 ret = -ENOMEM;
1117 goto release;
1118 }
1119
1120 sdhost = mmc_priv(mmc);
1121 sdhost->mmc = mmc;
1122 dev_set_drvdata(&pcidev->dev, sdhost);
1123
1124 len = pci_resource_len(pcidev, 0);
1125 base = pci_resource_start(pcidev, 0);
1126 sdhost->mmiobase = ioremap_nocache(base, len);
1127 if (!sdhost->mmiobase) {
1128 ret = -ENOMEM;
1129 goto free_mmc_host;
1130 }
1131
1132 sdhost->sdhc_mmiobase =
1133 sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1134 sdhost->ddma_mmiobase =
1135 sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1136 sdhost->pcictrl_mmiobase =
1137 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1138
1139 sdhost->power = MMC_VDD_165_195;
1140
1141 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1142 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1143 via_pwron_sleep(sdhost);
1144 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1145 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1146 msleep(3);
1147
1148 via_init_mmc_host(sdhost);
1149
1150 ret =
1151 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1152 sdhost);
1153 if (ret)
1154 goto unmap;
1155
1156 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1157 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1158 writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1159 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1160
1161 /* device-specific quirks */
1162 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1163 pcidev->subsystem_device == 0x3891)
1164 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1165
1166 mmc_add_host(mmc);
1167
1168 return 0;
1169
1170 unmap:
1171 iounmap(sdhost->mmiobase);
1172 free_mmc_host:
1173 dev_set_drvdata(&pcidev->dev, NULL);
1174 mmc_free_host(mmc);
1175 release:
1176 pci_release_regions(pcidev);
1177 disable:
1178 pci_disable_device(pcidev);
1179
1180 return ret;
1181 }
1182
1183 static void via_sd_remove(struct pci_dev *pcidev)
1184 {
1185 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1186 unsigned long flags;
1187 u8 gatt;
1188
1189 spin_lock_irqsave(&sdhost->lock, flags);
1190
1191 /* Ensure we don't accept more commands from mmc layer */
1192 sdhost->reject = 1;
1193
1194 /* Disable generating further interrupts */
1195 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1196 mmiowb();
1197
1198 if (sdhost->mrq) {
1199 pr_err("%s: Controller removed during "
1200 "transfer\n", mmc_hostname(sdhost->mmc));
1201
1202 /* make sure all DMA is stopped */
1203 writel(VIA_CRDR_DMACTRL_SFTRST,
1204 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1205 mmiowb();
1206 sdhost->mrq->cmd->error = -ENOMEDIUM;
1207 if (sdhost->mrq->stop)
1208 sdhost->mrq->stop->error = -ENOMEDIUM;
1209 tasklet_schedule(&sdhost->finish_tasklet);
1210 }
1211 spin_unlock_irqrestore(&sdhost->lock, flags);
1212
1213 mmc_remove_host(sdhost->mmc);
1214
1215 free_irq(pcidev->irq, sdhost);
1216
1217 del_timer_sync(&sdhost->timer);
1218
1219 tasklet_kill(&sdhost->finish_tasklet);
1220
1221 /* switch off power */
1222 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1223 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1224 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1225
1226 iounmap(sdhost->mmiobase);
1227 dev_set_drvdata(&pcidev->dev, NULL);
1228 mmc_free_host(sdhost->mmc);
1229 pci_release_regions(pcidev);
1230 pci_disable_device(pcidev);
1231
1232 pr_info(DRV_NAME
1233 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1234 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1235 }
1236
1237 #ifdef CONFIG_PM
1238
1239 static void via_init_sdc_pm(struct via_crdr_mmc_host *host)
1240 {
1241 struct sdhcreg *pm_sdhcreg;
1242 void __iomem *addrbase;
1243 u32 lenreg;
1244 u16 status;
1245
1246 pm_sdhcreg = &(host->pm_sdhc_reg);
1247 addrbase = host->sdhc_mmiobase;
1248
1249 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1250
1251 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1252 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1253
1254 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1255 status &= VIA_CRDR_SDSTS_W1C_MASK;
1256 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1257
1258 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1259 status |= VIA_CRDR_SDSTS_CFE;
1260 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1261
1262 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1263 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1264 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1265 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1266 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1267 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1268
1269 via_print_pcictrl(host);
1270 via_print_sdchc(host);
1271 }
1272
1273 static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state)
1274 {
1275 struct via_crdr_mmc_host *host;
1276
1277 host = pci_get_drvdata(pcidev);
1278
1279 via_save_pcictrlreg(host);
1280 via_save_sdcreg(host);
1281
1282 pci_save_state(pcidev);
1283 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1284 pci_disable_device(pcidev);
1285 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1286
1287 return 0;
1288 }
1289
1290 static int via_sd_resume(struct pci_dev *pcidev)
1291 {
1292 struct via_crdr_mmc_host *sdhost;
1293 int ret = 0;
1294 u8 gatt;
1295
1296 sdhost = pci_get_drvdata(pcidev);
1297
1298 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1299 if (sdhost->power == MMC_VDD_165_195)
1300 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1301 else
1302 gatt |= VIA_CRDR_PCICLKGATT_3V3;
1303 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1304 via_pwron_sleep(sdhost);
1305 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1306 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1307 msleep(3);
1308
1309 msleep(100);
1310
1311 pci_set_power_state(pcidev, PCI_D0);
1312 pci_restore_state(pcidev);
1313 ret = pci_enable_device(pcidev);
1314 if (ret)
1315 return ret;
1316
1317 via_restore_pcictrlreg(sdhost);
1318 via_init_sdc_pm(sdhost);
1319
1320 return ret;
1321 }
1322
1323 #else /* CONFIG_PM */
1324
1325 #define via_sd_suspend NULL
1326 #define via_sd_resume NULL
1327
1328 #endif /* CONFIG_PM */
1329
1330 static struct pci_driver via_sd_driver = {
1331 .name = DRV_NAME,
1332 .id_table = via_ids,
1333 .probe = via_sd_probe,
1334 .remove = via_sd_remove,
1335 .suspend = via_sd_suspend,
1336 .resume = via_sd_resume,
1337 };
1338
1339 module_pci_driver(via_sd_driver);
1340
1341 MODULE_LICENSE("GPL");
1342 MODULE_AUTHOR("VIA Technologies Inc.");
1343 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");
Linux with added FPC-III support