drivers/mtd/nand/raw/ams-delta.c

   1 /*
   2  *  Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
   3  *
   4  *  Derived from drivers/mtd/nand/toto.c (removed in v2.6.28)
   5  *    Copyright (c) 2003 Texas Instruments
   6  *    Copyright (c) 2002 Thomas Gleixner <tgxl@linutronix.de>
   7  *
   8  *  Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
   9  *  Partially stolen from plat_nand.c
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  *  Overview:
  16  *   This is a device driver for the NAND flash device found on the
  17  *   Amstrad E3 (Delta).
  18  */
  19
  20 #include <linux/slab.h>
  21 #include <linux/module.h>
  22 #include <linux/delay.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/rawnand.h>
  25 #include <linux/mtd/partitions.h>
  26 #include <linux/gpio.h>
  27 #include <linux/platform_data/gpio-omap.h>
  28
  29 #include <asm/io.h>
  30 #include <asm/sizes.h>
  31
  32 #include <mach/board-ams-delta.h>
  33
  34 #include <mach/hardware.h>
  35
  36 /*
  37  * MTD structure for E3 (Delta)
  38  */
  39 static struct mtd_info *ams_delta_mtd = NULL;
  40
  41 /*
  42  * Define partitions for flash devices
  43  */
  44
  45 static const struct mtd_partition partition_info[] = {
  46         { .name         = "Kernel",
  47           .offset       = 0,
  48           .size         = 3 * SZ_1M + SZ_512K },
  49         { .name         = "u-boot",
  50           .offset       = 3 * SZ_1M + SZ_512K,
  51           .size         = SZ_256K },
  52         { .name         = "u-boot params",
  53           .offset       = 3 * SZ_1M + SZ_512K + SZ_256K,
  54           .size         = SZ_256K },
  55         { .name         = "Amstrad LDR",
  56           .offset       = 4 * SZ_1M,
  57           .size         = SZ_256K },
  58         { .name         = "File system",
  59           .offset       = 4 * SZ_1M + 1 * SZ_256K,
  60           .size         = 27 * SZ_1M },
  61         { .name         = "PBL reserved",
  62           .offset       = 32 * SZ_1M - 3 * SZ_256K,
  63           .size         =  3 * SZ_256K },
  64 };
  65
  66 static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
  67 {
  68         struct nand_chip *this = mtd_to_nand(mtd);
  69         void __iomem *io_base = (void __iomem *)nand_get_controller_data(this);
  70
  71         writew(0, io_base + OMAP_MPUIO_IO_CNTL);
  72         writew(byte, this->IO_ADDR_W);
  73         gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0);
  74         ndelay(40);
  75         gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1);
  76 }
  77
  78 static u_char ams_delta_read_byte(struct mtd_info *mtd)
  79 {
  80         u_char res;
  81         struct nand_chip *this = mtd_to_nand(mtd);
  82         void __iomem *io_base = (void __iomem *)nand_get_controller_data(this);
  83
  84         gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 0);
  85         ndelay(40);
  86         writew(~0, io_base + OMAP_MPUIO_IO_CNTL);
  87         res = readw(this->IO_ADDR_R);
  88         gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 1);
  89
  90         return res;
  91 }
  92
  93 static void ams_delta_write_buf(struct mtd_info *mtd, const u_char *buf,
  94                                 int len)
  95 {
  96         int i;
  97
  98         for (i=0; i<len; i++)
  99                 ams_delta_write_byte(mtd, buf[i]);
 100 }
 101
 102 static void ams_delta_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 103 {
 104         int i;
 105
 106         for (i=0; i<len; i++)
 107                 buf[i] = ams_delta_read_byte(mtd);
 108 }
 109
 110 /*
 111  * Command control function
 112  *
 113  * ctrl:
 114  * NAND_NCE: bit 0 -> bit 2
 115  * NAND_CLE: bit 1 -> bit 7
 116  * NAND_ALE: bit 2 -> bit 6
 117  */
 118 static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd,
 119                                 unsigned int ctrl)
 120 {
 121
 122         if (ctrl & NAND_CTRL_CHANGE) {
 123                 gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NCE,
 124                                 (ctrl & NAND_NCE) == 0);
 125                 gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_CLE,
 126                                 (ctrl & NAND_CLE) != 0);
 127                 gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_ALE,
 128                                 (ctrl & NAND_ALE) != 0);
 129         }
 130
 131         if (cmd != NAND_CMD_NONE)
 132                 ams_delta_write_byte(mtd, cmd);
 133 }
 134
 135 static int ams_delta_nand_ready(struct mtd_info *mtd)
 136 {
 137         return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB);
 138 }
 139
 140 static const struct gpio _mandatory_gpio[] = {
 141         {
 142                 .gpio   = AMS_DELTA_GPIO_PIN_NAND_NCE,
 143                 .flags  = GPIOF_OUT_INIT_HIGH,
 144                 .label  = "nand_nce",
 145         },
 146         {
 147                 .gpio   = AMS_DELTA_GPIO_PIN_NAND_NRE,
 148                 .flags  = GPIOF_OUT_INIT_HIGH,
 149                 .label  = "nand_nre",
 150         },
 151         {
 152                 .gpio   = AMS_DELTA_GPIO_PIN_NAND_NWP,
 153                 .flags  = GPIOF_OUT_INIT_HIGH,
 154                 .label  = "nand_nwp",
 155         },
 156         {
 157                 .gpio   = AMS_DELTA_GPIO_PIN_NAND_NWE,
 158                 .flags  = GPIOF_OUT_INIT_HIGH,
 159                 .label  = "nand_nwe",
 160         },
 161         {
 162                 .gpio   = AMS_DELTA_GPIO_PIN_NAND_ALE,
 163                 .flags  = GPIOF_OUT_INIT_LOW,
 164                 .label  = "nand_ale",
 165         },
 166         {
 167                 .gpio   = AMS_DELTA_GPIO_PIN_NAND_CLE,
 168                 .flags  = GPIOF_OUT_INIT_LOW,
 169                 .label  = "nand_cle",
 170         },
 171 };
 172
 173 /*
 174  * Main initialization routine
 175  */
 176 static int ams_delta_init(struct platform_device *pdev)
 177 {
 178         struct nand_chip *this;
 179         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 180         void __iomem *io_base;
 181         int err = 0;
 182
 183         if (!res)
 184                 return -ENXIO;
 185
 186         /* Allocate memory for MTD device structure and private data */
 187         this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
 188         if (!this) {
 189                 pr_warn("Unable to allocate E3 NAND MTD device structure.\n");
 190                 err = -ENOMEM;
 191                 goto out;
 192         }
 193
 194         ams_delta_mtd = nand_to_mtd(this);
 195         ams_delta_mtd->owner = THIS_MODULE;
 196
 197         /*
 198          * Don't try to request the memory region from here,
 199          * it should have been already requested from the
 200          * gpio-omap driver and requesting it again would fail.
 201          */
 202
 203         io_base = ioremap(res->start, resource_size(res));
 204         if (io_base == NULL) {
 205                 dev_err(&pdev->dev, "ioremap failed\n");
 206                 err = -EIO;
 207                 goto out_free;
 208         }
 209
 210         nand_set_controller_data(this, (void *)io_base);
 211
 212         /* Set address of NAND IO lines */
 213         this->IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH;
 214         this->IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT;
 215         this->read_byte = ams_delta_read_byte;
 216         this->write_buf = ams_delta_write_buf;
 217         this->read_buf = ams_delta_read_buf;
 218         this->cmd_ctrl = ams_delta_hwcontrol;
 219         if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) {
 220                 this->dev_ready = ams_delta_nand_ready;
 221         } else {
 222                 this->dev_ready = NULL;
 223                 pr_notice("Couldn't request gpio for Delta NAND ready.\n");
 224         }
 225         /* 25 us command delay time */
 226         this->chip_delay = 30;
 227         this->ecc.mode = NAND_ECC_SOFT;
 228         this->ecc.algo = NAND_ECC_HAMMING;
 229
 230         platform_set_drvdata(pdev, io_base);
 231
 232         /* Set chip enabled, but  */
 233         err = gpio_request_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
 234         if (err)
 235                 goto out_gpio;
 236
 237         /* Scan to find existence of the device */
 238         err = nand_scan(this, 1);
 239         if (err)
 240                 goto out_mtd;
 241
 242         /* Register the partitions */
 243         mtd_device_register(ams_delta_mtd, partition_info,
 244                             ARRAY_SIZE(partition_info));
 245
 246         goto out;
 247
 248  out_mtd:
 249         gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
 250 out_gpio:
 251         gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
 252         iounmap(io_base);
 253 out_free:
 254         kfree(this);
 255  out:
 256         return err;
 257 }
 258
 259 /*
 260  * Clean up routine
 261  */
 262 static int ams_delta_cleanup(struct platform_device *pdev)
 263 {
 264         void __iomem *io_base = platform_get_drvdata(pdev);
 265
 266         /* Release resources, unregister device */
 267         nand_release(mtd_to_nand(ams_delta_mtd));
 268
 269         gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
 270         gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
 271         iounmap(io_base);
 272
 273         /* Free the MTD device structure */
 274         kfree(mtd_to_nand(ams_delta_mtd));
 275
 276         return 0;
 277 }
 278
 279 static struct platform_driver ams_delta_nand_driver = {
 280         .probe          = ams_delta_init,
 281         .remove         = ams_delta_cleanup,
 282         .driver         = {
 283                 .name   = "ams-delta-nand",
 284         },
 285 };
 286
 287 module_platform_driver(ams_delta_nand_driver);
 288
 289 MODULE_LICENSE("GPL");
 290 MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
 291 MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");