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Linux 4.19.133
[linux/fpc-iii.git] / drivers / mtd / nand / raw / atmel / nand-controller.c
blobee1c401f131f46e3d6694c0b4abcc8d00b69a900
1 /*
2 * Copyright 2017 ATMEL
3 * Copyright 2017 Free Electrons
4 *
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
6 *
7 * Derived from the atmel_nand.c driver which contained the following
8 * copyrights:
9 *
10 * Copyright 2003 Rick Bronson
11 *
12 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
13 * Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
14 *
15 * Derived from drivers/mtd/spia.c (removed in v3.8)
16 * Copyright 2000 Steven J. Hill (sjhill@cotw.com)
17 *
18 *
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
20 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
21 *
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
24 * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
25 *
26 * Add Programmable Multibit ECC support for various AT91 SoC
27 * Copyright 2012 ATMEL, Hong Xu
28 *
29 * Add Nand Flash Controller support for SAMA5 SoC
30 * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
31 *
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License version 2 as
34 * published by the Free Software Foundation.
35 *
36 * A few words about the naming convention in this file. This convention
37 * applies to structure and function names.
38 *
39 * Prefixes:
40 *
41 * - atmel_nand_: all generic structures/functions
42 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
43 * (at91sam9 and avr32 SoCs)
44 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
45 * (sama5 SoCs and later)
46 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
47 * that is available in the HSMC block
48 * - <soc>_nand_: all SoC specific structures/functions
49 */
50
51 #include <linux/clk.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/dmaengine.h>
54 #include <linux/genalloc.h>
55 #include <linux/gpio/consumer.h>
56 #include <linux/interrupt.h>
57 #include <linux/mfd/syscon.h>
58 #include <linux/mfd/syscon/atmel-matrix.h>
59 #include <linux/mfd/syscon/atmel-smc.h>
60 #include <linux/module.h>
61 #include <linux/mtd/rawnand.h>
62 #include <linux/of_address.h>
63 #include <linux/of_irq.h>
64 #include <linux/of_platform.h>
65 #include <linux/iopoll.h>
66 #include <linux/platform_device.h>
67 #include <linux/regmap.h>
68
69 #include "pmecc.h"
70
71 #define ATMEL_HSMC_NFC_CFG 0x0
72 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)
73 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)
74 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20))
75 #define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16)
76 #define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13)
77 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12)
78 #define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9)
79 #define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8)
80 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0)
81 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
82
83 #define ATMEL_HSMC_NFC_CTRL 0x4
84 #define ATMEL_HSMC_NFC_CTRL_EN BIT(0)
85 #define ATMEL_HSMC_NFC_CTRL_DIS BIT(1)
86
87 #define ATMEL_HSMC_NFC_SR 0x8
88 #define ATMEL_HSMC_NFC_IER 0xc
89 #define ATMEL_HSMC_NFC_IDR 0x10
90 #define ATMEL_HSMC_NFC_IMR 0x14
91 #define ATMEL_HSMC_NFC_SR_ENABLED BIT(1)
92 #define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4)
93 #define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5)
94 #define ATMEL_HSMC_NFC_SR_BUSY BIT(8)
95 #define ATMEL_HSMC_NFC_SR_WR BIT(11)
96 #define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12)
97 #define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16)
98 #define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17)
99 #define ATMEL_HSMC_NFC_SR_DTOE BIT(20)
100 #define ATMEL_HSMC_NFC_SR_UNDEF BIT(21)
101 #define ATMEL_HSMC_NFC_SR_AWB BIT(22)
102 #define ATMEL_HSMC_NFC_SR_NFCASE BIT(23)
103 #define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \
104 ATMEL_HSMC_NFC_SR_UNDEF | \
105 ATMEL_HSMC_NFC_SR_AWB | \
106 ATMEL_HSMC_NFC_SR_NFCASE)
107 #define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24)
108
109 #define ATMEL_HSMC_NFC_ADDR 0x18
110 #define ATMEL_HSMC_NFC_BANK 0x1c
111
112 #define ATMEL_NFC_MAX_RB_ID 7
113
114 #define ATMEL_NFC_SRAM_SIZE 0x2400
115
116 #define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2))
117 #define ATMEL_NFC_VCMD2 BIT(18)
118 #define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19)
119 #define ATMEL_NFC_CSID(cs) ((cs) << 22)
120 #define ATMEL_NFC_DATAEN BIT(25)
121 #define ATMEL_NFC_NFCWR BIT(26)
122
123 #define ATMEL_NFC_MAX_ADDR_CYCLES 5
124
125 #define ATMEL_NAND_ALE_OFFSET BIT(21)
126 #define ATMEL_NAND_CLE_OFFSET BIT(22)
127
128 #define DEFAULT_TIMEOUT_MS 1000
129 #define MIN_DMA_LEN 128
130
131 static bool atmel_nand_avoid_dma __read_mostly;
132
133 MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
134 module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);
135
136 enum atmel_nand_rb_type {
137 ATMEL_NAND_NO_RB,
138 ATMEL_NAND_NATIVE_RB,
139 ATMEL_NAND_GPIO_RB,
140 };
141
142 struct atmel_nand_rb {
143 enum atmel_nand_rb_type type;
144 union {
145 struct gpio_desc *gpio;
146 int id;
147 };
148 };
149
150 struct atmel_nand_cs {
151 int id;
152 struct atmel_nand_rb rb;
153 struct gpio_desc *csgpio;
154 struct {
155 void __iomem *virt;
156 dma_addr_t dma;
157 } io;
158
159 struct atmel_smc_cs_conf smcconf;
160 };
161
162 struct atmel_nand {
163 struct list_head node;
164 struct device *dev;
165 struct nand_chip base;
166 struct atmel_nand_cs *activecs;
167 struct atmel_pmecc_user *pmecc;
168 struct gpio_desc *cdgpio;
169 int numcs;
170 struct atmel_nand_cs cs[];
171 };
172
173 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
174 {
175 return container_of(chip, struct atmel_nand, base);
176 }
177
178 enum atmel_nfc_data_xfer {
179 ATMEL_NFC_NO_DATA,
180 ATMEL_NFC_READ_DATA,
181 ATMEL_NFC_WRITE_DATA,
182 };
183
184 struct atmel_nfc_op {
185 u8 cs;
186 u8 ncmds;
187 u8 cmds[2];
188 u8 naddrs;
189 u8 addrs[5];
190 enum atmel_nfc_data_xfer data;
191 u32 wait;
192 u32 errors;
193 };
194
195 struct atmel_nand_controller;
196 struct atmel_nand_controller_caps;
197
198 struct atmel_nand_controller_ops {
199 int (*probe)(struct platform_device *pdev,
200 const struct atmel_nand_controller_caps *caps);
201 int (*remove)(struct atmel_nand_controller *nc);
202 void (*nand_init)(struct atmel_nand_controller *nc,
203 struct atmel_nand *nand);
204 int (*ecc_init)(struct nand_chip *chip);
205 int (*setup_data_interface)(struct atmel_nand *nand, int csline,
206 const struct nand_data_interface *conf);
207 };
208
209 struct atmel_nand_controller_caps {
210 bool has_dma;
211 bool legacy_of_bindings;
212 u32 ale_offs;
213 u32 cle_offs;
214 const struct atmel_nand_controller_ops *ops;
215 };
216
217 struct atmel_nand_controller {
218 struct nand_controller base;
219 const struct atmel_nand_controller_caps *caps;
220 struct device *dev;
221 struct regmap *smc;
222 struct dma_chan *dmac;
223 struct atmel_pmecc *pmecc;
224 struct list_head chips;
225 struct clk *mck;
226 };
227
228 static inline struct atmel_nand_controller *
229 to_nand_controller(struct nand_controller *ctl)
230 {
231 return container_of(ctl, struct atmel_nand_controller, base);
232 }
233
234 struct atmel_smc_nand_controller {
235 struct atmel_nand_controller base;
236 struct regmap *matrix;
237 unsigned int ebi_csa_offs;
238 };
239
240 static inline struct atmel_smc_nand_controller *
241 to_smc_nand_controller(struct nand_controller *ctl)
242 {
243 return container_of(to_nand_controller(ctl),
244 struct atmel_smc_nand_controller, base);
245 }
246
247 struct atmel_hsmc_nand_controller {
248 struct atmel_nand_controller base;
249 struct {
250 struct gen_pool *pool;
251 void __iomem *virt;
252 dma_addr_t dma;
253 } sram;
254 const struct atmel_hsmc_reg_layout *hsmc_layout;
255 struct regmap *io;
256 struct atmel_nfc_op op;
257 struct completion complete;
258 int irq;
259
260 /* Only used when instantiating from legacy DT bindings. */
261 struct clk *clk;
262 };
263
264 static inline struct atmel_hsmc_nand_controller *
265 to_hsmc_nand_controller(struct nand_controller *ctl)
266 {
267 return container_of(to_nand_controller(ctl),
268 struct atmel_hsmc_nand_controller, base);
269 }
270
271 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
272 {
273 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
274 op->wait ^= status & op->wait;
275
276 return !op->wait || op->errors;
277 }
278
279 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
280 {
281 struct atmel_hsmc_nand_controller *nc = data;
282 u32 sr, rcvd;
283 bool done;
284
285 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
286
287 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
288 done = atmel_nfc_op_done(&nc->op, sr);
289
290 if (rcvd)
291 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
292
293 if (done)
294 complete(&nc->complete);
295
296 return rcvd ? IRQ_HANDLED : IRQ_NONE;
297 }
298
299 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
300 unsigned int timeout_ms)
301 {
302 int ret;
303
304 if (!timeout_ms)
305 timeout_ms = DEFAULT_TIMEOUT_MS;
306
307 if (poll) {
308 u32 status;
309
310 ret = regmap_read_poll_timeout(nc->base.smc,
311 ATMEL_HSMC_NFC_SR, status,
312 atmel_nfc_op_done(&nc->op,
313 status),
314 0, timeout_ms * 1000);
315 } else {
316 init_completion(&nc->complete);
317 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
318 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
319 ret = wait_for_completion_timeout(&nc->complete,
320 msecs_to_jiffies(timeout_ms));
321 if (!ret)
322 ret = -ETIMEDOUT;
323 else
324 ret = 0;
325
326 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
327 }
328
329 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
330 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
331 ret = -ETIMEDOUT;
332 }
333
334 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
335 dev_err(nc->base.dev, "Access to an undefined area\n");
336 ret = -EIO;
337 }
338
339 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
340 dev_err(nc->base.dev, "Access while busy\n");
341 ret = -EIO;
342 }
343
344 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
345 dev_err(nc->base.dev, "Wrong access size\n");
346 ret = -EIO;
347 }
348
349 return ret;
350 }
351
352 static void atmel_nand_dma_transfer_finished(void *data)
353 {
354 struct completion *finished = data;
355
356 complete(finished);
357 }
358
359 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
360 void *buf, dma_addr_t dev_dma, size_t len,
361 enum dma_data_direction dir)
362 {
363 DECLARE_COMPLETION_ONSTACK(finished);
364 dma_addr_t src_dma, dst_dma, buf_dma;
365 struct dma_async_tx_descriptor *tx;
366 dma_cookie_t cookie;
367
368 buf_dma = dma_map_single(nc->dev, buf, len, dir);
369 if (dma_mapping_error(nc->dev, dev_dma)) {
370 dev_err(nc->dev,
371 "Failed to prepare a buffer for DMA access\n");
372 goto err;
373 }
374
375 if (dir == DMA_FROM_DEVICE) {
376 src_dma = dev_dma;
377 dst_dma = buf_dma;
378 } else {
379 src_dma = buf_dma;
380 dst_dma = dev_dma;
381 }
382
383 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
384 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
385 if (!tx) {
386 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
387 goto err_unmap;
388 }
389
390 tx->callback = atmel_nand_dma_transfer_finished;
391 tx->callback_param = &finished;
392
393 cookie = dmaengine_submit(tx);
394 if (dma_submit_error(cookie)) {
395 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
396 goto err_unmap;
397 }
398
399 dma_async_issue_pending(nc->dmac);
400 wait_for_completion(&finished);
401
402 return 0;
403
404 err_unmap:
405 dma_unmap_single(nc->dev, buf_dma, len, dir);
406
407 err:
408 dev_dbg(nc->dev, "Fall back to CPU I/O\n");
409
410 return -EIO;
411 }
412
413 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
414 {
415 struct nand_chip *chip = mtd_to_nand(mtd);
416 struct atmel_nand *nand = to_atmel_nand(chip);
417
418 return ioread8(nand->activecs->io.virt);
419 }
420
421 static u16 atmel_nand_read_word(struct mtd_info *mtd)
422 {
423 struct nand_chip *chip = mtd_to_nand(mtd);
424 struct atmel_nand *nand = to_atmel_nand(chip);
425
426 return ioread16(nand->activecs->io.virt);
427 }
428
429 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
430 {
431 struct nand_chip *chip = mtd_to_nand(mtd);
432 struct atmel_nand *nand = to_atmel_nand(chip);
433
434 if (chip->options & NAND_BUSWIDTH_16)
435 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
436 else
437 iowrite8(byte, nand->activecs->io.virt);
438 }
439
440 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
441 {
442 struct nand_chip *chip = mtd_to_nand(mtd);
443 struct atmel_nand *nand = to_atmel_nand(chip);
444 struct atmel_nand_controller *nc;
445
446 nc = to_nand_controller(chip->controller);
447
448 /*
449 * If the controller supports DMA, the buffer address is DMA-able and
450 * len is long enough to make DMA transfers profitable, let's trigger
451 * a DMA transfer. If it fails, fallback to PIO mode.
452 */
453 if (nc->dmac && virt_addr_valid(buf) &&
454 len >= MIN_DMA_LEN &&
455 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
456 DMA_FROM_DEVICE))
457 return;
458
459 if (chip->options & NAND_BUSWIDTH_16)
460 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
461 else
462 ioread8_rep(nand->activecs->io.virt, buf, len);
463 }
464
465 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
466 {
467 struct nand_chip *chip = mtd_to_nand(mtd);
468 struct atmel_nand *nand = to_atmel_nand(chip);
469 struct atmel_nand_controller *nc;
470
471 nc = to_nand_controller(chip->controller);
472
473 /*
474 * If the controller supports DMA, the buffer address is DMA-able and
475 * len is long enough to make DMA transfers profitable, let's trigger
476 * a DMA transfer. If it fails, fallback to PIO mode.
477 */
478 if (nc->dmac && virt_addr_valid(buf) &&
479 len >= MIN_DMA_LEN &&
480 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
481 len, DMA_TO_DEVICE))
482 return;
483
484 if (chip->options & NAND_BUSWIDTH_16)
485 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
486 else
487 iowrite8_rep(nand->activecs->io.virt, buf, len);
488 }
489
490 static int atmel_nand_dev_ready(struct mtd_info *mtd)
491 {
492 struct nand_chip *chip = mtd_to_nand(mtd);
493 struct atmel_nand *nand = to_atmel_nand(chip);
494
495 return gpiod_get_value(nand->activecs->rb.gpio);
496 }
497
498 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
499 {
500 struct nand_chip *chip = mtd_to_nand(mtd);
501 struct atmel_nand *nand = to_atmel_nand(chip);
502
503 if (cs < 0 || cs >= nand->numcs) {
504 nand->activecs = NULL;
505 chip->dev_ready = NULL;
506 return;
507 }
508
509 nand->activecs = &nand->cs[cs];
510
511 if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
512 chip->dev_ready = atmel_nand_dev_ready;
513 }
514
515 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
516 {
517 struct nand_chip *chip = mtd_to_nand(mtd);
518 struct atmel_nand *nand = to_atmel_nand(chip);
519 struct atmel_hsmc_nand_controller *nc;
520 u32 status;
521
522 nc = to_hsmc_nand_controller(chip->controller);
523
524 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
525
526 return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
527 }
528
529 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
530 {
531 struct nand_chip *chip = mtd_to_nand(mtd);
532 struct atmel_nand *nand = to_atmel_nand(chip);
533 struct atmel_hsmc_nand_controller *nc;
534
535 nc = to_hsmc_nand_controller(chip->controller);
536
537 atmel_nand_select_chip(mtd, cs);
538
539 if (!nand->activecs) {
540 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
541 ATMEL_HSMC_NFC_CTRL_DIS);
542 return;
543 }
544
545 if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
546 chip->dev_ready = atmel_hsmc_nand_dev_ready;
547
548 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
549 ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
550 ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
551 ATMEL_HSMC_NFC_CFG_RSPARE |
552 ATMEL_HSMC_NFC_CFG_WSPARE,
553 ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
554 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
555 ATMEL_HSMC_NFC_CFG_RSPARE);
556 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
557 ATMEL_HSMC_NFC_CTRL_EN);
558 }
559
560 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
561 {
562 u8 *addrs = nc->op.addrs;
563 unsigned int op = 0;
564 u32 addr, val;
565 int i, ret;
566
567 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
568
569 for (i = 0; i < nc->op.ncmds; i++)
570 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
571
572 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
573 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
574
575 op |= ATMEL_NFC_CSID(nc->op.cs) |
576 ATMEL_NFC_ACYCLE(nc->op.naddrs);
577
578 if (nc->op.ncmds > 1)
579 op |= ATMEL_NFC_VCMD2;
580
581 addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
582 (addrs[3] << 24);
583
584 if (nc->op.data != ATMEL_NFC_NO_DATA) {
585 op |= ATMEL_NFC_DATAEN;
586 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
587
588 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
589 op |= ATMEL_NFC_NFCWR;
590 }
591
592 /* Clear all flags. */
593 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
594
595 /* Send the command. */
596 regmap_write(nc->io, op, addr);
597
598 ret = atmel_nfc_wait(nc, poll, 0);
599 if (ret)
600 dev_err(nc->base.dev,
601 "Failed to send NAND command (err = %d)!",
602 ret);
603
604 /* Reset the op state. */
605 memset(&nc->op, 0, sizeof(nc->op));
606
607 return ret;
608 }
609
610 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
611 unsigned int ctrl)
612 {
613 struct nand_chip *chip = mtd_to_nand(mtd);
614 struct atmel_nand *nand = to_atmel_nand(chip);
615 struct atmel_hsmc_nand_controller *nc;
616
617 nc = to_hsmc_nand_controller(chip->controller);
618
619 if (ctrl & NAND_ALE) {
620 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
621 return;
622
623 nc->op.addrs[nc->op.naddrs++] = dat;
624 } else if (ctrl & NAND_CLE) {
625 if (nc->op.ncmds > 1)
626 return;
627
628 nc->op.cmds[nc->op.ncmds++] = dat;
629 }
630
631 if (dat == NAND_CMD_NONE) {
632 nc->op.cs = nand->activecs->id;
633 atmel_nfc_exec_op(nc, true);
634 }
635 }
636
637 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
638 unsigned int ctrl)
639 {
640 struct nand_chip *chip = mtd_to_nand(mtd);
641 struct atmel_nand *nand = to_atmel_nand(chip);
642 struct atmel_nand_controller *nc;
643
644 nc = to_nand_controller(chip->controller);
645
646 if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
647 if (ctrl & NAND_NCE)
648 gpiod_set_value(nand->activecs->csgpio, 0);
649 else
650 gpiod_set_value(nand->activecs->csgpio, 1);
651 }
652
653 if (ctrl & NAND_ALE)
654 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
655 else if (ctrl & NAND_CLE)
656 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
657 }
658
659 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
660 bool oob_required)
661 {
662 struct mtd_info *mtd = nand_to_mtd(chip);
663 struct atmel_hsmc_nand_controller *nc;
664 int ret = -EIO;
665
666 nc = to_hsmc_nand_controller(chip->controller);
667
668 if (nc->base.dmac)
669 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
670 nc->sram.dma, mtd->writesize,
671 DMA_TO_DEVICE);
672
673 /* Falling back to CPU copy. */
674 if (ret)
675 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
676
677 if (oob_required)
678 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
679 mtd->oobsize);
680 }
681
682 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
683 bool oob_required)
684 {
685 struct mtd_info *mtd = nand_to_mtd(chip);
686 struct atmel_hsmc_nand_controller *nc;
687 int ret = -EIO;
688
689 nc = to_hsmc_nand_controller(chip->controller);
690
691 if (nc->base.dmac)
692 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
693 mtd->writesize, DMA_FROM_DEVICE);
694
695 /* Falling back to CPU copy. */
696 if (ret)
697 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
698
699 if (oob_required)
700 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
701 mtd->oobsize);
702 }
703
704 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
705 {
706 struct mtd_info *mtd = nand_to_mtd(chip);
707 struct atmel_hsmc_nand_controller *nc;
708
709 nc = to_hsmc_nand_controller(chip->controller);
710
711 if (column >= 0) {
712 nc->op.addrs[nc->op.naddrs++] = column;
713
714 /*
715 * 2 address cycles for the column offset on large page NANDs.
716 */
717 if (mtd->writesize > 512)
718 nc->op.addrs[nc->op.naddrs++] = column >> 8;
719 }
720
721 if (page >= 0) {
722 nc->op.addrs[nc->op.naddrs++] = page;
723 nc->op.addrs[nc->op.naddrs++] = page >> 8;
724
725 if (chip->options & NAND_ROW_ADDR_3)
726 nc->op.addrs[nc->op.naddrs++] = page >> 16;
727 }
728 }
729
730 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
731 {
732 struct atmel_nand *nand = to_atmel_nand(chip);
733 struct atmel_nand_controller *nc;
734 int ret;
735
736 nc = to_nand_controller(chip->controller);
737
738 if (raw)
739 return 0;
740
741 ret = atmel_pmecc_enable(nand->pmecc, op);
742 if (ret)
743 dev_err(nc->dev,
744 "Failed to enable ECC engine (err = %d)\n", ret);
745
746 return ret;
747 }
748
749 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
750 {
751 struct atmel_nand *nand = to_atmel_nand(chip);
752
753 if (!raw)
754 atmel_pmecc_disable(nand->pmecc);
755 }
756
757 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
758 {
759 struct atmel_nand *nand = to_atmel_nand(chip);
760 struct mtd_info *mtd = nand_to_mtd(chip);
761 struct atmel_nand_controller *nc;
762 struct mtd_oob_region oobregion;
763 void *eccbuf;
764 int ret, i;
765
766 nc = to_nand_controller(chip->controller);
767
768 if (raw)
769 return 0;
770
771 ret = atmel_pmecc_wait_rdy(nand->pmecc);
772 if (ret) {
773 dev_err(nc->dev,
774 "Failed to transfer NAND page data (err = %d)\n",
775 ret);
776 return ret;
777 }
778
779 mtd_ooblayout_ecc(mtd, 0, &oobregion);
780 eccbuf = chip->oob_poi + oobregion.offset;
781
782 for (i = 0; i < chip->ecc.steps; i++) {
783 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
784 eccbuf);
785 eccbuf += chip->ecc.bytes;
786 }
787
788 return 0;
789 }
790
791 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
792 bool raw)
793 {
794 struct atmel_nand *nand = to_atmel_nand(chip);
795 struct mtd_info *mtd = nand_to_mtd(chip);
796 struct atmel_nand_controller *nc;
797 struct mtd_oob_region oobregion;
798 int ret, i, max_bitflips = 0;
799 void *databuf, *eccbuf;
800
801 nc = to_nand_controller(chip->controller);
802
803 if (raw)
804 return 0;
805
806 ret = atmel_pmecc_wait_rdy(nand->pmecc);
807 if (ret) {
808 dev_err(nc->dev,
809 "Failed to read NAND page data (err = %d)\n",
810 ret);
811 return ret;
812 }
813
814 mtd_ooblayout_ecc(mtd, 0, &oobregion);
815 eccbuf = chip->oob_poi + oobregion.offset;
816 databuf = buf;
817
818 for (i = 0; i < chip->ecc.steps; i++) {
819 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
820 eccbuf);
821 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
822 ret = nand_check_erased_ecc_chunk(databuf,
823 chip->ecc.size,
824 eccbuf,
825 chip->ecc.bytes,
826 NULL, 0,
827 chip->ecc.strength);
828
829 if (ret >= 0)
830 max_bitflips = max(ret, max_bitflips);
831 else
832 mtd->ecc_stats.failed++;
833
834 databuf += chip->ecc.size;
835 eccbuf += chip->ecc.bytes;
836 }
837
838 return max_bitflips;
839 }
840
841 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
842 bool oob_required, int page, bool raw)
843 {
844 struct mtd_info *mtd = nand_to_mtd(chip);
845 struct atmel_nand *nand = to_atmel_nand(chip);
846 int ret;
847
848 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
849
850 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
851 if (ret)
852 return ret;
853
854 atmel_nand_write_buf(mtd, buf, mtd->writesize);
855
856 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
857 if (ret) {
858 atmel_pmecc_disable(nand->pmecc);
859 return ret;
860 }
861
862 atmel_nand_pmecc_disable(chip, raw);
863
864 atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
865
866 return nand_prog_page_end_op(chip);
867 }
868
869 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
870 struct nand_chip *chip, const u8 *buf,
871 int oob_required, int page)
872 {
873 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
874 }
875
876 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
877 struct nand_chip *chip,
878 const u8 *buf, int oob_required,
879 int page)
880 {
881 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
882 }
883
884 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
885 bool oob_required, int page, bool raw)
886 {
887 struct mtd_info *mtd = nand_to_mtd(chip);
888 int ret;
889
890 nand_read_page_op(chip, page, 0, NULL, 0);
891
892 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
893 if (ret)
894 return ret;
895
896 atmel_nand_read_buf(mtd, buf, mtd->writesize);
897 atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
898
899 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
900
901 atmel_nand_pmecc_disable(chip, raw);
902
903 return ret;
904 }
905
906 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
907 struct nand_chip *chip, u8 *buf,
908 int oob_required, int page)
909 {
910 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
911 }
912
913 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
914 struct nand_chip *chip, u8 *buf,
915 int oob_required, int page)
916 {
917 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
918 }
919
920 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
921 const u8 *buf, bool oob_required,
922 int page, bool raw)
923 {
924 struct mtd_info *mtd = nand_to_mtd(chip);
925 struct atmel_nand *nand = to_atmel_nand(chip);
926 struct atmel_hsmc_nand_controller *nc;
927 int ret, status;
928
929 nc = to_hsmc_nand_controller(chip->controller);
930
931 atmel_nfc_copy_to_sram(chip, buf, false);
932
933 nc->op.cmds[0] = NAND_CMD_SEQIN;
934 nc->op.ncmds = 1;
935 atmel_nfc_set_op_addr(chip, page, 0x0);
936 nc->op.cs = nand->activecs->id;
937 nc->op.data = ATMEL_NFC_WRITE_DATA;
938
939 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
940 if (ret)
941 return ret;
942
943 ret = atmel_nfc_exec_op(nc, false);
944 if (ret) {
945 atmel_nand_pmecc_disable(chip, raw);
946 dev_err(nc->base.dev,
947 "Failed to transfer NAND page data (err = %d)\n",
948 ret);
949 return ret;
950 }
951
952 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
953
954 atmel_nand_pmecc_disable(chip, raw);
955
956 if (ret)
957 return ret;
958
959 atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
960
961 nc->op.cmds[0] = NAND_CMD_PAGEPROG;
962 nc->op.ncmds = 1;
963 nc->op.cs = nand->activecs->id;
964 ret = atmel_nfc_exec_op(nc, false);
965 if (ret)
966 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
967 ret);
968
969 status = chip->waitfunc(mtd, chip);
970 if (status & NAND_STATUS_FAIL)
971 return -EIO;
972
973 return ret;
974 }
975
976 static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
977 struct nand_chip *chip,
978 const u8 *buf, int oob_required,
979 int page)
980 {
981 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
982 false);
983 }
984
985 static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
986 struct nand_chip *chip,
987 const u8 *buf,
988 int oob_required, int page)
989 {
990 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
991 true);
992 }
993
994 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
995 bool oob_required, int page,
996 bool raw)
997 {
998 struct mtd_info *mtd = nand_to_mtd(chip);
999 struct atmel_nand *nand = to_atmel_nand(chip);
1000 struct atmel_hsmc_nand_controller *nc;
1001 int ret;
1002
1003 nc = to_hsmc_nand_controller(chip->controller);
1004
1005 /*
1006 * Optimized read page accessors only work when the NAND R/B pin is
1007 * connected to a native SoC R/B pin. If that's not the case, fallback
1008 * to the non-optimized one.
1009 */
1010 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
1011 nand_read_page_op(chip, page, 0, NULL, 0);
1012
1013 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1014 raw);
1015 }
1016
1017 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1018
1019 if (mtd->writesize > 512)
1020 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1021
1022 atmel_nfc_set_op_addr(chip, page, 0x0);
1023 nc->op.cs = nand->activecs->id;
1024 nc->op.data = ATMEL_NFC_READ_DATA;
1025
1026 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1027 if (ret)
1028 return ret;
1029
1030 ret = atmel_nfc_exec_op(nc, false);
1031 if (ret) {
1032 atmel_nand_pmecc_disable(chip, raw);
1033 dev_err(nc->base.dev,
1034 "Failed to load NAND page data (err = %d)\n",
1035 ret);
1036 return ret;
1037 }
1038
1039 atmel_nfc_copy_from_sram(chip, buf, true);
1040
1041 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1042
1043 atmel_nand_pmecc_disable(chip, raw);
1044
1045 return ret;
1046 }
1047
1048 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
1049 struct nand_chip *chip, u8 *buf,
1050 int oob_required, int page)
1051 {
1052 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1053 false);
1054 }
1055
1056 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
1057 struct nand_chip *chip,
1058 u8 *buf, int oob_required,
1059 int page)
1060 {
1061 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1062 true);
1063 }
1064
1065 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1066 {
1067 struct mtd_info *mtd = nand_to_mtd(chip);
1068 struct atmel_nand *nand = to_atmel_nand(chip);
1069 struct atmel_nand_controller *nc;
1070 struct atmel_pmecc_user_req req;
1071
1072 nc = to_nand_controller(chip->controller);
1073
1074 if (!nc->pmecc) {
1075 dev_err(nc->dev, "HW ECC not supported\n");
1076 return -ENOTSUPP;
1077 }
1078
1079 if (nc->caps->legacy_of_bindings) {
1080 u32 val;
1081
1082 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1083 &val))
1084 chip->ecc.strength = val;
1085
1086 if (!of_property_read_u32(nc->dev->of_node,
1087 "atmel,pmecc-sector-size",
1088 &val))
1089 chip->ecc.size = val;
1090 }
1091
1092 if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1093 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1094 else if (chip->ecc.strength)
1095 req.ecc.strength = chip->ecc.strength;
1096 else if (chip->ecc_strength_ds)
1097 req.ecc.strength = chip->ecc_strength_ds;
1098 else
1099 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1100
1101 if (chip->ecc.size)
1102 req.ecc.sectorsize = chip->ecc.size;
1103 else if (chip->ecc_step_ds)
1104 req.ecc.sectorsize = chip->ecc_step_ds;
1105 else
1106 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1107
1108 req.pagesize = mtd->writesize;
1109 req.oobsize = mtd->oobsize;
1110
1111 if (mtd->writesize <= 512) {
1112 req.ecc.bytes = 4;
1113 req.ecc.ooboffset = 0;
1114 } else {
1115 req.ecc.bytes = mtd->oobsize - 2;
1116 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1117 }
1118
1119 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1120 if (IS_ERR(nand->pmecc))
1121 return PTR_ERR(nand->pmecc);
1122
1123 chip->ecc.algo = NAND_ECC_BCH;
1124 chip->ecc.size = req.ecc.sectorsize;
1125 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1126 chip->ecc.strength = req.ecc.strength;
1127
1128 chip->options |= NAND_NO_SUBPAGE_WRITE;
1129
1130 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1131
1132 return 0;
1133 }
1134
1135 static int atmel_nand_ecc_init(struct nand_chip *chip)
1136 {
1137 struct atmel_nand_controller *nc;
1138 int ret;
1139
1140 nc = to_nand_controller(chip->controller);
1141
1142 switch (chip->ecc.mode) {
1143 case NAND_ECC_NONE:
1144 case NAND_ECC_SOFT:
1145 /*
1146 * Nothing to do, the core will initialize everything for us.
1147 */
1148 break;
1149
1150 case NAND_ECC_HW:
1151 ret = atmel_nand_pmecc_init(chip);
1152 if (ret)
1153 return ret;
1154
1155 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1156 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1157 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1158 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1159 break;
1160
1161 default:
1162 /* Other modes are not supported. */
1163 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1164 chip->ecc.mode);
1165 return -ENOTSUPP;
1166 }
1167
1168 return 0;
1169 }
1170
1171 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1172 {
1173 int ret;
1174
1175 ret = atmel_nand_ecc_init(chip);
1176 if (ret)
1177 return ret;
1178
1179 if (chip->ecc.mode != NAND_ECC_HW)
1180 return 0;
1181
1182 /* Adjust the ECC operations for the HSMC IP. */
1183 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1184 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1185 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1186 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1187
1188 return 0;
1189 }
1190
1191 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1192 const struct nand_data_interface *conf,
1193 struct atmel_smc_cs_conf *smcconf)
1194 {
1195 u32 ncycles, totalcycles, timeps, mckperiodps;
1196 struct atmel_nand_controller *nc;
1197 int ret;
1198
1199 nc = to_nand_controller(nand->base.controller);
1200
1201 /* DDR interface not supported. */
1202 if (conf->type != NAND_SDR_IFACE)
1203 return -ENOTSUPP;
1204
1205 /*
1206 * tRC < 30ns implies EDO mode. This controller does not support this
1207 * mode.
1208 */
1209 if (conf->timings.sdr.tRC_min < 30000)
1210 return -ENOTSUPP;
1211
1212 atmel_smc_cs_conf_init(smcconf);
1213
1214 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1215 mckperiodps *= 1000;
1216
1217 /*
1218 * Set write pulse timing. This one is easy to extract:
1219 *
1220 * NWE_PULSE = tWP
1221 */
1222 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1223 totalcycles = ncycles;
1224 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1225 ncycles);
1226 if (ret)
1227 return ret;
1228
1229 /*
1230 * The write setup timing depends on the operation done on the NAND.
1231 * All operations goes through the same data bus, but the operation
1232 * type depends on the address we are writing to (ALE/CLE address
1233 * lines).
1234 * Since we have no way to differentiate the different operations at
1235 * the SMC level, we must consider the worst case (the biggest setup
1236 * time among all operation types):
1237 *
1238 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1239 */
1240 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1241 conf->timings.sdr.tALS_min);
1242 timeps = max(timeps, conf->timings.sdr.tDS_min);
1243 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1244 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1245 totalcycles += ncycles;
1246 ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1247 ncycles);
1248 if (ret)
1249 return ret;
1250
1251 /*
1252 * As for the write setup timing, the write hold timing depends on the
1253 * operation done on the NAND:
1254 *
1255 * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1256 */
1257 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1258 conf->timings.sdr.tALH_min);
1259 timeps = max3(timeps, conf->timings.sdr.tDH_min,
1260 conf->timings.sdr.tWH_min);
1261 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1262 totalcycles += ncycles;
1263
1264 /*
1265 * The write cycle timing is directly matching tWC, but is also
1266 * dependent on the other timings on the setup and hold timings we
1267 * calculated earlier, which gives:
1268 *
1269 * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1270 */
1271 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1272 ncycles = max(totalcycles, ncycles);
1273 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1274 ncycles);
1275 if (ret)
1276 return ret;
1277
1278 /*
1279 * We don't want the CS line to be toggled between each byte/word
1280 * transfer to the NAND. The only way to guarantee that is to have the
1281 * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1282 *
1283 * NCS_WR_PULSE = NWE_CYCLE
1284 */
1285 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1286 ncycles);
1287 if (ret)
1288 return ret;
1289
1290 /*
1291 * As for the write setup timing, the read hold timing depends on the
1292 * operation done on the NAND:
1293 *
1294 * NRD_HOLD = max(tREH, tRHOH)
1295 */
1296 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1297 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1298 totalcycles = ncycles;
1299
1300 /*
1301 * TDF = tRHZ - NRD_HOLD
1302 */
1303 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1304 ncycles -= totalcycles;
1305
1306 /*
1307 * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1308 * we might end up with a config that does not fit in the TDF field.
1309 * Just take the max value in this case and hope that the NAND is more
1310 * tolerant than advertised.
1311 */
1312 if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1313 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1314 else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1315 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1316
1317 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1318 ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1319
1320 /*
1321 * Read pulse timing directly matches tRP:
1322 *
1323 * NRD_PULSE = tRP
1324 */
1325 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1326 totalcycles += ncycles;
1327 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1328 ncycles);
1329 if (ret)
1330 return ret;
1331
1332 /*
1333 * The write cycle timing is directly matching tWC, but is also
1334 * dependent on the setup and hold timings we calculated earlier,
1335 * which gives:
1336 *
1337 * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1338 *
1339 * NRD_SETUP is always 0.
1340 */
1341 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1342 ncycles = max(totalcycles, ncycles);
1343 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1344 ncycles);
1345 if (ret)
1346 return ret;
1347
1348 /*
1349 * We don't want the CS line to be toggled between each byte/word
1350 * transfer from the NAND. The only way to guarantee that is to have
1351 * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1352 *
1353 * NCS_RD_PULSE = NRD_CYCLE
1354 */
1355 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1356 ncycles);
1357 if (ret)
1358 return ret;
1359
1360 /* Txxx timings are directly matching tXXX ones. */
1361 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1362 ret = atmel_smc_cs_conf_set_timing(smcconf,
1363 ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1364 ncycles);
1365 if (ret)
1366 return ret;
1367
1368 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1369 ret = atmel_smc_cs_conf_set_timing(smcconf,
1370 ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1371 ncycles);
1372 /*
1373 * Version 4 of the ONFI spec mandates that tADL be at least 400
1374 * nanoseconds, but, depending on the master clock rate, 400 ns may not
1375 * fit in the tADL field of the SMC reg. We need to relax the check and
1376 * accept the -ERANGE return code.
1377 *
1378 * Note that previous versions of the ONFI spec had a lower tADL_min
1379 * (100 or 200 ns). It's not clear why this timing constraint got
1380 * increased but it seems most NANDs are fine with values lower than
1381 * 400ns, so we should be safe.
1382 */
1383 if (ret && ret != -ERANGE)
1384 return ret;
1385
1386 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1387 ret = atmel_smc_cs_conf_set_timing(smcconf,
1388 ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1389 ncycles);
1390 if (ret)
1391 return ret;
1392
1393 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1394 ret = atmel_smc_cs_conf_set_timing(smcconf,
1395 ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1396 ncycles);
1397 if (ret)
1398 return ret;
1399
1400 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1401 ret = atmel_smc_cs_conf_set_timing(smcconf,
1402 ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1403 ncycles);
1404 if (ret)
1405 return ret;
1406
1407 /* Attach the CS line to the NFC logic. */
1408 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1409
1410 /* Set the appropriate data bus width. */
1411 if (nand->base.options & NAND_BUSWIDTH_16)
1412 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1413
1414 /* Operate in NRD/NWE READ/WRITEMODE. */
1415 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1416 ATMEL_SMC_MODE_WRITEMODE_NWE;
1417
1418 return 0;
1419 }
1420
1421 static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1422 int csline,
1423 const struct nand_data_interface *conf)
1424 {
1425 struct atmel_nand_controller *nc;
1426 struct atmel_smc_cs_conf smcconf;
1427 struct atmel_nand_cs *cs;
1428 int ret;
1429
1430 nc = to_nand_controller(nand->base.controller);
1431
1432 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1433 if (ret)
1434 return ret;
1435
1436 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1437 return 0;
1438
1439 cs = &nand->cs[csline];
1440 cs->smcconf = smcconf;
1441 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1442
1443 return 0;
1444 }
1445
1446 static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1447 int csline,
1448 const struct nand_data_interface *conf)
1449 {
1450 struct atmel_hsmc_nand_controller *nc;
1451 struct atmel_smc_cs_conf smcconf;
1452 struct atmel_nand_cs *cs;
1453 int ret;
1454
1455 nc = to_hsmc_nand_controller(nand->base.controller);
1456
1457 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1458 if (ret)
1459 return ret;
1460
1461 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1462 return 0;
1463
1464 cs = &nand->cs[csline];
1465 cs->smcconf = smcconf;
1466
1467 if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1468 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1469
1470 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1471 &cs->smcconf);
1472
1473 return 0;
1474 }
1475
1476 static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1477 const struct nand_data_interface *conf)
1478 {
1479 struct nand_chip *chip = mtd_to_nand(mtd);
1480 struct atmel_nand *nand = to_atmel_nand(chip);
1481 struct atmel_nand_controller *nc;
1482
1483 nc = to_nand_controller(nand->base.controller);
1484
1485 if (csline >= nand->numcs ||
1486 (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1487 return -EINVAL;
1488
1489 return nc->caps->ops->setup_data_interface(nand, csline, conf);
1490 }
1491
1492 static void atmel_nand_init(struct atmel_nand_controller *nc,
1493 struct atmel_nand *nand)
1494 {
1495 struct nand_chip *chip = &nand->base;
1496 struct mtd_info *mtd = nand_to_mtd(chip);
1497
1498 mtd->dev.parent = nc->dev;
1499 nand->base.controller = &nc->base;
1500
1501 chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1502 chip->read_byte = atmel_nand_read_byte;
1503 chip->read_word = atmel_nand_read_word;
1504 chip->write_byte = atmel_nand_write_byte;
1505 chip->read_buf = atmel_nand_read_buf;
1506 chip->write_buf = atmel_nand_write_buf;
1507 chip->select_chip = atmel_nand_select_chip;
1508
1509 if (nc->mck && nc->caps->ops->setup_data_interface)
1510 chip->setup_data_interface = atmel_nand_setup_data_interface;
1511
1512 /* Some NANDs require a longer delay than the default one (20us). */
1513 chip->chip_delay = 40;
1514
1515 /*
1516 * Use a bounce buffer when the buffer passed by the MTD user is not
1517 * suitable for DMA.
1518 */
1519 if (nc->dmac)
1520 chip->options |= NAND_USE_BOUNCE_BUFFER;
1521
1522 /* Default to HW ECC if pmecc is available. */
1523 if (nc->pmecc)
1524 chip->ecc.mode = NAND_ECC_HW;
1525 }
1526
1527 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1528 struct atmel_nand *nand)
1529 {
1530 struct nand_chip *chip = &nand->base;
1531 struct atmel_smc_nand_controller *smc_nc;
1532 int i;
1533
1534 atmel_nand_init(nc, nand);
1535
1536 smc_nc = to_smc_nand_controller(chip->controller);
1537 if (!smc_nc->matrix)
1538 return;
1539
1540 /* Attach the CS to the NAND Flash logic. */
1541 for (i = 0; i < nand->numcs; i++)
1542 regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1543 BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1544 }
1545
1546 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1547 struct atmel_nand *nand)
1548 {
1549 struct nand_chip *chip = &nand->base;
1550
1551 atmel_nand_init(nc, nand);
1552
1553 /* Overload some methods for the HSMC controller. */
1554 chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1555 chip->select_chip = atmel_hsmc_nand_select_chip;
1556 }
1557
1558 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1559 {
1560 struct nand_chip *chip = &nand->base;
1561 struct mtd_info *mtd = nand_to_mtd(chip);
1562 int ret;
1563
1564 ret = mtd_device_unregister(mtd);
1565 if (ret)
1566 return ret;
1567
1568 nand_cleanup(chip);
1569 list_del(&nand->node);
1570
1571 return 0;
1572 }
1573
1574 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1575 struct device_node *np,
1576 int reg_cells)
1577 {
1578 struct atmel_nand *nand;
1579 struct gpio_desc *gpio;
1580 int numcs, ret, i;
1581
1582 numcs = of_property_count_elems_of_size(np, "reg",
1583 reg_cells * sizeof(u32));
1584 if (numcs < 1) {
1585 dev_err(nc->dev, "Missing or invalid reg property\n");
1586 return ERR_PTR(-EINVAL);
1587 }
1588
1589 nand = devm_kzalloc(nc->dev,
1590 sizeof(*nand) + (numcs * sizeof(*nand->cs)),
1591 GFP_KERNEL);
1592 if (!nand) {
1593 dev_err(nc->dev, "Failed to allocate NAND object\n");
1594 return ERR_PTR(-ENOMEM);
1595 }
1596
1597 nand->numcs = numcs;
1598
1599 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1600 &np->fwnode, GPIOD_IN,
1601 "nand-det");
1602 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1603 dev_err(nc->dev,
1604 "Failed to get detect gpio (err = %ld)\n",
1605 PTR_ERR(gpio));
1606 return ERR_CAST(gpio);
1607 }
1608
1609 if (!IS_ERR(gpio))
1610 nand->cdgpio = gpio;
1611
1612 for (i = 0; i < numcs; i++) {
1613 struct resource res;
1614 u32 val;
1615
1616 ret = of_address_to_resource(np, 0, &res);
1617 if (ret) {
1618 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1619 ret);
1620 return ERR_PTR(ret);
1621 }
1622
1623 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1624 &val);
1625 if (ret) {
1626 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1627 ret);
1628 return ERR_PTR(ret);
1629 }
1630
1631 nand->cs[i].id = val;
1632
1633 nand->cs[i].io.dma = res.start;
1634 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1635 if (IS_ERR(nand->cs[i].io.virt))
1636 return ERR_CAST(nand->cs[i].io.virt);
1637
1638 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1639 if (val > ATMEL_NFC_MAX_RB_ID)
1640 return ERR_PTR(-EINVAL);
1641
1642 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1643 nand->cs[i].rb.id = val;
1644 } else {
1645 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1646 "rb", i, &np->fwnode,
1647 GPIOD_IN, "nand-rb");
1648 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1649 dev_err(nc->dev,
1650 "Failed to get R/B gpio (err = %ld)\n",
1651 PTR_ERR(gpio));
1652 return ERR_CAST(gpio);
1653 }
1654
1655 if (!IS_ERR(gpio)) {
1656 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1657 nand->cs[i].rb.gpio = gpio;
1658 }
1659 }
1660
1661 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1662 i, &np->fwnode,
1663 GPIOD_OUT_HIGH,
1664 "nand-cs");
1665 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1666 dev_err(nc->dev,
1667 "Failed to get CS gpio (err = %ld)\n",
1668 PTR_ERR(gpio));
1669 return ERR_CAST(gpio);
1670 }
1671
1672 if (!IS_ERR(gpio))
1673 nand->cs[i].csgpio = gpio;
1674 }
1675
1676 nand_set_flash_node(&nand->base, np);
1677
1678 return nand;
1679 }
1680
1681 static int
1682 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1683 struct atmel_nand *nand)
1684 {
1685 struct nand_chip *chip = &nand->base;
1686 struct mtd_info *mtd = nand_to_mtd(chip);
1687 int ret;
1688
1689 /* No card inserted, skip this NAND. */
1690 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1691 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1692 return 0;
1693 }
1694
1695 nc->caps->ops->nand_init(nc, nand);
1696
1697 ret = nand_scan(chip, nand->numcs);
1698 if (ret) {
1699 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1700 return ret;
1701 }
1702
1703 ret = mtd_device_register(mtd, NULL, 0);
1704 if (ret) {
1705 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1706 nand_cleanup(chip);
1707 return ret;
1708 }
1709
1710 list_add_tail(&nand->node, &nc->chips);
1711
1712 return 0;
1713 }
1714
1715 static int
1716 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1717 {
1718 struct atmel_nand *nand, *tmp;
1719 int ret;
1720
1721 list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1722 ret = atmel_nand_controller_remove_nand(nand);
1723 if (ret)
1724 return ret;
1725 }
1726
1727 return 0;
1728 }
1729
1730 static int
1731 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1732 {
1733 struct device *dev = nc->dev;
1734 struct platform_device *pdev = to_platform_device(dev);
1735 struct atmel_nand *nand;
1736 struct gpio_desc *gpio;
1737 struct resource *res;
1738
1739 /*
1740 * Legacy bindings only allow connecting a single NAND with a unique CS
1741 * line to the controller.
1742 */
1743 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1744 GFP_KERNEL);
1745 if (!nand)
1746 return -ENOMEM;
1747
1748 nand->numcs = 1;
1749
1750 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1751 nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1752 if (IS_ERR(nand->cs[0].io.virt))
1753 return PTR_ERR(nand->cs[0].io.virt);
1754
1755 nand->cs[0].io.dma = res->start;
1756
1757 /*
1758 * The old driver was hardcoding the CS id to 3 for all sama5
1759 * controllers. Since this id is only meaningful for the sama5
1760 * controller we can safely assign this id to 3 no matter the
1761 * controller.
1762 * If one wants to connect a NAND to a different CS line, he will
1763 * have to use the new bindings.
1764 */
1765 nand->cs[0].id = 3;
1766
1767 /* R/B GPIO. */
1768 gpio = devm_gpiod_get_index_optional(dev, NULL, 0, GPIOD_IN);
1769 if (IS_ERR(gpio)) {
1770 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1771 PTR_ERR(gpio));
1772 return PTR_ERR(gpio);
1773 }
1774
1775 if (gpio) {
1776 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1777 nand->cs[0].rb.gpio = gpio;
1778 }
1779
1780 /* CS GPIO. */
1781 gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1782 if (IS_ERR(gpio)) {
1783 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1784 PTR_ERR(gpio));
1785 return PTR_ERR(gpio);
1786 }
1787
1788 nand->cs[0].csgpio = gpio;
1789
1790 /* Card detect GPIO. */
1791 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1792 if (IS_ERR(gpio)) {
1793 dev_err(dev,
1794 "Failed to get detect gpio (err = %ld)\n",
1795 PTR_ERR(gpio));
1796 return PTR_ERR(gpio);
1797 }
1798
1799 nand->cdgpio = gpio;
1800
1801 nand_set_flash_node(&nand->base, nc->dev->of_node);
1802
1803 return atmel_nand_controller_add_nand(nc, nand);
1804 }
1805
1806 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1807 {
1808 struct device_node *np, *nand_np;
1809 struct device *dev = nc->dev;
1810 int ret, reg_cells;
1811 u32 val;
1812
1813 /* We do not retrieve the SMC syscon when parsing old DTs. */
1814 if (nc->caps->legacy_of_bindings)
1815 return atmel_nand_controller_legacy_add_nands(nc);
1816
1817 np = dev->of_node;
1818
1819 ret = of_property_read_u32(np, "#address-cells", &val);
1820 if (ret) {
1821 dev_err(dev, "missing #address-cells property\n");
1822 return ret;
1823 }
1824
1825 reg_cells = val;
1826
1827 ret = of_property_read_u32(np, "#size-cells", &val);
1828 if (ret) {
1829 dev_err(dev, "missing #size-cells property\n");
1830 return ret;
1831 }
1832
1833 reg_cells += val;
1834
1835 for_each_child_of_node(np, nand_np) {
1836 struct atmel_nand *nand;
1837
1838 nand = atmel_nand_create(nc, nand_np, reg_cells);
1839 if (IS_ERR(nand)) {
1840 ret = PTR_ERR(nand);
1841 goto err;
1842 }
1843
1844 ret = atmel_nand_controller_add_nand(nc, nand);
1845 if (ret)
1846 goto err;
1847 }
1848
1849 return 0;
1850
1851 err:
1852 atmel_nand_controller_remove_nands(nc);
1853
1854 return ret;
1855 }
1856
1857 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1858 {
1859 if (nc->dmac)
1860 dma_release_channel(nc->dmac);
1861
1862 clk_put(nc->mck);
1863 }
1864
1865 static const struct of_device_id atmel_matrix_of_ids[] = {
1866 {
1867 .compatible = "atmel,at91sam9260-matrix",
1868 .data = (void *)AT91SAM9260_MATRIX_EBICSA,
1869 },
1870 {
1871 .compatible = "atmel,at91sam9261-matrix",
1872 .data = (void *)AT91SAM9261_MATRIX_EBICSA,
1873 },
1874 {
1875 .compatible = "atmel,at91sam9263-matrix",
1876 .data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1877 },
1878 {
1879 .compatible = "atmel,at91sam9rl-matrix",
1880 .data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1881 },
1882 {
1883 .compatible = "atmel,at91sam9g45-matrix",
1884 .data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1885 },
1886 {
1887 .compatible = "atmel,at91sam9n12-matrix",
1888 .data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1889 },
1890 {
1891 .compatible = "atmel,at91sam9x5-matrix",
1892 .data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1893 },
1894 { /* sentinel */ },
1895 };
1896
1897 static int atmel_nand_attach_chip(struct nand_chip *chip)
1898 {
1899 struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
1900 struct atmel_nand *nand = to_atmel_nand(chip);
1901 struct mtd_info *mtd = nand_to_mtd(chip);
1902 int ret;
1903
1904 ret = nc->caps->ops->ecc_init(chip);
1905 if (ret)
1906 return ret;
1907
1908 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1909 /*
1910 * We keep the MTD name unchanged to avoid breaking platforms
1911 * where the MTD cmdline parser is used and the bootloader
1912 * has not been updated to use the new naming scheme.
1913 */
1914 mtd->name = "atmel_nand";
1915 } else if (!mtd->name) {
1916 /*
1917 * If the new bindings are used and the bootloader has not been
1918 * updated to pass a new mtdparts parameter on the cmdline, you
1919 * should define the following property in your nand node:
1920 *
1921 * label = "atmel_nand";
1922 *
1923 * This way, mtd->name will be set by the core when
1924 * nand_set_flash_node() is called.
1925 */
1926 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1927 "%s:nand.%d", dev_name(nc->dev),
1928 nand->cs[0].id);
1929 if (!mtd->name) {
1930 dev_err(nc->dev, "Failed to allocate mtd->name\n");
1931 return -ENOMEM;
1932 }
1933 }
1934
1935 return 0;
1936 }
1937
1938 static const struct nand_controller_ops atmel_nand_controller_ops = {
1939 .attach_chip = atmel_nand_attach_chip,
1940 };
1941
1942 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1943 struct platform_device *pdev,
1944 const struct atmel_nand_controller_caps *caps)
1945 {
1946 struct device *dev = &pdev->dev;
1947 struct device_node *np = dev->of_node;
1948 int ret;
1949
1950 nand_controller_init(&nc->base);
1951 nc->base.ops = &atmel_nand_controller_ops;
1952 INIT_LIST_HEAD(&nc->chips);
1953 nc->dev = dev;
1954 nc->caps = caps;
1955
1956 platform_set_drvdata(pdev, nc);
1957
1958 nc->pmecc = devm_atmel_pmecc_get(dev);
1959 if (IS_ERR(nc->pmecc)) {
1960 ret = PTR_ERR(nc->pmecc);
1961 if (ret != -EPROBE_DEFER)
1962 dev_err(dev, "Could not get PMECC object (err = %d)\n",
1963 ret);
1964 return ret;
1965 }
1966
1967 if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
1968 dma_cap_mask_t mask;
1969
1970 dma_cap_zero(mask);
1971 dma_cap_set(DMA_MEMCPY, mask);
1972
1973 nc->dmac = dma_request_channel(mask, NULL, NULL);
1974 if (!nc->dmac)
1975 dev_err(nc->dev, "Failed to request DMA channel\n");
1976 }
1977
1978 /* We do not retrieve the SMC syscon when parsing old DTs. */
1979 if (nc->caps->legacy_of_bindings)
1980 return 0;
1981
1982 nc->mck = of_clk_get(dev->parent->of_node, 0);
1983 if (IS_ERR(nc->mck)) {
1984 dev_err(dev, "Failed to retrieve MCK clk\n");
1985 return PTR_ERR(nc->mck);
1986 }
1987
1988 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1989 if (!np) {
1990 dev_err(dev, "Missing or invalid atmel,smc property\n");
1991 return -EINVAL;
1992 }
1993
1994 nc->smc = syscon_node_to_regmap(np);
1995 of_node_put(np);
1996 if (IS_ERR(nc->smc)) {
1997 ret = PTR_ERR(nc->smc);
1998 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
1999 return ret;
2000 }
2001
2002 return 0;
2003 }
2004
2005 static int
2006 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2007 {
2008 struct device *dev = nc->base.dev;
2009 const struct of_device_id *match;
2010 struct device_node *np;
2011 int ret;
2012
2013 /* We do not retrieve the matrix syscon when parsing old DTs. */
2014 if (nc->base.caps->legacy_of_bindings)
2015 return 0;
2016
2017 np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
2018 if (!np)
2019 return 0;
2020
2021 match = of_match_node(atmel_matrix_of_ids, np);
2022 if (!match) {
2023 of_node_put(np);
2024 return 0;
2025 }
2026
2027 nc->matrix = syscon_node_to_regmap(np);
2028 of_node_put(np);
2029 if (IS_ERR(nc->matrix)) {
2030 ret = PTR_ERR(nc->matrix);
2031 dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
2032 return ret;
2033 }
2034
2035 nc->ebi_csa_offs = (uintptr_t)match->data;
2036
2037 /*
2038 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2039 * add 4 to ->ebi_csa_offs.
2040 */
2041 if (of_device_is_compatible(dev->parent->of_node,
2042 "atmel,at91sam9263-ebi1"))
2043 nc->ebi_csa_offs += 4;
2044
2045 return 0;
2046 }
2047
2048 static int
2049 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2050 {
2051 struct regmap_config regmap_conf = {
2052 .reg_bits = 32,
2053 .val_bits = 32,
2054 .reg_stride = 4,
2055 };
2056
2057 struct device *dev = nc->base.dev;
2058 struct device_node *nand_np, *nfc_np;
2059 void __iomem *iomem;
2060 struct resource res;
2061 int ret;
2062
2063 nand_np = dev->of_node;
2064 nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
2065 if (!nfc_np) {
2066 dev_err(dev, "Could not find device node for sama5d3-nfc\n");
2067 return -ENODEV;
2068 }
2069
2070 nc->clk = of_clk_get(nfc_np, 0);
2071 if (IS_ERR(nc->clk)) {
2072 ret = PTR_ERR(nc->clk);
2073 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2074 ret);
2075 goto out;
2076 }
2077
2078 ret = clk_prepare_enable(nc->clk);
2079 if (ret) {
2080 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2081 ret);
2082 goto out;
2083 }
2084
2085 nc->irq = of_irq_get(nand_np, 0);
2086 if (nc->irq <= 0) {
2087 ret = nc->irq ?: -ENXIO;
2088 if (ret != -EPROBE_DEFER)
2089 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2090 ret);
2091 goto out;
2092 }
2093
2094 ret = of_address_to_resource(nfc_np, 0, &res);
2095 if (ret) {
2096 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2097 ret);
2098 goto out;
2099 }
2100
2101 iomem = devm_ioremap_resource(dev, &res);
2102 if (IS_ERR(iomem)) {
2103 ret = PTR_ERR(iomem);
2104 goto out;
2105 }
2106
2107 regmap_conf.name = "nfc-io";
2108 regmap_conf.max_register = resource_size(&res) - 4;
2109 nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2110 if (IS_ERR(nc->io)) {
2111 ret = PTR_ERR(nc->io);
2112 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2113 ret);
2114 goto out;
2115 }
2116
2117 ret = of_address_to_resource(nfc_np, 1, &res);
2118 if (ret) {
2119 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2120 ret);
2121 goto out;
2122 }
2123
2124 iomem = devm_ioremap_resource(dev, &res);
2125 if (IS_ERR(iomem)) {
2126 ret = PTR_ERR(iomem);
2127 goto out;
2128 }
2129
2130 regmap_conf.name = "smc";
2131 regmap_conf.max_register = resource_size(&res) - 4;
2132 nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2133 if (IS_ERR(nc->base.smc)) {
2134 ret = PTR_ERR(nc->base.smc);
2135 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2136 ret);
2137 goto out;
2138 }
2139
2140 ret = of_address_to_resource(nfc_np, 2, &res);
2141 if (ret) {
2142 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2143 ret);
2144 goto out;
2145 }
2146
2147 nc->sram.virt = devm_ioremap_resource(dev, &res);
2148 if (IS_ERR(nc->sram.virt)) {
2149 ret = PTR_ERR(nc->sram.virt);
2150 goto out;
2151 }
2152
2153 nc->sram.dma = res.start;
2154
2155 out:
2156 of_node_put(nfc_np);
2157
2158 return ret;
2159 }
2160
2161 static int
2162 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2163 {
2164 struct device *dev = nc->base.dev;
2165 struct device_node *np;
2166 int ret;
2167
2168 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2169 if (!np) {
2170 dev_err(dev, "Missing or invalid atmel,smc property\n");
2171 return -EINVAL;
2172 }
2173
2174 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2175
2176 nc->irq = of_irq_get(np, 0);
2177 of_node_put(np);
2178 if (nc->irq <= 0) {
2179 ret = nc->irq ?: -ENXIO;
2180 if (ret != -EPROBE_DEFER)
2181 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2182 ret);
2183 return ret;
2184 }
2185
2186 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2187 if (!np) {
2188 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2189 return -EINVAL;
2190 }
2191
2192 nc->io = syscon_node_to_regmap(np);
2193 of_node_put(np);
2194 if (IS_ERR(nc->io)) {
2195 ret = PTR_ERR(nc->io);
2196 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2197 return ret;
2198 }
2199
2200 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2201 "atmel,nfc-sram", 0);
2202 if (!nc->sram.pool) {
2203 dev_err(nc->base.dev, "Missing SRAM\n");
2204 return -ENOMEM;
2205 }
2206
2207 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,
2208 ATMEL_NFC_SRAM_SIZE,
2209 &nc->sram.dma);
2210 if (!nc->sram.virt) {
2211 dev_err(nc->base.dev,
2212 "Could not allocate memory from the NFC SRAM pool\n");
2213 return -ENOMEM;
2214 }
2215
2216 return 0;
2217 }
2218
2219 static int
2220 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2221 {
2222 struct atmel_hsmc_nand_controller *hsmc_nc;
2223 int ret;
2224
2225 ret = atmel_nand_controller_remove_nands(nc);
2226 if (ret)
2227 return ret;
2228
2229 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2230 if (hsmc_nc->sram.pool)
2231 gen_pool_free(hsmc_nc->sram.pool,
2232 (unsigned long)hsmc_nc->sram.virt,
2233 ATMEL_NFC_SRAM_SIZE);
2234
2235 if (hsmc_nc->clk) {
2236 clk_disable_unprepare(hsmc_nc->clk);
2237 clk_put(hsmc_nc->clk);
2238 }
2239
2240 atmel_nand_controller_cleanup(nc);
2241
2242 return 0;
2243 }
2244
2245 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2246 const struct atmel_nand_controller_caps *caps)
2247 {
2248 struct device *dev = &pdev->dev;
2249 struct atmel_hsmc_nand_controller *nc;
2250 int ret;
2251
2252 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2253 if (!nc)
2254 return -ENOMEM;
2255
2256 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2257 if (ret)
2258 return ret;
2259
2260 if (caps->legacy_of_bindings)
2261 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2262 else
2263 ret = atmel_hsmc_nand_controller_init(nc);
2264
2265 if (ret)
2266 return ret;
2267
2268 /* Make sure all irqs are masked before registering our IRQ handler. */
2269 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2270 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2271 IRQF_SHARED, "nfc", nc);
2272 if (ret) {
2273 dev_err(dev,
2274 "Could not get register NFC interrupt handler (err = %d)\n",
2275 ret);
2276 goto err;
2277 }
2278
2279 /* Initial NFC configuration. */
2280 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2281 ATMEL_HSMC_NFC_CFG_DTO_MAX);
2282
2283 ret = atmel_nand_controller_add_nands(&nc->base);
2284 if (ret)
2285 goto err;
2286
2287 return 0;
2288
2289 err:
2290 atmel_hsmc_nand_controller_remove(&nc->base);
2291
2292 return ret;
2293 }
2294
2295 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2296 .probe = atmel_hsmc_nand_controller_probe,
2297 .remove = atmel_hsmc_nand_controller_remove,
2298 .ecc_init = atmel_hsmc_nand_ecc_init,
2299 .nand_init = atmel_hsmc_nand_init,
2300 .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2301 };
2302
2303 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2304 .has_dma = true,
2305 .ale_offs = BIT(21),
2306 .cle_offs = BIT(22),
2307 .ops = &atmel_hsmc_nc_ops,
2308 };
2309
2310 /* Only used to parse old bindings. */
2311 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2312 .has_dma = true,
2313 .ale_offs = BIT(21),
2314 .cle_offs = BIT(22),
2315 .ops = &atmel_hsmc_nc_ops,
2316 .legacy_of_bindings = true,
2317 };
2318
2319 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2320 const struct atmel_nand_controller_caps *caps)
2321 {
2322 struct device *dev = &pdev->dev;
2323 struct atmel_smc_nand_controller *nc;
2324 int ret;
2325
2326 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2327 if (!nc)
2328 return -ENOMEM;
2329
2330 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2331 if (ret)
2332 return ret;
2333
2334 ret = atmel_smc_nand_controller_init(nc);
2335 if (ret)
2336 return ret;
2337
2338 return atmel_nand_controller_add_nands(&nc->base);
2339 }
2340
2341 static int
2342 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2343 {
2344 int ret;
2345
2346 ret = atmel_nand_controller_remove_nands(nc);
2347 if (ret)
2348 return ret;
2349
2350 atmel_nand_controller_cleanup(nc);
2351
2352 return 0;
2353 }
2354
2355 /*
2356 * The SMC reg layout of at91rm9200 is completely different which prevents us
2357 * from re-using atmel_smc_nand_setup_data_interface() for the
2358 * ->setup_data_interface() hook.
2359 * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2360 * ->setup_data_interface() unassigned.
2361 */
2362 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2363 .probe = atmel_smc_nand_controller_probe,
2364 .remove = atmel_smc_nand_controller_remove,
2365 .ecc_init = atmel_nand_ecc_init,
2366 .nand_init = atmel_smc_nand_init,
2367 };
2368
2369 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2370 .ale_offs = BIT(21),
2371 .cle_offs = BIT(22),
2372 .ops = &at91rm9200_nc_ops,
2373 };
2374
2375 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2376 .probe = atmel_smc_nand_controller_probe,
2377 .remove = atmel_smc_nand_controller_remove,
2378 .ecc_init = atmel_nand_ecc_init,
2379 .nand_init = atmel_smc_nand_init,
2380 .setup_data_interface = atmel_smc_nand_setup_data_interface,
2381 };
2382
2383 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2384 .ale_offs = BIT(21),
2385 .cle_offs = BIT(22),
2386 .ops = &atmel_smc_nc_ops,
2387 };
2388
2389 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2390 .ale_offs = BIT(22),
2391 .cle_offs = BIT(21),
2392 .ops = &atmel_smc_nc_ops,
2393 };
2394
2395 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2396 .has_dma = true,
2397 .ale_offs = BIT(21),
2398 .cle_offs = BIT(22),
2399 .ops = &atmel_smc_nc_ops,
2400 };
2401
2402 /* Only used to parse old bindings. */
2403 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2404 .ale_offs = BIT(21),
2405 .cle_offs = BIT(22),
2406 .ops = &atmel_smc_nc_ops,
2407 .legacy_of_bindings = true,
2408 };
2409
2410 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2411 .ale_offs = BIT(22),
2412 .cle_offs = BIT(21),
2413 .ops = &atmel_smc_nc_ops,
2414 .legacy_of_bindings = true,
2415 };
2416
2417 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2418 .has_dma = true,
2419 .ale_offs = BIT(21),
2420 .cle_offs = BIT(22),
2421 .ops = &atmel_smc_nc_ops,
2422 .legacy_of_bindings = true,
2423 };
2424
2425 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2426 {
2427 .compatible = "atmel,at91rm9200-nand-controller",
2428 .data = &atmel_rm9200_nc_caps,
2429 },
2430 {
2431 .compatible = "atmel,at91sam9260-nand-controller",
2432 .data = &atmel_sam9260_nc_caps,
2433 },
2434 {
2435 .compatible = "atmel,at91sam9261-nand-controller",
2436 .data = &atmel_sam9261_nc_caps,
2437 },
2438 {
2439 .compatible = "atmel,at91sam9g45-nand-controller",
2440 .data = &atmel_sam9g45_nc_caps,
2441 },
2442 {
2443 .compatible = "atmel,sama5d3-nand-controller",
2444 .data = &atmel_sama5_nc_caps,
2445 },
2446 /* Support for old/deprecated bindings: */
2447 {
2448 .compatible = "atmel,at91rm9200-nand",
2449 .data = &atmel_rm9200_nand_caps,
2450 },
2451 {
2452 .compatible = "atmel,sama5d4-nand",
2453 .data = &atmel_rm9200_nand_caps,
2454 },
2455 {
2456 .compatible = "atmel,sama5d2-nand",
2457 .data = &atmel_rm9200_nand_caps,
2458 },
2459 { /* sentinel */ },
2460 };
2461 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2462
2463 static int atmel_nand_controller_probe(struct platform_device *pdev)
2464 {
2465 const struct atmel_nand_controller_caps *caps;
2466
2467 if (pdev->id_entry)
2468 caps = (void *)pdev->id_entry->driver_data;
2469 else
2470 caps = of_device_get_match_data(&pdev->dev);
2471
2472 if (!caps) {
2473 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2474 return -EINVAL;
2475 }
2476
2477 if (caps->legacy_of_bindings) {
2478 struct device_node *nfc_node;
2479 u32 ale_offs = 21;
2480
2481 /*
2482 * If we are parsing legacy DT props and the DT contains a
2483 * valid NFC node, forward the request to the sama5 logic.
2484 */
2485 nfc_node = of_get_compatible_child(pdev->dev.of_node,
2486 "atmel,sama5d3-nfc");
2487 if (nfc_node) {
2488 caps = &atmel_sama5_nand_caps;
2489 of_node_put(nfc_node);
2490 }
2491
2492 /*
2493 * Even if the compatible says we are dealing with an
2494 * at91rm9200 controller, the atmel,nand-has-dma specify that
2495 * this controller supports DMA, which means we are in fact
2496 * dealing with an at91sam9g45+ controller.
2497 */
2498 if (!caps->has_dma &&
2499 of_property_read_bool(pdev->dev.of_node,
2500 "atmel,nand-has-dma"))
2501 caps = &atmel_sam9g45_nand_caps;
2502
2503 /*
2504 * All SoCs except the at91sam9261 are assigning ALE to A21 and
2505 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2506 * actually dealing with an at91sam9261 controller.
2507 */
2508 of_property_read_u32(pdev->dev.of_node,
2509 "atmel,nand-addr-offset", &ale_offs);
2510 if (ale_offs != 21)
2511 caps = &atmel_sam9261_nand_caps;
2512 }
2513
2514 return caps->ops->probe(pdev, caps);
2515 }
2516
2517 static int atmel_nand_controller_remove(struct platform_device *pdev)
2518 {
2519 struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2520
2521 return nc->caps->ops->remove(nc);
2522 }
2523
2524 static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2525 {
2526 struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2527 struct atmel_nand *nand;
2528
2529 if (nc->pmecc)
2530 atmel_pmecc_reset(nc->pmecc);
2531
2532 list_for_each_entry(nand, &nc->chips, node) {
2533 int i;
2534
2535 for (i = 0; i < nand->numcs; i++)
2536 nand_reset(&nand->base, i);
2537 }
2538
2539 return 0;
2540 }
2541
2542 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2543 atmel_nand_controller_resume);
2544
2545 static struct platform_driver atmel_nand_controller_driver = {
2546 .driver = {
2547 .name = "atmel-nand-controller",
2548 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2549 .pm = &atmel_nand_controller_pm_ops,
2550 },
2551 .probe = atmel_nand_controller_probe,
2552 .remove = atmel_nand_controller_remove,
2553 };
2554 module_platform_driver(atmel_nand_controller_driver);
2555
2556 MODULE_LICENSE("GPL");
2557 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2558 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2559 MODULE_ALIAS("platform:atmel-nand-controller");
Linux with added FPC-III support