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Linux 4.19.133
[linux/fpc-iii.git] / drivers / mtd / nand / raw / mtk_nand.c
blobbb40022e109f23a8f98e5aa6917a76805944fc98
1 /*
2 * MTK NAND Flash controller driver.
3 * Copyright (C) 2016 MediaTek Inc.
4 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
5 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/clk.h>
22 #include <linux/mtd/rawnand.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/module.h>
25 #include <linux/iopoll.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include "mtk_ecc.h"
29
30 /* NAND controller register definition */
31 #define NFI_CNFG (0x00)
32 #define CNFG_AHB BIT(0)
33 #define CNFG_READ_EN BIT(1)
34 #define CNFG_DMA_BURST_EN BIT(2)
35 #define CNFG_BYTE_RW BIT(6)
36 #define CNFG_HW_ECC_EN BIT(8)
37 #define CNFG_AUTO_FMT_EN BIT(9)
38 #define CNFG_OP_CUST (6 << 12)
39 #define NFI_PAGEFMT (0x04)
40 #define PAGEFMT_FDM_ECC_SHIFT (12)
41 #define PAGEFMT_FDM_SHIFT (8)
42 #define PAGEFMT_SEC_SEL_512 BIT(2)
43 #define PAGEFMT_512_2K (0)
44 #define PAGEFMT_2K_4K (1)
45 #define PAGEFMT_4K_8K (2)
46 #define PAGEFMT_8K_16K (3)
47 /* NFI control */
48 #define NFI_CON (0x08)
49 #define CON_FIFO_FLUSH BIT(0)
50 #define CON_NFI_RST BIT(1)
51 #define CON_BRD BIT(8) /* burst read */
52 #define CON_BWR BIT(9) /* burst write */
53 #define CON_SEC_SHIFT (12)
54 /* Timming control register */
55 #define NFI_ACCCON (0x0C)
56 #define NFI_INTR_EN (0x10)
57 #define INTR_AHB_DONE_EN BIT(6)
58 #define NFI_INTR_STA (0x14)
59 #define NFI_CMD (0x20)
60 #define NFI_ADDRNOB (0x30)
61 #define NFI_COLADDR (0x34)
62 #define NFI_ROWADDR (0x38)
63 #define NFI_STRDATA (0x40)
64 #define STAR_EN (1)
65 #define STAR_DE (0)
66 #define NFI_CNRNB (0x44)
67 #define NFI_DATAW (0x50)
68 #define NFI_DATAR (0x54)
69 #define NFI_PIO_DIRDY (0x58)
70 #define PIO_DI_RDY (0x01)
71 #define NFI_STA (0x60)
72 #define STA_CMD BIT(0)
73 #define STA_ADDR BIT(1)
74 #define STA_BUSY BIT(8)
75 #define STA_EMP_PAGE BIT(12)
76 #define NFI_FSM_CUSTDATA (0xe << 16)
77 #define NFI_FSM_MASK (0xf << 16)
78 #define NFI_ADDRCNTR (0x70)
79 #define CNTR_MASK GENMASK(16, 12)
80 #define ADDRCNTR_SEC_SHIFT (12)
81 #define ADDRCNTR_SEC(val) \
82 (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT)
83 #define NFI_STRADDR (0x80)
84 #define NFI_BYTELEN (0x84)
85 #define NFI_CSEL (0x90)
86 #define NFI_FDML(x) (0xA0 + (x) * sizeof(u32) * 2)
87 #define NFI_FDMM(x) (0xA4 + (x) * sizeof(u32) * 2)
88 #define NFI_FDM_MAX_SIZE (8)
89 #define NFI_FDM_MIN_SIZE (1)
90 #define NFI_MASTER_STA (0x224)
91 #define MASTER_STA_MASK (0x0FFF)
92 #define NFI_EMPTY_THRESH (0x23C)
93
94 #define MTK_NAME "mtk-nand"
95 #define KB(x) ((x) * 1024UL)
96 #define MB(x) (KB(x) * 1024UL)
97
98 #define MTK_TIMEOUT (500000)
99 #define MTK_RESET_TIMEOUT (1000000)
100 #define MTK_NAND_MAX_NSELS (2)
101 #define MTK_NFC_MIN_SPARE (16)
102 #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \
103 ((tpoecs) << 28 | (tprecs) << 22 | (tc2r) << 16 | \
104 (tw2r) << 12 | (twh) << 8 | (twst) << 4 | (trlt))
105
106 struct mtk_nfc_caps {
107 const u8 *spare_size;
108 u8 num_spare_size;
109 u8 pageformat_spare_shift;
110 u8 nfi_clk_div;
111 u8 max_sector;
112 u32 max_sector_size;
113 };
114
115 struct mtk_nfc_bad_mark_ctl {
116 void (*bm_swap)(struct mtd_info *, u8 *buf, int raw);
117 u32 sec;
118 u32 pos;
119 };
120
121 /*
122 * FDM: region used to store free OOB data
123 */
124 struct mtk_nfc_fdm {
125 u32 reg_size;
126 u32 ecc_size;
127 };
128
129 struct mtk_nfc_nand_chip {
130 struct list_head node;
131 struct nand_chip nand;
132
133 struct mtk_nfc_bad_mark_ctl bad_mark;
134 struct mtk_nfc_fdm fdm;
135 u32 spare_per_sector;
136
137 int nsels;
138 u8 sels[0];
139 /* nothing after this field */
140 };
141
142 struct mtk_nfc_clk {
143 struct clk *nfi_clk;
144 struct clk *pad_clk;
145 };
146
147 struct mtk_nfc {
148 struct nand_controller controller;
149 struct mtk_ecc_config ecc_cfg;
150 struct mtk_nfc_clk clk;
151 struct mtk_ecc *ecc;
152
153 struct device *dev;
154 const struct mtk_nfc_caps *caps;
155 void __iomem *regs;
156
157 struct completion done;
158 struct list_head chips;
159
160 u8 *buffer;
161 };
162
163 /*
164 * supported spare size of each IP.
165 * order should be the same with the spare size bitfiled defination of
166 * register NFI_PAGEFMT.
167 */
168 static const u8 spare_size_mt2701[] = {
169 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 63, 64
170 };
171
172 static const u8 spare_size_mt2712[] = {
173 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67,
174 74
175 };
176
177 static const u8 spare_size_mt7622[] = {
178 16, 26, 27, 28
179 };
180
181 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
182 {
183 return container_of(nand, struct mtk_nfc_nand_chip, nand);
184 }
185
186 static inline u8 *data_ptr(struct nand_chip *chip, const u8 *p, int i)
187 {
188 return (u8 *)p + i * chip->ecc.size;
189 }
190
191 static inline u8 *oob_ptr(struct nand_chip *chip, int i)
192 {
193 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
194 u8 *poi;
195
196 /* map the sector's FDM data to free oob:
197 * the beginning of the oob area stores the FDM data of bad mark sectors
198 */
199
200 if (i < mtk_nand->bad_mark.sec)
201 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size;
202 else if (i == mtk_nand->bad_mark.sec)
203 poi = chip->oob_poi;
204 else
205 poi = chip->oob_poi + i * mtk_nand->fdm.reg_size;
206
207 return poi;
208 }
209
210 static inline int mtk_data_len(struct nand_chip *chip)
211 {
212 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
213
214 return chip->ecc.size + mtk_nand->spare_per_sector;
215 }
216
217 static inline u8 *mtk_data_ptr(struct nand_chip *chip, int i)
218 {
219 struct mtk_nfc *nfc = nand_get_controller_data(chip);
220
221 return nfc->buffer + i * mtk_data_len(chip);
222 }
223
224 static inline u8 *mtk_oob_ptr(struct nand_chip *chip, int i)
225 {
226 struct mtk_nfc *nfc = nand_get_controller_data(chip);
227
228 return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size;
229 }
230
231 static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg)
232 {
233 writel(val, nfc->regs + reg);
234 }
235
236 static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg)
237 {
238 writew(val, nfc->regs + reg);
239 }
240
241 static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg)
242 {
243 writeb(val, nfc->regs + reg);
244 }
245
246 static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg)
247 {
248 return readl_relaxed(nfc->regs + reg);
249 }
250
251 static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg)
252 {
253 return readw_relaxed(nfc->regs + reg);
254 }
255
256 static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
257 {
258 return readb_relaxed(nfc->regs + reg);
259 }
260
261 static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
262 {
263 struct device *dev = nfc->dev;
264 u32 val;
265 int ret;
266
267 /* reset all registers and force the NFI master to terminate */
268 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
269
270 /* wait for the master to finish the last transaction */
271 ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val,
272 !(val & MASTER_STA_MASK), 50,
273 MTK_RESET_TIMEOUT);
274 if (ret)
275 dev_warn(dev, "master active in reset [0x%x] = 0x%x\n",
276 NFI_MASTER_STA, val);
277
278 /* ensure any status register affected by the NFI master is reset */
279 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
280 nfi_writew(nfc, STAR_DE, NFI_STRDATA);
281 }
282
283 static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command)
284 {
285 struct device *dev = nfc->dev;
286 u32 val;
287 int ret;
288
289 nfi_writel(nfc, command, NFI_CMD);
290
291 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
292 !(val & STA_CMD), 10, MTK_TIMEOUT);
293 if (ret) {
294 dev_warn(dev, "nfi core timed out entering command mode\n");
295 return -EIO;
296 }
297
298 return 0;
299 }
300
301 static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr)
302 {
303 struct device *dev = nfc->dev;
304 u32 val;
305 int ret;
306
307 nfi_writel(nfc, addr, NFI_COLADDR);
308 nfi_writel(nfc, 0, NFI_ROWADDR);
309 nfi_writew(nfc, 1, NFI_ADDRNOB);
310
311 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
312 !(val & STA_ADDR), 10, MTK_TIMEOUT);
313 if (ret) {
314 dev_warn(dev, "nfi core timed out entering address mode\n");
315 return -EIO;
316 }
317
318 return 0;
319 }
320
321 static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd)
322 {
323 struct nand_chip *chip = mtd_to_nand(mtd);
324 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
325 struct mtk_nfc *nfc = nand_get_controller_data(chip);
326 u32 fmt, spare, i;
327
328 if (!mtd->writesize)
329 return 0;
330
331 spare = mtk_nand->spare_per_sector;
332
333 switch (mtd->writesize) {
334 case 512:
335 fmt = PAGEFMT_512_2K | PAGEFMT_SEC_SEL_512;
336 break;
337 case KB(2):
338 if (chip->ecc.size == 512)
339 fmt = PAGEFMT_2K_4K | PAGEFMT_SEC_SEL_512;
340 else
341 fmt = PAGEFMT_512_2K;
342 break;
343 case KB(4):
344 if (chip->ecc.size == 512)
345 fmt = PAGEFMT_4K_8K | PAGEFMT_SEC_SEL_512;
346 else
347 fmt = PAGEFMT_2K_4K;
348 break;
349 case KB(8):
350 if (chip->ecc.size == 512)
351 fmt = PAGEFMT_8K_16K | PAGEFMT_SEC_SEL_512;
352 else
353 fmt = PAGEFMT_4K_8K;
354 break;
355 case KB(16):
356 fmt = PAGEFMT_8K_16K;
357 break;
358 default:
359 dev_err(nfc->dev, "invalid page len: %d\n", mtd->writesize);
360 return -EINVAL;
361 }
362
363 /*
364 * the hardware will double the value for this eccsize, so we need to
365 * halve it
366 */
367 if (chip->ecc.size == 1024)
368 spare >>= 1;
369
370 for (i = 0; i < nfc->caps->num_spare_size; i++) {
371 if (nfc->caps->spare_size[i] == spare)
372 break;
373 }
374
375 if (i == nfc->caps->num_spare_size) {
376 dev_err(nfc->dev, "invalid spare size %d\n", spare);
377 return -EINVAL;
378 }
379
380 fmt |= i << nfc->caps->pageformat_spare_shift;
381
382 fmt |= mtk_nand->fdm.reg_size << PAGEFMT_FDM_SHIFT;
383 fmt |= mtk_nand->fdm.ecc_size << PAGEFMT_FDM_ECC_SHIFT;
384 nfi_writel(nfc, fmt, NFI_PAGEFMT);
385
386 nfc->ecc_cfg.strength = chip->ecc.strength;
387 nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size;
388
389 return 0;
390 }
391
392 static void mtk_nfc_select_chip(struct mtd_info *mtd, int chip)
393 {
394 struct nand_chip *nand = mtd_to_nand(mtd);
395 struct mtk_nfc *nfc = nand_get_controller_data(nand);
396 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand);
397
398 if (chip < 0)
399 return;
400
401 mtk_nfc_hw_runtime_config(mtd);
402
403 nfi_writel(nfc, mtk_nand->sels[chip], NFI_CSEL);
404 }
405
406 static int mtk_nfc_dev_ready(struct mtd_info *mtd)
407 {
408 struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
409
410 if (nfi_readl(nfc, NFI_STA) & STA_BUSY)
411 return 0;
412
413 return 1;
414 }
415
416 static void mtk_nfc_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
417 {
418 struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
419
420 if (ctrl & NAND_ALE) {
421 mtk_nfc_send_address(nfc, dat);
422 } else if (ctrl & NAND_CLE) {
423 mtk_nfc_hw_reset(nfc);
424
425 nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG);
426 mtk_nfc_send_command(nfc, dat);
427 }
428 }
429
430 static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc)
431 {
432 int rc;
433 u8 val;
434
435 rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val,
436 val & PIO_DI_RDY, 10, MTK_TIMEOUT);
437 if (rc < 0)
438 dev_err(nfc->dev, "data not ready\n");
439 }
440
441 static inline u8 mtk_nfc_read_byte(struct mtd_info *mtd)
442 {
443 struct nand_chip *chip = mtd_to_nand(mtd);
444 struct mtk_nfc *nfc = nand_get_controller_data(chip);
445 u32 reg;
446
447 /* after each byte read, the NFI_STA reg is reset by the hardware */
448 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
449 if (reg != NFI_FSM_CUSTDATA) {
450 reg = nfi_readw(nfc, NFI_CNFG);
451 reg |= CNFG_BYTE_RW | CNFG_READ_EN;
452 nfi_writew(nfc, reg, NFI_CNFG);
453
454 /*
455 * set to max sector to allow the HW to continue reading over
456 * unaligned accesses
457 */
458 reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD;
459 nfi_writel(nfc, reg, NFI_CON);
460
461 /* trigger to fetch data */
462 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
463 }
464
465 mtk_nfc_wait_ioready(nfc);
466
467 return nfi_readb(nfc, NFI_DATAR);
468 }
469
470 static void mtk_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
471 {
472 int i;
473
474 for (i = 0; i < len; i++)
475 buf[i] = mtk_nfc_read_byte(mtd);
476 }
477
478 static void mtk_nfc_write_byte(struct mtd_info *mtd, u8 byte)
479 {
480 struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
481 u32 reg;
482
483 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
484
485 if (reg != NFI_FSM_CUSTDATA) {
486 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
487 nfi_writew(nfc, reg, NFI_CNFG);
488
489 reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR;
490 nfi_writel(nfc, reg, NFI_CON);
491
492 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
493 }
494
495 mtk_nfc_wait_ioready(nfc);
496 nfi_writeb(nfc, byte, NFI_DATAW);
497 }
498
499 static void mtk_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
500 {
501 int i;
502
503 for (i = 0; i < len; i++)
504 mtk_nfc_write_byte(mtd, buf[i]);
505 }
506
507 static int mtk_nfc_setup_data_interface(struct mtd_info *mtd, int csline,
508 const struct nand_data_interface *conf)
509 {
510 struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
511 const struct nand_sdr_timings *timings;
512 u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
513 u32 thold;
514
515 timings = nand_get_sdr_timings(conf);
516 if (IS_ERR(timings))
517 return -ENOTSUPP;
518
519 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
520 return 0;
521
522 rate = clk_get_rate(nfc->clk.nfi_clk);
523 /* There is a frequency divider in some IPs */
524 rate /= nfc->caps->nfi_clk_div;
525
526 /* turn clock rate into KHZ */
527 rate /= 1000;
528
529 tpoecs = max(timings->tALH_min, timings->tCLH_min) / 1000;
530 tpoecs = DIV_ROUND_UP(tpoecs * rate, 1000000);
531 tpoecs &= 0xf;
532
533 tprecs = max(timings->tCLS_min, timings->tALS_min) / 1000;
534 tprecs = DIV_ROUND_UP(tprecs * rate, 1000000);
535 tprecs &= 0x3f;
536
537 /* sdr interface has no tCR which means CE# low to RE# low */
538 tc2r = 0;
539
540 tw2r = timings->tWHR_min / 1000;
541 tw2r = DIV_ROUND_UP(tw2r * rate, 1000000);
542 tw2r = DIV_ROUND_UP(tw2r - 1, 2);
543 tw2r &= 0xf;
544
545 twh = max(timings->tREH_min, timings->tWH_min) / 1000;
546 twh = DIV_ROUND_UP(twh * rate, 1000000) - 1;
547 twh &= 0xf;
548
549 /* Calculate real WE#/RE# hold time in nanosecond */
550 thold = (twh + 1) * 1000000 / rate;
551 /* nanosecond to picosecond */
552 thold *= 1000;
553
554 /*
555 * WE# low level time should be expaned to meet WE# pulse time
556 * and WE# cycle time at the same time.
557 */
558 if (thold < timings->tWC_min)
559 twst = timings->tWC_min - thold;
560 twst = max(timings->tWP_min, twst) / 1000;
561 twst = DIV_ROUND_UP(twst * rate, 1000000) - 1;
562 twst &= 0xf;
563
564 /*
565 * RE# low level time should be expaned to meet RE# pulse time,
566 * RE# access time and RE# cycle time at the same time.
567 */
568 if (thold < timings->tRC_min)
569 trlt = timings->tRC_min - thold;
570 trlt = max3(trlt, timings->tREA_max, timings->tRP_min) / 1000;
571 trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
572 trlt &= 0xf;
573
574 /*
575 * ACCON: access timing control register
576 * -------------------------------------
577 * 31:28: tpoecs, minimum required time for CS post pulling down after
578 * accessing the device
579 * 27:22: tprecs, minimum required time for CS pre pulling down before
580 * accessing the device
581 * 21:16: tc2r, minimum required time from NCEB low to NREB low
582 * 15:12: tw2r, minimum required time from NWEB high to NREB low.
583 * 11:08: twh, write enable hold time
584 * 07:04: twst, write wait states
585 * 03:00: trlt, read wait states
586 */
587 trlt = ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt);
588 nfi_writel(nfc, trlt, NFI_ACCCON);
589
590 return 0;
591 }
592
593 static int mtk_nfc_sector_encode(struct nand_chip *chip, u8 *data)
594 {
595 struct mtk_nfc *nfc = nand_get_controller_data(chip);
596 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
597 int size = chip->ecc.size + mtk_nand->fdm.reg_size;
598
599 nfc->ecc_cfg.mode = ECC_DMA_MODE;
600 nfc->ecc_cfg.op = ECC_ENCODE;
601
602 return mtk_ecc_encode(nfc->ecc, &nfc->ecc_cfg, data, size);
603 }
604
605 static void mtk_nfc_no_bad_mark_swap(struct mtd_info *a, u8 *b, int c)
606 {
607 /* nop */
608 }
609
610 static void mtk_nfc_bad_mark_swap(struct mtd_info *mtd, u8 *buf, int raw)
611 {
612 struct nand_chip *chip = mtd_to_nand(mtd);
613 struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip);
614 u32 bad_pos = nand->bad_mark.pos;
615
616 if (raw)
617 bad_pos += nand->bad_mark.sec * mtk_data_len(chip);
618 else
619 bad_pos += nand->bad_mark.sec * chip->ecc.size;
620
621 swap(chip->oob_poi[0], buf[bad_pos]);
622 }
623
624 static int mtk_nfc_format_subpage(struct mtd_info *mtd, u32 offset,
625 u32 len, const u8 *buf)
626 {
627 struct nand_chip *chip = mtd_to_nand(mtd);
628 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
629 struct mtk_nfc *nfc = nand_get_controller_data(chip);
630 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
631 u32 start, end;
632 int i, ret;
633
634 start = offset / chip->ecc.size;
635 end = DIV_ROUND_UP(offset + len, chip->ecc.size);
636
637 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
638 for (i = 0; i < chip->ecc.steps; i++) {
639 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i),
640 chip->ecc.size);
641
642 if (start > i || i >= end)
643 continue;
644
645 if (i == mtk_nand->bad_mark.sec)
646 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
647
648 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
649
650 /* program the CRC back to the OOB */
651 ret = mtk_nfc_sector_encode(chip, mtk_data_ptr(chip, i));
652 if (ret < 0)
653 return ret;
654 }
655
656 return 0;
657 }
658
659 static void mtk_nfc_format_page(struct mtd_info *mtd, const u8 *buf)
660 {
661 struct nand_chip *chip = mtd_to_nand(mtd);
662 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
663 struct mtk_nfc *nfc = nand_get_controller_data(chip);
664 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
665 u32 i;
666
667 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
668 for (i = 0; i < chip->ecc.steps; i++) {
669 if (buf)
670 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i),
671 chip->ecc.size);
672
673 if (i == mtk_nand->bad_mark.sec)
674 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
675
676 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
677 }
678 }
679
680 static inline void mtk_nfc_read_fdm(struct nand_chip *chip, u32 start,
681 u32 sectors)
682 {
683 struct mtk_nfc *nfc = nand_get_controller_data(chip);
684 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
685 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
686 u32 vall, valm;
687 u8 *oobptr;
688 int i, j;
689
690 for (i = 0; i < sectors; i++) {
691 oobptr = oob_ptr(chip, start + i);
692 vall = nfi_readl(nfc, NFI_FDML(i));
693 valm = nfi_readl(nfc, NFI_FDMM(i));
694
695 for (j = 0; j < fdm->reg_size; j++)
696 oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
697 }
698 }
699
700 static inline void mtk_nfc_write_fdm(struct nand_chip *chip)
701 {
702 struct mtk_nfc *nfc = nand_get_controller_data(chip);
703 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
704 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
705 u32 vall, valm;
706 u8 *oobptr;
707 int i, j;
708
709 for (i = 0; i < chip->ecc.steps; i++) {
710 oobptr = oob_ptr(chip, i);
711 vall = 0;
712 valm = 0;
713 for (j = 0; j < 8; j++) {
714 if (j < 4)
715 vall |= (j < fdm->reg_size ? oobptr[j] : 0xff)
716 << (j * 8);
717 else
718 valm |= (j < fdm->reg_size ? oobptr[j] : 0xff)
719 << ((j - 4) * 8);
720 }
721 nfi_writel(nfc, vall, NFI_FDML(i));
722 nfi_writel(nfc, valm, NFI_FDMM(i));
723 }
724 }
725
726 static int mtk_nfc_do_write_page(struct mtd_info *mtd, struct nand_chip *chip,
727 const u8 *buf, int page, int len)
728 {
729 struct mtk_nfc *nfc = nand_get_controller_data(chip);
730 struct device *dev = nfc->dev;
731 dma_addr_t addr;
732 u32 reg;
733 int ret;
734
735 addr = dma_map_single(dev, (void *)buf, len, DMA_TO_DEVICE);
736 ret = dma_mapping_error(nfc->dev, addr);
737 if (ret) {
738 dev_err(nfc->dev, "dma mapping error\n");
739 return -EINVAL;
740 }
741
742 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN;
743 nfi_writew(nfc, reg, NFI_CNFG);
744
745 nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON);
746 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
747 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
748
749 init_completion(&nfc->done);
750
751 reg = nfi_readl(nfc, NFI_CON) | CON_BWR;
752 nfi_writel(nfc, reg, NFI_CON);
753 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
754
755 ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
756 if (!ret) {
757 dev_err(dev, "program ahb done timeout\n");
758 nfi_writew(nfc, 0, NFI_INTR_EN);
759 ret = -ETIMEDOUT;
760 goto timeout;
761 }
762
763 ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg,
764 ADDRCNTR_SEC(reg) >= chip->ecc.steps,
765 10, MTK_TIMEOUT);
766 if (ret)
767 dev_err(dev, "hwecc write timeout\n");
768
769 timeout:
770
771 dma_unmap_single(nfc->dev, addr, len, DMA_TO_DEVICE);
772 nfi_writel(nfc, 0, NFI_CON);
773
774 return ret;
775 }
776
777 static int mtk_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
778 const u8 *buf, int page, int raw)
779 {
780 struct mtk_nfc *nfc = nand_get_controller_data(chip);
781 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
782 size_t len;
783 const u8 *bufpoi;
784 u32 reg;
785 int ret;
786
787 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
788
789 if (!raw) {
790 /* OOB => FDM: from register, ECC: from HW */
791 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN;
792 nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG);
793
794 nfc->ecc_cfg.op = ECC_ENCODE;
795 nfc->ecc_cfg.mode = ECC_NFI_MODE;
796 ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
797 if (ret) {
798 /* clear NFI config */
799 reg = nfi_readw(nfc, NFI_CNFG);
800 reg &= ~(CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
801 nfi_writew(nfc, reg, NFI_CNFG);
802
803 return ret;
804 }
805
806 memcpy(nfc->buffer, buf, mtd->writesize);
807 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, raw);
808 bufpoi = nfc->buffer;
809
810 /* write OOB into the FDM registers (OOB area in MTK NAND) */
811 mtk_nfc_write_fdm(chip);
812 } else {
813 bufpoi = buf;
814 }
815
816 len = mtd->writesize + (raw ? mtd->oobsize : 0);
817 ret = mtk_nfc_do_write_page(mtd, chip, bufpoi, page, len);
818
819 if (!raw)
820 mtk_ecc_disable(nfc->ecc);
821
822 if (ret)
823 return ret;
824
825 return nand_prog_page_end_op(chip);
826 }
827
828 static int mtk_nfc_write_page_hwecc(struct mtd_info *mtd,
829 struct nand_chip *chip, const u8 *buf,
830 int oob_on, int page)
831 {
832 return mtk_nfc_write_page(mtd, chip, buf, page, 0);
833 }
834
835 static int mtk_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
836 const u8 *buf, int oob_on, int pg)
837 {
838 struct mtk_nfc *nfc = nand_get_controller_data(chip);
839
840 mtk_nfc_format_page(mtd, buf);
841 return mtk_nfc_write_page(mtd, chip, nfc->buffer, pg, 1);
842 }
843
844 static int mtk_nfc_write_subpage_hwecc(struct mtd_info *mtd,
845 struct nand_chip *chip, u32 offset,
846 u32 data_len, const u8 *buf,
847 int oob_on, int page)
848 {
849 struct mtk_nfc *nfc = nand_get_controller_data(chip);
850 int ret;
851
852 ret = mtk_nfc_format_subpage(mtd, offset, data_len, buf);
853 if (ret < 0)
854 return ret;
855
856 /* use the data in the private buffer (now with FDM and CRC) */
857 return mtk_nfc_write_page(mtd, chip, nfc->buffer, page, 1);
858 }
859
860 static int mtk_nfc_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
861 int page)
862 {
863 return mtk_nfc_write_page_raw(mtd, chip, NULL, 1, page);
864 }
865
866 static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 start,
867 u32 sectors)
868 {
869 struct nand_chip *chip = mtd_to_nand(mtd);
870 struct mtk_nfc *nfc = nand_get_controller_data(chip);
871 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
872 struct mtk_ecc_stats stats;
873 u32 reg_size = mtk_nand->fdm.reg_size;
874 int rc, i;
875
876 rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
877 if (rc) {
878 memset(buf, 0xff, sectors * chip->ecc.size);
879 for (i = 0; i < sectors; i++)
880 memset(oob_ptr(chip, start + i), 0xff, reg_size);
881 return 0;
882 }
883
884 mtk_ecc_get_stats(nfc->ecc, &stats, sectors);
885 mtd->ecc_stats.corrected += stats.corrected;
886 mtd->ecc_stats.failed += stats.failed;
887
888 return stats.bitflips;
889 }
890
891 static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
892 u32 data_offs, u32 readlen,
893 u8 *bufpoi, int page, int raw)
894 {
895 struct mtk_nfc *nfc = nand_get_controller_data(chip);
896 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
897 u32 spare = mtk_nand->spare_per_sector;
898 u32 column, sectors, start, end, reg;
899 dma_addr_t addr;
900 int bitflips = 0;
901 size_t len;
902 u8 *buf;
903 int rc;
904
905 start = data_offs / chip->ecc.size;
906 end = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size);
907
908 sectors = end - start;
909 column = start * (chip->ecc.size + spare);
910
911 len = sectors * chip->ecc.size + (raw ? sectors * spare : 0);
912 buf = bufpoi + start * chip->ecc.size;
913
914 nand_read_page_op(chip, page, column, NULL, 0);
915
916 addr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE);
917 rc = dma_mapping_error(nfc->dev, addr);
918 if (rc) {
919 dev_err(nfc->dev, "dma mapping error\n");
920
921 return -EINVAL;
922 }
923
924 reg = nfi_readw(nfc, NFI_CNFG);
925 reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB;
926 if (!raw) {
927 reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN;
928 nfi_writew(nfc, reg, NFI_CNFG);
929
930 nfc->ecc_cfg.mode = ECC_NFI_MODE;
931 nfc->ecc_cfg.sectors = sectors;
932 nfc->ecc_cfg.op = ECC_DECODE;
933 rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
934 if (rc) {
935 dev_err(nfc->dev, "ecc enable\n");
936 /* clear NFI_CNFG */
937 reg &= ~(CNFG_DMA_BURST_EN | CNFG_AHB | CNFG_READ_EN |
938 CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
939 nfi_writew(nfc, reg, NFI_CNFG);
940 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
941
942 return rc;
943 }
944 } else {
945 nfi_writew(nfc, reg, NFI_CNFG);
946 }
947
948 nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON);
949 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
950 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
951
952 init_completion(&nfc->done);
953 reg = nfi_readl(nfc, NFI_CON) | CON_BRD;
954 nfi_writel(nfc, reg, NFI_CON);
955 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
956
957 rc = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
958 if (!rc)
959 dev_warn(nfc->dev, "read ahb/dma done timeout\n");
960
961 rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg,
962 ADDRCNTR_SEC(reg) >= sectors, 10,
963 MTK_TIMEOUT);
964 if (rc < 0) {
965 dev_err(nfc->dev, "subpage done timeout\n");
966 bitflips = -EIO;
967 } else if (!raw) {
968 rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
969 bitflips = rc < 0 ? -ETIMEDOUT :
970 mtk_nfc_update_ecc_stats(mtd, buf, start, sectors);
971 mtk_nfc_read_fdm(chip, start, sectors);
972 }
973
974 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
975
976 if (raw)
977 goto done;
978
979 mtk_ecc_disable(nfc->ecc);
980
981 if (clamp(mtk_nand->bad_mark.sec, start, end) == mtk_nand->bad_mark.sec)
982 mtk_nand->bad_mark.bm_swap(mtd, bufpoi, raw);
983 done:
984 nfi_writel(nfc, 0, NFI_CON);
985
986 return bitflips;
987 }
988
989 static int mtk_nfc_read_subpage_hwecc(struct mtd_info *mtd,
990 struct nand_chip *chip, u32 off,
991 u32 len, u8 *p, int pg)
992 {
993 return mtk_nfc_read_subpage(mtd, chip, off, len, p, pg, 0);
994 }
995
996 static int mtk_nfc_read_page_hwecc(struct mtd_info *mtd,
997 struct nand_chip *chip, u8 *p,
998 int oob_on, int pg)
999 {
1000 return mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, p, pg, 0);
1001 }
1002
1003 static int mtk_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1004 u8 *buf, int oob_on, int page)
1005 {
1006 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1007 struct mtk_nfc *nfc = nand_get_controller_data(chip);
1008 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
1009 int i, ret;
1010
1011 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
1012 ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, nfc->buffer,
1013 page, 1);
1014 if (ret < 0)
1015 return ret;
1016
1017 for (i = 0; i < chip->ecc.steps; i++) {
1018 memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
1019
1020 if (i == mtk_nand->bad_mark.sec)
1021 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
1022
1023 if (buf)
1024 memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i),
1025 chip->ecc.size);
1026 }
1027
1028 return ret;
1029 }
1030
1031 static int mtk_nfc_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1032 int page)
1033 {
1034 return mtk_nfc_read_page_raw(mtd, chip, NULL, 1, page);
1035 }
1036
1037 static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc)
1038 {
1039 /*
1040 * CNRNB: nand ready/busy register
1041 * -------------------------------
1042 * 7:4: timeout register for polling the NAND busy/ready signal
1043 * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles.
1044 */
1045 nfi_writew(nfc, 0xf1, NFI_CNRNB);
1046 nfi_writel(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT);
1047
1048 mtk_nfc_hw_reset(nfc);
1049
1050 nfi_readl(nfc, NFI_INTR_STA);
1051 nfi_writel(nfc, 0, NFI_INTR_EN);
1052 }
1053
1054 static irqreturn_t mtk_nfc_irq(int irq, void *id)
1055 {
1056 struct mtk_nfc *nfc = id;
1057 u16 sta, ien;
1058
1059 sta = nfi_readw(nfc, NFI_INTR_STA);
1060 ien = nfi_readw(nfc, NFI_INTR_EN);
1061
1062 if (!(sta & ien))
1063 return IRQ_NONE;
1064
1065 nfi_writew(nfc, ~sta & ien, NFI_INTR_EN);
1066 complete(&nfc->done);
1067
1068 return IRQ_HANDLED;
1069 }
1070
1071 static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk)
1072 {
1073 int ret;
1074
1075 ret = clk_prepare_enable(clk->nfi_clk);
1076 if (ret) {
1077 dev_err(dev, "failed to enable nfi clk\n");
1078 return ret;
1079 }
1080
1081 ret = clk_prepare_enable(clk->pad_clk);
1082 if (ret) {
1083 dev_err(dev, "failed to enable pad clk\n");
1084 clk_disable_unprepare(clk->nfi_clk);
1085 return ret;
1086 }
1087
1088 return 0;
1089 }
1090
1091 static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk)
1092 {
1093 clk_disable_unprepare(clk->nfi_clk);
1094 clk_disable_unprepare(clk->pad_clk);
1095 }
1096
1097 static int mtk_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1098 struct mtd_oob_region *oob_region)
1099 {
1100 struct nand_chip *chip = mtd_to_nand(mtd);
1101 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1102 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
1103 u32 eccsteps;
1104
1105 eccsteps = mtd->writesize / chip->ecc.size;
1106
1107 if (section >= eccsteps)
1108 return -ERANGE;
1109
1110 oob_region->length = fdm->reg_size - fdm->ecc_size;
1111 oob_region->offset = section * fdm->reg_size + fdm->ecc_size;
1112
1113 return 0;
1114 }
1115
1116 static int mtk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1117 struct mtd_oob_region *oob_region)
1118 {
1119 struct nand_chip *chip = mtd_to_nand(mtd);
1120 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1121 u32 eccsteps;
1122
1123 if (section)
1124 return -ERANGE;
1125
1126 eccsteps = mtd->writesize / chip->ecc.size;
1127 oob_region->offset = mtk_nand->fdm.reg_size * eccsteps;
1128 oob_region->length = mtd->oobsize - oob_region->offset;
1129
1130 return 0;
1131 }
1132
1133 static const struct mtd_ooblayout_ops mtk_nfc_ooblayout_ops = {
1134 .free = mtk_nfc_ooblayout_free,
1135 .ecc = mtk_nfc_ooblayout_ecc,
1136 };
1137
1138 static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
1139 {
1140 struct nand_chip *nand = mtd_to_nand(mtd);
1141 struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
1142 struct mtk_nfc *nfc = nand_get_controller_data(nand);
1143 u32 ecc_bytes;
1144
1145 ecc_bytes = DIV_ROUND_UP(nand->ecc.strength *
1146 mtk_ecc_get_parity_bits(nfc->ecc), 8);
1147
1148 fdm->reg_size = chip->spare_per_sector - ecc_bytes;
1149 if (fdm->reg_size > NFI_FDM_MAX_SIZE)
1150 fdm->reg_size = NFI_FDM_MAX_SIZE;
1151
1152 /* bad block mark storage */
1153 fdm->ecc_size = 1;
1154 }
1155
1156 static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
1157 struct mtd_info *mtd)
1158 {
1159 struct nand_chip *nand = mtd_to_nand(mtd);
1160
1161 if (mtd->writesize == 512) {
1162 bm_ctl->bm_swap = mtk_nfc_no_bad_mark_swap;
1163 } else {
1164 bm_ctl->bm_swap = mtk_nfc_bad_mark_swap;
1165 bm_ctl->sec = mtd->writesize / mtk_data_len(nand);
1166 bm_ctl->pos = mtd->writesize % mtk_data_len(nand);
1167 }
1168 }
1169
1170 static int mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd)
1171 {
1172 struct nand_chip *nand = mtd_to_nand(mtd);
1173 struct mtk_nfc *nfc = nand_get_controller_data(nand);
1174 const u8 *spare = nfc->caps->spare_size;
1175 u32 eccsteps, i, closest_spare = 0;
1176
1177 eccsteps = mtd->writesize / nand->ecc.size;
1178 *sps = mtd->oobsize / eccsteps;
1179
1180 if (nand->ecc.size == 1024)
1181 *sps >>= 1;
1182
1183 if (*sps < MTK_NFC_MIN_SPARE)
1184 return -EINVAL;
1185
1186 for (i = 0; i < nfc->caps->num_spare_size; i++) {
1187 if (*sps >= spare[i] && spare[i] >= spare[closest_spare]) {
1188 closest_spare = i;
1189 if (*sps == spare[i])
1190 break;
1191 }
1192 }
1193
1194 *sps = spare[closest_spare];
1195
1196 if (nand->ecc.size == 1024)
1197 *sps <<= 1;
1198
1199 return 0;
1200 }
1201
1202 static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
1203 {
1204 struct nand_chip *nand = mtd_to_nand(mtd);
1205 struct mtk_nfc *nfc = nand_get_controller_data(nand);
1206 u32 spare;
1207 int free, ret;
1208
1209 /* support only ecc hw mode */
1210 if (nand->ecc.mode != NAND_ECC_HW) {
1211 dev_err(dev, "ecc.mode not supported\n");
1212 return -EINVAL;
1213 }
1214
1215 /* if optional dt settings not present */
1216 if (!nand->ecc.size || !nand->ecc.strength) {
1217 /* use datasheet requirements */
1218 nand->ecc.strength = nand->ecc_strength_ds;
1219 nand->ecc.size = nand->ecc_step_ds;
1220
1221 /*
1222 * align eccstrength and eccsize
1223 * this controller only supports 512 and 1024 sizes
1224 */
1225 if (nand->ecc.size < 1024) {
1226 if (mtd->writesize > 512 &&
1227 nfc->caps->max_sector_size > 512) {
1228 nand->ecc.size = 1024;
1229 nand->ecc.strength <<= 1;
1230 } else {
1231 nand->ecc.size = 512;
1232 }
1233 } else {
1234 nand->ecc.size = 1024;
1235 }
1236
1237 ret = mtk_nfc_set_spare_per_sector(&spare, mtd);
1238 if (ret)
1239 return ret;
1240
1241 /* calculate oob bytes except ecc parity data */
1242 free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc)
1243 + 7) >> 3;
1244 free = spare - free;
1245
1246 /*
1247 * enhance ecc strength if oob left is bigger than max FDM size
1248 * or reduce ecc strength if oob size is not enough for ecc
1249 * parity data.
1250 */
1251 if (free > NFI_FDM_MAX_SIZE) {
1252 spare -= NFI_FDM_MAX_SIZE;
1253 nand->ecc.strength = (spare << 3) /
1254 mtk_ecc_get_parity_bits(nfc->ecc);
1255 } else if (free < 0) {
1256 spare -= NFI_FDM_MIN_SIZE;
1257 nand->ecc.strength = (spare << 3) /
1258 mtk_ecc_get_parity_bits(nfc->ecc);
1259 }
1260 }
1261
1262 mtk_ecc_adjust_strength(nfc->ecc, &nand->ecc.strength);
1263
1264 dev_info(dev, "eccsize %d eccstrength %d\n",
1265 nand->ecc.size, nand->ecc.strength);
1266
1267 return 0;
1268 }
1269
1270 static int mtk_nfc_attach_chip(struct nand_chip *chip)
1271 {
1272 struct mtd_info *mtd = nand_to_mtd(chip);
1273 struct device *dev = mtd->dev.parent;
1274 struct mtk_nfc *nfc = nand_get_controller_data(chip);
1275 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1276 int len;
1277 int ret;
1278
1279 if (chip->options & NAND_BUSWIDTH_16) {
1280 dev_err(dev, "16bits buswidth not supported");
1281 return -EINVAL;
1282 }
1283
1284 /* store bbt magic in page, cause OOB is not protected */
1285 if (chip->bbt_options & NAND_BBT_USE_FLASH)
1286 chip->bbt_options |= NAND_BBT_NO_OOB;
1287
1288 ret = mtk_nfc_ecc_init(dev, mtd);
1289 if (ret)
1290 return ret;
1291
1292 ret = mtk_nfc_set_spare_per_sector(&mtk_nand->spare_per_sector, mtd);
1293 if (ret)
1294 return ret;
1295
1296 mtk_nfc_set_fdm(&mtk_nand->fdm, mtd);
1297 mtk_nfc_set_bad_mark_ctl(&mtk_nand->bad_mark, mtd);
1298
1299 len = mtd->writesize + mtd->oobsize;
1300 nfc->buffer = devm_kzalloc(dev, len, GFP_KERNEL);
1301 if (!nfc->buffer)
1302 return -ENOMEM;
1303
1304 return 0;
1305 }
1306
1307 static const struct nand_controller_ops mtk_nfc_controller_ops = {
1308 .attach_chip = mtk_nfc_attach_chip,
1309 };
1310
1311 static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
1312 struct device_node *np)
1313 {
1314 struct mtk_nfc_nand_chip *chip;
1315 struct nand_chip *nand;
1316 struct mtd_info *mtd;
1317 int nsels;
1318 u32 tmp;
1319 int ret;
1320 int i;
1321
1322 if (!of_get_property(np, "reg", &nsels))
1323 return -ENODEV;
1324
1325 nsels /= sizeof(u32);
1326 if (!nsels || nsels > MTK_NAND_MAX_NSELS) {
1327 dev_err(dev, "invalid reg property size %d\n", nsels);
1328 return -EINVAL;
1329 }
1330
1331 chip = devm_kzalloc(dev, sizeof(*chip) + nsels * sizeof(u8),
1332 GFP_KERNEL);
1333 if (!chip)
1334 return -ENOMEM;
1335
1336 chip->nsels = nsels;
1337 for (i = 0; i < nsels; i++) {
1338 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1339 if (ret) {
1340 dev_err(dev, "reg property failure : %d\n", ret);
1341 return ret;
1342 }
1343 chip->sels[i] = tmp;
1344 }
1345
1346 nand = &chip->nand;
1347 nand->controller = &nfc->controller;
1348
1349 nand_set_flash_node(nand, np);
1350 nand_set_controller_data(nand, nfc);
1351
1352 nand->options |= NAND_USE_BOUNCE_BUFFER | NAND_SUBPAGE_READ;
1353 nand->dev_ready = mtk_nfc_dev_ready;
1354 nand->select_chip = mtk_nfc_select_chip;
1355 nand->write_byte = mtk_nfc_write_byte;
1356 nand->write_buf = mtk_nfc_write_buf;
1357 nand->read_byte = mtk_nfc_read_byte;
1358 nand->read_buf = mtk_nfc_read_buf;
1359 nand->cmd_ctrl = mtk_nfc_cmd_ctrl;
1360 nand->setup_data_interface = mtk_nfc_setup_data_interface;
1361
1362 /* set default mode in case dt entry is missing */
1363 nand->ecc.mode = NAND_ECC_HW;
1364
1365 nand->ecc.write_subpage = mtk_nfc_write_subpage_hwecc;
1366 nand->ecc.write_page_raw = mtk_nfc_write_page_raw;
1367 nand->ecc.write_page = mtk_nfc_write_page_hwecc;
1368 nand->ecc.write_oob_raw = mtk_nfc_write_oob_std;
1369 nand->ecc.write_oob = mtk_nfc_write_oob_std;
1370
1371 nand->ecc.read_subpage = mtk_nfc_read_subpage_hwecc;
1372 nand->ecc.read_page_raw = mtk_nfc_read_page_raw;
1373 nand->ecc.read_page = mtk_nfc_read_page_hwecc;
1374 nand->ecc.read_oob_raw = mtk_nfc_read_oob_std;
1375 nand->ecc.read_oob = mtk_nfc_read_oob_std;
1376
1377 mtd = nand_to_mtd(nand);
1378 mtd->owner = THIS_MODULE;
1379 mtd->dev.parent = dev;
1380 mtd->name = MTK_NAME;
1381 mtd_set_ooblayout(mtd, &mtk_nfc_ooblayout_ops);
1382
1383 mtk_nfc_hw_init(nfc);
1384
1385 ret = nand_scan(nand, nsels);
1386 if (ret)
1387 return ret;
1388
1389 ret = mtd_device_register(mtd, NULL, 0);
1390 if (ret) {
1391 dev_err(dev, "mtd parse partition error\n");
1392 nand_cleanup(nand);
1393 return ret;
1394 }
1395
1396 list_add_tail(&chip->node, &nfc->chips);
1397
1398 return 0;
1399 }
1400
1401 static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
1402 {
1403 struct device_node *np = dev->of_node;
1404 struct device_node *nand_np;
1405 int ret;
1406
1407 for_each_child_of_node(np, nand_np) {
1408 ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np);
1409 if (ret) {
1410 of_node_put(nand_np);
1411 return ret;
1412 }
1413 }
1414
1415 return 0;
1416 }
1417
1418 static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
1419 .spare_size = spare_size_mt2701,
1420 .num_spare_size = 16,
1421 .pageformat_spare_shift = 4,
1422 .nfi_clk_div = 1,
1423 .max_sector = 16,
1424 .max_sector_size = 1024,
1425 };
1426
1427 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
1428 .spare_size = spare_size_mt2712,
1429 .num_spare_size = 19,
1430 .pageformat_spare_shift = 16,
1431 .nfi_clk_div = 2,
1432 .max_sector = 16,
1433 .max_sector_size = 1024,
1434 };
1435
1436 static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
1437 .spare_size = spare_size_mt7622,
1438 .num_spare_size = 4,
1439 .pageformat_spare_shift = 4,
1440 .nfi_clk_div = 1,
1441 .max_sector = 8,
1442 .max_sector_size = 512,
1443 };
1444
1445 static const struct of_device_id mtk_nfc_id_table[] = {
1446 {
1447 .compatible = "mediatek,mt2701-nfc",
1448 .data = &mtk_nfc_caps_mt2701,
1449 }, {
1450 .compatible = "mediatek,mt2712-nfc",
1451 .data = &mtk_nfc_caps_mt2712,
1452 }, {
1453 .compatible = "mediatek,mt7622-nfc",
1454 .data = &mtk_nfc_caps_mt7622,
1455 },
1456 {}
1457 };
1458 MODULE_DEVICE_TABLE(of, mtk_nfc_id_table);
1459
1460 static int mtk_nfc_probe(struct platform_device *pdev)
1461 {
1462 struct device *dev = &pdev->dev;
1463 struct device_node *np = dev->of_node;
1464 struct mtk_nfc *nfc;
1465 struct resource *res;
1466 int ret, irq;
1467
1468 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1469 if (!nfc)
1470 return -ENOMEM;
1471
1472 spin_lock_init(&nfc->controller.lock);
1473 init_waitqueue_head(&nfc->controller.wq);
1474 INIT_LIST_HEAD(&nfc->chips);
1475 nfc->controller.ops = &mtk_nfc_controller_ops;
1476
1477 /* probe defer if not ready */
1478 nfc->ecc = of_mtk_ecc_get(np);
1479 if (IS_ERR(nfc->ecc))
1480 return PTR_ERR(nfc->ecc);
1481 else if (!nfc->ecc)
1482 return -ENODEV;
1483
1484 nfc->caps = of_device_get_match_data(dev);
1485 nfc->dev = dev;
1486
1487 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1488 nfc->regs = devm_ioremap_resource(dev, res);
1489 if (IS_ERR(nfc->regs)) {
1490 ret = PTR_ERR(nfc->regs);
1491 goto release_ecc;
1492 }
1493
1494 nfc->clk.nfi_clk = devm_clk_get(dev, "nfi_clk");
1495 if (IS_ERR(nfc->clk.nfi_clk)) {
1496 dev_err(dev, "no clk\n");
1497 ret = PTR_ERR(nfc->clk.nfi_clk);
1498 goto release_ecc;
1499 }
1500
1501 nfc->clk.pad_clk = devm_clk_get(dev, "pad_clk");
1502 if (IS_ERR(nfc->clk.pad_clk)) {
1503 dev_err(dev, "no pad clk\n");
1504 ret = PTR_ERR(nfc->clk.pad_clk);
1505 goto release_ecc;
1506 }
1507
1508 ret = mtk_nfc_enable_clk(dev, &nfc->clk);
1509 if (ret)
1510 goto release_ecc;
1511
1512 irq = platform_get_irq(pdev, 0);
1513 if (irq < 0) {
1514 dev_err(dev, "no nfi irq resource\n");
1515 ret = -EINVAL;
1516 goto clk_disable;
1517 }
1518
1519 ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc);
1520 if (ret) {
1521 dev_err(dev, "failed to request nfi irq\n");
1522 goto clk_disable;
1523 }
1524
1525 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
1526 if (ret) {
1527 dev_err(dev, "failed to set dma mask\n");
1528 goto clk_disable;
1529 }
1530
1531 platform_set_drvdata(pdev, nfc);
1532
1533 ret = mtk_nfc_nand_chips_init(dev, nfc);
1534 if (ret) {
1535 dev_err(dev, "failed to init nand chips\n");
1536 goto clk_disable;
1537 }
1538
1539 return 0;
1540
1541 clk_disable:
1542 mtk_nfc_disable_clk(&nfc->clk);
1543
1544 release_ecc:
1545 mtk_ecc_release(nfc->ecc);
1546
1547 return ret;
1548 }
1549
1550 static int mtk_nfc_remove(struct platform_device *pdev)
1551 {
1552 struct mtk_nfc *nfc = platform_get_drvdata(pdev);
1553 struct mtk_nfc_nand_chip *chip;
1554
1555 while (!list_empty(&nfc->chips)) {
1556 chip = list_first_entry(&nfc->chips, struct mtk_nfc_nand_chip,
1557 node);
1558 nand_release(&chip->nand);
1559 list_del(&chip->node);
1560 }
1561
1562 mtk_ecc_release(nfc->ecc);
1563 mtk_nfc_disable_clk(&nfc->clk);
1564
1565 return 0;
1566 }
1567
1568 #ifdef CONFIG_PM_SLEEP
1569 static int mtk_nfc_suspend(struct device *dev)
1570 {
1571 struct mtk_nfc *nfc = dev_get_drvdata(dev);
1572
1573 mtk_nfc_disable_clk(&nfc->clk);
1574
1575 return 0;
1576 }
1577
1578 static int mtk_nfc_resume(struct device *dev)
1579 {
1580 struct mtk_nfc *nfc = dev_get_drvdata(dev);
1581 struct mtk_nfc_nand_chip *chip;
1582 struct nand_chip *nand;
1583 int ret;
1584 u32 i;
1585
1586 udelay(200);
1587
1588 ret = mtk_nfc_enable_clk(dev, &nfc->clk);
1589 if (ret)
1590 return ret;
1591
1592 /* reset NAND chip if VCC was powered off */
1593 list_for_each_entry(chip, &nfc->chips, node) {
1594 nand = &chip->nand;
1595 for (i = 0; i < chip->nsels; i++)
1596 nand_reset(nand, i);
1597 }
1598
1599 return 0;
1600 }
1601
1602 static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume);
1603 #endif
1604
1605 static struct platform_driver mtk_nfc_driver = {
1606 .probe = mtk_nfc_probe,
1607 .remove = mtk_nfc_remove,
1608 .driver = {
1609 .name = MTK_NAME,
1610 .of_match_table = mtk_nfc_id_table,
1611 #ifdef CONFIG_PM_SLEEP
1612 .pm = &mtk_nfc_pm_ops,
1613 #endif
1614 },
1615 };
1616
1617 module_platform_driver(mtk_nfc_driver);
1618
1619 MODULE_LICENSE("GPL");
1620 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
1621 MODULE_DESCRIPTION("MTK Nand Flash Controller Driver");
Linux with added FPC-III support