?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / mtd / nand / raw / nandsim.c
blob6e908e4fa8e85eba39b56216fd6cd9d936bb9444
1 /*
2 * NAND flash simulator.
3 *
4 * Author: Artem B. Bityuckiy <dedekind@oktetlabs.ru>, <dedekind@infradead.org>
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 *
8 * Note: NS means "NAND Simulator".
9 * Note: Input means input TO flash chip, output means output FROM chip.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2, or (at your option) any later
14 * version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
19 * Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
24 */
25
26 #define pr_fmt(fmt) "[nandsim]" fmt
27
28 #include <linux/init.h>
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/vmalloc.h>
33 #include <linux/math64.h>
34 #include <linux/slab.h>
35 #include <linux/errno.h>
36 #include <linux/string.h>
37 #include <linux/mtd/mtd.h>
38 #include <linux/mtd/rawnand.h>
39 #include <linux/mtd/nand_bch.h>
40 #include <linux/mtd/partitions.h>
41 #include <linux/delay.h>
42 #include <linux/list.h>
43 #include <linux/random.h>
44 #include <linux/sched.h>
45 #include <linux/sched/mm.h>
46 #include <linux/fs.h>
47 #include <linux/pagemap.h>
48 #include <linux/seq_file.h>
49 #include <linux/debugfs.h>
50
51 /* Default simulator parameters values */
52 #if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \
53 !defined(CONFIG_NANDSIM_SECOND_ID_BYTE) || \
54 !defined(CONFIG_NANDSIM_THIRD_ID_BYTE) || \
55 !defined(CONFIG_NANDSIM_FOURTH_ID_BYTE)
56 #define CONFIG_NANDSIM_FIRST_ID_BYTE 0x98
57 #define CONFIG_NANDSIM_SECOND_ID_BYTE 0x39
58 #define CONFIG_NANDSIM_THIRD_ID_BYTE 0xFF /* No byte */
59 #define CONFIG_NANDSIM_FOURTH_ID_BYTE 0xFF /* No byte */
60 #endif
61
62 #ifndef CONFIG_NANDSIM_ACCESS_DELAY
63 #define CONFIG_NANDSIM_ACCESS_DELAY 25
64 #endif
65 #ifndef CONFIG_NANDSIM_PROGRAMM_DELAY
66 #define CONFIG_NANDSIM_PROGRAMM_DELAY 200
67 #endif
68 #ifndef CONFIG_NANDSIM_ERASE_DELAY
69 #define CONFIG_NANDSIM_ERASE_DELAY 2
70 #endif
71 #ifndef CONFIG_NANDSIM_OUTPUT_CYCLE
72 #define CONFIG_NANDSIM_OUTPUT_CYCLE 40
73 #endif
74 #ifndef CONFIG_NANDSIM_INPUT_CYCLE
75 #define CONFIG_NANDSIM_INPUT_CYCLE 50
76 #endif
77 #ifndef CONFIG_NANDSIM_BUS_WIDTH
78 #define CONFIG_NANDSIM_BUS_WIDTH 8
79 #endif
80 #ifndef CONFIG_NANDSIM_DO_DELAYS
81 #define CONFIG_NANDSIM_DO_DELAYS 0
82 #endif
83 #ifndef CONFIG_NANDSIM_LOG
84 #define CONFIG_NANDSIM_LOG 0
85 #endif
86 #ifndef CONFIG_NANDSIM_DBG
87 #define CONFIG_NANDSIM_DBG 0
88 #endif
89 #ifndef CONFIG_NANDSIM_MAX_PARTS
90 #define CONFIG_NANDSIM_MAX_PARTS 32
91 #endif
92
93 static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY;
94 static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY;
95 static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY;
96 static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE;
97 static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE;
98 static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH;
99 static uint do_delays = CONFIG_NANDSIM_DO_DELAYS;
100 static uint log = CONFIG_NANDSIM_LOG;
101 static uint dbg = CONFIG_NANDSIM_DBG;
102 static unsigned long parts[CONFIG_NANDSIM_MAX_PARTS];
103 static unsigned int parts_num;
104 static char *badblocks = NULL;
105 static char *weakblocks = NULL;
106 static char *weakpages = NULL;
107 static unsigned int bitflips = 0;
108 static char *gravepages = NULL;
109 static unsigned int overridesize = 0;
110 static char *cache_file = NULL;
111 static unsigned int bbt;
112 static unsigned int bch;
113 static u_char id_bytes[8] = {
114 [0] = CONFIG_NANDSIM_FIRST_ID_BYTE,
115 [1] = CONFIG_NANDSIM_SECOND_ID_BYTE,
116 [2] = CONFIG_NANDSIM_THIRD_ID_BYTE,
117 [3] = CONFIG_NANDSIM_FOURTH_ID_BYTE,
118 [4 ... 7] = 0xFF,
119 };
120
121 module_param_array(id_bytes, byte, NULL, 0400);
122 module_param_named(first_id_byte, id_bytes[0], byte, 0400);
123 module_param_named(second_id_byte, id_bytes[1], byte, 0400);
124 module_param_named(third_id_byte, id_bytes[2], byte, 0400);
125 module_param_named(fourth_id_byte, id_bytes[3], byte, 0400);
126 module_param(access_delay, uint, 0400);
127 module_param(programm_delay, uint, 0400);
128 module_param(erase_delay, uint, 0400);
129 module_param(output_cycle, uint, 0400);
130 module_param(input_cycle, uint, 0400);
131 module_param(bus_width, uint, 0400);
132 module_param(do_delays, uint, 0400);
133 module_param(log, uint, 0400);
134 module_param(dbg, uint, 0400);
135 module_param_array(parts, ulong, &parts_num, 0400);
136 module_param(badblocks, charp, 0400);
137 module_param(weakblocks, charp, 0400);
138 module_param(weakpages, charp, 0400);
139 module_param(bitflips, uint, 0400);
140 module_param(gravepages, charp, 0400);
141 module_param(overridesize, uint, 0400);
142 module_param(cache_file, charp, 0400);
143 module_param(bbt, uint, 0400);
144 module_param(bch, uint, 0400);
145
146 MODULE_PARM_DESC(id_bytes, "The ID bytes returned by NAND Flash 'read ID' command");
147 MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufacturer ID) (obsolete)");
148 MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID) (obsolete)");
149 MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command (obsolete)");
150 MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command (obsolete)");
151 MODULE_PARM_DESC(access_delay, "Initial page access delay (microseconds)");
152 MODULE_PARM_DESC(programm_delay, "Page programm delay (microseconds");
153 MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)");
154 MODULE_PARM_DESC(output_cycle, "Word output (from flash) time (nanoseconds)");
155 MODULE_PARM_DESC(input_cycle, "Word input (to flash) time (nanoseconds)");
156 MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
157 MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero");
158 MODULE_PARM_DESC(log, "Perform logging if not zero");
159 MODULE_PARM_DESC(dbg, "Output debug information if not zero");
160 MODULE_PARM_DESC(parts, "Partition sizes (in erase blocks) separated by commas");
161 /* Page and erase block positions for the following parameters are independent of any partitions */
162 MODULE_PARM_DESC(badblocks, "Erase blocks that are initially marked bad, separated by commas");
163 MODULE_PARM_DESC(weakblocks, "Weak erase blocks [: remaining erase cycles (defaults to 3)]"
164 " separated by commas e.g. 113:2 means eb 113"
165 " can be erased only twice before failing");
166 MODULE_PARM_DESC(weakpages, "Weak pages [: maximum writes (defaults to 3)]"
167 " separated by commas e.g. 1401:2 means page 1401"
168 " can be written only twice before failing");
169 MODULE_PARM_DESC(bitflips, "Maximum number of random bit flips per page (zero by default)");
170 MODULE_PARM_DESC(gravepages, "Pages that lose data [: maximum reads (defaults to 3)]"
171 " separated by commas e.g. 1401:2 means page 1401"
172 " can be read only twice before failing");
173 MODULE_PARM_DESC(overridesize, "Specifies the NAND Flash size overriding the ID bytes. "
174 "The size is specified in erase blocks and as the exponent of a power of two"
175 " e.g. 5 means a size of 32 erase blocks");
176 MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory");
177 MODULE_PARM_DESC(bbt, "0 OOB, 1 BBT with marker in OOB, 2 BBT with marker in data area");
178 MODULE_PARM_DESC(bch, "Enable BCH ecc and set how many bits should "
179 "be correctable in 512-byte blocks");
180
181 /* The largest possible page size */
182 #define NS_LARGEST_PAGE_SIZE 4096
183
184 /* Simulator's output macros (logging, debugging, warning, error) */
185 #define NS_LOG(args...) \
186 do { if (log) pr_debug(" log: " args); } while(0)
187 #define NS_DBG(args...) \
188 do { if (dbg) pr_debug(" debug: " args); } while(0)
189 #define NS_WARN(args...) \
190 do { pr_warn(" warning: " args); } while(0)
191 #define NS_ERR(args...) \
192 do { pr_err(" error: " args); } while(0)
193 #define NS_INFO(args...) \
194 do { pr_info(" " args); } while(0)
195
196 /* Busy-wait delay macros (microseconds, milliseconds) */
197 #define NS_UDELAY(us) \
198 do { if (do_delays) udelay(us); } while(0)
199 #define NS_MDELAY(us) \
200 do { if (do_delays) mdelay(us); } while(0)
201
202 /* Is the nandsim structure initialized ? */
203 #define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0)
204
205 /* Good operation completion status */
206 #define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))
207
208 /* Operation failed completion status */
209 #define NS_STATUS_FAILED(ns) (NAND_STATUS_FAIL | NS_STATUS_OK(ns))
210
211 /* Calculate the page offset in flash RAM image by (row, column) address */
212 #define NS_RAW_OFFSET(ns) \
213 (((ns)->regs.row * (ns)->geom.pgszoob) + (ns)->regs.column)
214
215 /* Calculate the OOB offset in flash RAM image by (row, column) address */
216 #define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz)
217
218 /* After a command is input, the simulator goes to one of the following states */
219 #define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */
220 #define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */
221 #define STATE_CMD_READSTART 0x00000003 /* read data second command (large page devices) */
222 #define STATE_CMD_PAGEPROG 0x00000004 /* start page program */
223 #define STATE_CMD_READOOB 0x00000005 /* read OOB area */
224 #define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */
225 #define STATE_CMD_STATUS 0x00000007 /* read status */
226 #define STATE_CMD_SEQIN 0x00000009 /* sequential data input */
227 #define STATE_CMD_READID 0x0000000A /* read ID */
228 #define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */
229 #define STATE_CMD_RESET 0x0000000C /* reset */
230 #define STATE_CMD_RNDOUT 0x0000000D /* random output command */
231 #define STATE_CMD_RNDOUTSTART 0x0000000E /* random output start command */
232 #define STATE_CMD_MASK 0x0000000F /* command states mask */
233
234 /* After an address is input, the simulator goes to one of these states */
235 #define STATE_ADDR_PAGE 0x00000010 /* full (row, column) address is accepted */
236 #define STATE_ADDR_SEC 0x00000020 /* sector address was accepted */
237 #define STATE_ADDR_COLUMN 0x00000030 /* column address was accepted */
238 #define STATE_ADDR_ZERO 0x00000040 /* one byte zero address was accepted */
239 #define STATE_ADDR_MASK 0x00000070 /* address states mask */
240
241 /* During data input/output the simulator is in these states */
242 #define STATE_DATAIN 0x00000100 /* waiting for data input */
243 #define STATE_DATAIN_MASK 0x00000100 /* data input states mask */
244
245 #define STATE_DATAOUT 0x00001000 /* waiting for page data output */
246 #define STATE_DATAOUT_ID 0x00002000 /* waiting for ID bytes output */
247 #define STATE_DATAOUT_STATUS 0x00003000 /* waiting for status output */
248 #define STATE_DATAOUT_MASK 0x00007000 /* data output states mask */
249
250 /* Previous operation is done, ready to accept new requests */
251 #define STATE_READY 0x00000000
252
253 /* This state is used to mark that the next state isn't known yet */
254 #define STATE_UNKNOWN 0x10000000
255
256 /* Simulator's actions bit masks */
257 #define ACTION_CPY 0x00100000 /* copy page/OOB to the internal buffer */
258 #define ACTION_PRGPAGE 0x00200000 /* program the internal buffer to flash */
259 #define ACTION_SECERASE 0x00300000 /* erase sector */
260 #define ACTION_ZEROOFF 0x00400000 /* don't add any offset to address */
261 #define ACTION_HALFOFF 0x00500000 /* add to address half of page */
262 #define ACTION_OOBOFF 0x00600000 /* add to address OOB offset */
263 #define ACTION_MASK 0x00700000 /* action mask */
264
265 #define NS_OPER_NUM 13 /* Number of operations supported by the simulator */
266 #define NS_OPER_STATES 6 /* Maximum number of states in operation */
267
268 #define OPT_ANY 0xFFFFFFFF /* any chip supports this operation */
269 #define OPT_PAGE512 0x00000002 /* 512-byte page chips */
270 #define OPT_PAGE2048 0x00000008 /* 2048-byte page chips */
271 #define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */
272 #define OPT_PAGE4096 0x00000080 /* 4096-byte page chips */
273 #define OPT_LARGEPAGE (OPT_PAGE2048 | OPT_PAGE4096) /* 2048 & 4096-byte page chips */
274 #define OPT_SMALLPAGE (OPT_PAGE512) /* 512-byte page chips */
275
276 /* Remove action bits from state */
277 #define NS_STATE(x) ((x) & ~ACTION_MASK)
278
279 /*
280 * Maximum previous states which need to be saved. Currently saving is
281 * only needed for page program operation with preceded read command
282 * (which is only valid for 512-byte pages).
283 */
284 #define NS_MAX_PREVSTATES 1
285
286 /* Maximum page cache pages needed to read or write a NAND page to the cache_file */
287 #define NS_MAX_HELD_PAGES 16
288
289 /*
290 * A union to represent flash memory contents and flash buffer.
291 */
292 union ns_mem {
293 u_char *byte; /* for byte access */
294 uint16_t *word; /* for 16-bit word access */
295 };
296
297 /*
298 * The structure which describes all the internal simulator data.
299 */
300 struct nandsim {
301 struct mtd_partition partitions[CONFIG_NANDSIM_MAX_PARTS];
302 unsigned int nbparts;
303
304 uint busw; /* flash chip bus width (8 or 16) */
305 u_char ids[8]; /* chip's ID bytes */
306 uint32_t options; /* chip's characteristic bits */
307 uint32_t state; /* current chip state */
308 uint32_t nxstate; /* next expected state */
309
310 uint32_t *op; /* current operation, NULL operations isn't known yet */
311 uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */
312 uint16_t npstates; /* number of previous states saved */
313 uint16_t stateidx; /* current state index */
314
315 /* The simulated NAND flash pages array */
316 union ns_mem *pages;
317
318 /* Slab allocator for nand pages */
319 struct kmem_cache *nand_pages_slab;
320
321 /* Internal buffer of page + OOB size bytes */
322 union ns_mem buf;
323
324 /* NAND flash "geometry" */
325 struct {
326 uint64_t totsz; /* total flash size, bytes */
327 uint32_t secsz; /* flash sector (erase block) size, bytes */
328 uint pgsz; /* NAND flash page size, bytes */
329 uint oobsz; /* page OOB area size, bytes */
330 uint64_t totszoob; /* total flash size including OOB, bytes */
331 uint pgszoob; /* page size including OOB , bytes*/
332 uint secszoob; /* sector size including OOB, bytes */
333 uint pgnum; /* total number of pages */
334 uint pgsec; /* number of pages per sector */
335 uint secshift; /* bits number in sector size */
336 uint pgshift; /* bits number in page size */
337 uint pgaddrbytes; /* bytes per page address */
338 uint secaddrbytes; /* bytes per sector address */
339 uint idbytes; /* the number ID bytes that this chip outputs */
340 } geom;
341
342 /* NAND flash internal registers */
343 struct {
344 unsigned command; /* the command register */
345 u_char status; /* the status register */
346 uint row; /* the page number */
347 uint column; /* the offset within page */
348 uint count; /* internal counter */
349 uint num; /* number of bytes which must be processed */
350 uint off; /* fixed page offset */
351 } regs;
352
353 /* NAND flash lines state */
354 struct {
355 int ce; /* chip Enable */
356 int cle; /* command Latch Enable */
357 int ale; /* address Latch Enable */
358 int wp; /* write Protect */
359 } lines;
360
361 /* Fields needed when using a cache file */
362 struct file *cfile; /* Open file */
363 unsigned long *pages_written; /* Which pages have been written */
364 void *file_buf;
365 struct page *held_pages[NS_MAX_HELD_PAGES];
366 int held_cnt;
367 };
368
369 /*
370 * Operations array. To perform any operation the simulator must pass
371 * through the correspondent states chain.
372 */
373 static struct nandsim_operations {
374 uint32_t reqopts; /* options which are required to perform the operation */
375 uint32_t states[NS_OPER_STATES]; /* operation's states */
376 } ops[NS_OPER_NUM] = {
377 /* Read page + OOB from the beginning */
378 {OPT_SMALLPAGE, {STATE_CMD_READ0 | ACTION_ZEROOFF, STATE_ADDR_PAGE | ACTION_CPY,
379 STATE_DATAOUT, STATE_READY}},
380 /* Read page + OOB from the second half */
381 {OPT_PAGE512_8BIT, {STATE_CMD_READ1 | ACTION_HALFOFF, STATE_ADDR_PAGE | ACTION_CPY,
382 STATE_DATAOUT, STATE_READY}},
383 /* Read OOB */
384 {OPT_SMALLPAGE, {STATE_CMD_READOOB | ACTION_OOBOFF, STATE_ADDR_PAGE | ACTION_CPY,
385 STATE_DATAOUT, STATE_READY}},
386 /* Program page starting from the beginning */
387 {OPT_ANY, {STATE_CMD_SEQIN, STATE_ADDR_PAGE, STATE_DATAIN,
388 STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
389 /* Program page starting from the beginning */
390 {OPT_SMALLPAGE, {STATE_CMD_READ0, STATE_CMD_SEQIN | ACTION_ZEROOFF, STATE_ADDR_PAGE,
391 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
392 /* Program page starting from the second half */
393 {OPT_PAGE512, {STATE_CMD_READ1, STATE_CMD_SEQIN | ACTION_HALFOFF, STATE_ADDR_PAGE,
394 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
395 /* Program OOB */
396 {OPT_SMALLPAGE, {STATE_CMD_READOOB, STATE_CMD_SEQIN | ACTION_OOBOFF, STATE_ADDR_PAGE,
397 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
398 /* Erase sector */
399 {OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}},
400 /* Read status */
401 {OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}},
402 /* Read ID */
403 {OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}},
404 /* Large page devices read page */
405 {OPT_LARGEPAGE, {STATE_CMD_READ0, STATE_ADDR_PAGE, STATE_CMD_READSTART | ACTION_CPY,
406 STATE_DATAOUT, STATE_READY}},
407 /* Large page devices random page read */
408 {OPT_LARGEPAGE, {STATE_CMD_RNDOUT, STATE_ADDR_COLUMN, STATE_CMD_RNDOUTSTART | ACTION_CPY,
409 STATE_DATAOUT, STATE_READY}},
410 };
411
412 struct weak_block {
413 struct list_head list;
414 unsigned int erase_block_no;
415 unsigned int max_erases;
416 unsigned int erases_done;
417 };
418
419 static LIST_HEAD(weak_blocks);
420
421 struct weak_page {
422 struct list_head list;
423 unsigned int page_no;
424 unsigned int max_writes;
425 unsigned int writes_done;
426 };
427
428 static LIST_HEAD(weak_pages);
429
430 struct grave_page {
431 struct list_head list;
432 unsigned int page_no;
433 unsigned int max_reads;
434 unsigned int reads_done;
435 };
436
437 static LIST_HEAD(grave_pages);
438
439 static unsigned long *erase_block_wear = NULL;
440 static unsigned int wear_eb_count = 0;
441 static unsigned long total_wear = 0;
442
443 /* MTD structure for NAND controller */
444 static struct mtd_info *nsmtd;
445
446 static int nandsim_debugfs_show(struct seq_file *m, void *private)
447 {
448 unsigned long wmin = -1, wmax = 0, avg;
449 unsigned long deciles[10], decile_max[10], tot = 0;
450 unsigned int i;
451
452 /* Calc wear stats */
453 for (i = 0; i < wear_eb_count; ++i) {
454 unsigned long wear = erase_block_wear[i];
455 if (wear < wmin)
456 wmin = wear;
457 if (wear > wmax)
458 wmax = wear;
459 tot += wear;
460 }
461
462 for (i = 0; i < 9; ++i) {
463 deciles[i] = 0;
464 decile_max[i] = (wmax * (i + 1) + 5) / 10;
465 }
466 deciles[9] = 0;
467 decile_max[9] = wmax;
468 for (i = 0; i < wear_eb_count; ++i) {
469 int d;
470 unsigned long wear = erase_block_wear[i];
471 for (d = 0; d < 10; ++d)
472 if (wear <= decile_max[d]) {
473 deciles[d] += 1;
474 break;
475 }
476 }
477 avg = tot / wear_eb_count;
478
479 /* Output wear report */
480 seq_printf(m, "Total numbers of erases: %lu\n", tot);
481 seq_printf(m, "Number of erase blocks: %u\n", wear_eb_count);
482 seq_printf(m, "Average number of erases: %lu\n", avg);
483 seq_printf(m, "Maximum number of erases: %lu\n", wmax);
484 seq_printf(m, "Minimum number of erases: %lu\n", wmin);
485 for (i = 0; i < 10; ++i) {
486 unsigned long from = (i ? decile_max[i - 1] + 1 : 0);
487 if (from > decile_max[i])
488 continue;
489 seq_printf(m, "Number of ebs with erase counts from %lu to %lu : %lu\n",
490 from,
491 decile_max[i],
492 deciles[i]);
493 }
494
495 return 0;
496 }
497
498 static int nandsim_debugfs_open(struct inode *inode, struct file *file)
499 {
500 return single_open(file, nandsim_debugfs_show, inode->i_private);
501 }
502
503 static const struct file_operations dfs_fops = {
504 .open = nandsim_debugfs_open,
505 .read = seq_read,
506 .llseek = seq_lseek,
507 .release = single_release,
508 };
509
510 /**
511 * nandsim_debugfs_create - initialize debugfs
512 * @dev: nandsim device description object
513 *
514 * This function creates all debugfs files for UBI device @ubi. Returns zero in
515 * case of success and a negative error code in case of failure.
516 */
517 static int nandsim_debugfs_create(struct nandsim *dev)
518 {
519 struct dentry *root = nsmtd->dbg.dfs_dir;
520 struct dentry *dent;
521
522 /*
523 * Just skip debugfs initialization when the debugfs directory is
524 * missing.
525 */
526 if (IS_ERR_OR_NULL(root)) {
527 if (IS_ENABLED(CONFIG_DEBUG_FS) &&
528 !IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER))
529 NS_WARN("CONFIG_MTD_PARTITIONED_MASTER must be enabled to expose debugfs stuff\n");
530 return 0;
531 }
532
533 dent = debugfs_create_file("nandsim_wear_report", S_IRUSR,
534 root, dev, &dfs_fops);
535 if (IS_ERR_OR_NULL(dent)) {
536 NS_ERR("cannot create \"nandsim_wear_report\" debugfs entry\n");
537 return -1;
538 }
539
540 return 0;
541 }
542
543 /*
544 * Allocate array of page pointers, create slab allocation for an array
545 * and initialize the array by NULL pointers.
546 *
547 * RETURNS: 0 if success, -ENOMEM if memory alloc fails.
548 */
549 static int __init alloc_device(struct nandsim *ns)
550 {
551 struct file *cfile;
552 int i, err;
553
554 if (cache_file) {
555 cfile = filp_open(cache_file, O_CREAT | O_RDWR | O_LARGEFILE, 0600);
556 if (IS_ERR(cfile))
557 return PTR_ERR(cfile);
558 if (!(cfile->f_mode & FMODE_CAN_READ)) {
559 NS_ERR("alloc_device: cache file not readable\n");
560 err = -EINVAL;
561 goto err_close;
562 }
563 if (!(cfile->f_mode & FMODE_CAN_WRITE)) {
564 NS_ERR("alloc_device: cache file not writeable\n");
565 err = -EINVAL;
566 goto err_close;
567 }
568 ns->pages_written =
569 vzalloc(array_size(sizeof(unsigned long),
570 BITS_TO_LONGS(ns->geom.pgnum)));
571 if (!ns->pages_written) {
572 NS_ERR("alloc_device: unable to allocate pages written array\n");
573 err = -ENOMEM;
574 goto err_close;
575 }
576 ns->file_buf = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
577 if (!ns->file_buf) {
578 NS_ERR("alloc_device: unable to allocate file buf\n");
579 err = -ENOMEM;
580 goto err_free;
581 }
582 ns->cfile = cfile;
583 return 0;
584 }
585
586 ns->pages = vmalloc(array_size(sizeof(union ns_mem), ns->geom.pgnum));
587 if (!ns->pages) {
588 NS_ERR("alloc_device: unable to allocate page array\n");
589 return -ENOMEM;
590 }
591 for (i = 0; i < ns->geom.pgnum; i++) {
592 ns->pages[i].byte = NULL;
593 }
594 ns->nand_pages_slab = kmem_cache_create("nandsim",
595 ns->geom.pgszoob, 0, 0, NULL);
596 if (!ns->nand_pages_slab) {
597 NS_ERR("cache_create: unable to create kmem_cache\n");
598 return -ENOMEM;
599 }
600
601 return 0;
602
603 err_free:
604 vfree(ns->pages_written);
605 err_close:
606 filp_close(cfile, NULL);
607 return err;
608 }
609
610 /*
611 * Free any allocated pages, and free the array of page pointers.
612 */
613 static void free_device(struct nandsim *ns)
614 {
615 int i;
616
617 if (ns->cfile) {
618 kfree(ns->file_buf);
619 vfree(ns->pages_written);
620 filp_close(ns->cfile, NULL);
621 return;
622 }
623
624 if (ns->pages) {
625 for (i = 0; i < ns->geom.pgnum; i++) {
626 if (ns->pages[i].byte)
627 kmem_cache_free(ns->nand_pages_slab,
628 ns->pages[i].byte);
629 }
630 kmem_cache_destroy(ns->nand_pages_slab);
631 vfree(ns->pages);
632 }
633 }
634
635 static char __init *get_partition_name(int i)
636 {
637 return kasprintf(GFP_KERNEL, "NAND simulator partition %d", i);
638 }
639
640 /*
641 * Initialize the nandsim structure.
642 *
643 * RETURNS: 0 if success, -ERRNO if failure.
644 */
645 static int __init init_nandsim(struct mtd_info *mtd)
646 {
647 struct nand_chip *chip = mtd_to_nand(mtd);
648 struct nandsim *ns = nand_get_controller_data(chip);
649 int i, ret = 0;
650 uint64_t remains;
651 uint64_t next_offset;
652
653 if (NS_IS_INITIALIZED(ns)) {
654 NS_ERR("init_nandsim: nandsim is already initialized\n");
655 return -EIO;
656 }
657
658 /* Force mtd to not do delays */
659 chip->chip_delay = 0;
660
661 /* Initialize the NAND flash parameters */
662 ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8;
663 ns->geom.totsz = mtd->size;
664 ns->geom.pgsz = mtd->writesize;
665 ns->geom.oobsz = mtd->oobsize;
666 ns->geom.secsz = mtd->erasesize;
667 ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz;
668 ns->geom.pgnum = div_u64(ns->geom.totsz, ns->geom.pgsz);
669 ns->geom.totszoob = ns->geom.totsz + (uint64_t)ns->geom.pgnum * ns->geom.oobsz;
670 ns->geom.secshift = ffs(ns->geom.secsz) - 1;
671 ns->geom.pgshift = chip->page_shift;
672 ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz;
673 ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec;
674 ns->options = 0;
675
676 if (ns->geom.pgsz == 512) {
677 ns->options |= OPT_PAGE512;
678 if (ns->busw == 8)
679 ns->options |= OPT_PAGE512_8BIT;
680 } else if (ns->geom.pgsz == 2048) {
681 ns->options |= OPT_PAGE2048;
682 } else if (ns->geom.pgsz == 4096) {
683 ns->options |= OPT_PAGE4096;
684 } else {
685 NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz);
686 return -EIO;
687 }
688
689 if (ns->options & OPT_SMALLPAGE) {
690 if (ns->geom.totsz <= (32 << 20)) {
691 ns->geom.pgaddrbytes = 3;
692 ns->geom.secaddrbytes = 2;
693 } else {
694 ns->geom.pgaddrbytes = 4;
695 ns->geom.secaddrbytes = 3;
696 }
697 } else {
698 if (ns->geom.totsz <= (128 << 20)) {
699 ns->geom.pgaddrbytes = 4;
700 ns->geom.secaddrbytes = 2;
701 } else {
702 ns->geom.pgaddrbytes = 5;
703 ns->geom.secaddrbytes = 3;
704 }
705 }
706
707 /* Fill the partition_info structure */
708 if (parts_num > ARRAY_SIZE(ns->partitions)) {
709 NS_ERR("too many partitions.\n");
710 return -EINVAL;
711 }
712 remains = ns->geom.totsz;
713 next_offset = 0;
714 for (i = 0; i < parts_num; ++i) {
715 uint64_t part_sz = (uint64_t)parts[i] * ns->geom.secsz;
716
717 if (!part_sz || part_sz > remains) {
718 NS_ERR("bad partition size.\n");
719 return -EINVAL;
720 }
721 ns->partitions[i].name = get_partition_name(i);
722 if (!ns->partitions[i].name) {
723 NS_ERR("unable to allocate memory.\n");
724 return -ENOMEM;
725 }
726 ns->partitions[i].offset = next_offset;
727 ns->partitions[i].size = part_sz;
728 next_offset += ns->partitions[i].size;
729 remains -= ns->partitions[i].size;
730 }
731 ns->nbparts = parts_num;
732 if (remains) {
733 if (parts_num + 1 > ARRAY_SIZE(ns->partitions)) {
734 NS_ERR("too many partitions.\n");
735 return -EINVAL;
736 }
737 ns->partitions[i].name = get_partition_name(i);
738 if (!ns->partitions[i].name) {
739 NS_ERR("unable to allocate memory.\n");
740 return -ENOMEM;
741 }
742 ns->partitions[i].offset = next_offset;
743 ns->partitions[i].size = remains;
744 ns->nbparts += 1;
745 }
746
747 if (ns->busw == 16)
748 NS_WARN("16-bit flashes support wasn't tested\n");
749
750 printk("flash size: %llu MiB\n",
751 (unsigned long long)ns->geom.totsz >> 20);
752 printk("page size: %u bytes\n", ns->geom.pgsz);
753 printk("OOB area size: %u bytes\n", ns->geom.oobsz);
754 printk("sector size: %u KiB\n", ns->geom.secsz >> 10);
755 printk("pages number: %u\n", ns->geom.pgnum);
756 printk("pages per sector: %u\n", ns->geom.pgsec);
757 printk("bus width: %u\n", ns->busw);
758 printk("bits in sector size: %u\n", ns->geom.secshift);
759 printk("bits in page size: %u\n", ns->geom.pgshift);
760 printk("bits in OOB size: %u\n", ffs(ns->geom.oobsz) - 1);
761 printk("flash size with OOB: %llu KiB\n",
762 (unsigned long long)ns->geom.totszoob >> 10);
763 printk("page address bytes: %u\n", ns->geom.pgaddrbytes);
764 printk("sector address bytes: %u\n", ns->geom.secaddrbytes);
765 printk("options: %#x\n", ns->options);
766
767 if ((ret = alloc_device(ns)) != 0)
768 return ret;
769
770 /* Allocate / initialize the internal buffer */
771 ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
772 if (!ns->buf.byte) {
773 NS_ERR("init_nandsim: unable to allocate %u bytes for the internal buffer\n",
774 ns->geom.pgszoob);
775 return -ENOMEM;
776 }
777 memset(ns->buf.byte, 0xFF, ns->geom.pgszoob);
778
779 return 0;
780 }
781
782 /*
783 * Free the nandsim structure.
784 */
785 static void free_nandsim(struct nandsim *ns)
786 {
787 kfree(ns->buf.byte);
788 free_device(ns);
789
790 return;
791 }
792
793 static int parse_badblocks(struct nandsim *ns, struct mtd_info *mtd)
794 {
795 char *w;
796 int zero_ok;
797 unsigned int erase_block_no;
798 loff_t offset;
799
800 if (!badblocks)
801 return 0;
802 w = badblocks;
803 do {
804 zero_ok = (*w == '0' ? 1 : 0);
805 erase_block_no = simple_strtoul(w, &w, 0);
806 if (!zero_ok && !erase_block_no) {
807 NS_ERR("invalid badblocks.\n");
808 return -EINVAL;
809 }
810 offset = (loff_t)erase_block_no * ns->geom.secsz;
811 if (mtd_block_markbad(mtd, offset)) {
812 NS_ERR("invalid badblocks.\n");
813 return -EINVAL;
814 }
815 if (*w == ',')
816 w += 1;
817 } while (*w);
818 return 0;
819 }
820
821 static int parse_weakblocks(void)
822 {
823 char *w;
824 int zero_ok;
825 unsigned int erase_block_no;
826 unsigned int max_erases;
827 struct weak_block *wb;
828
829 if (!weakblocks)
830 return 0;
831 w = weakblocks;
832 do {
833 zero_ok = (*w == '0' ? 1 : 0);
834 erase_block_no = simple_strtoul(w, &w, 0);
835 if (!zero_ok && !erase_block_no) {
836 NS_ERR("invalid weakblocks.\n");
837 return -EINVAL;
838 }
839 max_erases = 3;
840 if (*w == ':') {
841 w += 1;
842 max_erases = simple_strtoul(w, &w, 0);
843 }
844 if (*w == ',')
845 w += 1;
846 wb = kzalloc(sizeof(*wb), GFP_KERNEL);
847 if (!wb) {
848 NS_ERR("unable to allocate memory.\n");
849 return -ENOMEM;
850 }
851 wb->erase_block_no = erase_block_no;
852 wb->max_erases = max_erases;
853 list_add(&wb->list, &weak_blocks);
854 } while (*w);
855 return 0;
856 }
857
858 static int erase_error(unsigned int erase_block_no)
859 {
860 struct weak_block *wb;
861
862 list_for_each_entry(wb, &weak_blocks, list)
863 if (wb->erase_block_no == erase_block_no) {
864 if (wb->erases_done >= wb->max_erases)
865 return 1;
866 wb->erases_done += 1;
867 return 0;
868 }
869 return 0;
870 }
871
872 static int parse_weakpages(void)
873 {
874 char *w;
875 int zero_ok;
876 unsigned int page_no;
877 unsigned int max_writes;
878 struct weak_page *wp;
879
880 if (!weakpages)
881 return 0;
882 w = weakpages;
883 do {
884 zero_ok = (*w == '0' ? 1 : 0);
885 page_no = simple_strtoul(w, &w, 0);
886 if (!zero_ok && !page_no) {
887 NS_ERR("invalid weakpages.\n");
888 return -EINVAL;
889 }
890 max_writes = 3;
891 if (*w == ':') {
892 w += 1;
893 max_writes = simple_strtoul(w, &w, 0);
894 }
895 if (*w == ',')
896 w += 1;
897 wp = kzalloc(sizeof(*wp), GFP_KERNEL);
898 if (!wp) {
899 NS_ERR("unable to allocate memory.\n");
900 return -ENOMEM;
901 }
902 wp->page_no = page_no;
903 wp->max_writes = max_writes;
904 list_add(&wp->list, &weak_pages);
905 } while (*w);
906 return 0;
907 }
908
909 static int write_error(unsigned int page_no)
910 {
911 struct weak_page *wp;
912
913 list_for_each_entry(wp, &weak_pages, list)
914 if (wp->page_no == page_no) {
915 if (wp->writes_done >= wp->max_writes)
916 return 1;
917 wp->writes_done += 1;
918 return 0;
919 }
920 return 0;
921 }
922
923 static int parse_gravepages(void)
924 {
925 char *g;
926 int zero_ok;
927 unsigned int page_no;
928 unsigned int max_reads;
929 struct grave_page *gp;
930
931 if (!gravepages)
932 return 0;
933 g = gravepages;
934 do {
935 zero_ok = (*g == '0' ? 1 : 0);
936 page_no = simple_strtoul(g, &g, 0);
937 if (!zero_ok && !page_no) {
938 NS_ERR("invalid gravepagess.\n");
939 return -EINVAL;
940 }
941 max_reads = 3;
942 if (*g == ':') {
943 g += 1;
944 max_reads = simple_strtoul(g, &g, 0);
945 }
946 if (*g == ',')
947 g += 1;
948 gp = kzalloc(sizeof(*gp), GFP_KERNEL);
949 if (!gp) {
950 NS_ERR("unable to allocate memory.\n");
951 return -ENOMEM;
952 }
953 gp->page_no = page_no;
954 gp->max_reads = max_reads;
955 list_add(&gp->list, &grave_pages);
956 } while (*g);
957 return 0;
958 }
959
960 static int read_error(unsigned int page_no)
961 {
962 struct grave_page *gp;
963
964 list_for_each_entry(gp, &grave_pages, list)
965 if (gp->page_no == page_no) {
966 if (gp->reads_done >= gp->max_reads)
967 return 1;
968 gp->reads_done += 1;
969 return 0;
970 }
971 return 0;
972 }
973
974 static void free_lists(void)
975 {
976 struct list_head *pos, *n;
977 list_for_each_safe(pos, n, &weak_blocks) {
978 list_del(pos);
979 kfree(list_entry(pos, struct weak_block, list));
980 }
981 list_for_each_safe(pos, n, &weak_pages) {
982 list_del(pos);
983 kfree(list_entry(pos, struct weak_page, list));
984 }
985 list_for_each_safe(pos, n, &grave_pages) {
986 list_del(pos);
987 kfree(list_entry(pos, struct grave_page, list));
988 }
989 kfree(erase_block_wear);
990 }
991
992 static int setup_wear_reporting(struct mtd_info *mtd)
993 {
994 size_t mem;
995
996 wear_eb_count = div_u64(mtd->size, mtd->erasesize);
997 mem = wear_eb_count * sizeof(unsigned long);
998 if (mem / sizeof(unsigned long) != wear_eb_count) {
999 NS_ERR("Too many erase blocks for wear reporting\n");
1000 return -ENOMEM;
1001 }
1002 erase_block_wear = kzalloc(mem, GFP_KERNEL);
1003 if (!erase_block_wear) {
1004 NS_ERR("Too many erase blocks for wear reporting\n");
1005 return -ENOMEM;
1006 }
1007 return 0;
1008 }
1009
1010 static void update_wear(unsigned int erase_block_no)
1011 {
1012 if (!erase_block_wear)
1013 return;
1014 total_wear += 1;
1015 /*
1016 * TODO: Notify this through a debugfs entry,
1017 * instead of showing an error message.
1018 */
1019 if (total_wear == 0)
1020 NS_ERR("Erase counter total overflow\n");
1021 erase_block_wear[erase_block_no] += 1;
1022 if (erase_block_wear[erase_block_no] == 0)
1023 NS_ERR("Erase counter overflow for erase block %u\n", erase_block_no);
1024 }
1025
1026 /*
1027 * Returns the string representation of 'state' state.
1028 */
1029 static char *get_state_name(uint32_t state)
1030 {
1031 switch (NS_STATE(state)) {
1032 case STATE_CMD_READ0:
1033 return "STATE_CMD_READ0";
1034 case STATE_CMD_READ1:
1035 return "STATE_CMD_READ1";
1036 case STATE_CMD_PAGEPROG:
1037 return "STATE_CMD_PAGEPROG";
1038 case STATE_CMD_READOOB:
1039 return "STATE_CMD_READOOB";
1040 case STATE_CMD_READSTART:
1041 return "STATE_CMD_READSTART";
1042 case STATE_CMD_ERASE1:
1043 return "STATE_CMD_ERASE1";
1044 case STATE_CMD_STATUS:
1045 return "STATE_CMD_STATUS";
1046 case STATE_CMD_SEQIN:
1047 return "STATE_CMD_SEQIN";
1048 case STATE_CMD_READID:
1049 return "STATE_CMD_READID";
1050 case STATE_CMD_ERASE2:
1051 return "STATE_CMD_ERASE2";
1052 case STATE_CMD_RESET:
1053 return "STATE_CMD_RESET";
1054 case STATE_CMD_RNDOUT:
1055 return "STATE_CMD_RNDOUT";
1056 case STATE_CMD_RNDOUTSTART:
1057 return "STATE_CMD_RNDOUTSTART";
1058 case STATE_ADDR_PAGE:
1059 return "STATE_ADDR_PAGE";
1060 case STATE_ADDR_SEC:
1061 return "STATE_ADDR_SEC";
1062 case STATE_ADDR_ZERO:
1063 return "STATE_ADDR_ZERO";
1064 case STATE_ADDR_COLUMN:
1065 return "STATE_ADDR_COLUMN";
1066 case STATE_DATAIN:
1067 return "STATE_DATAIN";
1068 case STATE_DATAOUT:
1069 return "STATE_DATAOUT";
1070 case STATE_DATAOUT_ID:
1071 return "STATE_DATAOUT_ID";
1072 case STATE_DATAOUT_STATUS:
1073 return "STATE_DATAOUT_STATUS";
1074 case STATE_READY:
1075 return "STATE_READY";
1076 case STATE_UNKNOWN:
1077 return "STATE_UNKNOWN";
1078 }
1079
1080 NS_ERR("get_state_name: unknown state, BUG\n");
1081 return NULL;
1082 }
1083
1084 /*
1085 * Check if command is valid.
1086 *
1087 * RETURNS: 1 if wrong command, 0 if right.
1088 */
1089 static int check_command(int cmd)
1090 {
1091 switch (cmd) {
1092
1093 case NAND_CMD_READ0:
1094 case NAND_CMD_READ1:
1095 case NAND_CMD_READSTART:
1096 case NAND_CMD_PAGEPROG:
1097 case NAND_CMD_READOOB:
1098 case NAND_CMD_ERASE1:
1099 case NAND_CMD_STATUS:
1100 case NAND_CMD_SEQIN:
1101 case NAND_CMD_READID:
1102 case NAND_CMD_ERASE2:
1103 case NAND_CMD_RESET:
1104 case NAND_CMD_RNDOUT:
1105 case NAND_CMD_RNDOUTSTART:
1106 return 0;
1107
1108 default:
1109 return 1;
1110 }
1111 }
1112
1113 /*
1114 * Returns state after command is accepted by command number.
1115 */
1116 static uint32_t get_state_by_command(unsigned command)
1117 {
1118 switch (command) {
1119 case NAND_CMD_READ0:
1120 return STATE_CMD_READ0;
1121 case NAND_CMD_READ1:
1122 return STATE_CMD_READ1;
1123 case NAND_CMD_PAGEPROG:
1124 return STATE_CMD_PAGEPROG;
1125 case NAND_CMD_READSTART:
1126 return STATE_CMD_READSTART;
1127 case NAND_CMD_READOOB:
1128 return STATE_CMD_READOOB;
1129 case NAND_CMD_ERASE1:
1130 return STATE_CMD_ERASE1;
1131 case NAND_CMD_STATUS:
1132 return STATE_CMD_STATUS;
1133 case NAND_CMD_SEQIN:
1134 return STATE_CMD_SEQIN;
1135 case NAND_CMD_READID:
1136 return STATE_CMD_READID;
1137 case NAND_CMD_ERASE2:
1138 return STATE_CMD_ERASE2;
1139 case NAND_CMD_RESET:
1140 return STATE_CMD_RESET;
1141 case NAND_CMD_RNDOUT:
1142 return STATE_CMD_RNDOUT;
1143 case NAND_CMD_RNDOUTSTART:
1144 return STATE_CMD_RNDOUTSTART;
1145 }
1146
1147 NS_ERR("get_state_by_command: unknown command, BUG\n");
1148 return 0;
1149 }
1150
1151 /*
1152 * Move an address byte to the correspondent internal register.
1153 */
1154 static inline void accept_addr_byte(struct nandsim *ns, u_char bt)
1155 {
1156 uint byte = (uint)bt;
1157
1158 if (ns->regs.count < (ns->geom.pgaddrbytes - ns->geom.secaddrbytes))
1159 ns->regs.column |= (byte << 8 * ns->regs.count);
1160 else {
1161 ns->regs.row |= (byte << 8 * (ns->regs.count -
1162 ns->geom.pgaddrbytes +
1163 ns->geom.secaddrbytes));
1164 }
1165
1166 return;
1167 }
1168
1169 /*
1170 * Switch to STATE_READY state.
1171 */
1172 static inline void switch_to_ready_state(struct nandsim *ns, u_char status)
1173 {
1174 NS_DBG("switch_to_ready_state: switch to %s state\n", get_state_name(STATE_READY));
1175
1176 ns->state = STATE_READY;
1177 ns->nxstate = STATE_UNKNOWN;
1178 ns->op = NULL;
1179 ns->npstates = 0;
1180 ns->stateidx = 0;
1181 ns->regs.num = 0;
1182 ns->regs.count = 0;
1183 ns->regs.off = 0;
1184 ns->regs.row = 0;
1185 ns->regs.column = 0;
1186 ns->regs.status = status;
1187 }
1188
1189 /*
1190 * If the operation isn't known yet, try to find it in the global array
1191 * of supported operations.
1192 *
1193 * Operation can be unknown because of the following.
1194 * 1. New command was accepted and this is the first call to find the
1195 * correspondent states chain. In this case ns->npstates = 0;
1196 * 2. There are several operations which begin with the same command(s)
1197 * (for example program from the second half and read from the
1198 * second half operations both begin with the READ1 command). In this
1199 * case the ns->pstates[] array contains previous states.
1200 *
1201 * Thus, the function tries to find operation containing the following
1202 * states (if the 'flag' parameter is 0):
1203 * ns->pstates[0], ... ns->pstates[ns->npstates], ns->state
1204 *
1205 * If (one and only one) matching operation is found, it is accepted (
1206 * ns->ops, ns->state, ns->nxstate are initialized, ns->npstate is
1207 * zeroed).
1208 *
1209 * If there are several matches, the current state is pushed to the
1210 * ns->pstates.
1211 *
1212 * The operation can be unknown only while commands are input to the chip.
1213 * As soon as address command is accepted, the operation must be known.
1214 * In such situation the function is called with 'flag' != 0, and the
1215 * operation is searched using the following pattern:
1216 * ns->pstates[0], ... ns->pstates[ns->npstates], <address input>
1217 *
1218 * It is supposed that this pattern must either match one operation or
1219 * none. There can't be ambiguity in that case.
1220 *
1221 * If no matches found, the function does the following:
1222 * 1. if there are saved states present, try to ignore them and search
1223 * again only using the last command. If nothing was found, switch
1224 * to the STATE_READY state.
1225 * 2. if there are no saved states, switch to the STATE_READY state.
1226 *
1227 * RETURNS: -2 - no matched operations found.
1228 * -1 - several matches.
1229 * 0 - operation is found.
1230 */
1231 static int find_operation(struct nandsim *ns, uint32_t flag)
1232 {
1233 int opsfound = 0;
1234 int i, j, idx = 0;
1235
1236 for (i = 0; i < NS_OPER_NUM; i++) {
1237
1238 int found = 1;
1239
1240 if (!(ns->options & ops[i].reqopts))
1241 /* Ignore operations we can't perform */
1242 continue;
1243
1244 if (flag) {
1245 if (!(ops[i].states[ns->npstates] & STATE_ADDR_MASK))
1246 continue;
1247 } else {
1248 if (NS_STATE(ns->state) != NS_STATE(ops[i].states[ns->npstates]))
1249 continue;
1250 }
1251
1252 for (j = 0; j < ns->npstates; j++)
1253 if (NS_STATE(ops[i].states[j]) != NS_STATE(ns->pstates[j])
1254 && (ns->options & ops[idx].reqopts)) {
1255 found = 0;
1256 break;
1257 }
1258
1259 if (found) {
1260 idx = i;
1261 opsfound += 1;
1262 }
1263 }
1264
1265 if (opsfound == 1) {
1266 /* Exact match */
1267 ns->op = &ops[idx].states[0];
1268 if (flag) {
1269 /*
1270 * In this case the find_operation function was
1271 * called when address has just began input. But it isn't
1272 * yet fully input and the current state must
1273 * not be one of STATE_ADDR_*, but the STATE_ADDR_*
1274 * state must be the next state (ns->nxstate).
1275 */
1276 ns->stateidx = ns->npstates - 1;
1277 } else {
1278 ns->stateidx = ns->npstates;
1279 }
1280 ns->npstates = 0;
1281 ns->state = ns->op[ns->stateidx];
1282 ns->nxstate = ns->op[ns->stateidx + 1];
1283 NS_DBG("find_operation: operation found, index: %d, state: %s, nxstate %s\n",
1284 idx, get_state_name(ns->state), get_state_name(ns->nxstate));
1285 return 0;
1286 }
1287
1288 if (opsfound == 0) {
1289 /* Nothing was found. Try to ignore previous commands (if any) and search again */
1290 if (ns->npstates != 0) {
1291 NS_DBG("find_operation: no operation found, try again with state %s\n",
1292 get_state_name(ns->state));
1293 ns->npstates = 0;
1294 return find_operation(ns, 0);
1295
1296 }
1297 NS_DBG("find_operation: no operations found\n");
1298 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1299 return -2;
1300 }
1301
1302 if (flag) {
1303 /* This shouldn't happen */
1304 NS_DBG("find_operation: BUG, operation must be known if address is input\n");
1305 return -2;
1306 }
1307
1308 NS_DBG("find_operation: there is still ambiguity\n");
1309
1310 ns->pstates[ns->npstates++] = ns->state;
1311
1312 return -1;
1313 }
1314
1315 static void put_pages(struct nandsim *ns)
1316 {
1317 int i;
1318
1319 for (i = 0; i < ns->held_cnt; i++)
1320 put_page(ns->held_pages[i]);
1321 }
1322
1323 /* Get page cache pages in advance to provide NOFS memory allocation */
1324 static int get_pages(struct nandsim *ns, struct file *file, size_t count, loff_t pos)
1325 {
1326 pgoff_t index, start_index, end_index;
1327 struct page *page;
1328 struct address_space *mapping = file->f_mapping;
1329
1330 start_index = pos >> PAGE_SHIFT;
1331 end_index = (pos + count - 1) >> PAGE_SHIFT;
1332 if (end_index - start_index + 1 > NS_MAX_HELD_PAGES)
1333 return -EINVAL;
1334 ns->held_cnt = 0;
1335 for (index = start_index; index <= end_index; index++) {
1336 page = find_get_page(mapping, index);
1337 if (page == NULL) {
1338 page = find_or_create_page(mapping, index, GFP_NOFS);
1339 if (page == NULL) {
1340 write_inode_now(mapping->host, 1);
1341 page = find_or_create_page(mapping, index, GFP_NOFS);
1342 }
1343 if (page == NULL) {
1344 put_pages(ns);
1345 return -ENOMEM;
1346 }
1347 unlock_page(page);
1348 }
1349 ns->held_pages[ns->held_cnt++] = page;
1350 }
1351 return 0;
1352 }
1353
1354 static ssize_t read_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t pos)
1355 {
1356 ssize_t tx;
1357 int err;
1358 unsigned int noreclaim_flag;
1359
1360 err = get_pages(ns, file, count, pos);
1361 if (err)
1362 return err;
1363 noreclaim_flag = memalloc_noreclaim_save();
1364 tx = kernel_read(file, buf, count, &pos);
1365 memalloc_noreclaim_restore(noreclaim_flag);
1366 put_pages(ns);
1367 return tx;
1368 }
1369
1370 static ssize_t write_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t pos)
1371 {
1372 ssize_t tx;
1373 int err;
1374 unsigned int noreclaim_flag;
1375
1376 err = get_pages(ns, file, count, pos);
1377 if (err)
1378 return err;
1379 noreclaim_flag = memalloc_noreclaim_save();
1380 tx = kernel_write(file, buf, count, &pos);
1381 memalloc_noreclaim_restore(noreclaim_flag);
1382 put_pages(ns);
1383 return tx;
1384 }
1385
1386 /*
1387 * Returns a pointer to the current page.
1388 */
1389 static inline union ns_mem *NS_GET_PAGE(struct nandsim *ns)
1390 {
1391 return &(ns->pages[ns->regs.row]);
1392 }
1393
1394 /*
1395 * Retuns a pointer to the current byte, within the current page.
1396 */
1397 static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns)
1398 {
1399 return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off;
1400 }
1401
1402 static int do_read_error(struct nandsim *ns, int num)
1403 {
1404 unsigned int page_no = ns->regs.row;
1405
1406 if (read_error(page_no)) {
1407 prandom_bytes(ns->buf.byte, num);
1408 NS_WARN("simulating read error in page %u\n", page_no);
1409 return 1;
1410 }
1411 return 0;
1412 }
1413
1414 static void do_bit_flips(struct nandsim *ns, int num)
1415 {
1416 if (bitflips && prandom_u32() < (1 << 22)) {
1417 int flips = 1;
1418 if (bitflips > 1)
1419 flips = (prandom_u32() % (int) bitflips) + 1;
1420 while (flips--) {
1421 int pos = prandom_u32() % (num * 8);
1422 ns->buf.byte[pos / 8] ^= (1 << (pos % 8));
1423 NS_WARN("read_page: flipping bit %d in page %d "
1424 "reading from %d ecc: corrected=%u failed=%u\n",
1425 pos, ns->regs.row, ns->regs.column + ns->regs.off,
1426 nsmtd->ecc_stats.corrected, nsmtd->ecc_stats.failed);
1427 }
1428 }
1429 }
1430
1431 /*
1432 * Fill the NAND buffer with data read from the specified page.
1433 */
1434 static void read_page(struct nandsim *ns, int num)
1435 {
1436 union ns_mem *mypage;
1437
1438 if (ns->cfile) {
1439 if (!test_bit(ns->regs.row, ns->pages_written)) {
1440 NS_DBG("read_page: page %d not written\n", ns->regs.row);
1441 memset(ns->buf.byte, 0xFF, num);
1442 } else {
1443 loff_t pos;
1444 ssize_t tx;
1445
1446 NS_DBG("read_page: page %d written, reading from %d\n",
1447 ns->regs.row, ns->regs.column + ns->regs.off);
1448 if (do_read_error(ns, num))
1449 return;
1450 pos = (loff_t)NS_RAW_OFFSET(ns) + ns->regs.off;
1451 tx = read_file(ns, ns->cfile, ns->buf.byte, num, pos);
1452 if (tx != num) {
1453 NS_ERR("read_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1454 return;
1455 }
1456 do_bit_flips(ns, num);
1457 }
1458 return;
1459 }
1460
1461 mypage = NS_GET_PAGE(ns);
1462 if (mypage->byte == NULL) {
1463 NS_DBG("read_page: page %d not allocated\n", ns->regs.row);
1464 memset(ns->buf.byte, 0xFF, num);
1465 } else {
1466 NS_DBG("read_page: page %d allocated, reading from %d\n",
1467 ns->regs.row, ns->regs.column + ns->regs.off);
1468 if (do_read_error(ns, num))
1469 return;
1470 memcpy(ns->buf.byte, NS_PAGE_BYTE_OFF(ns), num);
1471 do_bit_flips(ns, num);
1472 }
1473 }
1474
1475 /*
1476 * Erase all pages in the specified sector.
1477 */
1478 static void erase_sector(struct nandsim *ns)
1479 {
1480 union ns_mem *mypage;
1481 int i;
1482
1483 if (ns->cfile) {
1484 for (i = 0; i < ns->geom.pgsec; i++)
1485 if (__test_and_clear_bit(ns->regs.row + i,
1486 ns->pages_written)) {
1487 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row + i);
1488 }
1489 return;
1490 }
1491
1492 mypage = NS_GET_PAGE(ns);
1493 for (i = 0; i < ns->geom.pgsec; i++) {
1494 if (mypage->byte != NULL) {
1495 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row+i);
1496 kmem_cache_free(ns->nand_pages_slab, mypage->byte);
1497 mypage->byte = NULL;
1498 }
1499 mypage++;
1500 }
1501 }
1502
1503 /*
1504 * Program the specified page with the contents from the NAND buffer.
1505 */
1506 static int prog_page(struct nandsim *ns, int num)
1507 {
1508 int i;
1509 union ns_mem *mypage;
1510 u_char *pg_off;
1511
1512 if (ns->cfile) {
1513 loff_t off;
1514 ssize_t tx;
1515 int all;
1516
1517 NS_DBG("prog_page: writing page %d\n", ns->regs.row);
1518 pg_off = ns->file_buf + ns->regs.column + ns->regs.off;
1519 off = (loff_t)NS_RAW_OFFSET(ns) + ns->regs.off;
1520 if (!test_bit(ns->regs.row, ns->pages_written)) {
1521 all = 1;
1522 memset(ns->file_buf, 0xff, ns->geom.pgszoob);
1523 } else {
1524 all = 0;
1525 tx = read_file(ns, ns->cfile, pg_off, num, off);
1526 if (tx != num) {
1527 NS_ERR("prog_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1528 return -1;
1529 }
1530 }
1531 for (i = 0; i < num; i++)
1532 pg_off[i] &= ns->buf.byte[i];
1533 if (all) {
1534 loff_t pos = (loff_t)ns->regs.row * ns->geom.pgszoob;
1535 tx = write_file(ns, ns->cfile, ns->file_buf, ns->geom.pgszoob, pos);
1536 if (tx != ns->geom.pgszoob) {
1537 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1538 return -1;
1539 }
1540 __set_bit(ns->regs.row, ns->pages_written);
1541 } else {
1542 tx = write_file(ns, ns->cfile, pg_off, num, off);
1543 if (tx != num) {
1544 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1545 return -1;
1546 }
1547 }
1548 return 0;
1549 }
1550
1551 mypage = NS_GET_PAGE(ns);
1552 if (mypage->byte == NULL) {
1553 NS_DBG("prog_page: allocating page %d\n", ns->regs.row);
1554 /*
1555 * We allocate memory with GFP_NOFS because a flash FS may
1556 * utilize this. If it is holding an FS lock, then gets here,
1557 * then kernel memory alloc runs writeback which goes to the FS
1558 * again and deadlocks. This was seen in practice.
1559 */
1560 mypage->byte = kmem_cache_alloc(ns->nand_pages_slab, GFP_NOFS);
1561 if (mypage->byte == NULL) {
1562 NS_ERR("prog_page: error allocating memory for page %d\n", ns->regs.row);
1563 return -1;
1564 }
1565 memset(mypage->byte, 0xFF, ns->geom.pgszoob);
1566 }
1567
1568 pg_off = NS_PAGE_BYTE_OFF(ns);
1569 for (i = 0; i < num; i++)
1570 pg_off[i] &= ns->buf.byte[i];
1571
1572 return 0;
1573 }
1574
1575 /*
1576 * If state has any action bit, perform this action.
1577 *
1578 * RETURNS: 0 if success, -1 if error.
1579 */
1580 static int do_state_action(struct nandsim *ns, uint32_t action)
1581 {
1582 int num;
1583 int busdiv = ns->busw == 8 ? 1 : 2;
1584 unsigned int erase_block_no, page_no;
1585
1586 action &= ACTION_MASK;
1587
1588 /* Check that page address input is correct */
1589 if (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) {
1590 NS_WARN("do_state_action: wrong page number (%#x)\n", ns->regs.row);
1591 return -1;
1592 }
1593
1594 switch (action) {
1595
1596 case ACTION_CPY:
1597 /*
1598 * Copy page data to the internal buffer.
1599 */
1600
1601 /* Column shouldn't be very large */
1602 if (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) {
1603 NS_ERR("do_state_action: column number is too large\n");
1604 break;
1605 }
1606 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1607 read_page(ns, num);
1608
1609 NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n",
1610 num, NS_RAW_OFFSET(ns) + ns->regs.off);
1611
1612 if (ns->regs.off == 0)
1613 NS_LOG("read page %d\n", ns->regs.row);
1614 else if (ns->regs.off < ns->geom.pgsz)
1615 NS_LOG("read page %d (second half)\n", ns->regs.row);
1616 else
1617 NS_LOG("read OOB of page %d\n", ns->regs.row);
1618
1619 NS_UDELAY(access_delay);
1620 NS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv);
1621
1622 break;
1623
1624 case ACTION_SECERASE:
1625 /*
1626 * Erase sector.
1627 */
1628
1629 if (ns->lines.wp) {
1630 NS_ERR("do_state_action: device is write-protected, ignore sector erase\n");
1631 return -1;
1632 }
1633
1634 if (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec
1635 || (ns->regs.row & ~(ns->geom.secsz - 1))) {
1636 NS_ERR("do_state_action: wrong sector address (%#x)\n", ns->regs.row);
1637 return -1;
1638 }
1639
1640 ns->regs.row = (ns->regs.row <<
1641 8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column;
1642 ns->regs.column = 0;
1643
1644 erase_block_no = ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift);
1645
1646 NS_DBG("do_state_action: erase sector at address %#x, off = %d\n",
1647 ns->regs.row, NS_RAW_OFFSET(ns));
1648 NS_LOG("erase sector %u\n", erase_block_no);
1649
1650 erase_sector(ns);
1651
1652 NS_MDELAY(erase_delay);
1653
1654 if (erase_block_wear)
1655 update_wear(erase_block_no);
1656
1657 if (erase_error(erase_block_no)) {
1658 NS_WARN("simulating erase failure in erase block %u\n", erase_block_no);
1659 return -1;
1660 }
1661
1662 break;
1663
1664 case ACTION_PRGPAGE:
1665 /*
1666 * Program page - move internal buffer data to the page.
1667 */
1668
1669 if (ns->lines.wp) {
1670 NS_WARN("do_state_action: device is write-protected, programm\n");
1671 return -1;
1672 }
1673
1674 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1675 if (num != ns->regs.count) {
1676 NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n",
1677 ns->regs.count, num);
1678 return -1;
1679 }
1680
1681 if (prog_page(ns, num) == -1)
1682 return -1;
1683
1684 page_no = ns->regs.row;
1685
1686 NS_DBG("do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\n",
1687 num, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off);
1688 NS_LOG("programm page %d\n", ns->regs.row);
1689
1690 NS_UDELAY(programm_delay);
1691 NS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv);
1692
1693 if (write_error(page_no)) {
1694 NS_WARN("simulating write failure in page %u\n", page_no);
1695 return -1;
1696 }
1697
1698 break;
1699
1700 case ACTION_ZEROOFF:
1701 NS_DBG("do_state_action: set internal offset to 0\n");
1702 ns->regs.off = 0;
1703 break;
1704
1705 case ACTION_HALFOFF:
1706 if (!(ns->options & OPT_PAGE512_8BIT)) {
1707 NS_ERR("do_state_action: BUG! can't skip half of page for non-512"
1708 "byte page size 8x chips\n");
1709 return -1;
1710 }
1711 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz/2);
1712 ns->regs.off = ns->geom.pgsz/2;
1713 break;
1714
1715 case ACTION_OOBOFF:
1716 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz);
1717 ns->regs.off = ns->geom.pgsz;
1718 break;
1719
1720 default:
1721 NS_DBG("do_state_action: BUG! unknown action\n");
1722 }
1723
1724 return 0;
1725 }
1726
1727 /*
1728 * Switch simulator's state.
1729 */
1730 static void switch_state(struct nandsim *ns)
1731 {
1732 if (ns->op) {
1733 /*
1734 * The current operation have already been identified.
1735 * Just follow the states chain.
1736 */
1737
1738 ns->stateidx += 1;
1739 ns->state = ns->nxstate;
1740 ns->nxstate = ns->op[ns->stateidx + 1];
1741
1742 NS_DBG("switch_state: operation is known, switch to the next state, "
1743 "state: %s, nxstate: %s\n",
1744 get_state_name(ns->state), get_state_name(ns->nxstate));
1745
1746 /* See, whether we need to do some action */
1747 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1748 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1749 return;
1750 }
1751
1752 } else {
1753 /*
1754 * We don't yet know which operation we perform.
1755 * Try to identify it.
1756 */
1757
1758 /*
1759 * The only event causing the switch_state function to
1760 * be called with yet unknown operation is new command.
1761 */
1762 ns->state = get_state_by_command(ns->regs.command);
1763
1764 NS_DBG("switch_state: operation is unknown, try to find it\n");
1765
1766 if (find_operation(ns, 0) != 0)
1767 return;
1768
1769 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1770 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1771 return;
1772 }
1773 }
1774
1775 /* For 16x devices column means the page offset in words */
1776 if ((ns->nxstate & STATE_ADDR_MASK) && ns->busw == 16) {
1777 NS_DBG("switch_state: double the column number for 16x device\n");
1778 ns->regs.column <<= 1;
1779 }
1780
1781 if (NS_STATE(ns->nxstate) == STATE_READY) {
1782 /*
1783 * The current state is the last. Return to STATE_READY
1784 */
1785
1786 u_char status = NS_STATUS_OK(ns);
1787
1788 /* In case of data states, see if all bytes were input/output */
1789 if ((ns->state & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK))
1790 && ns->regs.count != ns->regs.num) {
1791 NS_WARN("switch_state: not all bytes were processed, %d left\n",
1792 ns->regs.num - ns->regs.count);
1793 status = NS_STATUS_FAILED(ns);
1794 }
1795
1796 NS_DBG("switch_state: operation complete, switch to STATE_READY state\n");
1797
1798 switch_to_ready_state(ns, status);
1799
1800 return;
1801 } else if (ns->nxstate & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) {
1802 /*
1803 * If the next state is data input/output, switch to it now
1804 */
1805
1806 ns->state = ns->nxstate;
1807 ns->nxstate = ns->op[++ns->stateidx + 1];
1808 ns->regs.num = ns->regs.count = 0;
1809
1810 NS_DBG("switch_state: the next state is data I/O, switch, "
1811 "state: %s, nxstate: %s\n",
1812 get_state_name(ns->state), get_state_name(ns->nxstate));
1813
1814 /*
1815 * Set the internal register to the count of bytes which
1816 * are expected to be input or output
1817 */
1818 switch (NS_STATE(ns->state)) {
1819 case STATE_DATAIN:
1820 case STATE_DATAOUT:
1821 ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1822 break;
1823
1824 case STATE_DATAOUT_ID:
1825 ns->regs.num = ns->geom.idbytes;
1826 break;
1827
1828 case STATE_DATAOUT_STATUS:
1829 ns->regs.count = ns->regs.num = 0;
1830 break;
1831
1832 default:
1833 NS_ERR("switch_state: BUG! unknown data state\n");
1834 }
1835
1836 } else if (ns->nxstate & STATE_ADDR_MASK) {
1837 /*
1838 * If the next state is address input, set the internal
1839 * register to the number of expected address bytes
1840 */
1841
1842 ns->regs.count = 0;
1843
1844 switch (NS_STATE(ns->nxstate)) {
1845 case STATE_ADDR_PAGE:
1846 ns->regs.num = ns->geom.pgaddrbytes;
1847
1848 break;
1849 case STATE_ADDR_SEC:
1850 ns->regs.num = ns->geom.secaddrbytes;
1851 break;
1852
1853 case STATE_ADDR_ZERO:
1854 ns->regs.num = 1;
1855 break;
1856
1857 case STATE_ADDR_COLUMN:
1858 /* Column address is always 2 bytes */
1859 ns->regs.num = ns->geom.pgaddrbytes - ns->geom.secaddrbytes;
1860 break;
1861
1862 default:
1863 NS_ERR("switch_state: BUG! unknown address state\n");
1864 }
1865 } else {
1866 /*
1867 * Just reset internal counters.
1868 */
1869
1870 ns->regs.num = 0;
1871 ns->regs.count = 0;
1872 }
1873 }
1874
1875 static u_char ns_nand_read_byte(struct mtd_info *mtd)
1876 {
1877 struct nand_chip *chip = mtd_to_nand(mtd);
1878 struct nandsim *ns = nand_get_controller_data(chip);
1879 u_char outb = 0x00;
1880
1881 /* Sanity and correctness checks */
1882 if (!ns->lines.ce) {
1883 NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb);
1884 return outb;
1885 }
1886 if (ns->lines.ale || ns->lines.cle) {
1887 NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb);
1888 return outb;
1889 }
1890 if (!(ns->state & STATE_DATAOUT_MASK)) {
1891 NS_WARN("read_byte: unexpected data output cycle, state is %s "
1892 "return %#x\n", get_state_name(ns->state), (uint)outb);
1893 return outb;
1894 }
1895
1896 /* Status register may be read as many times as it is wanted */
1897 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS) {
1898 NS_DBG("read_byte: return %#x status\n", ns->regs.status);
1899 return ns->regs.status;
1900 }
1901
1902 /* Check if there is any data in the internal buffer which may be read */
1903 if (ns->regs.count == ns->regs.num) {
1904 NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb);
1905 return outb;
1906 }
1907
1908 switch (NS_STATE(ns->state)) {
1909 case STATE_DATAOUT:
1910 if (ns->busw == 8) {
1911 outb = ns->buf.byte[ns->regs.count];
1912 ns->regs.count += 1;
1913 } else {
1914 outb = (u_char)cpu_to_le16(ns->buf.word[ns->regs.count >> 1]);
1915 ns->regs.count += 2;
1916 }
1917 break;
1918 case STATE_DATAOUT_ID:
1919 NS_DBG("read_byte: read ID byte %d, total = %d\n", ns->regs.count, ns->regs.num);
1920 outb = ns->ids[ns->regs.count];
1921 ns->regs.count += 1;
1922 break;
1923 default:
1924 BUG();
1925 }
1926
1927 if (ns->regs.count == ns->regs.num) {
1928 NS_DBG("read_byte: all bytes were read\n");
1929
1930 if (NS_STATE(ns->nxstate) == STATE_READY)
1931 switch_state(ns);
1932 }
1933
1934 return outb;
1935 }
1936
1937 static void ns_nand_write_byte(struct mtd_info *mtd, u_char byte)
1938 {
1939 struct nand_chip *chip = mtd_to_nand(mtd);
1940 struct nandsim *ns = nand_get_controller_data(chip);
1941
1942 /* Sanity and correctness checks */
1943 if (!ns->lines.ce) {
1944 NS_ERR("write_byte: chip is disabled, ignore write\n");
1945 return;
1946 }
1947 if (ns->lines.ale && ns->lines.cle) {
1948 NS_ERR("write_byte: ALE and CLE pins are high simultaneously, ignore write\n");
1949 return;
1950 }
1951
1952 if (ns->lines.cle == 1) {
1953 /*
1954 * The byte written is a command.
1955 */
1956
1957 if (byte == NAND_CMD_RESET) {
1958 NS_LOG("reset chip\n");
1959 switch_to_ready_state(ns, NS_STATUS_OK(ns));
1960 return;
1961 }
1962
1963 /* Check that the command byte is correct */
1964 if (check_command(byte)) {
1965 NS_ERR("write_byte: unknown command %#x\n", (uint)byte);
1966 return;
1967 }
1968
1969 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS
1970 || NS_STATE(ns->state) == STATE_DATAOUT) {
1971 int row = ns->regs.row;
1972
1973 switch_state(ns);
1974 if (byte == NAND_CMD_RNDOUT)
1975 ns->regs.row = row;
1976 }
1977
1978 /* Check if chip is expecting command */
1979 if (NS_STATE(ns->nxstate) != STATE_UNKNOWN && !(ns->nxstate & STATE_CMD_MASK)) {
1980 /* Do not warn if only 2 id bytes are read */
1981 if (!(ns->regs.command == NAND_CMD_READID &&
1982 NS_STATE(ns->state) == STATE_DATAOUT_ID && ns->regs.count == 2)) {
1983 /*
1984 * We are in situation when something else (not command)
1985 * was expected but command was input. In this case ignore
1986 * previous command(s)/state(s) and accept the last one.
1987 */
1988 NS_WARN("write_byte: command (%#x) wasn't expected, expected state is %s, "
1989 "ignore previous states\n", (uint)byte, get_state_name(ns->nxstate));
1990 }
1991 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1992 }
1993
1994 NS_DBG("command byte corresponding to %s state accepted\n",
1995 get_state_name(get_state_by_command(byte)));
1996 ns->regs.command = byte;
1997 switch_state(ns);
1998
1999 } else if (ns->lines.ale == 1) {
2000 /*
2001 * The byte written is an address.
2002 */
2003
2004 if (NS_STATE(ns->nxstate) == STATE_UNKNOWN) {
2005
2006 NS_DBG("write_byte: operation isn't known yet, identify it\n");
2007
2008 if (find_operation(ns, 1) < 0)
2009 return;
2010
2011 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
2012 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2013 return;
2014 }
2015
2016 ns->regs.count = 0;
2017 switch (NS_STATE(ns->nxstate)) {
2018 case STATE_ADDR_PAGE:
2019 ns->regs.num = ns->geom.pgaddrbytes;
2020 break;
2021 case STATE_ADDR_SEC:
2022 ns->regs.num = ns->geom.secaddrbytes;
2023 break;
2024 case STATE_ADDR_ZERO:
2025 ns->regs.num = 1;
2026 break;
2027 default:
2028 BUG();
2029 }
2030 }
2031
2032 /* Check that chip is expecting address */
2033 if (!(ns->nxstate & STATE_ADDR_MASK)) {
2034 NS_ERR("write_byte: address (%#x) isn't expected, expected state is %s, "
2035 "switch to STATE_READY\n", (uint)byte, get_state_name(ns->nxstate));
2036 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2037 return;
2038 }
2039
2040 /* Check if this is expected byte */
2041 if (ns->regs.count == ns->regs.num) {
2042 NS_ERR("write_byte: no more address bytes expected\n");
2043 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2044 return;
2045 }
2046
2047 accept_addr_byte(ns, byte);
2048
2049 ns->regs.count += 1;
2050
2051 NS_DBG("write_byte: address byte %#x was accepted (%d bytes input, %d expected)\n",
2052 (uint)byte, ns->regs.count, ns->regs.num);
2053
2054 if (ns->regs.count == ns->regs.num) {
2055 NS_DBG("address (%#x, %#x) is accepted\n", ns->regs.row, ns->regs.column);
2056 switch_state(ns);
2057 }
2058
2059 } else {
2060 /*
2061 * The byte written is an input data.
2062 */
2063
2064 /* Check that chip is expecting data input */
2065 if (!(ns->state & STATE_DATAIN_MASK)) {
2066 NS_ERR("write_byte: data input (%#x) isn't expected, state is %s, "
2067 "switch to %s\n", (uint)byte,
2068 get_state_name(ns->state), get_state_name(STATE_READY));
2069 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2070 return;
2071 }
2072
2073 /* Check if this is expected byte */
2074 if (ns->regs.count == ns->regs.num) {
2075 NS_WARN("write_byte: %u input bytes has already been accepted, ignore write\n",
2076 ns->regs.num);
2077 return;
2078 }
2079
2080 if (ns->busw == 8) {
2081 ns->buf.byte[ns->regs.count] = byte;
2082 ns->regs.count += 1;
2083 } else {
2084 ns->buf.word[ns->regs.count >> 1] = cpu_to_le16((uint16_t)byte);
2085 ns->regs.count += 2;
2086 }
2087 }
2088
2089 return;
2090 }
2091
2092 static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask)
2093 {
2094 struct nand_chip *chip = mtd_to_nand(mtd);
2095 struct nandsim *ns = nand_get_controller_data(chip);
2096
2097 ns->lines.cle = bitmask & NAND_CLE ? 1 : 0;
2098 ns->lines.ale = bitmask & NAND_ALE ? 1 : 0;
2099 ns->lines.ce = bitmask & NAND_NCE ? 1 : 0;
2100
2101 if (cmd != NAND_CMD_NONE)
2102 ns_nand_write_byte(mtd, cmd);
2103 }
2104
2105 static int ns_device_ready(struct mtd_info *mtd)
2106 {
2107 NS_DBG("device_ready\n");
2108 return 1;
2109 }
2110
2111 static uint16_t ns_nand_read_word(struct mtd_info *mtd)
2112 {
2113 struct nand_chip *chip = mtd_to_nand(mtd);
2114
2115 NS_DBG("read_word\n");
2116
2117 return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8);
2118 }
2119
2120 static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
2121 {
2122 struct nand_chip *chip = mtd_to_nand(mtd);
2123 struct nandsim *ns = nand_get_controller_data(chip);
2124
2125 /* Check that chip is expecting data input */
2126 if (!(ns->state & STATE_DATAIN_MASK)) {
2127 NS_ERR("write_buf: data input isn't expected, state is %s, "
2128 "switch to STATE_READY\n", get_state_name(ns->state));
2129 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2130 return;
2131 }
2132
2133 /* Check if these are expected bytes */
2134 if (ns->regs.count + len > ns->regs.num) {
2135 NS_ERR("write_buf: too many input bytes\n");
2136 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2137 return;
2138 }
2139
2140 memcpy(ns->buf.byte + ns->regs.count, buf, len);
2141 ns->regs.count += len;
2142
2143 if (ns->regs.count == ns->regs.num) {
2144 NS_DBG("write_buf: %d bytes were written\n", ns->regs.count);
2145 }
2146 }
2147
2148 static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
2149 {
2150 struct nand_chip *chip = mtd_to_nand(mtd);
2151 struct nandsim *ns = nand_get_controller_data(chip);
2152
2153 /* Sanity and correctness checks */
2154 if (!ns->lines.ce) {
2155 NS_ERR("read_buf: chip is disabled\n");
2156 return;
2157 }
2158 if (ns->lines.ale || ns->lines.cle) {
2159 NS_ERR("read_buf: ALE or CLE pin is high\n");
2160 return;
2161 }
2162 if (!(ns->state & STATE_DATAOUT_MASK)) {
2163 NS_WARN("read_buf: unexpected data output cycle, current state is %s\n",
2164 get_state_name(ns->state));
2165 return;
2166 }
2167
2168 if (NS_STATE(ns->state) != STATE_DATAOUT) {
2169 int i;
2170
2171 for (i = 0; i < len; i++)
2172 buf[i] = mtd_to_nand(mtd)->read_byte(mtd);
2173
2174 return;
2175 }
2176
2177 /* Check if these are expected bytes */
2178 if (ns->regs.count + len > ns->regs.num) {
2179 NS_ERR("read_buf: too many bytes to read\n");
2180 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2181 return;
2182 }
2183
2184 memcpy(buf, ns->buf.byte + ns->regs.count, len);
2185 ns->regs.count += len;
2186
2187 if (ns->regs.count == ns->regs.num) {
2188 if (NS_STATE(ns->nxstate) == STATE_READY)
2189 switch_state(ns);
2190 }
2191
2192 return;
2193 }
2194
2195 static int ns_attach_chip(struct nand_chip *chip)
2196 {
2197 unsigned int eccsteps, eccbytes;
2198
2199 if (!bch)
2200 return 0;
2201
2202 if (!mtd_nand_has_bch()) {
2203 NS_ERR("BCH ECC support is disabled\n");
2204 return -EINVAL;
2205 }
2206
2207 /* Use 512-byte ecc blocks */
2208 eccsteps = nsmtd->writesize / 512;
2209 eccbytes = ((bch * 13) + 7) / 8;
2210
2211 /* Do not bother supporting small page devices */
2212 if (nsmtd->oobsize < 64 || !eccsteps) {
2213 NS_ERR("BCH not available on small page devices\n");
2214 return -EINVAL;
2215 }
2216
2217 if (((eccbytes * eccsteps) + 2) > nsmtd->oobsize) {
2218 NS_ERR("Invalid BCH value %u\n", bch);
2219 return -EINVAL;
2220 }
2221
2222 chip->ecc.mode = NAND_ECC_SOFT;
2223 chip->ecc.algo = NAND_ECC_BCH;
2224 chip->ecc.size = 512;
2225 chip->ecc.strength = bch;
2226 chip->ecc.bytes = eccbytes;
2227
2228 NS_INFO("Using %u-bit/%u bytes BCH ECC\n", bch, chip->ecc.size);
2229
2230 return 0;
2231 }
2232
2233 static const struct nand_controller_ops ns_controller_ops = {
2234 .attach_chip = ns_attach_chip,
2235 };
2236
2237 /*
2238 * Module initialization function
2239 */
2240 static int __init ns_init_module(void)
2241 {
2242 struct nand_chip *chip;
2243 struct nandsim *nand;
2244 int retval = -ENOMEM, i;
2245
2246 if (bus_width != 8 && bus_width != 16) {
2247 NS_ERR("wrong bus width (%d), use only 8 or 16\n", bus_width);
2248 return -EINVAL;
2249 }
2250
2251 /* Allocate and initialize mtd_info, nand_chip and nandsim structures */
2252 chip = kzalloc(sizeof(struct nand_chip) + sizeof(struct nandsim),
2253 GFP_KERNEL);
2254 if (!chip) {
2255 NS_ERR("unable to allocate core structures.\n");
2256 return -ENOMEM;
2257 }
2258 nsmtd = nand_to_mtd(chip);
2259 nand = (struct nandsim *)(chip + 1);
2260 nand_set_controller_data(chip, (void *)nand);
2261
2262 /*
2263 * Register simulator's callbacks.
2264 */
2265 chip->cmd_ctrl = ns_hwcontrol;
2266 chip->read_byte = ns_nand_read_byte;
2267 chip->dev_ready = ns_device_ready;
2268 chip->write_buf = ns_nand_write_buf;
2269 chip->read_buf = ns_nand_read_buf;
2270 chip->read_word = ns_nand_read_word;
2271 chip->ecc.mode = NAND_ECC_SOFT;
2272 chip->ecc.algo = NAND_ECC_HAMMING;
2273 /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
2274 /* and 'badblocks' parameters to work */
2275 chip->options |= NAND_SKIP_BBTSCAN;
2276
2277 switch (bbt) {
2278 case 2:
2279 chip->bbt_options |= NAND_BBT_NO_OOB;
2280 case 1:
2281 chip->bbt_options |= NAND_BBT_USE_FLASH;
2282 case 0:
2283 break;
2284 default:
2285 NS_ERR("bbt has to be 0..2\n");
2286 retval = -EINVAL;
2287 goto error;
2288 }
2289 /*
2290 * Perform minimum nandsim structure initialization to handle
2291 * the initial ID read command correctly
2292 */
2293 if (id_bytes[6] != 0xFF || id_bytes[7] != 0xFF)
2294 nand->geom.idbytes = 8;
2295 else if (id_bytes[4] != 0xFF || id_bytes[5] != 0xFF)
2296 nand->geom.idbytes = 6;
2297 else if (id_bytes[2] != 0xFF || id_bytes[3] != 0xFF)
2298 nand->geom.idbytes = 4;
2299 else
2300 nand->geom.idbytes = 2;
2301 nand->regs.status = NS_STATUS_OK(nand);
2302 nand->nxstate = STATE_UNKNOWN;
2303 nand->options |= OPT_PAGE512; /* temporary value */
2304 memcpy(nand->ids, id_bytes, sizeof(nand->ids));
2305 if (bus_width == 16) {
2306 nand->busw = 16;
2307 chip->options |= NAND_BUSWIDTH_16;
2308 }
2309
2310 nsmtd->owner = THIS_MODULE;
2311
2312 if ((retval = parse_weakblocks()) != 0)
2313 goto error;
2314
2315 if ((retval = parse_weakpages()) != 0)
2316 goto error;
2317
2318 if ((retval = parse_gravepages()) != 0)
2319 goto error;
2320
2321 chip->dummy_controller.ops = &ns_controller_ops;
2322 retval = nand_scan(chip, 1);
2323 if (retval) {
2324 NS_ERR("Could not scan NAND Simulator device\n");
2325 goto error;
2326 }
2327
2328 if (overridesize) {
2329 uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize;
2330 if (new_size >> overridesize != nsmtd->erasesize) {
2331 NS_ERR("overridesize is too big\n");
2332 retval = -EINVAL;
2333 goto err_exit;
2334 }
2335 /* N.B. This relies on nand_scan not doing anything with the size before we change it */
2336 nsmtd->size = new_size;
2337 chip->chipsize = new_size;
2338 chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1;
2339 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2340 }
2341
2342 if ((retval = setup_wear_reporting(nsmtd)) != 0)
2343 goto err_exit;
2344
2345 if ((retval = init_nandsim(nsmtd)) != 0)
2346 goto err_exit;
2347
2348 if ((retval = nand_create_bbt(chip)) != 0)
2349 goto err_exit;
2350
2351 if ((retval = parse_badblocks(nand, nsmtd)) != 0)
2352 goto err_exit;
2353
2354 /* Register NAND partitions */
2355 retval = mtd_device_register(nsmtd, &nand->partitions[0],
2356 nand->nbparts);
2357 if (retval != 0)
2358 goto err_exit;
2359
2360 if ((retval = nandsim_debugfs_create(nand)) != 0)
2361 goto err_exit;
2362
2363 return 0;
2364
2365 err_exit:
2366 free_nandsim(nand);
2367 nand_release(chip);
2368 for (i = 0;i < ARRAY_SIZE(nand->partitions); ++i)
2369 kfree(nand->partitions[i].name);
2370 error:
2371 kfree(chip);
2372 free_lists();
2373
2374 return retval;
2375 }
2376
2377 module_init(ns_init_module);
2378
2379 /*
2380 * Module clean-up function
2381 */
2382 static void __exit ns_cleanup_module(void)
2383 {
2384 struct nand_chip *chip = mtd_to_nand(nsmtd);
2385 struct nandsim *ns = nand_get_controller_data(chip);
2386 int i;
2387
2388 free_nandsim(ns); /* Free nandsim private resources */
2389 nand_release(chip); /* Unregister driver */
2390 for (i = 0;i < ARRAY_SIZE(ns->partitions); ++i)
2391 kfree(ns->partitions[i].name);
2392 kfree(mtd_to_nand(nsmtd)); /* Free other structures */
2393 free_lists();
2394 }
2395
2396 module_exit(ns_cleanup_module);
2397
2398 MODULE_LICENSE ("GPL");
2399 MODULE_AUTHOR ("Artem B. Bityuckiy");
2400 MODULE_DESCRIPTION ("The NAND flash simulator");
Linux with added FPC-III support