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Linux 4.19.133
[linux/fpc-iii.git] / drivers / mtd / spi-nor / cadence-quadspi.c
blob04cedd3a2bf6634c5d1f05ef3d27ba302d12935f
1 /*
2 * Driver for Cadence QSPI Controller
3 *
4 * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18 #include <linux/clk.h>
19 #include <linux/completion.h>
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dmaengine.h>
23 #include <linux/err.h>
24 #include <linux/errno.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/jiffies.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/mtd/spi-nor.h>
33 #include <linux/of_device.h>
34 #include <linux/of.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/sched.h>
38 #include <linux/spi/spi.h>
39 #include <linux/timer.h>
40
41 #define CQSPI_NAME "cadence-qspi"
42 #define CQSPI_MAX_CHIPSELECT 16
43
44 /* Quirks */
45 #define CQSPI_NEEDS_WR_DELAY BIT(0)
46
47 struct cqspi_st;
48
49 struct cqspi_flash_pdata {
50 struct spi_nor nor;
51 struct cqspi_st *cqspi;
52 u32 clk_rate;
53 u32 read_delay;
54 u32 tshsl_ns;
55 u32 tsd2d_ns;
56 u32 tchsh_ns;
57 u32 tslch_ns;
58 u8 inst_width;
59 u8 addr_width;
60 u8 data_width;
61 u8 cs;
62 bool registered;
63 bool use_direct_mode;
64 };
65
66 struct cqspi_st {
67 struct platform_device *pdev;
68
69 struct clk *clk;
70 unsigned int sclk;
71
72 void __iomem *iobase;
73 void __iomem *ahb_base;
74 resource_size_t ahb_size;
75 struct completion transfer_complete;
76 struct mutex bus_mutex;
77
78 struct dma_chan *rx_chan;
79 struct completion rx_dma_complete;
80 dma_addr_t mmap_phys_base;
81
82 int current_cs;
83 int current_page_size;
84 int current_erase_size;
85 int current_addr_width;
86 unsigned long master_ref_clk_hz;
87 bool is_decoded_cs;
88 u32 fifo_depth;
89 u32 fifo_width;
90 bool rclk_en;
91 u32 trigger_address;
92 u32 wr_delay;
93 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
94 };
95
96 /* Operation timeout value */
97 #define CQSPI_TIMEOUT_MS 500
98 #define CQSPI_READ_TIMEOUT_MS 10
99
100 /* Instruction type */
101 #define CQSPI_INST_TYPE_SINGLE 0
102 #define CQSPI_INST_TYPE_DUAL 1
103 #define CQSPI_INST_TYPE_QUAD 2
104
105 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
106 #define CQSPI_DUMMY_BYTES_MAX 4
107 #define CQSPI_DUMMY_CLKS_MAX 31
108
109 #define CQSPI_STIG_DATA_LEN_MAX 8
110
111 /* Register map */
112 #define CQSPI_REG_CONFIG 0x00
113 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
114 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
115 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
116 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
117 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
118 #define CQSPI_REG_CONFIG_BAUD_LSB 19
119 #define CQSPI_REG_CONFIG_IDLE_LSB 31
120 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
121 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
122
123 #define CQSPI_REG_RD_INSTR 0x04
124 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
125 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
126 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
127 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
128 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
129 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
130 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
131 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
132 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
133 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
134
135 #define CQSPI_REG_WR_INSTR 0x08
136 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
137 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
138 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
139
140 #define CQSPI_REG_DELAY 0x0C
141 #define CQSPI_REG_DELAY_TSLCH_LSB 0
142 #define CQSPI_REG_DELAY_TCHSH_LSB 8
143 #define CQSPI_REG_DELAY_TSD2D_LSB 16
144 #define CQSPI_REG_DELAY_TSHSL_LSB 24
145 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
146 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
147 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
148 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
149
150 #define CQSPI_REG_READCAPTURE 0x10
151 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
152 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
153 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
154
155 #define CQSPI_REG_SIZE 0x14
156 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
157 #define CQSPI_REG_SIZE_PAGE_LSB 4
158 #define CQSPI_REG_SIZE_BLOCK_LSB 16
159 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
160 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
161 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
162
163 #define CQSPI_REG_SRAMPARTITION 0x18
164 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
165
166 #define CQSPI_REG_DMA 0x20
167 #define CQSPI_REG_DMA_SINGLE_LSB 0
168 #define CQSPI_REG_DMA_BURST_LSB 8
169 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
170 #define CQSPI_REG_DMA_BURST_MASK 0xFF
171
172 #define CQSPI_REG_REMAP 0x24
173 #define CQSPI_REG_MODE_BIT 0x28
174
175 #define CQSPI_REG_SDRAMLEVEL 0x2C
176 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
177 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
178 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
179 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
180
181 #define CQSPI_REG_IRQSTATUS 0x40
182 #define CQSPI_REG_IRQMASK 0x44
183
184 #define CQSPI_REG_INDIRECTRD 0x60
185 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
186 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
187 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
188
189 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
190 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
191 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
192
193 #define CQSPI_REG_CMDCTRL 0x90
194 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
195 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
196 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
197 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
198 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
199 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
200 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
201 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
202 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
203 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
204 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
205 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
206
207 #define CQSPI_REG_INDIRECTWR 0x70
208 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
209 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
210 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
211
212 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
213 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
214 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
215
216 #define CQSPI_REG_CMDADDRESS 0x94
217 #define CQSPI_REG_CMDREADDATALOWER 0xA0
218 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
219 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
220 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
221
222 /* Interrupt status bits */
223 #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
224 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
225 #define CQSPI_REG_IRQ_IND_COMP BIT(2)
226 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
227 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
228 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
229 #define CQSPI_REG_IRQ_WATERMARK BIT(6)
230 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
231
232 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
233 CQSPI_REG_IRQ_IND_SRAM_FULL | \
234 CQSPI_REG_IRQ_IND_COMP)
235
236 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
237 CQSPI_REG_IRQ_WATERMARK | \
238 CQSPI_REG_IRQ_UNDERFLOW)
239
240 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
241
242 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
243 {
244 unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
245 u32 val;
246
247 while (1) {
248 val = readl(reg);
249 if (clear)
250 val = ~val;
251 val &= mask;
252
253 if (val == mask)
254 return 0;
255
256 if (time_after(jiffies, end))
257 return -ETIMEDOUT;
258 }
259 }
260
261 static bool cqspi_is_idle(struct cqspi_st *cqspi)
262 {
263 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
264
265 return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
266 }
267
268 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
269 {
270 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
271
272 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
273 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
274 }
275
276 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
277 {
278 struct cqspi_st *cqspi = dev;
279 unsigned int irq_status;
280
281 /* Read interrupt status */
282 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
283
284 /* Clear interrupt */
285 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
286
287 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
288
289 if (irq_status)
290 complete(&cqspi->transfer_complete);
291
292 return IRQ_HANDLED;
293 }
294
295 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
296 {
297 struct cqspi_flash_pdata *f_pdata = nor->priv;
298 u32 rdreg = 0;
299
300 rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
301 rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
302 rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
303
304 return rdreg;
305 }
306
307 static int cqspi_wait_idle(struct cqspi_st *cqspi)
308 {
309 const unsigned int poll_idle_retry = 3;
310 unsigned int count = 0;
311 unsigned long timeout;
312
313 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
314 while (1) {
315 /*
316 * Read few times in succession to ensure the controller
317 * is indeed idle, that is, the bit does not transition
318 * low again.
319 */
320 if (cqspi_is_idle(cqspi))
321 count++;
322 else
323 count = 0;
324
325 if (count >= poll_idle_retry)
326 return 0;
327
328 if (time_after(jiffies, timeout)) {
329 /* Timeout, in busy mode. */
330 dev_err(&cqspi->pdev->dev,
331 "QSPI is still busy after %dms timeout.\n",
332 CQSPI_TIMEOUT_MS);
333 return -ETIMEDOUT;
334 }
335
336 cpu_relax();
337 }
338 }
339
340 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
341 {
342 void __iomem *reg_base = cqspi->iobase;
343 int ret;
344
345 /* Write the CMDCTRL without start execution. */
346 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
347 /* Start execute */
348 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
349 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
350
351 /* Polling for completion. */
352 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
353 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
354 if (ret) {
355 dev_err(&cqspi->pdev->dev,
356 "Flash command execution timed out.\n");
357 return ret;
358 }
359
360 /* Polling QSPI idle status. */
361 return cqspi_wait_idle(cqspi);
362 }
363
364 static int cqspi_command_read(struct spi_nor *nor,
365 const u8 *txbuf, const unsigned n_tx,
366 u8 *rxbuf, const unsigned n_rx)
367 {
368 struct cqspi_flash_pdata *f_pdata = nor->priv;
369 struct cqspi_st *cqspi = f_pdata->cqspi;
370 void __iomem *reg_base = cqspi->iobase;
371 unsigned int rdreg;
372 unsigned int reg;
373 unsigned int read_len;
374 int status;
375
376 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
377 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
378 n_rx, rxbuf);
379 return -EINVAL;
380 }
381
382 reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
383
384 rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
385 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
386
387 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
388
389 /* 0 means 1 byte. */
390 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
391 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
392 status = cqspi_exec_flash_cmd(cqspi, reg);
393 if (status)
394 return status;
395
396 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
397
398 /* Put the read value into rx_buf */
399 read_len = (n_rx > 4) ? 4 : n_rx;
400 memcpy(rxbuf, &reg, read_len);
401 rxbuf += read_len;
402
403 if (n_rx > 4) {
404 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
405
406 read_len = n_rx - read_len;
407 memcpy(rxbuf, &reg, read_len);
408 }
409
410 return 0;
411 }
412
413 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
414 const u8 *txbuf, const unsigned n_tx)
415 {
416 struct cqspi_flash_pdata *f_pdata = nor->priv;
417 struct cqspi_st *cqspi = f_pdata->cqspi;
418 void __iomem *reg_base = cqspi->iobase;
419 unsigned int reg;
420 unsigned int data;
421 int ret;
422
423 if (n_tx > 4 || (n_tx && !txbuf)) {
424 dev_err(nor->dev,
425 "Invalid input argument, cmdlen %d txbuf 0x%p\n",
426 n_tx, txbuf);
427 return -EINVAL;
428 }
429
430 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
431 if (n_tx) {
432 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
433 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
434 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
435 data = 0;
436 memcpy(&data, txbuf, n_tx);
437 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
438 }
439
440 ret = cqspi_exec_flash_cmd(cqspi, reg);
441 return ret;
442 }
443
444 static int cqspi_command_write_addr(struct spi_nor *nor,
445 const u8 opcode, const unsigned int addr)
446 {
447 struct cqspi_flash_pdata *f_pdata = nor->priv;
448 struct cqspi_st *cqspi = f_pdata->cqspi;
449 void __iomem *reg_base = cqspi->iobase;
450 unsigned int reg;
451
452 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
453 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
454 reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
455 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
456
457 writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
458
459 return cqspi_exec_flash_cmd(cqspi, reg);
460 }
461
462 static int cqspi_read_setup(struct spi_nor *nor)
463 {
464 struct cqspi_flash_pdata *f_pdata = nor->priv;
465 struct cqspi_st *cqspi = f_pdata->cqspi;
466 void __iomem *reg_base = cqspi->iobase;
467 unsigned int dummy_clk = 0;
468 unsigned int reg;
469
470 reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
471 reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
472
473 /* Setup dummy clock cycles */
474 dummy_clk = nor->read_dummy;
475 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
476 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
477
478 if (dummy_clk / 8) {
479 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
480 /* Set mode bits high to ensure chip doesn't enter XIP */
481 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
482
483 /* Need to subtract the mode byte (8 clocks). */
484 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
485 dummy_clk -= 8;
486
487 if (dummy_clk)
488 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
489 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
490 }
491
492 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
493
494 /* Set address width */
495 reg = readl(reg_base + CQSPI_REG_SIZE);
496 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
497 reg |= (nor->addr_width - 1);
498 writel(reg, reg_base + CQSPI_REG_SIZE);
499 return 0;
500 }
501
502 static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
503 loff_t from_addr, const size_t n_rx)
504 {
505 struct cqspi_flash_pdata *f_pdata = nor->priv;
506 struct cqspi_st *cqspi = f_pdata->cqspi;
507 void __iomem *reg_base = cqspi->iobase;
508 void __iomem *ahb_base = cqspi->ahb_base;
509 unsigned int remaining = n_rx;
510 unsigned int mod_bytes = n_rx % 4;
511 unsigned int bytes_to_read = 0;
512 u8 *rxbuf_end = rxbuf + n_rx;
513 int ret = 0;
514
515 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
516 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
517
518 /* Clear all interrupts. */
519 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
520
521 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
522
523 reinit_completion(&cqspi->transfer_complete);
524 writel(CQSPI_REG_INDIRECTRD_START_MASK,
525 reg_base + CQSPI_REG_INDIRECTRD);
526
527 while (remaining > 0) {
528 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
529 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
530 ret = -ETIMEDOUT;
531
532 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
533
534 if (ret && bytes_to_read == 0) {
535 dev_err(nor->dev, "Indirect read timeout, no bytes\n");
536 goto failrd;
537 }
538
539 while (bytes_to_read != 0) {
540 unsigned int word_remain = round_down(remaining, 4);
541
542 bytes_to_read *= cqspi->fifo_width;
543 bytes_to_read = bytes_to_read > remaining ?
544 remaining : bytes_to_read;
545 bytes_to_read = round_down(bytes_to_read, 4);
546 /* Read 4 byte word chunks then single bytes */
547 if (bytes_to_read) {
548 ioread32_rep(ahb_base, rxbuf,
549 (bytes_to_read / 4));
550 } else if (!word_remain && mod_bytes) {
551 unsigned int temp = ioread32(ahb_base);
552
553 bytes_to_read = mod_bytes;
554 memcpy(rxbuf, &temp, min((unsigned int)
555 (rxbuf_end - rxbuf),
556 bytes_to_read));
557 }
558 rxbuf += bytes_to_read;
559 remaining -= bytes_to_read;
560 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
561 }
562
563 if (remaining > 0)
564 reinit_completion(&cqspi->transfer_complete);
565 }
566
567 /* Check indirect done status */
568 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
569 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
570 if (ret) {
571 dev_err(nor->dev,
572 "Indirect read completion error (%i)\n", ret);
573 goto failrd;
574 }
575
576 /* Disable interrupt */
577 writel(0, reg_base + CQSPI_REG_IRQMASK);
578
579 /* Clear indirect completion status */
580 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
581
582 return 0;
583
584 failrd:
585 /* Disable interrupt */
586 writel(0, reg_base + CQSPI_REG_IRQMASK);
587
588 /* Cancel the indirect read */
589 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
590 reg_base + CQSPI_REG_INDIRECTRD);
591 return ret;
592 }
593
594 static int cqspi_write_setup(struct spi_nor *nor)
595 {
596 unsigned int reg;
597 struct cqspi_flash_pdata *f_pdata = nor->priv;
598 struct cqspi_st *cqspi = f_pdata->cqspi;
599 void __iomem *reg_base = cqspi->iobase;
600
601 /* Set opcode. */
602 reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
603 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
604 reg = cqspi_calc_rdreg(nor, nor->program_opcode);
605 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
606
607 reg = readl(reg_base + CQSPI_REG_SIZE);
608 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
609 reg |= (nor->addr_width - 1);
610 writel(reg, reg_base + CQSPI_REG_SIZE);
611 return 0;
612 }
613
614 static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
615 const u8 *txbuf, const size_t n_tx)
616 {
617 const unsigned int page_size = nor->page_size;
618 struct cqspi_flash_pdata *f_pdata = nor->priv;
619 struct cqspi_st *cqspi = f_pdata->cqspi;
620 void __iomem *reg_base = cqspi->iobase;
621 unsigned int remaining = n_tx;
622 unsigned int write_bytes;
623 int ret;
624
625 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
626 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
627
628 /* Clear all interrupts. */
629 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
630
631 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
632
633 reinit_completion(&cqspi->transfer_complete);
634 writel(CQSPI_REG_INDIRECTWR_START_MASK,
635 reg_base + CQSPI_REG_INDIRECTWR);
636 /*
637 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
638 * Controller programming sequence, couple of cycles of
639 * QSPI_REF_CLK delay is required for the above bit to
640 * be internally synchronized by the QSPI module. Provide 5
641 * cycles of delay.
642 */
643 if (cqspi->wr_delay)
644 ndelay(cqspi->wr_delay);
645
646 while (remaining > 0) {
647 size_t write_words, mod_bytes;
648
649 write_bytes = remaining > page_size ? page_size : remaining;
650 write_words = write_bytes / 4;
651 mod_bytes = write_bytes % 4;
652 /* Write 4 bytes at a time then single bytes. */
653 if (write_words) {
654 iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
655 txbuf += (write_words * 4);
656 }
657 if (mod_bytes) {
658 unsigned int temp = 0xFFFFFFFF;
659
660 memcpy(&temp, txbuf, mod_bytes);
661 iowrite32(temp, cqspi->ahb_base);
662 txbuf += mod_bytes;
663 }
664
665 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
666 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
667 dev_err(nor->dev, "Indirect write timeout\n");
668 ret = -ETIMEDOUT;
669 goto failwr;
670 }
671
672 remaining -= write_bytes;
673
674 if (remaining > 0)
675 reinit_completion(&cqspi->transfer_complete);
676 }
677
678 /* Check indirect done status */
679 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
680 CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
681 if (ret) {
682 dev_err(nor->dev,
683 "Indirect write completion error (%i)\n", ret);
684 goto failwr;
685 }
686
687 /* Disable interrupt. */
688 writel(0, reg_base + CQSPI_REG_IRQMASK);
689
690 /* Clear indirect completion status */
691 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
692
693 cqspi_wait_idle(cqspi);
694
695 return 0;
696
697 failwr:
698 /* Disable interrupt. */
699 writel(0, reg_base + CQSPI_REG_IRQMASK);
700
701 /* Cancel the indirect write */
702 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
703 reg_base + CQSPI_REG_INDIRECTWR);
704 return ret;
705 }
706
707 static void cqspi_chipselect(struct spi_nor *nor)
708 {
709 struct cqspi_flash_pdata *f_pdata = nor->priv;
710 struct cqspi_st *cqspi = f_pdata->cqspi;
711 void __iomem *reg_base = cqspi->iobase;
712 unsigned int chip_select = f_pdata->cs;
713 unsigned int reg;
714
715 reg = readl(reg_base + CQSPI_REG_CONFIG);
716 if (cqspi->is_decoded_cs) {
717 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
718 } else {
719 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
720
721 /* Convert CS if without decoder.
722 * CS0 to 4b'1110
723 * CS1 to 4b'1101
724 * CS2 to 4b'1011
725 * CS3 to 4b'0111
726 */
727 chip_select = 0xF & ~(1 << chip_select);
728 }
729
730 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
731 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
732 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
733 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
734 writel(reg, reg_base + CQSPI_REG_CONFIG);
735 }
736
737 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
738 {
739 struct cqspi_flash_pdata *f_pdata = nor->priv;
740 struct cqspi_st *cqspi = f_pdata->cqspi;
741 void __iomem *iobase = cqspi->iobase;
742 unsigned int reg;
743
744 /* configure page size and block size. */
745 reg = readl(iobase + CQSPI_REG_SIZE);
746 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
747 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
748 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
749 reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
750 reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
751 reg |= (nor->addr_width - 1);
752 writel(reg, iobase + CQSPI_REG_SIZE);
753
754 /* configure the chip select */
755 cqspi_chipselect(nor);
756
757 /* Store the new configuration of the controller */
758 cqspi->current_page_size = nor->page_size;
759 cqspi->current_erase_size = nor->mtd.erasesize;
760 cqspi->current_addr_width = nor->addr_width;
761 }
762
763 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
764 const unsigned int ns_val)
765 {
766 unsigned int ticks;
767
768 ticks = ref_clk_hz / 1000; /* kHz */
769 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
770
771 return ticks;
772 }
773
774 static void cqspi_delay(struct spi_nor *nor)
775 {
776 struct cqspi_flash_pdata *f_pdata = nor->priv;
777 struct cqspi_st *cqspi = f_pdata->cqspi;
778 void __iomem *iobase = cqspi->iobase;
779 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
780 unsigned int tshsl, tchsh, tslch, tsd2d;
781 unsigned int reg;
782 unsigned int tsclk;
783
784 /* calculate the number of ref ticks for one sclk tick */
785 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
786
787 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
788 /* this particular value must be at least one sclk */
789 if (tshsl < tsclk)
790 tshsl = tsclk;
791
792 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
793 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
794 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
795
796 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
797 << CQSPI_REG_DELAY_TSHSL_LSB;
798 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
799 << CQSPI_REG_DELAY_TCHSH_LSB;
800 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
801 << CQSPI_REG_DELAY_TSLCH_LSB;
802 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
803 << CQSPI_REG_DELAY_TSD2D_LSB;
804 writel(reg, iobase + CQSPI_REG_DELAY);
805 }
806
807 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
808 {
809 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
810 void __iomem *reg_base = cqspi->iobase;
811 u32 reg, div;
812
813 /* Recalculate the baudrate divisor based on QSPI specification. */
814 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
815
816 reg = readl(reg_base + CQSPI_REG_CONFIG);
817 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
818 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
819 writel(reg, reg_base + CQSPI_REG_CONFIG);
820 }
821
822 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
823 const bool bypass,
824 const unsigned int delay)
825 {
826 void __iomem *reg_base = cqspi->iobase;
827 unsigned int reg;
828
829 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
830
831 if (bypass)
832 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
833 else
834 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
835
836 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
837 << CQSPI_REG_READCAPTURE_DELAY_LSB);
838
839 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
840 << CQSPI_REG_READCAPTURE_DELAY_LSB;
841
842 writel(reg, reg_base + CQSPI_REG_READCAPTURE);
843 }
844
845 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
846 {
847 void __iomem *reg_base = cqspi->iobase;
848 unsigned int reg;
849
850 reg = readl(reg_base + CQSPI_REG_CONFIG);
851
852 if (enable)
853 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
854 else
855 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
856
857 writel(reg, reg_base + CQSPI_REG_CONFIG);
858 }
859
860 static void cqspi_configure(struct spi_nor *nor)
861 {
862 struct cqspi_flash_pdata *f_pdata = nor->priv;
863 struct cqspi_st *cqspi = f_pdata->cqspi;
864 const unsigned int sclk = f_pdata->clk_rate;
865 int switch_cs = (cqspi->current_cs != f_pdata->cs);
866 int switch_ck = (cqspi->sclk != sclk);
867
868 if ((cqspi->current_page_size != nor->page_size) ||
869 (cqspi->current_erase_size != nor->mtd.erasesize) ||
870 (cqspi->current_addr_width != nor->addr_width))
871 switch_cs = 1;
872
873 if (switch_cs || switch_ck)
874 cqspi_controller_enable(cqspi, 0);
875
876 /* Switch chip select. */
877 if (switch_cs) {
878 cqspi->current_cs = f_pdata->cs;
879 cqspi_configure_cs_and_sizes(nor);
880 }
881
882 /* Setup baudrate divisor and delays */
883 if (switch_ck) {
884 cqspi->sclk = sclk;
885 cqspi_config_baudrate_div(cqspi);
886 cqspi_delay(nor);
887 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
888 f_pdata->read_delay);
889 }
890
891 if (switch_cs || switch_ck)
892 cqspi_controller_enable(cqspi, 1);
893 }
894
895 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
896 {
897 struct cqspi_flash_pdata *f_pdata = nor->priv;
898
899 f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
900 f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
901 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
902
903 if (read) {
904 switch (nor->read_proto) {
905 case SNOR_PROTO_1_1_1:
906 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
907 break;
908 case SNOR_PROTO_1_1_2:
909 f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
910 break;
911 case SNOR_PROTO_1_1_4:
912 f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
913 break;
914 default:
915 return -EINVAL;
916 }
917 }
918
919 cqspi_configure(nor);
920
921 return 0;
922 }
923
924 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
925 size_t len, const u_char *buf)
926 {
927 struct cqspi_flash_pdata *f_pdata = nor->priv;
928 struct cqspi_st *cqspi = f_pdata->cqspi;
929 int ret;
930
931 ret = cqspi_set_protocol(nor, 0);
932 if (ret)
933 return ret;
934
935 ret = cqspi_write_setup(nor);
936 if (ret)
937 return ret;
938
939 if (f_pdata->use_direct_mode) {
940 memcpy_toio(cqspi->ahb_base + to, buf, len);
941 ret = cqspi_wait_idle(cqspi);
942 } else {
943 ret = cqspi_indirect_write_execute(nor, to, buf, len);
944 }
945 if (ret)
946 return ret;
947
948 return len;
949 }
950
951 static void cqspi_rx_dma_callback(void *param)
952 {
953 struct cqspi_st *cqspi = param;
954
955 complete(&cqspi->rx_dma_complete);
956 }
957
958 static int cqspi_direct_read_execute(struct spi_nor *nor, u_char *buf,
959 loff_t from, size_t len)
960 {
961 struct cqspi_flash_pdata *f_pdata = nor->priv;
962 struct cqspi_st *cqspi = f_pdata->cqspi;
963 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
964 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
965 int ret = 0;
966 struct dma_async_tx_descriptor *tx;
967 dma_cookie_t cookie;
968 dma_addr_t dma_dst;
969
970 if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
971 memcpy_fromio(buf, cqspi->ahb_base + from, len);
972 return 0;
973 }
974
975 dma_dst = dma_map_single(nor->dev, buf, len, DMA_FROM_DEVICE);
976 if (dma_mapping_error(nor->dev, dma_dst)) {
977 dev_err(nor->dev, "dma mapping failed\n");
978 return -ENOMEM;
979 }
980 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
981 len, flags);
982 if (!tx) {
983 dev_err(nor->dev, "device_prep_dma_memcpy error\n");
984 ret = -EIO;
985 goto err_unmap;
986 }
987
988 tx->callback = cqspi_rx_dma_callback;
989 tx->callback_param = cqspi;
990 cookie = tx->tx_submit(tx);
991 reinit_completion(&cqspi->rx_dma_complete);
992
993 ret = dma_submit_error(cookie);
994 if (ret) {
995 dev_err(nor->dev, "dma_submit_error %d\n", cookie);
996 ret = -EIO;
997 goto err_unmap;
998 }
999
1000 dma_async_issue_pending(cqspi->rx_chan);
1001 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1002 msecs_to_jiffies(len))) {
1003 dmaengine_terminate_sync(cqspi->rx_chan);
1004 dev_err(nor->dev, "DMA wait_for_completion_timeout\n");
1005 ret = -ETIMEDOUT;
1006 goto err_unmap;
1007 }
1008
1009 err_unmap:
1010 dma_unmap_single(nor->dev, dma_dst, len, DMA_FROM_DEVICE);
1011
1012 return ret;
1013 }
1014
1015 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
1016 size_t len, u_char *buf)
1017 {
1018 struct cqspi_flash_pdata *f_pdata = nor->priv;
1019 int ret;
1020
1021 ret = cqspi_set_protocol(nor, 1);
1022 if (ret)
1023 return ret;
1024
1025 ret = cqspi_read_setup(nor);
1026 if (ret)
1027 return ret;
1028
1029 if (f_pdata->use_direct_mode)
1030 ret = cqspi_direct_read_execute(nor, buf, from, len);
1031 else
1032 ret = cqspi_indirect_read_execute(nor, buf, from, len);
1033 if (ret)
1034 return ret;
1035
1036 return len;
1037 }
1038
1039 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
1040 {
1041 int ret;
1042
1043 ret = cqspi_set_protocol(nor, 0);
1044 if (ret)
1045 return ret;
1046
1047 /* Send write enable, then erase commands. */
1048 ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
1049 if (ret)
1050 return ret;
1051
1052 /* Set up command buffer. */
1053 ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
1054 if (ret)
1055 return ret;
1056
1057 return 0;
1058 }
1059
1060 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
1061 {
1062 struct cqspi_flash_pdata *f_pdata = nor->priv;
1063 struct cqspi_st *cqspi = f_pdata->cqspi;
1064
1065 mutex_lock(&cqspi->bus_mutex);
1066
1067 return 0;
1068 }
1069
1070 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
1071 {
1072 struct cqspi_flash_pdata *f_pdata = nor->priv;
1073 struct cqspi_st *cqspi = f_pdata->cqspi;
1074
1075 mutex_unlock(&cqspi->bus_mutex);
1076 }
1077
1078 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1079 {
1080 int ret;
1081
1082 ret = cqspi_set_protocol(nor, 0);
1083 if (!ret)
1084 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
1085
1086 return ret;
1087 }
1088
1089 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1090 {
1091 int ret;
1092
1093 ret = cqspi_set_protocol(nor, 0);
1094 if (!ret)
1095 ret = cqspi_command_write(nor, opcode, buf, len);
1096
1097 return ret;
1098 }
1099
1100 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1101 struct cqspi_flash_pdata *f_pdata,
1102 struct device_node *np)
1103 {
1104 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1105 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1106 return -ENXIO;
1107 }
1108
1109 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1110 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1111 return -ENXIO;
1112 }
1113
1114 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1115 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1116 return -ENXIO;
1117 }
1118
1119 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1120 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1121 return -ENXIO;
1122 }
1123
1124 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1125 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1126 return -ENXIO;
1127 }
1128
1129 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1130 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1131 return -ENXIO;
1132 }
1133
1134 return 0;
1135 }
1136
1137 static int cqspi_of_get_pdata(struct platform_device *pdev)
1138 {
1139 struct device_node *np = pdev->dev.of_node;
1140 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1141
1142 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1143
1144 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1145 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1146 return -ENXIO;
1147 }
1148
1149 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1150 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1151 return -ENXIO;
1152 }
1153
1154 if (of_property_read_u32(np, "cdns,trigger-address",
1155 &cqspi->trigger_address)) {
1156 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1157 return -ENXIO;
1158 }
1159
1160 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1161
1162 return 0;
1163 }
1164
1165 static void cqspi_controller_init(struct cqspi_st *cqspi)
1166 {
1167 u32 reg;
1168
1169 cqspi_controller_enable(cqspi, 0);
1170
1171 /* Configure the remap address register, no remap */
1172 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1173
1174 /* Disable all interrupts. */
1175 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1176
1177 /* Configure the SRAM split to 1:1 . */
1178 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1179
1180 /* Load indirect trigger address. */
1181 writel(cqspi->trigger_address,
1182 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1183
1184 /* Program read watermark -- 1/2 of the FIFO. */
1185 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1186 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1187 /* Program write watermark -- 1/8 of the FIFO. */
1188 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1189 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1190
1191 /* Enable Direct Access Controller */
1192 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1193 reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1194 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1195
1196 cqspi_controller_enable(cqspi, 1);
1197 }
1198
1199 static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1200 {
1201 dma_cap_mask_t mask;
1202
1203 dma_cap_zero(mask);
1204 dma_cap_set(DMA_MEMCPY, mask);
1205
1206 cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1207 if (IS_ERR(cqspi->rx_chan)) {
1208 dev_err(&cqspi->pdev->dev, "No Rx DMA available\n");
1209 cqspi->rx_chan = NULL;
1210 }
1211 init_completion(&cqspi->rx_dma_complete);
1212 }
1213
1214 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1215 {
1216 const struct spi_nor_hwcaps hwcaps = {
1217 .mask = SNOR_HWCAPS_READ |
1218 SNOR_HWCAPS_READ_FAST |
1219 SNOR_HWCAPS_READ_1_1_2 |
1220 SNOR_HWCAPS_READ_1_1_4 |
1221 SNOR_HWCAPS_PP,
1222 };
1223 struct platform_device *pdev = cqspi->pdev;
1224 struct device *dev = &pdev->dev;
1225 struct cqspi_flash_pdata *f_pdata;
1226 struct spi_nor *nor;
1227 struct mtd_info *mtd;
1228 unsigned int cs;
1229 int i, ret;
1230
1231 /* Get flash device data */
1232 for_each_available_child_of_node(dev->of_node, np) {
1233 ret = of_property_read_u32(np, "reg", &cs);
1234 if (ret) {
1235 dev_err(dev, "Couldn't determine chip select.\n");
1236 goto err;
1237 }
1238
1239 if (cs >= CQSPI_MAX_CHIPSELECT) {
1240 ret = -EINVAL;
1241 dev_err(dev, "Chip select %d out of range.\n", cs);
1242 goto err;
1243 }
1244
1245 f_pdata = &cqspi->f_pdata[cs];
1246 f_pdata->cqspi = cqspi;
1247 f_pdata->cs = cs;
1248
1249 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1250 if (ret)
1251 goto err;
1252
1253 nor = &f_pdata->nor;
1254 mtd = &nor->mtd;
1255
1256 mtd->priv = nor;
1257
1258 nor->dev = dev;
1259 spi_nor_set_flash_node(nor, np);
1260 nor->priv = f_pdata;
1261
1262 nor->read_reg = cqspi_read_reg;
1263 nor->write_reg = cqspi_write_reg;
1264 nor->read = cqspi_read;
1265 nor->write = cqspi_write;
1266 nor->erase = cqspi_erase;
1267 nor->prepare = cqspi_prep;
1268 nor->unprepare = cqspi_unprep;
1269
1270 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1271 dev_name(dev), cs);
1272 if (!mtd->name) {
1273 ret = -ENOMEM;
1274 goto err;
1275 }
1276
1277 ret = spi_nor_scan(nor, NULL, &hwcaps);
1278 if (ret)
1279 goto err;
1280
1281 ret = mtd_device_register(mtd, NULL, 0);
1282 if (ret)
1283 goto err;
1284
1285 f_pdata->registered = true;
1286
1287 if (mtd->size <= cqspi->ahb_size) {
1288 f_pdata->use_direct_mode = true;
1289 dev_dbg(nor->dev, "using direct mode for %s\n",
1290 mtd->name);
1291
1292 if (!cqspi->rx_chan)
1293 cqspi_request_mmap_dma(cqspi);
1294 }
1295 }
1296
1297 return 0;
1298
1299 err:
1300 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1301 if (cqspi->f_pdata[i].registered)
1302 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1303 return ret;
1304 }
1305
1306 static int cqspi_probe(struct platform_device *pdev)
1307 {
1308 struct device_node *np = pdev->dev.of_node;
1309 struct device *dev = &pdev->dev;
1310 struct cqspi_st *cqspi;
1311 struct resource *res;
1312 struct resource *res_ahb;
1313 unsigned long data;
1314 int ret;
1315 int irq;
1316
1317 cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1318 if (!cqspi)
1319 return -ENOMEM;
1320
1321 mutex_init(&cqspi->bus_mutex);
1322 cqspi->pdev = pdev;
1323 platform_set_drvdata(pdev, cqspi);
1324
1325 /* Obtain configuration from OF. */
1326 ret = cqspi_of_get_pdata(pdev);
1327 if (ret) {
1328 dev_err(dev, "Cannot get mandatory OF data.\n");
1329 return -ENODEV;
1330 }
1331
1332 /* Obtain QSPI clock. */
1333 cqspi->clk = devm_clk_get(dev, NULL);
1334 if (IS_ERR(cqspi->clk)) {
1335 dev_err(dev, "Cannot claim QSPI clock.\n");
1336 return PTR_ERR(cqspi->clk);
1337 }
1338
1339 /* Obtain and remap controller address. */
1340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1341 cqspi->iobase = devm_ioremap_resource(dev, res);
1342 if (IS_ERR(cqspi->iobase)) {
1343 dev_err(dev, "Cannot remap controller address.\n");
1344 return PTR_ERR(cqspi->iobase);
1345 }
1346
1347 /* Obtain and remap AHB address. */
1348 res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1349 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1350 if (IS_ERR(cqspi->ahb_base)) {
1351 dev_err(dev, "Cannot remap AHB address.\n");
1352 return PTR_ERR(cqspi->ahb_base);
1353 }
1354 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1355 cqspi->ahb_size = resource_size(res_ahb);
1356
1357 init_completion(&cqspi->transfer_complete);
1358
1359 /* Obtain IRQ line. */
1360 irq = platform_get_irq(pdev, 0);
1361 if (irq < 0) {
1362 dev_err(dev, "Cannot obtain IRQ.\n");
1363 return -ENXIO;
1364 }
1365
1366 pm_runtime_enable(dev);
1367 ret = pm_runtime_get_sync(dev);
1368 if (ret < 0) {
1369 pm_runtime_put_noidle(dev);
1370 return ret;
1371 }
1372
1373 ret = clk_prepare_enable(cqspi->clk);
1374 if (ret) {
1375 dev_err(dev, "Cannot enable QSPI clock.\n");
1376 goto probe_clk_failed;
1377 }
1378
1379 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1380 data = (unsigned long)of_device_get_match_data(dev);
1381 if (data & CQSPI_NEEDS_WR_DELAY)
1382 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1383 cqspi->master_ref_clk_hz);
1384
1385 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1386 pdev->name, cqspi);
1387 if (ret) {
1388 dev_err(dev, "Cannot request IRQ.\n");
1389 goto probe_irq_failed;
1390 }
1391
1392 cqspi_wait_idle(cqspi);
1393 cqspi_controller_init(cqspi);
1394 cqspi->current_cs = -1;
1395 cqspi->sclk = 0;
1396
1397 ret = cqspi_setup_flash(cqspi, np);
1398 if (ret) {
1399 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1400 goto probe_setup_failed;
1401 }
1402
1403 return ret;
1404 probe_setup_failed:
1405 cqspi_controller_enable(cqspi, 0);
1406 probe_irq_failed:
1407 clk_disable_unprepare(cqspi->clk);
1408 probe_clk_failed:
1409 pm_runtime_put_sync(dev);
1410 pm_runtime_disable(dev);
1411 return ret;
1412 }
1413
1414 static int cqspi_remove(struct platform_device *pdev)
1415 {
1416 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1417 int i;
1418
1419 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1420 if (cqspi->f_pdata[i].registered)
1421 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1422
1423 cqspi_controller_enable(cqspi, 0);
1424
1425 if (cqspi->rx_chan)
1426 dma_release_channel(cqspi->rx_chan);
1427
1428 clk_disable_unprepare(cqspi->clk);
1429
1430 pm_runtime_put_sync(&pdev->dev);
1431 pm_runtime_disable(&pdev->dev);
1432
1433 return 0;
1434 }
1435
1436 #ifdef CONFIG_PM_SLEEP
1437 static int cqspi_suspend(struct device *dev)
1438 {
1439 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1440
1441 cqspi_controller_enable(cqspi, 0);
1442 return 0;
1443 }
1444
1445 static int cqspi_resume(struct device *dev)
1446 {
1447 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1448
1449 cqspi_controller_enable(cqspi, 1);
1450 return 0;
1451 }
1452
1453 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1454 .suspend = cqspi_suspend,
1455 .resume = cqspi_resume,
1456 };
1457
1458 #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops)
1459 #else
1460 #define CQSPI_DEV_PM_OPS NULL
1461 #endif
1462
1463 static const struct of_device_id cqspi_dt_ids[] = {
1464 {
1465 .compatible = "cdns,qspi-nor",
1466 .data = (void *)0,
1467 },
1468 {
1469 .compatible = "ti,k2g-qspi",
1470 .data = (void *)CQSPI_NEEDS_WR_DELAY,
1471 },
1472 { /* end of table */ }
1473 };
1474
1475 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1476
1477 static struct platform_driver cqspi_platform_driver = {
1478 .probe = cqspi_probe,
1479 .remove = cqspi_remove,
1480 .driver = {
1481 .name = CQSPI_NAME,
1482 .pm = CQSPI_DEV_PM_OPS,
1483 .of_match_table = cqspi_dt_ids,
1484 },
1485 };
1486
1487 module_platform_driver(cqspi_platform_driver);
1488
1489 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1490 MODULE_LICENSE("GPL v2");
1491 MODULE_ALIAS("platform:" CQSPI_NAME);
1492 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1493 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
Linux with added FPC-III support