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Linux 4.19.133
[linux/fpc-iii.git] / drivers / mtd / spi-nor / spi-nor.c
blobff641c06003a8fb81f8ee6264a8c9c97a24c868d
1 /*
2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
4 *
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
7 *
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19 #include <linux/sizes.h>
20 #include <linux/slab.h>
21
22 #include <linux/mtd/mtd.h>
23 #include <linux/of_platform.h>
24 #include <linux/spi/flash.h>
25 #include <linux/mtd/spi-nor.h>
26
27 /* Define max times to check status register before we give up. */
28
29 /*
30 * For everything but full-chip erase; probably could be much smaller, but kept
31 * around for safety for now
32 */
33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
34
35 /*
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
37 * for larger flash
38 */
39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
40
41 #define SPI_NOR_MAX_ID_LEN 6
42 #define SPI_NOR_MAX_ADDR_WIDTH 4
43
44 struct flash_info {
45 char *name;
46
47 /*
48 * This array stores the ID bytes.
49 * The first three bytes are the JEDIC ID.
50 * JEDEC ID zero means "no ID" (mostly older chips).
51 */
52 u8 id[SPI_NOR_MAX_ID_LEN];
53 u8 id_len;
54
55 /* The size listed here is what works with SPINOR_OP_SE, which isn't
56 * necessarily called a "sector" by the vendor.
57 */
58 unsigned sector_size;
59 u16 n_sectors;
60
61 u16 page_size;
62 u16 addr_width;
63
64 u16 flags;
65 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
66 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
67 #define SST_WRITE BIT(2) /* use SST byte programming */
68 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
69 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
70 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
71 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
72 #define USE_FSR BIT(7) /* use flag status register */
73 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
74 #define SPI_NOR_HAS_TB BIT(9) /*
75 * Flash SR has Top/Bottom (TB) protect
76 * bit. Must be used with
77 * SPI_NOR_HAS_LOCK.
78 */
79 #define SPI_S3AN BIT(10) /*
80 * Xilinx Spartan 3AN In-System Flash
81 * (MFR cannot be used for probing
82 * because it has the same value as
83 * ATMEL flashes)
84 */
85 #define SPI_NOR_4B_OPCODES BIT(11) /*
86 * Use dedicated 4byte address op codes
87 * to support memory size above 128Mib.
88 */
89 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
90 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
91 #define USE_CLSR BIT(14) /* use CLSR command */
92
93 int (*quad_enable)(struct spi_nor *nor);
94 };
95
96 #define JEDEC_MFR(info) ((info)->id[0])
97
98 static const struct flash_info *spi_nor_match_id(const char *name);
99
100 /*
101 * Read the status register, returning its value in the location
102 * Return the status register value.
103 * Returns negative if error occurred.
104 */
105 static int read_sr(struct spi_nor *nor)
106 {
107 int ret;
108 u8 val;
109
110 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
111 if (ret < 0) {
112 pr_err("error %d reading SR\n", (int) ret);
113 return ret;
114 }
115
116 return val;
117 }
118
119 /*
120 * Read the flag status register, returning its value in the location
121 * Return the status register value.
122 * Returns negative if error occurred.
123 */
124 static int read_fsr(struct spi_nor *nor)
125 {
126 int ret;
127 u8 val;
128
129 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
130 if (ret < 0) {
131 pr_err("error %d reading FSR\n", ret);
132 return ret;
133 }
134
135 return val;
136 }
137
138 /*
139 * Read configuration register, returning its value in the
140 * location. Return the configuration register value.
141 * Returns negative if error occurred.
142 */
143 static int read_cr(struct spi_nor *nor)
144 {
145 int ret;
146 u8 val;
147
148 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
149 if (ret < 0) {
150 dev_err(nor->dev, "error %d reading CR\n", ret);
151 return ret;
152 }
153
154 return val;
155 }
156
157 /*
158 * Write status register 1 byte
159 * Returns negative if error occurred.
160 */
161 static inline int write_sr(struct spi_nor *nor, u8 val)
162 {
163 nor->cmd_buf[0] = val;
164 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
165 }
166
167 /*
168 * Set write enable latch with Write Enable command.
169 * Returns negative if error occurred.
170 */
171 static inline int write_enable(struct spi_nor *nor)
172 {
173 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
174 }
175
176 /*
177 * Send write disable instruction to the chip.
178 */
179 static inline int write_disable(struct spi_nor *nor)
180 {
181 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
182 }
183
184 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
185 {
186 return mtd->priv;
187 }
188
189
190 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
191 {
192 size_t i;
193
194 for (i = 0; i < size; i++)
195 if (table[i][0] == opcode)
196 return table[i][1];
197
198 /* No conversion found, keep input op code. */
199 return opcode;
200 }
201
202 static inline u8 spi_nor_convert_3to4_read(u8 opcode)
203 {
204 static const u8 spi_nor_3to4_read[][2] = {
205 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
206 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
207 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
208 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
209 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
210 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
211
212 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
213 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
214 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
215 };
216
217 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
218 ARRAY_SIZE(spi_nor_3to4_read));
219 }
220
221 static inline u8 spi_nor_convert_3to4_program(u8 opcode)
222 {
223 static const u8 spi_nor_3to4_program[][2] = {
224 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
225 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
226 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
227 };
228
229 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
230 ARRAY_SIZE(spi_nor_3to4_program));
231 }
232
233 static inline u8 spi_nor_convert_3to4_erase(u8 opcode)
234 {
235 static const u8 spi_nor_3to4_erase[][2] = {
236 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
237 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
238 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
239 };
240
241 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
242 ARRAY_SIZE(spi_nor_3to4_erase));
243 }
244
245 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
246 const struct flash_info *info)
247 {
248 /* Do some manufacturer fixups first */
249 switch (JEDEC_MFR(info)) {
250 case SNOR_MFR_SPANSION:
251 /* No small sector erase for 4-byte command set */
252 nor->erase_opcode = SPINOR_OP_SE;
253 nor->mtd.erasesize = info->sector_size;
254 break;
255
256 default:
257 break;
258 }
259
260 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
261 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
262 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
263 }
264
265 /* Enable/disable 4-byte addressing mode. */
266 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
267 int enable)
268 {
269 int status;
270 bool need_wren = false;
271 u8 cmd;
272
273 switch (JEDEC_MFR(info)) {
274 case SNOR_MFR_MICRON:
275 /* Some Micron need WREN command; all will accept it */
276 need_wren = true;
277 case SNOR_MFR_MACRONIX:
278 case SNOR_MFR_WINBOND:
279 if (need_wren)
280 write_enable(nor);
281
282 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
283 status = nor->write_reg(nor, cmd, NULL, 0);
284 if (need_wren)
285 write_disable(nor);
286
287 if (!status && !enable &&
288 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
289 /*
290 * On Winbond W25Q256FV, leaving 4byte mode causes
291 * the Extended Address Register to be set to 1, so all
292 * 3-byte-address reads come from the second 16M.
293 * We must clear the register to enable normal behavior.
294 */
295 write_enable(nor);
296 nor->cmd_buf[0] = 0;
297 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
298 write_disable(nor);
299 }
300
301 return status;
302 default:
303 /* Spansion style */
304 nor->cmd_buf[0] = enable << 7;
305 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
306 }
307 }
308
309 static int s3an_sr_ready(struct spi_nor *nor)
310 {
311 int ret;
312 u8 val;
313
314 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
315 if (ret < 0) {
316 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
317 return ret;
318 }
319
320 return !!(val & XSR_RDY);
321 }
322
323 static inline int spi_nor_sr_ready(struct spi_nor *nor)
324 {
325 int sr = read_sr(nor);
326 if (sr < 0)
327 return sr;
328
329 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
330 if (sr & SR_E_ERR)
331 dev_err(nor->dev, "Erase Error occurred\n");
332 else
333 dev_err(nor->dev, "Programming Error occurred\n");
334
335 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
336 return -EIO;
337 }
338
339 return !(sr & SR_WIP);
340 }
341
342 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
343 {
344 int fsr = read_fsr(nor);
345 if (fsr < 0)
346 return fsr;
347
348 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
349 if (fsr & FSR_E_ERR)
350 dev_err(nor->dev, "Erase operation failed.\n");
351 else
352 dev_err(nor->dev, "Program operation failed.\n");
353
354 if (fsr & FSR_PT_ERR)
355 dev_err(nor->dev,
356 "Attempted to modify a protected sector.\n");
357
358 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
359 return -EIO;
360 }
361
362 return fsr & FSR_READY;
363 }
364
365 static int spi_nor_ready(struct spi_nor *nor)
366 {
367 int sr, fsr;
368
369 if (nor->flags & SNOR_F_READY_XSR_RDY)
370 sr = s3an_sr_ready(nor);
371 else
372 sr = spi_nor_sr_ready(nor);
373 if (sr < 0)
374 return sr;
375 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
376 if (fsr < 0)
377 return fsr;
378 return sr && fsr;
379 }
380
381 /*
382 * Service routine to read status register until ready, or timeout occurs.
383 * Returns non-zero if error.
384 */
385 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
386 unsigned long timeout_jiffies)
387 {
388 unsigned long deadline;
389 int timeout = 0, ret;
390
391 deadline = jiffies + timeout_jiffies;
392
393 while (!timeout) {
394 if (time_after_eq(jiffies, deadline))
395 timeout = 1;
396
397 ret = spi_nor_ready(nor);
398 if (ret < 0)
399 return ret;
400 if (ret)
401 return 0;
402
403 cond_resched();
404 }
405
406 dev_err(nor->dev, "flash operation timed out\n");
407
408 return -ETIMEDOUT;
409 }
410
411 static int spi_nor_wait_till_ready(struct spi_nor *nor)
412 {
413 return spi_nor_wait_till_ready_with_timeout(nor,
414 DEFAULT_READY_WAIT_JIFFIES);
415 }
416
417 /*
418 * Erase the whole flash memory
419 *
420 * Returns 0 if successful, non-zero otherwise.
421 */
422 static int erase_chip(struct spi_nor *nor)
423 {
424 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
425
426 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
427 }
428
429 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
430 {
431 int ret = 0;
432
433 mutex_lock(&nor->lock);
434
435 if (nor->prepare) {
436 ret = nor->prepare(nor, ops);
437 if (ret) {
438 dev_err(nor->dev, "failed in the preparation.\n");
439 mutex_unlock(&nor->lock);
440 return ret;
441 }
442 }
443 return ret;
444 }
445
446 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
447 {
448 if (nor->unprepare)
449 nor->unprepare(nor, ops);
450 mutex_unlock(&nor->lock);
451 }
452
453 /*
454 * This code converts an address to the Default Address Mode, that has non
455 * power of two page sizes. We must support this mode because it is the default
456 * mode supported by Xilinx tools, it can access the whole flash area and
457 * changing over to the Power-of-two mode is irreversible and corrupts the
458 * original data.
459 * Addr can safely be unsigned int, the biggest S3AN device is smaller than
460 * 4 MiB.
461 */
462 static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr)
463 {
464 unsigned int offset;
465 unsigned int page;
466
467 offset = addr % nor->page_size;
468 page = addr / nor->page_size;
469 page <<= (nor->page_size > 512) ? 10 : 9;
470
471 return page | offset;
472 }
473
474 /*
475 * Initiate the erasure of a single sector
476 */
477 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
478 {
479 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
480 int i;
481
482 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
483 addr = spi_nor_s3an_addr_convert(nor, addr);
484
485 if (nor->erase)
486 return nor->erase(nor, addr);
487
488 /*
489 * Default implementation, if driver doesn't have a specialized HW
490 * control
491 */
492 for (i = nor->addr_width - 1; i >= 0; i--) {
493 buf[i] = addr & 0xff;
494 addr >>= 8;
495 }
496
497 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
498 }
499
500 /*
501 * Erase an address range on the nor chip. The address range may extend
502 * one or more erase sectors. Return an error is there is a problem erasing.
503 */
504 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
505 {
506 struct spi_nor *nor = mtd_to_spi_nor(mtd);
507 u32 addr, len;
508 uint32_t rem;
509 int ret;
510
511 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
512 (long long)instr->len);
513
514 div_u64_rem(instr->len, mtd->erasesize, &rem);
515 if (rem)
516 return -EINVAL;
517
518 addr = instr->addr;
519 len = instr->len;
520
521 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
522 if (ret)
523 return ret;
524
525 /* whole-chip erase? */
526 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
527 unsigned long timeout;
528
529 write_enable(nor);
530
531 if (erase_chip(nor)) {
532 ret = -EIO;
533 goto erase_err;
534 }
535
536 /*
537 * Scale the timeout linearly with the size of the flash, with
538 * a minimum calibrated to an old 2MB flash. We could try to
539 * pull these from CFI/SFDP, but these values should be good
540 * enough for now.
541 */
542 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
543 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
544 (unsigned long)(mtd->size / SZ_2M));
545 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
546 if (ret)
547 goto erase_err;
548
549 /* REVISIT in some cases we could speed up erasing large regions
550 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
551 * to use "small sector erase", but that's not always optimal.
552 */
553
554 /* "sector"-at-a-time erase */
555 } else {
556 while (len) {
557 write_enable(nor);
558
559 ret = spi_nor_erase_sector(nor, addr);
560 if (ret)
561 goto erase_err;
562
563 addr += mtd->erasesize;
564 len -= mtd->erasesize;
565
566 ret = spi_nor_wait_till_ready(nor);
567 if (ret)
568 goto erase_err;
569 }
570 }
571
572 write_disable(nor);
573
574 erase_err:
575 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
576
577 return ret;
578 }
579
580 /* Write status register and ensure bits in mask match written values */
581 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
582 {
583 int ret;
584
585 write_enable(nor);
586 ret = write_sr(nor, status_new);
587 if (ret)
588 return ret;
589
590 ret = spi_nor_wait_till_ready(nor);
591 if (ret)
592 return ret;
593
594 ret = read_sr(nor);
595 if (ret < 0)
596 return ret;
597
598 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
599 }
600
601 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
602 uint64_t *len)
603 {
604 struct mtd_info *mtd = &nor->mtd;
605 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
606 int shift = ffs(mask) - 1;
607 int pow;
608
609 if (!(sr & mask)) {
610 /* No protection */
611 *ofs = 0;
612 *len = 0;
613 } else {
614 pow = ((sr & mask) ^ mask) >> shift;
615 *len = mtd->size >> pow;
616 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
617 *ofs = 0;
618 else
619 *ofs = mtd->size - *len;
620 }
621 }
622
623 /*
624 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
625 * @locked is false); 0 otherwise
626 */
627 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
628 u8 sr, bool locked)
629 {
630 loff_t lock_offs;
631 uint64_t lock_len;
632
633 if (!len)
634 return 1;
635
636 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
637
638 if (locked)
639 /* Requested range is a sub-range of locked range */
640 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
641 else
642 /* Requested range does not overlap with locked range */
643 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
644 }
645
646 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
647 u8 sr)
648 {
649 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
650 }
651
652 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
653 u8 sr)
654 {
655 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
656 }
657
658 /*
659 * Lock a region of the flash. Compatible with ST Micro and similar flash.
660 * Supports the block protection bits BP{0,1,2} in the status register
661 * (SR). Does not support these features found in newer SR bitfields:
662 * - SEC: sector/block protect - only handle SEC=0 (block protect)
663 * - CMP: complement protect - only support CMP=0 (range is not complemented)
664 *
665 * Support for the following is provided conditionally for some flash:
666 * - TB: top/bottom protect
667 *
668 * Sample table portion for 8MB flash (Winbond w25q64fw):
669 *
670 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
671 * --------------------------------------------------------------------------
672 * X | X | 0 | 0 | 0 | NONE | NONE
673 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
674 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
675 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
676 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
677 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
678 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
679 * X | X | 1 | 1 | 1 | 8 MB | ALL
680 * ------|-------|-------|-------|-------|---------------|-------------------
681 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
682 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
683 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
684 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
685 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
686 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
687 *
688 * Returns negative on errors, 0 on success.
689 */
690 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
691 {
692 struct mtd_info *mtd = &nor->mtd;
693 int status_old, status_new;
694 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
695 u8 shift = ffs(mask) - 1, pow, val;
696 loff_t lock_len;
697 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
698 bool use_top;
699
700 status_old = read_sr(nor);
701 if (status_old < 0)
702 return status_old;
703
704 /* If nothing in our range is unlocked, we don't need to do anything */
705 if (stm_is_locked_sr(nor, ofs, len, status_old))
706 return 0;
707
708 /* If anything below us is unlocked, we can't use 'bottom' protection */
709 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
710 can_be_bottom = false;
711
712 /* If anything above us is unlocked, we can't use 'top' protection */
713 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
714 status_old))
715 can_be_top = false;
716
717 if (!can_be_bottom && !can_be_top)
718 return -EINVAL;
719
720 /* Prefer top, if both are valid */
721 use_top = can_be_top;
722
723 /* lock_len: length of region that should end up locked */
724 if (use_top)
725 lock_len = mtd->size - ofs;
726 else
727 lock_len = ofs + len;
728
729 /*
730 * Need smallest pow such that:
731 *
732 * 1 / (2^pow) <= (len / size)
733 *
734 * so (assuming power-of-2 size) we do:
735 *
736 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
737 */
738 pow = ilog2(mtd->size) - ilog2(lock_len);
739 val = mask - (pow << shift);
740 if (val & ~mask)
741 return -EINVAL;
742 /* Don't "lock" with no region! */
743 if (!(val & mask))
744 return -EINVAL;
745
746 status_new = (status_old & ~mask & ~SR_TB) | val;
747
748 /* Disallow further writes if WP pin is asserted */
749 status_new |= SR_SRWD;
750
751 if (!use_top)
752 status_new |= SR_TB;
753
754 /* Don't bother if they're the same */
755 if (status_new == status_old)
756 return 0;
757
758 /* Only modify protection if it will not unlock other areas */
759 if ((status_new & mask) < (status_old & mask))
760 return -EINVAL;
761
762 return write_sr_and_check(nor, status_new, mask);
763 }
764
765 /*
766 * Unlock a region of the flash. See stm_lock() for more info
767 *
768 * Returns negative on errors, 0 on success.
769 */
770 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
771 {
772 struct mtd_info *mtd = &nor->mtd;
773 int status_old, status_new;
774 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
775 u8 shift = ffs(mask) - 1, pow, val;
776 loff_t lock_len;
777 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
778 bool use_top;
779
780 status_old = read_sr(nor);
781 if (status_old < 0)
782 return status_old;
783
784 /* If nothing in our range is locked, we don't need to do anything */
785 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
786 return 0;
787
788 /* If anything below us is locked, we can't use 'top' protection */
789 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
790 can_be_top = false;
791
792 /* If anything above us is locked, we can't use 'bottom' protection */
793 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
794 status_old))
795 can_be_bottom = false;
796
797 if (!can_be_bottom && !can_be_top)
798 return -EINVAL;
799
800 /* Prefer top, if both are valid */
801 use_top = can_be_top;
802
803 /* lock_len: length of region that should remain locked */
804 if (use_top)
805 lock_len = mtd->size - (ofs + len);
806 else
807 lock_len = ofs;
808
809 /*
810 * Need largest pow such that:
811 *
812 * 1 / (2^pow) >= (len / size)
813 *
814 * so (assuming power-of-2 size) we do:
815 *
816 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
817 */
818 pow = ilog2(mtd->size) - order_base_2(lock_len);
819 if (lock_len == 0) {
820 val = 0; /* fully unlocked */
821 } else {
822 val = mask - (pow << shift);
823 /* Some power-of-two sizes are not supported */
824 if (val & ~mask)
825 return -EINVAL;
826 }
827
828 status_new = (status_old & ~mask & ~SR_TB) | val;
829
830 /* Don't protect status register if we're fully unlocked */
831 if (lock_len == 0)
832 status_new &= ~SR_SRWD;
833
834 if (!use_top)
835 status_new |= SR_TB;
836
837 /* Don't bother if they're the same */
838 if (status_new == status_old)
839 return 0;
840
841 /* Only modify protection if it will not lock other areas */
842 if ((status_new & mask) > (status_old & mask))
843 return -EINVAL;
844
845 return write_sr_and_check(nor, status_new, mask);
846 }
847
848 /*
849 * Check if a region of the flash is (completely) locked. See stm_lock() for
850 * more info.
851 *
852 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
853 * negative on errors.
854 */
855 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
856 {
857 int status;
858
859 status = read_sr(nor);
860 if (status < 0)
861 return status;
862
863 return stm_is_locked_sr(nor, ofs, len, status);
864 }
865
866 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
867 {
868 struct spi_nor *nor = mtd_to_spi_nor(mtd);
869 int ret;
870
871 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
872 if (ret)
873 return ret;
874
875 ret = nor->flash_lock(nor, ofs, len);
876
877 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
878 return ret;
879 }
880
881 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
882 {
883 struct spi_nor *nor = mtd_to_spi_nor(mtd);
884 int ret;
885
886 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
887 if (ret)
888 return ret;
889
890 ret = nor->flash_unlock(nor, ofs, len);
891
892 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
893 return ret;
894 }
895
896 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
897 {
898 struct spi_nor *nor = mtd_to_spi_nor(mtd);
899 int ret;
900
901 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
902 if (ret)
903 return ret;
904
905 ret = nor->flash_is_locked(nor, ofs, len);
906
907 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
908 return ret;
909 }
910
911 static int macronix_quad_enable(struct spi_nor *nor);
912
913 /* Used when the "_ext_id" is two bytes at most */
914 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
915 .id = { \
916 ((_jedec_id) >> 16) & 0xff, \
917 ((_jedec_id) >> 8) & 0xff, \
918 (_jedec_id) & 0xff, \
919 ((_ext_id) >> 8) & 0xff, \
920 (_ext_id) & 0xff, \
921 }, \
922 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
923 .sector_size = (_sector_size), \
924 .n_sectors = (_n_sectors), \
925 .page_size = 256, \
926 .flags = (_flags),
927
928 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
929 .id = { \
930 ((_jedec_id) >> 16) & 0xff, \
931 ((_jedec_id) >> 8) & 0xff, \
932 (_jedec_id) & 0xff, \
933 ((_ext_id) >> 16) & 0xff, \
934 ((_ext_id) >> 8) & 0xff, \
935 (_ext_id) & 0xff, \
936 }, \
937 .id_len = 6, \
938 .sector_size = (_sector_size), \
939 .n_sectors = (_n_sectors), \
940 .page_size = 256, \
941 .flags = (_flags),
942
943 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
944 .sector_size = (_sector_size), \
945 .n_sectors = (_n_sectors), \
946 .page_size = (_page_size), \
947 .addr_width = (_addr_width), \
948 .flags = (_flags),
949
950 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
951 .id = { \
952 ((_jedec_id) >> 16) & 0xff, \
953 ((_jedec_id) >> 8) & 0xff, \
954 (_jedec_id) & 0xff \
955 }, \
956 .id_len = 3, \
957 .sector_size = (8*_page_size), \
958 .n_sectors = (_n_sectors), \
959 .page_size = _page_size, \
960 .addr_width = 3, \
961 .flags = SPI_NOR_NO_FR | SPI_S3AN,
962
963 /* NOTE: double check command sets and memory organization when you add
964 * more nor chips. This current list focusses on newer chips, which
965 * have been converging on command sets which including JEDEC ID.
966 *
967 * All newly added entries should describe *hardware* and should use SECT_4K
968 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
969 * scenarios excluding small sectors there is config option that can be
970 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
971 * For historical (and compatibility) reasons (before we got above config) some
972 * old entries may be missing 4K flag.
973 */
974 static const struct flash_info spi_nor_ids[] = {
975 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
976 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
977 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
978
979 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
980 { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
981 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
982 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
983
984 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
985 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
986 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
987 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
988
989 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
990
991 /* EON -- en25xxx */
992 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
993 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
994 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
995 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
996 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
997 { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
998 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
999 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
1000 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
1001
1002 /* ESMT */
1003 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
1004 { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
1005 { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
1006
1007 /* Everspin */
1008 { "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1009 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1010 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1011 { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1012
1013 /* Fujitsu */
1014 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
1015
1016 /* GigaDevice */
1017 {
1018 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
1019 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1020 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1021 },
1022 {
1023 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
1024 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1025 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1026 },
1027 {
1028 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
1029 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1030 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1031 },
1032 {
1033 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
1034 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1035 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1036 },
1037 {
1038 "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
1039 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1040 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1041 },
1042 {
1043 "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
1044 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1045 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1046 },
1047 {
1048 "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
1049 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1050 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1051 .quad_enable = macronix_quad_enable,
1052 },
1053
1054 /* Intel/Numonyx -- xxxs33b */
1055 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
1056 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
1057 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
1058
1059 /* ISSI */
1060 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
1061 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
1062 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1063 { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
1064 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1065 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
1066 SECT_4K | SPI_NOR_DUAL_READ) },
1067 { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
1068 SECT_4K | SPI_NOR_DUAL_READ) },
1069 { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
1070 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1071 { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
1072 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1073 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
1074 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1075
1076 /* Macronix */
1077 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
1078 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
1079 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
1080 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
1081 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
1082 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
1083 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
1084 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
1085 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
1086 { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
1087 { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
1088 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
1089 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
1090 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
1091 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1092 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
1093 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
1094 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1095 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1096 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1097 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
1098
1099 /* Micron */
1100 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
1101 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1102 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1103 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1104 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1105 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1106 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1107 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1108 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
1109 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1110 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1111 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1112 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1113 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1114
1115 /* PMC */
1116 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
1117 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
1118 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
1119
1120 /* Spansion/Cypress -- single (large) sector size only, at least
1121 * for the chips listed here (without boot sectors).
1122 */
1123 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1124 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1125 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
1126 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1127 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1128 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
1129 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
1130 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
1131 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1132 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1133 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1134 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
1135 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
1136 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
1137 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
1138 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
1139 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1140 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1141 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1142 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1143 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1144 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
1145 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
1146 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
1147 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
1148 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1149 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1150 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1151
1152 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
1153 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1154 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1155 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
1156 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
1157 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
1158 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
1159 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
1160 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
1161 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
1162 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
1163 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1164 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1165 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1166
1167 /* ST Microelectronics -- newer production may have feature updates */
1168 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
1169 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
1170 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
1171 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
1172 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
1173 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
1174 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
1175 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
1176 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
1177
1178 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
1179 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
1180 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
1181 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
1182 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
1183 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
1184 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
1185 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
1186 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
1187
1188 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
1189 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
1190 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
1191
1192 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
1193 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
1194 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
1195
1196 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
1197 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
1198 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
1199 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
1200 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1201 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
1202
1203 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1204 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
1205 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
1206 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
1207 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
1208 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
1209 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
1210 {
1211 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
1212 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1213 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1214 },
1215 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
1216 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
1217 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
1218 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
1219 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
1220 {
1221 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
1222 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1223 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1224 },
1225 {
1226 "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
1227 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1228 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1229 },
1230 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1231 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1232 {
1233 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
1234 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1235 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1236 },
1237 {
1238 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
1239 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1240 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1241 },
1242 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1243 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1244 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1245 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1246 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
1247 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
1248
1249 /* Catalyst / On Semiconductor -- non-JEDEC */
1250 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1251 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1252 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1253 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1254 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1255
1256 /* Xilinx S3AN Internal Flash */
1257 { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
1258 { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
1259 { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
1260 { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
1261 { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
1262
1263 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
1264 { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1265 { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1266 { },
1267 };
1268
1269 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1270 {
1271 int tmp;
1272 u8 id[SPI_NOR_MAX_ID_LEN];
1273 const struct flash_info *info;
1274
1275 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1276 if (tmp < 0) {
1277 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1278 return ERR_PTR(tmp);
1279 }
1280
1281 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
1282 info = &spi_nor_ids[tmp];
1283 if (info->id_len) {
1284 if (!memcmp(info->id, id, info->id_len))
1285 return &spi_nor_ids[tmp];
1286 }
1287 }
1288 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1289 id[0], id[1], id[2]);
1290 return ERR_PTR(-ENODEV);
1291 }
1292
1293 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1294 size_t *retlen, u_char *buf)
1295 {
1296 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1297 ssize_t ret;
1298
1299 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1300
1301 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
1302 if (ret)
1303 return ret;
1304
1305 while (len) {
1306 loff_t addr = from;
1307
1308 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
1309 addr = spi_nor_s3an_addr_convert(nor, addr);
1310
1311 ret = nor->read(nor, addr, len, buf);
1312 if (ret == 0) {
1313 /* We shouldn't see 0-length reads */
1314 ret = -EIO;
1315 goto read_err;
1316 }
1317 if (ret < 0)
1318 goto read_err;
1319
1320 WARN_ON(ret > len);
1321 *retlen += ret;
1322 buf += ret;
1323 from += ret;
1324 len -= ret;
1325 }
1326 ret = 0;
1327
1328 read_err:
1329 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
1330 return ret;
1331 }
1332
1333 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1334 size_t *retlen, const u_char *buf)
1335 {
1336 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1337 size_t actual;
1338 int ret;
1339
1340 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1341
1342 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1343 if (ret)
1344 return ret;
1345
1346 write_enable(nor);
1347
1348 nor->sst_write_second = false;
1349
1350 actual = to % 2;
1351 /* Start write from odd address. */
1352 if (actual) {
1353 nor->program_opcode = SPINOR_OP_BP;
1354
1355 /* write one byte. */
1356 ret = nor->write(nor, to, 1, buf);
1357 if (ret < 0)
1358 goto sst_write_err;
1359 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1360 (int)ret);
1361 ret = spi_nor_wait_till_ready(nor);
1362 if (ret)
1363 goto sst_write_err;
1364 }
1365 to += actual;
1366
1367 /* Write out most of the data here. */
1368 for (; actual < len - 1; actual += 2) {
1369 nor->program_opcode = SPINOR_OP_AAI_WP;
1370
1371 /* write two bytes. */
1372 ret = nor->write(nor, to, 2, buf + actual);
1373 if (ret < 0)
1374 goto sst_write_err;
1375 WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
1376 (int)ret);
1377 ret = spi_nor_wait_till_ready(nor);
1378 if (ret)
1379 goto sst_write_err;
1380 to += 2;
1381 nor->sst_write_second = true;
1382 }
1383 nor->sst_write_second = false;
1384
1385 write_disable(nor);
1386 ret = spi_nor_wait_till_ready(nor);
1387 if (ret)
1388 goto sst_write_err;
1389
1390 /* Write out trailing byte if it exists. */
1391 if (actual != len) {
1392 write_enable(nor);
1393
1394 nor->program_opcode = SPINOR_OP_BP;
1395 ret = nor->write(nor, to, 1, buf + actual);
1396 if (ret < 0)
1397 goto sst_write_err;
1398 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1399 (int)ret);
1400 ret = spi_nor_wait_till_ready(nor);
1401 if (ret)
1402 goto sst_write_err;
1403 write_disable(nor);
1404 actual += 1;
1405 }
1406 sst_write_err:
1407 *retlen += actual;
1408 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1409 return ret;
1410 }
1411
1412 /*
1413 * Write an address range to the nor chip. Data must be written in
1414 * FLASH_PAGESIZE chunks. The address range may be any size provided
1415 * it is within the physical boundaries.
1416 */
1417 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1418 size_t *retlen, const u_char *buf)
1419 {
1420 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1421 size_t page_offset, page_remain, i;
1422 ssize_t ret;
1423
1424 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1425
1426 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1427 if (ret)
1428 return ret;
1429
1430 for (i = 0; i < len; ) {
1431 ssize_t written;
1432 loff_t addr = to + i;
1433
1434 /*
1435 * If page_size is a power of two, the offset can be quickly
1436 * calculated with an AND operation. On the other cases we
1437 * need to do a modulus operation (more expensive).
1438 * Power of two numbers have only one bit set and we can use
1439 * the instruction hweight32 to detect if we need to do a
1440 * modulus (do_div()) or not.
1441 */
1442 if (hweight32(nor->page_size) == 1) {
1443 page_offset = addr & (nor->page_size - 1);
1444 } else {
1445 uint64_t aux = addr;
1446
1447 page_offset = do_div(aux, nor->page_size);
1448 }
1449 /* the size of data remaining on the first page */
1450 page_remain = min_t(size_t,
1451 nor->page_size - page_offset, len - i);
1452
1453 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
1454 addr = spi_nor_s3an_addr_convert(nor, addr);
1455
1456 write_enable(nor);
1457 ret = nor->write(nor, addr, page_remain, buf + i);
1458 if (ret < 0)
1459 goto write_err;
1460 written = ret;
1461
1462 ret = spi_nor_wait_till_ready(nor);
1463 if (ret)
1464 goto write_err;
1465 *retlen += written;
1466 i += written;
1467 if (written != page_remain) {
1468 dev_err(nor->dev,
1469 "While writing %zu bytes written %zd bytes\n",
1470 page_remain, written);
1471 ret = -EIO;
1472 goto write_err;
1473 }
1474 }
1475
1476 write_err:
1477 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1478 return ret;
1479 }
1480
1481 /**
1482 * macronix_quad_enable() - set QE bit in Status Register.
1483 * @nor: pointer to a 'struct spi_nor'
1484 *
1485 * Set the Quad Enable (QE) bit in the Status Register.
1486 *
1487 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1488 *
1489 * Return: 0 on success, -errno otherwise.
1490 */
1491 static int macronix_quad_enable(struct spi_nor *nor)
1492 {
1493 int ret, val;
1494
1495 val = read_sr(nor);
1496 if (val < 0)
1497 return val;
1498 if (val & SR_QUAD_EN_MX)
1499 return 0;
1500
1501 write_enable(nor);
1502
1503 write_sr(nor, val | SR_QUAD_EN_MX);
1504
1505 ret = spi_nor_wait_till_ready(nor);
1506 if (ret)
1507 return ret;
1508
1509 ret = read_sr(nor);
1510 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1511 dev_err(nor->dev, "Macronix Quad bit not set\n");
1512 return -EINVAL;
1513 }
1514
1515 return 0;
1516 }
1517
1518 /*
1519 * Write status Register and configuration register with 2 bytes
1520 * The first byte will be written to the status register, while the
1521 * second byte will be written to the configuration register.
1522 * Return negative if error occurred.
1523 */
1524 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1525 {
1526 ssize_t ret;
1527
1528 write_enable(nor);
1529
1530 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1531 if (ret < 0) {
1532 dev_err(nor->dev,
1533 "error while writing configuration register\n");
1534 return -EINVAL;
1535 }
1536
1537 ret = spi_nor_wait_till_ready(nor);
1538 if (ret) {
1539 dev_err(nor->dev,
1540 "timeout while writing configuration register\n");
1541 return ret;
1542 }
1543
1544 return 0;
1545 }
1546
1547 /**
1548 * spansion_quad_enable() - set QE bit in Configuraiton Register.
1549 * @nor: pointer to a 'struct spi_nor'
1550 *
1551 * Set the Quad Enable (QE) bit in the Configuration Register.
1552 * This function is kept for legacy purpose because it has been used for a
1553 * long time without anybody complaining but it should be considered as
1554 * deprecated and maybe buggy.
1555 * First, this function doesn't care about the previous values of the Status
1556 * and Configuration Registers when it sets the QE bit (bit 1) in the
1557 * Configuration Register: all other bits are cleared, which may have unwanted
1558 * side effects like removing some block protections.
1559 * Secondly, it uses the Read Configuration Register (35h) instruction though
1560 * some very old and few memories don't support this instruction. If a pull-up
1561 * resistor is present on the MISO/IO1 line, we might still be able to pass the
1562 * "read back" test because the QSPI memory doesn't recognize the command,
1563 * so leaves the MISO/IO1 line state unchanged, hence read_cr() returns 0xFF.
1564 *
1565 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1566 * memories.
1567 *
1568 * Return: 0 on success, -errno otherwise.
1569 */
1570 static int spansion_quad_enable(struct spi_nor *nor)
1571 {
1572 u8 sr_cr[2] = {0, CR_QUAD_EN_SPAN};
1573 int ret;
1574
1575 ret = write_sr_cr(nor, sr_cr);
1576 if (ret)
1577 return ret;
1578
1579 /* read back and check it */
1580 ret = read_cr(nor);
1581 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1582 dev_err(nor->dev, "Spansion Quad bit not set\n");
1583 return -EINVAL;
1584 }
1585
1586 return 0;
1587 }
1588
1589 /**
1590 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1591 * @nor: pointer to a 'struct spi_nor'
1592 *
1593 * Set the Quad Enable (QE) bit in the Configuration Register.
1594 * This function should be used with QSPI memories not supporting the Read
1595 * Configuration Register (35h) instruction.
1596 *
1597 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1598 * memories.
1599 *
1600 * Return: 0 on success, -errno otherwise.
1601 */
1602 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1603 {
1604 u8 sr_cr[2];
1605 int ret;
1606
1607 /* Keep the current value of the Status Register. */
1608 ret = read_sr(nor);
1609 if (ret < 0) {
1610 dev_err(nor->dev, "error while reading status register\n");
1611 return -EINVAL;
1612 }
1613 sr_cr[0] = ret;
1614 sr_cr[1] = CR_QUAD_EN_SPAN;
1615
1616 return write_sr_cr(nor, sr_cr);
1617 }
1618
1619 /**
1620 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1621 * @nor: pointer to a 'struct spi_nor'
1622 *
1623 * Set the Quad Enable (QE) bit in the Configuration Register.
1624 * This function should be used with QSPI memories supporting the Read
1625 * Configuration Register (35h) instruction.
1626 *
1627 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1628 * memories.
1629 *
1630 * Return: 0 on success, -errno otherwise.
1631 */
1632 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1633 {
1634 struct device *dev = nor->dev;
1635 u8 sr_cr[2];
1636 int ret;
1637
1638 /* Check current Quad Enable bit value. */
1639 ret = read_cr(nor);
1640 if (ret < 0) {
1641 dev_err(dev, "error while reading configuration register\n");
1642 return -EINVAL;
1643 }
1644
1645 if (ret & CR_QUAD_EN_SPAN)
1646 return 0;
1647
1648 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1649
1650 /* Keep the current value of the Status Register. */
1651 ret = read_sr(nor);
1652 if (ret < 0) {
1653 dev_err(dev, "error while reading status register\n");
1654 return -EINVAL;
1655 }
1656 sr_cr[0] = ret;
1657
1658 ret = write_sr_cr(nor, sr_cr);
1659 if (ret)
1660 return ret;
1661
1662 /* Read back and check it. */
1663 ret = read_cr(nor);
1664 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1665 dev_err(nor->dev, "Spansion Quad bit not set\n");
1666 return -EINVAL;
1667 }
1668
1669 return 0;
1670 }
1671
1672 /**
1673 * sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1674 * @nor: pointer to a 'struct spi_nor'
1675 *
1676 * Set the Quad Enable (QE) bit in the Status Register 2.
1677 *
1678 * This is one of the procedures to set the QE bit described in the SFDP
1679 * (JESD216 rev B) specification but no manufacturer using this procedure has
1680 * been identified yet, hence the name of the function.
1681 *
1682 * Return: 0 on success, -errno otherwise.
1683 */
1684 static int sr2_bit7_quad_enable(struct spi_nor *nor)
1685 {
1686 u8 sr2;
1687 int ret;
1688
1689 /* Check current Quad Enable bit value. */
1690 ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
1691 if (ret)
1692 return ret;
1693 if (sr2 & SR2_QUAD_EN_BIT7)
1694 return 0;
1695
1696 /* Update the Quad Enable bit. */
1697 sr2 |= SR2_QUAD_EN_BIT7;
1698
1699 write_enable(nor);
1700
1701 ret = nor->write_reg(nor, SPINOR_OP_WRSR2, &sr2, 1);
1702 if (ret < 0) {
1703 dev_err(nor->dev, "error while writing status register 2\n");
1704 return -EINVAL;
1705 }
1706
1707 ret = spi_nor_wait_till_ready(nor);
1708 if (ret < 0) {
1709 dev_err(nor->dev, "timeout while writing status register 2\n");
1710 return ret;
1711 }
1712
1713 /* Read back and check it. */
1714 ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
1715 if (!(ret > 0 && (sr2 & SR2_QUAD_EN_BIT7))) {
1716 dev_err(nor->dev, "SR2 Quad bit not set\n");
1717 return -EINVAL;
1718 }
1719
1720 return 0;
1721 }
1722
1723 static int spi_nor_check(struct spi_nor *nor)
1724 {
1725 if (!nor->dev || !nor->read || !nor->write ||
1726 !nor->read_reg || !nor->write_reg) {
1727 pr_err("spi-nor: please fill all the necessary fields!\n");
1728 return -EINVAL;
1729 }
1730
1731 return 0;
1732 }
1733
1734 static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
1735 {
1736 int ret;
1737 u8 val;
1738
1739 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
1740 if (ret < 0) {
1741 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
1742 return ret;
1743 }
1744
1745 nor->erase_opcode = SPINOR_OP_XSE;
1746 nor->program_opcode = SPINOR_OP_XPP;
1747 nor->read_opcode = SPINOR_OP_READ;
1748 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
1749
1750 /*
1751 * This flashes have a page size of 264 or 528 bytes (known as
1752 * Default addressing mode). It can be changed to a more standard
1753 * Power of two mode where the page size is 256/512. This comes
1754 * with a price: there is 3% less of space, the data is corrupted
1755 * and the page size cannot be changed back to default addressing
1756 * mode.
1757 *
1758 * The current addressing mode can be read from the XRDSR register
1759 * and should not be changed, because is a destructive operation.
1760 */
1761 if (val & XSR_PAGESIZE) {
1762 /* Flash in Power of 2 mode */
1763 nor->page_size = (nor->page_size == 264) ? 256 : 512;
1764 nor->mtd.writebufsize = nor->page_size;
1765 nor->mtd.size = 8 * nor->page_size * info->n_sectors;
1766 nor->mtd.erasesize = 8 * nor->page_size;
1767 } else {
1768 /* Flash in Default addressing mode */
1769 nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
1770 }
1771
1772 return 0;
1773 }
1774
1775 struct spi_nor_read_command {
1776 u8 num_mode_clocks;
1777 u8 num_wait_states;
1778 u8 opcode;
1779 enum spi_nor_protocol proto;
1780 };
1781
1782 struct spi_nor_pp_command {
1783 u8 opcode;
1784 enum spi_nor_protocol proto;
1785 };
1786
1787 enum spi_nor_read_command_index {
1788 SNOR_CMD_READ,
1789 SNOR_CMD_READ_FAST,
1790 SNOR_CMD_READ_1_1_1_DTR,
1791
1792 /* Dual SPI */
1793 SNOR_CMD_READ_1_1_2,
1794 SNOR_CMD_READ_1_2_2,
1795 SNOR_CMD_READ_2_2_2,
1796 SNOR_CMD_READ_1_2_2_DTR,
1797
1798 /* Quad SPI */
1799 SNOR_CMD_READ_1_1_4,
1800 SNOR_CMD_READ_1_4_4,
1801 SNOR_CMD_READ_4_4_4,
1802 SNOR_CMD_READ_1_4_4_DTR,
1803
1804 /* Octo SPI */
1805 SNOR_CMD_READ_1_1_8,
1806 SNOR_CMD_READ_1_8_8,
1807 SNOR_CMD_READ_8_8_8,
1808 SNOR_CMD_READ_1_8_8_DTR,
1809
1810 SNOR_CMD_READ_MAX
1811 };
1812
1813 enum spi_nor_pp_command_index {
1814 SNOR_CMD_PP,
1815
1816 /* Quad SPI */
1817 SNOR_CMD_PP_1_1_4,
1818 SNOR_CMD_PP_1_4_4,
1819 SNOR_CMD_PP_4_4_4,
1820
1821 /* Octo SPI */
1822 SNOR_CMD_PP_1_1_8,
1823 SNOR_CMD_PP_1_8_8,
1824 SNOR_CMD_PP_8_8_8,
1825
1826 SNOR_CMD_PP_MAX
1827 };
1828
1829 struct spi_nor_flash_parameter {
1830 u64 size;
1831 u32 page_size;
1832
1833 struct spi_nor_hwcaps hwcaps;
1834 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
1835 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
1836
1837 int (*quad_enable)(struct spi_nor *nor);
1838 };
1839
1840 static void
1841 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1842 u8 num_mode_clocks,
1843 u8 num_wait_states,
1844 u8 opcode,
1845 enum spi_nor_protocol proto)
1846 {
1847 read->num_mode_clocks = num_mode_clocks;
1848 read->num_wait_states = num_wait_states;
1849 read->opcode = opcode;
1850 read->proto = proto;
1851 }
1852
1853 static void
1854 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1855 u8 opcode,
1856 enum spi_nor_protocol proto)
1857 {
1858 pp->opcode = opcode;
1859 pp->proto = proto;
1860 }
1861
1862 /*
1863 * Serial Flash Discoverable Parameters (SFDP) parsing.
1864 */
1865
1866 /**
1867 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1868 * @nor: pointer to a 'struct spi_nor'
1869 * @addr: offset in the SFDP area to start reading data from
1870 * @len: number of bytes to read
1871 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
1872 *
1873 * Whatever the actual numbers of bytes for address and dummy cycles are
1874 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1875 * followed by a 3-byte address and 8 dummy clock cycles.
1876 *
1877 * Return: 0 on success, -errno otherwise.
1878 */
1879 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1880 size_t len, void *buf)
1881 {
1882 u8 addr_width, read_opcode, read_dummy;
1883 int ret;
1884
1885 read_opcode = nor->read_opcode;
1886 addr_width = nor->addr_width;
1887 read_dummy = nor->read_dummy;
1888
1889 nor->read_opcode = SPINOR_OP_RDSFDP;
1890 nor->addr_width = 3;
1891 nor->read_dummy = 8;
1892
1893 while (len) {
1894 ret = nor->read(nor, addr, len, (u8 *)buf);
1895 if (!ret || ret > len) {
1896 ret = -EIO;
1897 goto read_err;
1898 }
1899 if (ret < 0)
1900 goto read_err;
1901
1902 buf += ret;
1903 addr += ret;
1904 len -= ret;
1905 }
1906 ret = 0;
1907
1908 read_err:
1909 nor->read_opcode = read_opcode;
1910 nor->addr_width = addr_width;
1911 nor->read_dummy = read_dummy;
1912
1913 return ret;
1914 }
1915
1916 /**
1917 * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters.
1918 * @nor: pointer to a 'struct spi_nor'
1919 * @addr: offset in the SFDP area to start reading data from
1920 * @len: number of bytes to read
1921 * @buf: buffer where the SFDP data are copied into
1922 *
1923 * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not
1924 * guaranteed to be dma-safe.
1925 *
1926 * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp()
1927 * otherwise.
1928 */
1929 static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
1930 size_t len, void *buf)
1931 {
1932 void *dma_safe_buf;
1933 int ret;
1934
1935 dma_safe_buf = kmalloc(len, GFP_KERNEL);
1936 if (!dma_safe_buf)
1937 return -ENOMEM;
1938
1939 ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf);
1940 memcpy(buf, dma_safe_buf, len);
1941 kfree(dma_safe_buf);
1942
1943 return ret;
1944 }
1945
1946 struct sfdp_parameter_header {
1947 u8 id_lsb;
1948 u8 minor;
1949 u8 major;
1950 u8 length; /* in double words */
1951 u8 parameter_table_pointer[3]; /* byte address */
1952 u8 id_msb;
1953 };
1954
1955 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
1956 #define SFDP_PARAM_HEADER_PTP(p) \
1957 (((p)->parameter_table_pointer[2] << 16) | \
1958 ((p)->parameter_table_pointer[1] << 8) | \
1959 ((p)->parameter_table_pointer[0] << 0))
1960
1961 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
1962 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
1963
1964 #define SFDP_SIGNATURE 0x50444653U
1965 #define SFDP_JESD216_MAJOR 1
1966 #define SFDP_JESD216_MINOR 0
1967 #define SFDP_JESD216A_MINOR 5
1968 #define SFDP_JESD216B_MINOR 6
1969
1970 struct sfdp_header {
1971 u32 signature; /* Ox50444653U <=> "SFDP" */
1972 u8 minor;
1973 u8 major;
1974 u8 nph; /* 0-base number of parameter headers */
1975 u8 unused;
1976
1977 /* Basic Flash Parameter Table. */
1978 struct sfdp_parameter_header bfpt_header;
1979 };
1980
1981 /* Basic Flash Parameter Table */
1982
1983 /*
1984 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
1985 * They are indexed from 1 but C arrays are indexed from 0.
1986 */
1987 #define BFPT_DWORD(i) ((i) - 1)
1988 #define BFPT_DWORD_MAX 16
1989
1990 /* The first version of JESB216 defined only 9 DWORDs. */
1991 #define BFPT_DWORD_MAX_JESD216 9
1992
1993 /* 1st DWORD. */
1994 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
1995 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
1996 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
1997 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
1998 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
1999 #define BFPT_DWORD1_DTR BIT(19)
2000 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
2001 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
2002 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
2003
2004 /* 5th DWORD. */
2005 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
2006 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
2007
2008 /* 11th DWORD. */
2009 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
2010 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
2011
2012 /* 15th DWORD. */
2013
2014 /*
2015 * (from JESD216 rev B)
2016 * Quad Enable Requirements (QER):
2017 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
2018 * reads based on instruction. DQ3/HOLD# functions are hold during
2019 * instruction phase.
2020 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
2021 * two data bytes where bit 1 of the second byte is one.
2022 * [...]
2023 * Writing only one byte to the status register has the side-effect of
2024 * clearing status register 2, including the QE bit. The 100b code is
2025 * used if writing one byte to the status register does not modify
2026 * status register 2.
2027 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
2028 * one data byte where bit 6 is one.
2029 * [...]
2030 * - 011b: QE is bit 7 of status register 2. It is set via Write status
2031 * register 2 instruction 3Eh with one data byte where bit 7 is one.
2032 * [...]
2033 * The status register 2 is read using instruction 3Fh.
2034 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
2035 * two data bytes where bit 1 of the second byte is one.
2036 * [...]
2037 * In contrast to the 001b code, writing one byte to the status
2038 * register does not modify status register 2.
2039 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
2040 * Read Status instruction 05h. Status register2 is read using
2041 * instruction 35h. QE is set via Writ Status instruction 01h with
2042 * two data bytes where bit 1 of the second byte is one.
2043 * [...]
2044 */
2045 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
2046 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
2047 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
2048 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
2049 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
2050 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
2051 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
2052
2053 struct sfdp_bfpt {
2054 u32 dwords[BFPT_DWORD_MAX];
2055 };
2056
2057 /* Fast Read settings. */
2058
2059 static inline void
2060 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
2061 u16 half,
2062 enum spi_nor_protocol proto)
2063 {
2064 read->num_mode_clocks = (half >> 5) & 0x07;
2065 read->num_wait_states = (half >> 0) & 0x1f;
2066 read->opcode = (half >> 8) & 0xff;
2067 read->proto = proto;
2068 }
2069
2070 struct sfdp_bfpt_read {
2071 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
2072 u32 hwcaps;
2073
2074 /*
2075 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
2076 * whether the Fast Read x-y-z command is supported.
2077 */
2078 u32 supported_dword;
2079 u32 supported_bit;
2080
2081 /*
2082 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
2083 * encodes the op code, the number of mode clocks and the number of wait
2084 * states to be used by Fast Read x-y-z command.
2085 */
2086 u32 settings_dword;
2087 u32 settings_shift;
2088
2089 /* The SPI protocol for this Fast Read x-y-z command. */
2090 enum spi_nor_protocol proto;
2091 };
2092
2093 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
2094 /* Fast Read 1-1-2 */
2095 {
2096 SNOR_HWCAPS_READ_1_1_2,
2097 BFPT_DWORD(1), BIT(16), /* Supported bit */
2098 BFPT_DWORD(4), 0, /* Settings */
2099 SNOR_PROTO_1_1_2,
2100 },
2101
2102 /* Fast Read 1-2-2 */
2103 {
2104 SNOR_HWCAPS_READ_1_2_2,
2105 BFPT_DWORD(1), BIT(20), /* Supported bit */
2106 BFPT_DWORD(4), 16, /* Settings */
2107 SNOR_PROTO_1_2_2,
2108 },
2109
2110 /* Fast Read 2-2-2 */
2111 {
2112 SNOR_HWCAPS_READ_2_2_2,
2113 BFPT_DWORD(5), BIT(0), /* Supported bit */
2114 BFPT_DWORD(6), 16, /* Settings */
2115 SNOR_PROTO_2_2_2,
2116 },
2117
2118 /* Fast Read 1-1-4 */
2119 {
2120 SNOR_HWCAPS_READ_1_1_4,
2121 BFPT_DWORD(1), BIT(22), /* Supported bit */
2122 BFPT_DWORD(3), 16, /* Settings */
2123 SNOR_PROTO_1_1_4,
2124 },
2125
2126 /* Fast Read 1-4-4 */
2127 {
2128 SNOR_HWCAPS_READ_1_4_4,
2129 BFPT_DWORD(1), BIT(21), /* Supported bit */
2130 BFPT_DWORD(3), 0, /* Settings */
2131 SNOR_PROTO_1_4_4,
2132 },
2133
2134 /* Fast Read 4-4-4 */
2135 {
2136 SNOR_HWCAPS_READ_4_4_4,
2137 BFPT_DWORD(5), BIT(4), /* Supported bit */
2138 BFPT_DWORD(7), 16, /* Settings */
2139 SNOR_PROTO_4_4_4,
2140 },
2141 };
2142
2143 struct sfdp_bfpt_erase {
2144 /*
2145 * The half-word at offset <shift> in DWORD <dwoard> encodes the
2146 * op code and erase sector size to be used by Sector Erase commands.
2147 */
2148 u32 dword;
2149 u32 shift;
2150 };
2151
2152 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
2153 /* Erase Type 1 in DWORD8 bits[15:0] */
2154 {BFPT_DWORD(8), 0},
2155
2156 /* Erase Type 2 in DWORD8 bits[31:16] */
2157 {BFPT_DWORD(8), 16},
2158
2159 /* Erase Type 3 in DWORD9 bits[15:0] */
2160 {BFPT_DWORD(9), 0},
2161
2162 /* Erase Type 4 in DWORD9 bits[31:16] */
2163 {BFPT_DWORD(9), 16},
2164 };
2165
2166 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
2167
2168 /**
2169 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
2170 * @nor: pointer to a 'struct spi_nor'
2171 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
2172 * the Basic Flash Parameter Table length and version
2173 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2174 * filled
2175 *
2176 * The Basic Flash Parameter Table is the main and only mandatory table as
2177 * defined by the SFDP (JESD216) specification.
2178 * It provides us with the total size (memory density) of the data array and
2179 * the number of address bytes for Fast Read, Page Program and Sector Erase
2180 * commands.
2181 * For Fast READ commands, it also gives the number of mode clock cycles and
2182 * wait states (regrouped in the number of dummy clock cycles) for each
2183 * supported instruction op code.
2184 * For Page Program, the page size is now available since JESD216 rev A, however
2185 * the supported instruction op codes are still not provided.
2186 * For Sector Erase commands, this table stores the supported instruction op
2187 * codes and the associated sector sizes.
2188 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
2189 * rev A. The QER bits encode the manufacturer dependent procedure to be
2190 * executed to set the Quad Enable (QE) bit in some internal register of the
2191 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
2192 * sending any Quad SPI command to the memory. Actually, setting the QE bit
2193 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
2194 * and IO3 hence enabling 4 (Quad) I/O lines.
2195 *
2196 * Return: 0 on success, -errno otherwise.
2197 */
2198 static int spi_nor_parse_bfpt(struct spi_nor *nor,
2199 const struct sfdp_parameter_header *bfpt_header,
2200 struct spi_nor_flash_parameter *params)
2201 {
2202 struct mtd_info *mtd = &nor->mtd;
2203 struct sfdp_bfpt bfpt;
2204 size_t len;
2205 int i, cmd, err;
2206 u32 addr;
2207 u16 half;
2208
2209 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
2210 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
2211 return -EINVAL;
2212
2213 /* Read the Basic Flash Parameter Table. */
2214 len = min_t(size_t, sizeof(bfpt),
2215 bfpt_header->length * sizeof(u32));
2216 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
2217 memset(&bfpt, 0, sizeof(bfpt));
2218 err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt);
2219 if (err < 0)
2220 return err;
2221
2222 /* Fix endianness of the BFPT DWORDs. */
2223 for (i = 0; i < BFPT_DWORD_MAX; i++)
2224 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
2225
2226 /* Number of address bytes. */
2227 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
2228 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
2229 nor->addr_width = 3;
2230 break;
2231
2232 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
2233 nor->addr_width = 4;
2234 break;
2235
2236 default:
2237 break;
2238 }
2239
2240 /* Flash Memory Density (in bits). */
2241 params->size = bfpt.dwords[BFPT_DWORD(2)];
2242 if (params->size & BIT(31)) {
2243 params->size &= ~BIT(31);
2244
2245 /*
2246 * Prevent overflows on params->size. Anyway, a NOR of 2^64
2247 * bits is unlikely to exist so this error probably means
2248 * the BFPT we are reading is corrupted/wrong.
2249 */
2250 if (params->size > 63)
2251 return -EINVAL;
2252
2253 params->size = 1ULL << params->size;
2254 } else {
2255 params->size++;
2256 }
2257 params->size >>= 3; /* Convert to bytes. */
2258
2259 /* Fast Read settings. */
2260 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
2261 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
2262 struct spi_nor_read_command *read;
2263
2264 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
2265 params->hwcaps.mask &= ~rd->hwcaps;
2266 continue;
2267 }
2268
2269 params->hwcaps.mask |= rd->hwcaps;
2270 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
2271 read = &params->reads[cmd];
2272 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
2273 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
2274 }
2275
2276 /* Sector Erase settings. */
2277 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
2278 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
2279 u32 erasesize;
2280 u8 opcode;
2281
2282 half = bfpt.dwords[er->dword] >> er->shift;
2283 erasesize = half & 0xff;
2284
2285 /* erasesize == 0 means this Erase Type is not supported. */
2286 if (!erasesize)
2287 continue;
2288
2289 erasesize = 1U << erasesize;
2290 opcode = (half >> 8) & 0xff;
2291 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2292 if (erasesize == SZ_4K) {
2293 nor->erase_opcode = opcode;
2294 mtd->erasesize = erasesize;
2295 break;
2296 }
2297 #endif
2298 if (!mtd->erasesize || mtd->erasesize < erasesize) {
2299 nor->erase_opcode = opcode;
2300 mtd->erasesize = erasesize;
2301 }
2302 }
2303
2304 /* Stop here if not JESD216 rev A or later. */
2305 if (bfpt_header->length < BFPT_DWORD_MAX)
2306 return 0;
2307
2308 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
2309 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
2310 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
2311 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
2312 params->page_size = 1U << params->page_size;
2313
2314 /* Quad Enable Requirements. */
2315 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
2316 case BFPT_DWORD15_QER_NONE:
2317 params->quad_enable = NULL;
2318 break;
2319
2320 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
2321 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
2322 params->quad_enable = spansion_no_read_cr_quad_enable;
2323 break;
2324
2325 case BFPT_DWORD15_QER_SR1_BIT6:
2326 params->quad_enable = macronix_quad_enable;
2327 break;
2328
2329 case BFPT_DWORD15_QER_SR2_BIT7:
2330 params->quad_enable = sr2_bit7_quad_enable;
2331 break;
2332
2333 case BFPT_DWORD15_QER_SR2_BIT1:
2334 params->quad_enable = spansion_read_cr_quad_enable;
2335 break;
2336
2337 default:
2338 return -EINVAL;
2339 }
2340
2341 return 0;
2342 }
2343
2344 /**
2345 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
2346 * @nor: pointer to a 'struct spi_nor'
2347 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2348 * filled
2349 *
2350 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
2351 * specification. This is a standard which tends to supported by almost all
2352 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
2353 * runtime the main parameters needed to perform basic SPI flash operations such
2354 * as Fast Read, Page Program or Sector Erase commands.
2355 *
2356 * Return: 0 on success, -errno otherwise.
2357 */
2358 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2359 struct spi_nor_flash_parameter *params)
2360 {
2361 const struct sfdp_parameter_header *param_header, *bfpt_header;
2362 struct sfdp_parameter_header *param_headers = NULL;
2363 struct sfdp_header header;
2364 struct device *dev = nor->dev;
2365 size_t psize;
2366 int i, err;
2367
2368 /* Get the SFDP header. */
2369 err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header);
2370 if (err < 0)
2371 return err;
2372
2373 /* Check the SFDP header version. */
2374 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
2375 header.major != SFDP_JESD216_MAJOR)
2376 return -EINVAL;
2377
2378 /*
2379 * Verify that the first and only mandatory parameter header is a
2380 * Basic Flash Parameter Table header as specified in JESD216.
2381 */
2382 bfpt_header = &header.bfpt_header;
2383 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
2384 bfpt_header->major != SFDP_JESD216_MAJOR)
2385 return -EINVAL;
2386
2387 /*
2388 * Allocate memory then read all parameter headers with a single
2389 * Read SFDP command. These parameter headers will actually be parsed
2390 * twice: a first time to get the latest revision of the basic flash
2391 * parameter table, then a second time to handle the supported optional
2392 * tables.
2393 * Hence we read the parameter headers once for all to reduce the
2394 * processing time. Also we use kmalloc() instead of devm_kmalloc()
2395 * because we don't need to keep these parameter headers: the allocated
2396 * memory is always released with kfree() before exiting this function.
2397 */
2398 if (header.nph) {
2399 psize = header.nph * sizeof(*param_headers);
2400
2401 param_headers = kmalloc(psize, GFP_KERNEL);
2402 if (!param_headers)
2403 return -ENOMEM;
2404
2405 err = spi_nor_read_sfdp(nor, sizeof(header),
2406 psize, param_headers);
2407 if (err < 0) {
2408 dev_err(dev, "failed to read SFDP parameter headers\n");
2409 goto exit;
2410 }
2411 }
2412
2413 /*
2414 * Check other parameter headers to get the latest revision of
2415 * the basic flash parameter table.
2416 */
2417 for (i = 0; i < header.nph; i++) {
2418 param_header = &param_headers[i];
2419
2420 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
2421 param_header->major == SFDP_JESD216_MAJOR &&
2422 (param_header->minor > bfpt_header->minor ||
2423 (param_header->minor == bfpt_header->minor &&
2424 param_header->length > bfpt_header->length)))
2425 bfpt_header = param_header;
2426 }
2427
2428 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
2429 if (err)
2430 goto exit;
2431
2432 /* Parse other parameter headers. */
2433 for (i = 0; i < header.nph; i++) {
2434 param_header = &param_headers[i];
2435
2436 switch (SFDP_PARAM_HEADER_ID(param_header)) {
2437 case SFDP_SECTOR_MAP_ID:
2438 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n");
2439 break;
2440
2441 default:
2442 break;
2443 }
2444
2445 if (err)
2446 goto exit;
2447 }
2448
2449 exit:
2450 kfree(param_headers);
2451 return err;
2452 }
2453
2454 static int spi_nor_init_params(struct spi_nor *nor,
2455 const struct flash_info *info,
2456 struct spi_nor_flash_parameter *params)
2457 {
2458 /* Set legacy flash parameters as default. */
2459 memset(params, 0, sizeof(*params));
2460
2461 /* Set SPI NOR sizes. */
2462 params->size = (u64)info->sector_size * info->n_sectors;
2463 params->page_size = info->page_size;
2464
2465 /* (Fast) Read settings. */
2466 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2467 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
2468 0, 0, SPINOR_OP_READ,
2469 SNOR_PROTO_1_1_1);
2470
2471 if (!(info->flags & SPI_NOR_NO_FR)) {
2472 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2473 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
2474 0, 8, SPINOR_OP_READ_FAST,
2475 SNOR_PROTO_1_1_1);
2476 }
2477
2478 if (info->flags & SPI_NOR_DUAL_READ) {
2479 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2480 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
2481 0, 8, SPINOR_OP_READ_1_1_2,
2482 SNOR_PROTO_1_1_2);
2483 }
2484
2485 if (info->flags & SPI_NOR_QUAD_READ) {
2486 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2487 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
2488 0, 8, SPINOR_OP_READ_1_1_4,
2489 SNOR_PROTO_1_1_4);
2490 }
2491
2492 /* Page Program settings. */
2493 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2494 spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
2495 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2496
2497 /* Select the procedure to set the Quad Enable bit. */
2498 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
2499 SNOR_HWCAPS_PP_QUAD)) {
2500 switch (JEDEC_MFR(info)) {
2501 case SNOR_MFR_MACRONIX:
2502 params->quad_enable = macronix_quad_enable;
2503 break;
2504
2505 case SNOR_MFR_MICRON:
2506 break;
2507
2508 default:
2509 /* Kept only for backward compatibility purpose. */
2510 params->quad_enable = spansion_quad_enable;
2511 break;
2512 }
2513
2514 /*
2515 * Some manufacturer like GigaDevice may use different
2516 * bit to set QE on different memories, so the MFR can't
2517 * indicate the quad_enable method for this case, we need
2518 * set it in flash info list.
2519 */
2520 if (info->quad_enable)
2521 params->quad_enable = info->quad_enable;
2522 }
2523
2524 /* Override the parameters with data read from SFDP tables. */
2525 nor->addr_width = 0;
2526 nor->mtd.erasesize = 0;
2527 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
2528 !(info->flags & SPI_NOR_SKIP_SFDP)) {
2529 struct spi_nor_flash_parameter sfdp_params;
2530
2531 memcpy(&sfdp_params, params, sizeof(sfdp_params));
2532 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2533 nor->addr_width = 0;
2534 nor->mtd.erasesize = 0;
2535 } else {
2536 memcpy(params, &sfdp_params, sizeof(*params));
2537 }
2538 }
2539
2540 return 0;
2541 }
2542
2543 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2544 {
2545 size_t i;
2546
2547 for (i = 0; i < size; i++)
2548 if (table[i][0] == (int)hwcaps)
2549 return table[i][1];
2550
2551 return -EINVAL;
2552 }
2553
2554 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2555 {
2556 static const int hwcaps_read2cmd[][2] = {
2557 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2558 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2559 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2560 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2561 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2562 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2563 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2564 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2565 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2566 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2567 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2568 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2569 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2570 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2571 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2572 };
2573
2574 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2575 ARRAY_SIZE(hwcaps_read2cmd));
2576 }
2577
2578 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2579 {
2580 static const int hwcaps_pp2cmd[][2] = {
2581 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2582 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2583 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2584 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2585 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2586 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2587 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2588 };
2589
2590 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2591 ARRAY_SIZE(hwcaps_pp2cmd));
2592 }
2593
2594 static int spi_nor_select_read(struct spi_nor *nor,
2595 const struct spi_nor_flash_parameter *params,
2596 u32 shared_hwcaps)
2597 {
2598 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2599 const struct spi_nor_read_command *read;
2600
2601 if (best_match < 0)
2602 return -EINVAL;
2603
2604 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2605 if (cmd < 0)
2606 return -EINVAL;
2607
2608 read = &params->reads[cmd];
2609 nor->read_opcode = read->opcode;
2610 nor->read_proto = read->proto;
2611
2612 /*
2613 * In the spi-nor framework, we don't need to make the difference
2614 * between mode clock cycles and wait state clock cycles.
2615 * Indeed, the value of the mode clock cycles is used by a QSPI
2616 * flash memory to know whether it should enter or leave its 0-4-4
2617 * (Continuous Read / XIP) mode.
2618 * eXecution In Place is out of the scope of the mtd sub-system.
2619 * Hence we choose to merge both mode and wait state clock cycles
2620 * into the so called dummy clock cycles.
2621 */
2622 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2623 return 0;
2624 }
2625
2626 static int spi_nor_select_pp(struct spi_nor *nor,
2627 const struct spi_nor_flash_parameter *params,
2628 u32 shared_hwcaps)
2629 {
2630 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2631 const struct spi_nor_pp_command *pp;
2632
2633 if (best_match < 0)
2634 return -EINVAL;
2635
2636 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2637 if (cmd < 0)
2638 return -EINVAL;
2639
2640 pp = &params->page_programs[cmd];
2641 nor->program_opcode = pp->opcode;
2642 nor->write_proto = pp->proto;
2643 return 0;
2644 }
2645
2646 static int spi_nor_select_erase(struct spi_nor *nor,
2647 const struct flash_info *info)
2648 {
2649 struct mtd_info *mtd = &nor->mtd;
2650
2651 /* Do nothing if already configured from SFDP. */
2652 if (mtd->erasesize)
2653 return 0;
2654
2655 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2656 /* prefer "small sector" erase if possible */
2657 if (info->flags & SECT_4K) {
2658 nor->erase_opcode = SPINOR_OP_BE_4K;
2659 mtd->erasesize = 4096;
2660 } else if (info->flags & SECT_4K_PMC) {
2661 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
2662 mtd->erasesize = 4096;
2663 } else
2664 #endif
2665 {
2666 nor->erase_opcode = SPINOR_OP_SE;
2667 mtd->erasesize = info->sector_size;
2668 }
2669 return 0;
2670 }
2671
2672 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
2673 const struct spi_nor_flash_parameter *params,
2674 const struct spi_nor_hwcaps *hwcaps)
2675 {
2676 u32 ignored_mask, shared_mask;
2677 bool enable_quad_io;
2678 int err;
2679
2680 /*
2681 * Keep only the hardware capabilities supported by both the SPI
2682 * controller and the SPI flash memory.
2683 */
2684 shared_mask = hwcaps->mask & params->hwcaps.mask;
2685
2686 /* SPI n-n-n protocols are not supported yet. */
2687 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
2688 SNOR_HWCAPS_READ_4_4_4 |
2689 SNOR_HWCAPS_READ_8_8_8 |
2690 SNOR_HWCAPS_PP_4_4_4 |
2691 SNOR_HWCAPS_PP_8_8_8);
2692 if (shared_mask & ignored_mask) {
2693 dev_dbg(nor->dev,
2694 "SPI n-n-n protocols are not supported yet.\n");
2695 shared_mask &= ~ignored_mask;
2696 }
2697
2698 /* Select the (Fast) Read command. */
2699 err = spi_nor_select_read(nor, params, shared_mask);
2700 if (err) {
2701 dev_err(nor->dev,
2702 "can't select read settings supported by both the SPI controller and memory.\n");
2703 return err;
2704 }
2705
2706 /* Select the Page Program command. */
2707 err = spi_nor_select_pp(nor, params, shared_mask);
2708 if (err) {
2709 dev_err(nor->dev,
2710 "can't select write settings supported by both the SPI controller and memory.\n");
2711 return err;
2712 }
2713
2714 /* Select the Sector Erase command. */
2715 err = spi_nor_select_erase(nor, info);
2716 if (err) {
2717 dev_err(nor->dev,
2718 "can't select erase settings supported by both the SPI controller and memory.\n");
2719 return err;
2720 }
2721
2722 /* Enable Quad I/O if needed. */
2723 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2724 spi_nor_get_protocol_width(nor->write_proto) == 4);
2725 if (enable_quad_io && params->quad_enable)
2726 nor->quad_enable = params->quad_enable;
2727 else
2728 nor->quad_enable = NULL;
2729
2730 return 0;
2731 }
2732
2733 static int spi_nor_init(struct spi_nor *nor)
2734 {
2735 int err;
2736
2737 /*
2738 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
2739 * with the software protection bits set
2740 */
2741 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
2742 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
2743 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
2744 nor->info->flags & SPI_NOR_HAS_LOCK) {
2745 write_enable(nor);
2746 write_sr(nor, 0);
2747 spi_nor_wait_till_ready(nor);
2748 }
2749
2750 if (nor->quad_enable) {
2751 err = nor->quad_enable(nor);
2752 if (err) {
2753 dev_err(nor->dev, "quad mode not supported\n");
2754 return err;
2755 }
2756 }
2757
2758 if ((nor->addr_width == 4) &&
2759 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
2760 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
2761 /*
2762 * If the RESET# pin isn't hooked up properly, or the system
2763 * otherwise doesn't perform a reset command in the boot
2764 * sequence, it's impossible to 100% protect against unexpected
2765 * reboots (e.g., crashes). Warn the user (or hopefully, system
2766 * designer) that this is bad.
2767 */
2768 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
2769 "enabling reset hack; may not recover from unexpected reboots\n");
2770 set_4byte(nor, nor->info, 1);
2771 }
2772
2773 return 0;
2774 }
2775
2776 /* mtd resume handler */
2777 static void spi_nor_resume(struct mtd_info *mtd)
2778 {
2779 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2780 struct device *dev = nor->dev;
2781 int ret;
2782
2783 /* re-initialize the nor chip */
2784 ret = spi_nor_init(nor);
2785 if (ret)
2786 dev_err(dev, "resume() failed\n");
2787 }
2788
2789 void spi_nor_restore(struct spi_nor *nor)
2790 {
2791 /* restore the addressing mode */
2792 if ((nor->addr_width == 4) &&
2793 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
2794 !(nor->info->flags & SPI_NOR_4B_OPCODES) &&
2795 (nor->flags & SNOR_F_BROKEN_RESET))
2796 set_4byte(nor, nor->info, 0);
2797 }
2798 EXPORT_SYMBOL_GPL(spi_nor_restore);
2799
2800 int spi_nor_scan(struct spi_nor *nor, const char *name,
2801 const struct spi_nor_hwcaps *hwcaps)
2802 {
2803 struct spi_nor_flash_parameter params;
2804 const struct flash_info *info = NULL;
2805 struct device *dev = nor->dev;
2806 struct mtd_info *mtd = &nor->mtd;
2807 struct device_node *np = spi_nor_get_flash_node(nor);
2808 int ret;
2809 int i;
2810
2811 ret = spi_nor_check(nor);
2812 if (ret)
2813 return ret;
2814
2815 /* Reset SPI protocol for all commands. */
2816 nor->reg_proto = SNOR_PROTO_1_1_1;
2817 nor->read_proto = SNOR_PROTO_1_1_1;
2818 nor->write_proto = SNOR_PROTO_1_1_1;
2819
2820 if (name)
2821 info = spi_nor_match_id(name);
2822 /* Try to auto-detect if chip name wasn't specified or not found */
2823 if (!info)
2824 info = spi_nor_read_id(nor);
2825 if (IS_ERR_OR_NULL(info))
2826 return -ENOENT;
2827
2828 /*
2829 * If caller has specified name of flash model that can normally be
2830 * detected using JEDEC, let's verify it.
2831 */
2832 if (name && info->id_len) {
2833 const struct flash_info *jinfo;
2834
2835 jinfo = spi_nor_read_id(nor);
2836 if (IS_ERR(jinfo)) {
2837 return PTR_ERR(jinfo);
2838 } else if (jinfo != info) {
2839 /*
2840 * JEDEC knows better, so overwrite platform ID. We
2841 * can't trust partitions any longer, but we'll let
2842 * mtd apply them anyway, since some partitions may be
2843 * marked read-only, and we don't want to lose that
2844 * information, even if it's not 100% accurate.
2845 */
2846 dev_warn(dev, "found %s, expected %s\n",
2847 jinfo->name, info->name);
2848 info = jinfo;
2849 }
2850 }
2851
2852 mutex_init(&nor->lock);
2853
2854 /*
2855 * Make sure the XSR_RDY flag is set before calling
2856 * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
2857 * with Atmel spi-nor
2858 */
2859 if (info->flags & SPI_S3AN)
2860 nor->flags |= SNOR_F_READY_XSR_RDY;
2861
2862 /* Parse the Serial Flash Discoverable Parameters table. */
2863 ret = spi_nor_init_params(nor, info, &params);
2864 if (ret)
2865 return ret;
2866
2867 if (!mtd->name)
2868 mtd->name = dev_name(dev);
2869 mtd->priv = nor;
2870 mtd->type = MTD_NORFLASH;
2871 mtd->writesize = 1;
2872 mtd->flags = MTD_CAP_NORFLASH;
2873 mtd->size = params.size;
2874 mtd->_erase = spi_nor_erase;
2875 mtd->_read = spi_nor_read;
2876 mtd->_resume = spi_nor_resume;
2877
2878 /* NOR protection support for STmicro/Micron chips and similar */
2879 if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
2880 info->flags & SPI_NOR_HAS_LOCK) {
2881 nor->flash_lock = stm_lock;
2882 nor->flash_unlock = stm_unlock;
2883 nor->flash_is_locked = stm_is_locked;
2884 }
2885
2886 if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
2887 mtd->_lock = spi_nor_lock;
2888 mtd->_unlock = spi_nor_unlock;
2889 mtd->_is_locked = spi_nor_is_locked;
2890 }
2891
2892 /* sst nor chips use AAI word program */
2893 if (info->flags & SST_WRITE)
2894 mtd->_write = sst_write;
2895 else
2896 mtd->_write = spi_nor_write;
2897
2898 if (info->flags & USE_FSR)
2899 nor->flags |= SNOR_F_USE_FSR;
2900 if (info->flags & SPI_NOR_HAS_TB)
2901 nor->flags |= SNOR_F_HAS_SR_TB;
2902 if (info->flags & NO_CHIP_ERASE)
2903 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2904 if (info->flags & USE_CLSR)
2905 nor->flags |= SNOR_F_USE_CLSR;
2906
2907 if (info->flags & SPI_NOR_NO_ERASE)
2908 mtd->flags |= MTD_NO_ERASE;
2909
2910 mtd->dev.parent = dev;
2911 nor->page_size = params.page_size;
2912 mtd->writebufsize = nor->page_size;
2913
2914 if (np) {
2915 /* If we were instantiated by DT, use it */
2916 if (of_property_read_bool(np, "m25p,fast-read"))
2917 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2918 else
2919 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2920 } else {
2921 /* If we weren't instantiated by DT, default to fast-read */
2922 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2923 }
2924
2925 if (of_property_read_bool(np, "broken-flash-reset"))
2926 nor->flags |= SNOR_F_BROKEN_RESET;
2927
2928 /* Some devices cannot do fast-read, no matter what DT tells us */
2929 if (info->flags & SPI_NOR_NO_FR)
2930 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2931
2932 /*
2933 * Configure the SPI memory:
2934 * - select op codes for (Fast) Read, Page Program and Sector Erase.
2935 * - set the number of dummy cycles (mode cycles + wait states).
2936 * - set the SPI protocols for register and memory accesses.
2937 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
2938 */
2939 ret = spi_nor_setup(nor, info, &params, hwcaps);
2940 if (ret)
2941 return ret;
2942
2943 if (nor->addr_width) {
2944 /* already configured from SFDP */
2945 } else if (info->addr_width) {
2946 nor->addr_width = info->addr_width;
2947 } else if (mtd->size > 0x1000000) {
2948 /* enable 4-byte addressing if the device exceeds 16MiB */
2949 nor->addr_width = 4;
2950 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
2951 info->flags & SPI_NOR_4B_OPCODES)
2952 spi_nor_set_4byte_opcodes(nor, info);
2953 } else {
2954 nor->addr_width = 3;
2955 }
2956
2957 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2958 dev_err(dev, "address width is too large: %u\n",
2959 nor->addr_width);
2960 return -EINVAL;
2961 }
2962
2963 if (info->flags & SPI_S3AN) {
2964 ret = s3an_nor_scan(info, nor);
2965 if (ret)
2966 return ret;
2967 }
2968
2969 /* Send all the required SPI flash commands to initialize device */
2970 nor->info = info;
2971 ret = spi_nor_init(nor);
2972 if (ret)
2973 return ret;
2974
2975 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
2976 (long long)mtd->size >> 10);
2977
2978 dev_dbg(dev,
2979 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
2980 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
2981 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
2982 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
2983
2984 if (mtd->numeraseregions)
2985 for (i = 0; i < mtd->numeraseregions; i++)
2986 dev_dbg(dev,
2987 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
2988 ".erasesize = 0x%.8x (%uKiB), "
2989 ".numblocks = %d }\n",
2990 i, (long long)mtd->eraseregions[i].offset,
2991 mtd->eraseregions[i].erasesize,
2992 mtd->eraseregions[i].erasesize / 1024,
2993 mtd->eraseregions[i].numblocks);
2994 return 0;
2995 }
2996 EXPORT_SYMBOL_GPL(spi_nor_scan);
2997
2998 static const struct flash_info *spi_nor_match_id(const char *name)
2999 {
3000 const struct flash_info *id = spi_nor_ids;
3001
3002 while (id->name) {
3003 if (!strcmp(name, id->name))
3004 return id;
3005 id++;
3006 }
3007 return NULL;
3008 }
3009
3010 MODULE_LICENSE("GPL");
3011 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
3012 MODULE_AUTHOR("Mike Lavender");
3013 MODULE_DESCRIPTION("framework for SPI NOR");
Linux with added FPC-III support