drivers/net/can/mscan/mpc5xxx_can.c

   1 /*
   2  * CAN bus driver for the Freescale MPC5xxx embedded CPU.
   3  *
   4  * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
   5  *                         Varma Electronics Oy
   6  * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
   7  * Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the version 2 of the GNU General Public License
  11  * as published by the Free Software Foundation
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/can/dev.h>
  28 #include <linux/of_platform.h>
  29 #include <sysdev/fsl_soc.h>
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32 #include <asm/mpc52xx.h>
  33
  34 #include "mscan.h"
  35
  36 #define DRV_NAME "mpc5xxx_can"
  37
  38 struct mpc5xxx_can_data {
  39         unsigned int type;
  40         u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name,
  41                          int *mscan_clksrc);
  42         void (*put_clock)(struct platform_device *ofdev);
  43 };
  44
  45 #ifdef CONFIG_PPC_MPC52xx
  46 static const struct of_device_id mpc52xx_cdm_ids[] = {
  47         { .compatible = "fsl,mpc5200-cdm", },
  48         {}
  49 };
  50
  51 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
  52                                  const char *clock_name, int *mscan_clksrc)
  53 {
  54         unsigned int pvr;
  55         struct mpc52xx_cdm  __iomem *cdm;
  56         struct device_node *np_cdm;
  57         unsigned int freq;
  58         u32 val;
  59
  60         pvr = mfspr(SPRN_PVR);
  61
  62         /*
  63          * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
  64          * (IP_CLK) can be selected as MSCAN clock source. According to
  65          * the MPC5200 user's manual, the oscillator clock is the better
  66          * choice as it has less jitter. For this reason, it is selected
  67          * by default. Unfortunately, it can not be selected for the old
  68          * MPC5200 Rev. A chips due to a hardware bug (check errata).
  69          */
  70         if (clock_name && strcmp(clock_name, "ip") == 0)
  71                 *mscan_clksrc = MSCAN_CLKSRC_BUS;
  72         else
  73                 *mscan_clksrc = MSCAN_CLKSRC_XTAL;
  74
  75         freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
  76         if (!freq)
  77                 return 0;
  78
  79         if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
  80                 return freq;
  81
  82         /* Determine SYS_XTAL_IN frequency from the clock domain settings */
  83         np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids);
  84         if (!np_cdm) {
  85                 dev_err(&ofdev->dev, "can't get clock node!\n");
  86                 return 0;
  87         }
  88         cdm = of_iomap(np_cdm, 0);
  89         if (!cdm) {
  90                 of_node_put(np_cdm);
  91                 dev_err(&ofdev->dev, "can't map clock node!\n");
  92                 return 0;
  93         }
  94
  95         if (in_8(&cdm->ipb_clk_sel) & 0x1)
  96                 freq *= 2;
  97         val = in_be32(&cdm->rstcfg);
  98
  99         freq *= (val & (1 << 5)) ? 8 : 4;
 100         freq /= (val & (1 << 6)) ? 12 : 16;
 101
 102         of_node_put(np_cdm);
 103         iounmap(cdm);
 104
 105         return freq;
 106 }
 107 #else /* !CONFIG_PPC_MPC52xx */
 108 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
 109                                  const char *clock_name, int *mscan_clksrc)
 110 {
 111         return 0;
 112 }
 113 #endif /* CONFIG_PPC_MPC52xx */
 114
 115 #ifdef CONFIG_PPC_MPC512x
 116 static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
 117                                  const char *clock_source, int *mscan_clksrc)
 118 {
 119         struct device_node *np;
 120         u32 clockdiv;
 121         enum {
 122                 CLK_FROM_AUTO,
 123                 CLK_FROM_IPS,
 124                 CLK_FROM_SYS,
 125                 CLK_FROM_REF,
 126         } clk_from;
 127         struct clk *clk_in, *clk_can;
 128         unsigned long freq_calc;
 129         struct mscan_priv *priv;
 130         struct clk *clk_ipg;
 131
 132         /* the caller passed in the clock source spec that was read from
 133          * the device tree, get the optional clock divider as well
 134          */
 135         np = ofdev->dev.of_node;
 136         clockdiv = 1;
 137         of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
 138         dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
 139                 clock_source ? clock_source : "<NULL>", clockdiv);
 140
 141         /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
 142          * get set, and the 'ips' clock is the input to the MSCAN
 143          * component
 144          *
 145          * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
 146          * bit needs to get cleared, an optional clock-divider may have
 147          * been specified (the default value is 1), the appropriate
 148          * MSCAN related MCLK is the input to the MSCAN component
 149          *
 150          * in the absence of a clock-source spec, first an optimal clock
 151          * gets determined based on the 'sys' clock, if that fails the
 152          * 'ref' clock is used
 153          */
 154         clk_from = CLK_FROM_AUTO;
 155         if (clock_source) {
 156                 /* interpret the device tree's spec for the clock source */
 157                 if (!strcmp(clock_source, "ip"))
 158                         clk_from = CLK_FROM_IPS;
 159                 else if (!strcmp(clock_source, "sys"))
 160                         clk_from = CLK_FROM_SYS;
 161                 else if (!strcmp(clock_source, "ref"))
 162                         clk_from = CLK_FROM_REF;
 163                 else
 164                         goto err_invalid;
 165                 dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
 166         }
 167         if (clk_from == CLK_FROM_AUTO) {
 168                 /* no spec so far, try the 'sys' clock; round to the
 169                  * next MHz and see if we can get a multiple of 16MHz
 170                  */
 171                 dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
 172                 clk_in = devm_clk_get(&ofdev->dev, "sys");
 173                 if (IS_ERR(clk_in))
 174                         goto err_notavail;
 175                 freq_calc = clk_get_rate(clk_in);
 176                 freq_calc +=  499999;
 177                 freq_calc /= 1000000;
 178                 freq_calc *= 1000000;
 179                 if ((freq_calc % 16000000) == 0) {
 180                         clk_from = CLK_FROM_SYS;
 181                         clockdiv = freq_calc / 16000000;
 182                         dev_dbg(&ofdev->dev,
 183                                 "clk fit, sys[%lu] div[%d] freq[%lu]\n",
 184                                 freq_calc, clockdiv, freq_calc / clockdiv);
 185                 }
 186         }
 187         if (clk_from == CLK_FROM_AUTO) {
 188                 /* no spec so far, use the 'ref' clock */
 189                 dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
 190                 clk_in = devm_clk_get(&ofdev->dev, "ref");
 191                 if (IS_ERR(clk_in))
 192                         goto err_notavail;
 193                 clk_from = CLK_FROM_REF;
 194                 freq_calc = clk_get_rate(clk_in);
 195                 dev_dbg(&ofdev->dev,
 196                         "clk fit, ref[%lu] (no div) freq[%lu]\n",
 197                         freq_calc, freq_calc);
 198         }
 199
 200         /* select IPS or MCLK as the MSCAN input (returned to the caller),
 201          * setup the MCLK mux source and rate if applicable, apply the
 202          * optionally specified or derived above divider, and determine
 203          * the actual resulting clock rate to return to the caller
 204          */
 205         switch (clk_from) {
 206         case CLK_FROM_IPS:
 207                 clk_can = devm_clk_get(&ofdev->dev, "ips");
 208                 if (IS_ERR(clk_can))
 209                         goto err_notavail;
 210                 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
 211                 priv->clk_can = clk_can;
 212                 freq_calc = clk_get_rate(clk_can);
 213                 *mscan_clksrc = MSCAN_CLKSRC_IPS;
 214                 dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
 215                         *mscan_clksrc, freq_calc);
 216                 break;
 217         case CLK_FROM_SYS:
 218         case CLK_FROM_REF:
 219                 clk_can = devm_clk_get(&ofdev->dev, "mclk");
 220                 if (IS_ERR(clk_can))
 221                         goto err_notavail;
 222                 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
 223                 priv->clk_can = clk_can;
 224                 if (clk_from == CLK_FROM_SYS)
 225                         clk_in = devm_clk_get(&ofdev->dev, "sys");
 226                 if (clk_from == CLK_FROM_REF)
 227                         clk_in = devm_clk_get(&ofdev->dev, "ref");
 228                 if (IS_ERR(clk_in))
 229                         goto err_notavail;
 230                 clk_set_parent(clk_can, clk_in);
 231                 freq_calc = clk_get_rate(clk_in);
 232                 freq_calc /= clockdiv;
 233                 clk_set_rate(clk_can, freq_calc);
 234                 freq_calc = clk_get_rate(clk_can);
 235                 *mscan_clksrc = MSCAN_CLKSRC_BUS;
 236                 dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
 237                         *mscan_clksrc, freq_calc);
 238                 break;
 239         default:
 240                 goto err_invalid;
 241         }
 242
 243         /* the above clk_can item is used for the bitrate, access to
 244          * the peripheral's register set needs the clk_ipg item
 245          */
 246         clk_ipg = devm_clk_get(&ofdev->dev, "ipg");
 247         if (IS_ERR(clk_ipg))
 248                 goto err_notavail_ipg;
 249         if (clk_prepare_enable(clk_ipg))
 250                 goto err_notavail_ipg;
 251         priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
 252         priv->clk_ipg = clk_ipg;
 253
 254         /* return the determined clock source rate */
 255         return freq_calc;
 256
 257 err_invalid:
 258         dev_err(&ofdev->dev, "invalid clock source specification\n");
 259         /* clock source rate could not get determined */
 260         return 0;
 261
 262 err_notavail:
 263         dev_err(&ofdev->dev, "cannot acquire or setup bitrate clock source\n");
 264         /* clock source rate could not get determined */
 265         return 0;
 266
 267 err_notavail_ipg:
 268         dev_err(&ofdev->dev, "cannot acquire or setup register clock\n");
 269         /* clock source rate could not get determined */
 270         return 0;
 271 }
 272
 273 static void mpc512x_can_put_clock(struct platform_device *ofdev)
 274 {
 275         struct mscan_priv *priv;
 276
 277         priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
 278         if (priv->clk_ipg)
 279                 clk_disable_unprepare(priv->clk_ipg);
 280 }
 281 #else /* !CONFIG_PPC_MPC512x */
 282 static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
 283                                  const char *clock_name, int *mscan_clksrc)
 284 {
 285         return 0;
 286 }
 287 #define mpc512x_can_put_clock NULL
 288 #endif /* CONFIG_PPC_MPC512x */
 289
 290 static const struct of_device_id mpc5xxx_can_table[];
 291 static int mpc5xxx_can_probe(struct platform_device *ofdev)
 292 {
 293         const struct of_device_id *match;
 294         const struct mpc5xxx_can_data *data;
 295         struct device_node *np = ofdev->dev.of_node;
 296         struct net_device *dev;
 297         struct mscan_priv *priv;
 298         void __iomem *base;
 299         const char *clock_name = NULL;
 300         int irq, mscan_clksrc = 0;
 301         int err = -ENOMEM;
 302
 303         match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
 304         if (!match)
 305                 return -EINVAL;
 306         data = match->data;
 307
 308         base = of_iomap(np, 0);
 309         if (!base) {
 310                 dev_err(&ofdev->dev, "couldn't ioremap\n");
 311                 return err;
 312         }
 313
 314         irq = irq_of_parse_and_map(np, 0);
 315         if (!irq) {
 316                 dev_err(&ofdev->dev, "no irq found\n");
 317                 err = -ENODEV;
 318                 goto exit_unmap_mem;
 319         }
 320
 321         dev = alloc_mscandev();
 322         if (!dev)
 323                 goto exit_dispose_irq;
 324         platform_set_drvdata(ofdev, dev);
 325         SET_NETDEV_DEV(dev, &ofdev->dev);
 326
 327         priv = netdev_priv(dev);
 328         priv->reg_base = base;
 329         dev->irq = irq;
 330
 331         clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);
 332
 333         BUG_ON(!data);
 334         priv->type = data->type;
 335         priv->can.clock.freq = data->get_clock(ofdev, clock_name,
 336                                                &mscan_clksrc);
 337         if (!priv->can.clock.freq) {
 338                 dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
 339                 goto exit_free_mscan;
 340         }
 341
 342         err = register_mscandev(dev, mscan_clksrc);
 343         if (err) {
 344                 dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
 345                         DRV_NAME, err);
 346                 goto exit_free_mscan;
 347         }
 348
 349         dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n",
 350                  priv->reg_base, dev->irq, priv->can.clock.freq);
 351
 352         return 0;
 353
 354 exit_free_mscan:
 355         free_candev(dev);
 356 exit_dispose_irq:
 357         irq_dispose_mapping(irq);
 358 exit_unmap_mem:
 359         iounmap(base);
 360
 361         return err;
 362 }
 363
 364 static int mpc5xxx_can_remove(struct platform_device *ofdev)
 365 {
 366         const struct of_device_id *match;
 367         const struct mpc5xxx_can_data *data;
 368         struct net_device *dev = platform_get_drvdata(ofdev);
 369         struct mscan_priv *priv = netdev_priv(dev);
 370
 371         match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
 372         data = match ? match->data : NULL;
 373
 374         unregister_mscandev(dev);
 375         if (data && data->put_clock)
 376                 data->put_clock(ofdev);
 377         iounmap(priv->reg_base);
 378         irq_dispose_mapping(dev->irq);
 379         free_candev(dev);
 380
 381         return 0;
 382 }
 383
 384 #ifdef CONFIG_PM
 385 static struct mscan_regs saved_regs;
 386 static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state)
 387 {
 388         struct net_device *dev = platform_get_drvdata(ofdev);
 389         struct mscan_priv *priv = netdev_priv(dev);
 390         struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
 391
 392         _memcpy_fromio(&saved_regs, regs, sizeof(*regs));
 393
 394         return 0;
 395 }
 396
 397 static int mpc5xxx_can_resume(struct platform_device *ofdev)
 398 {
 399         struct net_device *dev = platform_get_drvdata(ofdev);
 400         struct mscan_priv *priv = netdev_priv(dev);
 401         struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
 402
 403         regs->canctl0 |= MSCAN_INITRQ;
 404         while (!(regs->canctl1 & MSCAN_INITAK))
 405                 udelay(10);
 406
 407         regs->canctl1 = saved_regs.canctl1;
 408         regs->canbtr0 = saved_regs.canbtr0;
 409         regs->canbtr1 = saved_regs.canbtr1;
 410         regs->canidac = saved_regs.canidac;
 411
 412         /* restore masks, buffers etc. */
 413         _memcpy_toio(&regs->canidar1_0, (void *)&saved_regs.canidar1_0,
 414                      sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0));
 415
 416         regs->canctl0 &= ~MSCAN_INITRQ;
 417         regs->cantbsel = saved_regs.cantbsel;
 418         regs->canrier = saved_regs.canrier;
 419         regs->cantier = saved_regs.cantier;
 420         regs->canctl0 = saved_regs.canctl0;
 421
 422         return 0;
 423 }
 424 #endif
 425
 426 static const struct mpc5xxx_can_data mpc5200_can_data = {
 427         .type = MSCAN_TYPE_MPC5200,
 428         .get_clock = mpc52xx_can_get_clock,
 429         /* .put_clock not applicable */
 430 };
 431
 432 static const struct mpc5xxx_can_data mpc5121_can_data = {
 433         .type = MSCAN_TYPE_MPC5121,
 434         .get_clock = mpc512x_can_get_clock,
 435         .put_clock = mpc512x_can_put_clock,
 436 };
 437
 438 static const struct of_device_id mpc5xxx_can_table[] = {
 439         { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
 440         /* Note that only MPC5121 Rev. 2 (and later) is supported */
 441         { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
 442         {},
 443 };
 444 MODULE_DEVICE_TABLE(of, mpc5xxx_can_table);
 445
 446 static struct platform_driver mpc5xxx_can_driver = {
 447         .driver = {
 448                 .name = "mpc5xxx_can",
 449                 .of_match_table = mpc5xxx_can_table,
 450         },
 451         .probe = mpc5xxx_can_probe,
 452         .remove = mpc5xxx_can_remove,
 453 #ifdef CONFIG_PM
 454         .suspend = mpc5xxx_can_suspend,
 455         .resume = mpc5xxx_can_resume,
 456 #endif
 457 };
 458
 459 module_platform_driver(mpc5xxx_can_driver);
 460
 461 MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
 462 MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver");
 463 MODULE_LICENSE("GPL v2");