Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / can / spi / mcp251x.c
blob0b0dd3f096dc6ad8807809d1b89ca626544e0170
1 /*
2 * CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see <http://www.gnu.org/licenses/>.
35 * Your platform definition file should specify something like:
37 * static struct mcp251x_platform_data mcp251x_info = {
38 * .oscillator_frequency = 8000000,
39 * };
41 * static struct spi_board_info spi_board_info[] = {
42 * {
43 * .modalias = "mcp2510",
44 * // "mcp2515" or "mcp25625" depending on your controller
45 * .platform_data = &mcp251x_info,
46 * .irq = IRQ_EINT13,
47 * .max_speed_hz = 2*1000*1000,
48 * .chip_select = 2,
49 * },
50 * };
52 * Please see mcp251x.h for a description of the fields in
53 * struct mcp251x_platform_data.
57 #include <linux/can/core.h>
58 #include <linux/can/dev.h>
59 #include <linux/can/led.h>
60 #include <linux/can/platform/mcp251x.h>
61 #include <linux/clk.h>
62 #include <linux/completion.h>
63 #include <linux/delay.h>
64 #include <linux/device.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/freezer.h>
67 #include <linux/interrupt.h>
68 #include <linux/io.h>
69 #include <linux/kernel.h>
70 #include <linux/module.h>
71 #include <linux/netdevice.h>
72 #include <linux/of.h>
73 #include <linux/of_device.h>
74 #include <linux/platform_device.h>
75 #include <linux/slab.h>
76 #include <linux/spi/spi.h>
77 #include <linux/uaccess.h>
78 #include <linux/regulator/consumer.h>
80 /* SPI interface instruction set */
81 #define INSTRUCTION_WRITE 0x02
82 #define INSTRUCTION_READ 0x03
83 #define INSTRUCTION_BIT_MODIFY 0x05
84 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
85 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
86 #define INSTRUCTION_RESET 0xC0
87 #define RTS_TXB0 0x01
88 #define RTS_TXB1 0x02
89 #define RTS_TXB2 0x04
90 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
93 /* MPC251x registers */
94 #define CANSTAT 0x0e
95 #define CANCTRL 0x0f
96 # define CANCTRL_REQOP_MASK 0xe0
97 # define CANCTRL_REQOP_CONF 0x80
98 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
99 # define CANCTRL_REQOP_LOOPBACK 0x40
100 # define CANCTRL_REQOP_SLEEP 0x20
101 # define CANCTRL_REQOP_NORMAL 0x00
102 # define CANCTRL_OSM 0x08
103 # define CANCTRL_ABAT 0x10
104 #define TEC 0x1c
105 #define REC 0x1d
106 #define CNF1 0x2a
107 # define CNF1_SJW_SHIFT 6
108 #define CNF2 0x29
109 # define CNF2_BTLMODE 0x80
110 # define CNF2_SAM 0x40
111 # define CNF2_PS1_SHIFT 3
112 #define CNF3 0x28
113 # define CNF3_SOF 0x08
114 # define CNF3_WAKFIL 0x04
115 # define CNF3_PHSEG2_MASK 0x07
116 #define CANINTE 0x2b
117 # define CANINTE_MERRE 0x80
118 # define CANINTE_WAKIE 0x40
119 # define CANINTE_ERRIE 0x20
120 # define CANINTE_TX2IE 0x10
121 # define CANINTE_TX1IE 0x08
122 # define CANINTE_TX0IE 0x04
123 # define CANINTE_RX1IE 0x02
124 # define CANINTE_RX0IE 0x01
125 #define CANINTF 0x2c
126 # define CANINTF_MERRF 0x80
127 # define CANINTF_WAKIF 0x40
128 # define CANINTF_ERRIF 0x20
129 # define CANINTF_TX2IF 0x10
130 # define CANINTF_TX1IF 0x08
131 # define CANINTF_TX0IF 0x04
132 # define CANINTF_RX1IF 0x02
133 # define CANINTF_RX0IF 0x01
134 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
135 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
136 # define CANINTF_ERR (CANINTF_ERRIF)
137 #define EFLG 0x2d
138 # define EFLG_EWARN 0x01
139 # define EFLG_RXWAR 0x02
140 # define EFLG_TXWAR 0x04
141 # define EFLG_RXEP 0x08
142 # define EFLG_TXEP 0x10
143 # define EFLG_TXBO 0x20
144 # define EFLG_RX0OVR 0x40
145 # define EFLG_RX1OVR 0x80
146 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
147 # define TXBCTRL_ABTF 0x40
148 # define TXBCTRL_MLOA 0x20
149 # define TXBCTRL_TXERR 0x10
150 # define TXBCTRL_TXREQ 0x08
151 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
152 # define SIDH_SHIFT 3
153 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
154 # define SIDL_SID_MASK 7
155 # define SIDL_SID_SHIFT 5
156 # define SIDL_EXIDE_SHIFT 3
157 # define SIDL_EID_SHIFT 16
158 # define SIDL_EID_MASK 3
159 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
160 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
161 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
162 # define DLC_RTR_SHIFT 6
163 #define TXBCTRL_OFF 0
164 #define TXBSIDH_OFF 1
165 #define TXBSIDL_OFF 2
166 #define TXBEID8_OFF 3
167 #define TXBEID0_OFF 4
168 #define TXBDLC_OFF 5
169 #define TXBDAT_OFF 6
170 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
171 # define RXBCTRL_BUKT 0x04
172 # define RXBCTRL_RXM0 0x20
173 # define RXBCTRL_RXM1 0x40
174 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
175 # define RXBSIDH_SHIFT 3
176 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
177 # define RXBSIDL_IDE 0x08
178 # define RXBSIDL_SRR 0x10
179 # define RXBSIDL_EID 3
180 # define RXBSIDL_SHIFT 5
181 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
182 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
183 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
184 # define RXBDLC_LEN_MASK 0x0f
185 # define RXBDLC_RTR 0x40
186 #define RXBCTRL_OFF 0
187 #define RXBSIDH_OFF 1
188 #define RXBSIDL_OFF 2
189 #define RXBEID8_OFF 3
190 #define RXBEID0_OFF 4
191 #define RXBDLC_OFF 5
192 #define RXBDAT_OFF 6
193 #define RXFSID(n) ((n < 3) ? 0 : 4)
194 #define RXFSIDH(n) ((n) * 4 + RXFSID(n))
195 #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
196 #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
197 #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
198 #define RXMSIDH(n) ((n) * 4 + 0x20)
199 #define RXMSIDL(n) ((n) * 4 + 0x21)
200 #define RXMEID8(n) ((n) * 4 + 0x22)
201 #define RXMEID0(n) ((n) * 4 + 0x23)
203 #define GET_BYTE(val, byte) \
204 (((val) >> ((byte) * 8)) & 0xff)
205 #define SET_BYTE(val, byte) \
206 (((val) & 0xff) << ((byte) * 8))
209 * Buffer size required for the largest SPI transfer (i.e., reading a
210 * frame)
212 #define CAN_FRAME_MAX_DATA_LEN 8
213 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
214 #define CAN_FRAME_MAX_BITS 128
216 #define TX_ECHO_SKB_MAX 1
218 #define MCP251X_OST_DELAY_MS (5)
220 #define DEVICE_NAME "mcp251x"
222 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
223 module_param(mcp251x_enable_dma, int, 0444);
224 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
226 static const struct can_bittiming_const mcp251x_bittiming_const = {
227 .name = DEVICE_NAME,
228 .tseg1_min = 3,
229 .tseg1_max = 16,
230 .tseg2_min = 2,
231 .tseg2_max = 8,
232 .sjw_max = 4,
233 .brp_min = 1,
234 .brp_max = 64,
235 .brp_inc = 1,
238 enum mcp251x_model {
239 CAN_MCP251X_MCP2510 = 0x2510,
240 CAN_MCP251X_MCP2515 = 0x2515,
241 CAN_MCP251X_MCP25625 = 0x25625,
244 struct mcp251x_priv {
245 struct can_priv can;
246 struct net_device *net;
247 struct spi_device *spi;
248 enum mcp251x_model model;
250 struct mutex mcp_lock; /* SPI device lock */
252 u8 *spi_tx_buf;
253 u8 *spi_rx_buf;
254 dma_addr_t spi_tx_dma;
255 dma_addr_t spi_rx_dma;
257 struct sk_buff *tx_skb;
258 int tx_len;
260 struct workqueue_struct *wq;
261 struct work_struct tx_work;
262 struct work_struct restart_work;
264 int force_quit;
265 int after_suspend;
266 #define AFTER_SUSPEND_UP 1
267 #define AFTER_SUSPEND_DOWN 2
268 #define AFTER_SUSPEND_POWER 4
269 #define AFTER_SUSPEND_RESTART 8
270 int restart_tx;
271 struct regulator *power;
272 struct regulator *transceiver;
273 struct clk *clk;
276 #define MCP251X_IS(_model) \
277 static inline int mcp251x_is_##_model(struct spi_device *spi) \
279 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
280 return priv->model == CAN_MCP251X_MCP##_model; \
283 MCP251X_IS(2510);
285 static void mcp251x_clean(struct net_device *net)
287 struct mcp251x_priv *priv = netdev_priv(net);
289 if (priv->tx_skb || priv->tx_len)
290 net->stats.tx_errors++;
291 if (priv->tx_skb)
292 dev_kfree_skb(priv->tx_skb);
293 if (priv->tx_len)
294 can_free_echo_skb(priv->net, 0);
295 priv->tx_skb = NULL;
296 priv->tx_len = 0;
300 * Note about handling of error return of mcp251x_spi_trans: accessing
301 * registers via SPI is not really different conceptually than using
302 * normal I/O assembler instructions, although it's much more
303 * complicated from a practical POV. So it's not advisable to always
304 * check the return value of this function. Imagine that every
305 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
306 * error();", it would be a great mess (well there are some situation
307 * when exception handling C++ like could be useful after all). So we
308 * just check that transfers are OK at the beginning of our
309 * conversation with the chip and to avoid doing really nasty things
310 * (like injecting bogus packets in the network stack).
312 static int mcp251x_spi_trans(struct spi_device *spi, int len)
314 struct mcp251x_priv *priv = spi_get_drvdata(spi);
315 struct spi_transfer t = {
316 .tx_buf = priv->spi_tx_buf,
317 .rx_buf = priv->spi_rx_buf,
318 .len = len,
319 .cs_change = 0,
321 struct spi_message m;
322 int ret;
324 spi_message_init(&m);
326 if (mcp251x_enable_dma) {
327 t.tx_dma = priv->spi_tx_dma;
328 t.rx_dma = priv->spi_rx_dma;
329 m.is_dma_mapped = 1;
332 spi_message_add_tail(&t, &m);
334 ret = spi_sync(spi, &m);
335 if (ret)
336 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
337 return ret;
340 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
342 struct mcp251x_priv *priv = spi_get_drvdata(spi);
343 u8 val = 0;
345 priv->spi_tx_buf[0] = INSTRUCTION_READ;
346 priv->spi_tx_buf[1] = reg;
348 mcp251x_spi_trans(spi, 3);
349 val = priv->spi_rx_buf[2];
351 return val;
354 static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
355 uint8_t *v1, uint8_t *v2)
357 struct mcp251x_priv *priv = spi_get_drvdata(spi);
359 priv->spi_tx_buf[0] = INSTRUCTION_READ;
360 priv->spi_tx_buf[1] = reg;
362 mcp251x_spi_trans(spi, 4);
364 *v1 = priv->spi_rx_buf[2];
365 *v2 = priv->spi_rx_buf[3];
368 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
370 struct mcp251x_priv *priv = spi_get_drvdata(spi);
372 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
373 priv->spi_tx_buf[1] = reg;
374 priv->spi_tx_buf[2] = val;
376 mcp251x_spi_trans(spi, 3);
379 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
380 u8 mask, uint8_t val)
382 struct mcp251x_priv *priv = spi_get_drvdata(spi);
384 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
385 priv->spi_tx_buf[1] = reg;
386 priv->spi_tx_buf[2] = mask;
387 priv->spi_tx_buf[3] = val;
389 mcp251x_spi_trans(spi, 4);
392 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
393 int len, int tx_buf_idx)
395 struct mcp251x_priv *priv = spi_get_drvdata(spi);
397 if (mcp251x_is_2510(spi)) {
398 int i;
400 for (i = 1; i < TXBDAT_OFF + len; i++)
401 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
402 buf[i]);
403 } else {
404 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
405 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
409 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
410 int tx_buf_idx)
412 struct mcp251x_priv *priv = spi_get_drvdata(spi);
413 u32 sid, eid, exide, rtr;
414 u8 buf[SPI_TRANSFER_BUF_LEN];
416 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
417 if (exide)
418 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
419 else
420 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
421 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
422 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
424 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
425 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
426 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
427 (exide << SIDL_EXIDE_SHIFT) |
428 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
429 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
430 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
431 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
432 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
433 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
435 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
436 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
437 mcp251x_spi_trans(priv->spi, 1);
440 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
441 int buf_idx)
443 struct mcp251x_priv *priv = spi_get_drvdata(spi);
445 if (mcp251x_is_2510(spi)) {
446 int i, len;
448 for (i = 1; i < RXBDAT_OFF; i++)
449 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
451 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
452 for (; i < (RXBDAT_OFF + len); i++)
453 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
454 } else {
455 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
456 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
457 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
461 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
463 struct mcp251x_priv *priv = spi_get_drvdata(spi);
464 struct sk_buff *skb;
465 struct can_frame *frame;
466 u8 buf[SPI_TRANSFER_BUF_LEN];
468 skb = alloc_can_skb(priv->net, &frame);
469 if (!skb) {
470 dev_err(&spi->dev, "cannot allocate RX skb\n");
471 priv->net->stats.rx_dropped++;
472 return;
475 mcp251x_hw_rx_frame(spi, buf, buf_idx);
476 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
477 /* Extended ID format */
478 frame->can_id = CAN_EFF_FLAG;
479 frame->can_id |=
480 /* Extended ID part */
481 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
482 SET_BYTE(buf[RXBEID8_OFF], 1) |
483 SET_BYTE(buf[RXBEID0_OFF], 0) |
484 /* Standard ID part */
485 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
486 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
487 /* Remote transmission request */
488 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
489 frame->can_id |= CAN_RTR_FLAG;
490 } else {
491 /* Standard ID format */
492 frame->can_id =
493 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
494 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
495 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
496 frame->can_id |= CAN_RTR_FLAG;
498 /* Data length */
499 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
500 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
502 priv->net->stats.rx_packets++;
503 priv->net->stats.rx_bytes += frame->can_dlc;
505 can_led_event(priv->net, CAN_LED_EVENT_RX);
507 netif_rx_ni(skb);
510 static void mcp251x_hw_sleep(struct spi_device *spi)
512 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
515 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
516 struct net_device *net)
518 struct mcp251x_priv *priv = netdev_priv(net);
519 struct spi_device *spi = priv->spi;
521 if (priv->tx_skb || priv->tx_len) {
522 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
523 return NETDEV_TX_BUSY;
526 if (can_dropped_invalid_skb(net, skb))
527 return NETDEV_TX_OK;
529 netif_stop_queue(net);
530 priv->tx_skb = skb;
531 queue_work(priv->wq, &priv->tx_work);
533 return NETDEV_TX_OK;
536 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
538 struct mcp251x_priv *priv = netdev_priv(net);
540 switch (mode) {
541 case CAN_MODE_START:
542 mcp251x_clean(net);
543 /* We have to delay work since SPI I/O may sleep */
544 priv->can.state = CAN_STATE_ERROR_ACTIVE;
545 priv->restart_tx = 1;
546 if (priv->can.restart_ms == 0)
547 priv->after_suspend = AFTER_SUSPEND_RESTART;
548 queue_work(priv->wq, &priv->restart_work);
549 break;
550 default:
551 return -EOPNOTSUPP;
554 return 0;
557 static int mcp251x_set_normal_mode(struct spi_device *spi)
559 struct mcp251x_priv *priv = spi_get_drvdata(spi);
560 unsigned long timeout;
562 /* Enable interrupts */
563 mcp251x_write_reg(spi, CANINTE,
564 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
565 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
567 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
568 /* Put device into loopback mode */
569 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
570 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
571 /* Put device into listen-only mode */
572 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
573 } else {
574 /* Put device into normal mode */
575 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
577 /* Wait for the device to enter normal mode */
578 timeout = jiffies + HZ;
579 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
580 schedule();
581 if (time_after(jiffies, timeout)) {
582 dev_err(&spi->dev, "MCP251x didn't"
583 " enter in normal mode\n");
584 return -EBUSY;
588 priv->can.state = CAN_STATE_ERROR_ACTIVE;
589 return 0;
592 static int mcp251x_do_set_bittiming(struct net_device *net)
594 struct mcp251x_priv *priv = netdev_priv(net);
595 struct can_bittiming *bt = &priv->can.bittiming;
596 struct spi_device *spi = priv->spi;
598 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
599 (bt->brp - 1));
600 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
601 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
602 CNF2_SAM : 0) |
603 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
604 (bt->prop_seg - 1));
605 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
606 (bt->phase_seg2 - 1));
607 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
608 mcp251x_read_reg(spi, CNF1),
609 mcp251x_read_reg(spi, CNF2),
610 mcp251x_read_reg(spi, CNF3));
612 return 0;
615 static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
617 mcp251x_do_set_bittiming(net);
619 mcp251x_write_reg(spi, RXBCTRL(0),
620 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
621 mcp251x_write_reg(spi, RXBCTRL(1),
622 RXBCTRL_RXM0 | RXBCTRL_RXM1);
623 return 0;
626 static int mcp251x_hw_reset(struct spi_device *spi)
628 struct mcp251x_priv *priv = spi_get_drvdata(spi);
629 unsigned long timeout;
630 int ret;
632 /* Wait for oscillator startup timer after power up */
633 mdelay(MCP251X_OST_DELAY_MS);
635 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
636 ret = mcp251x_spi_trans(spi, 1);
637 if (ret)
638 return ret;
640 /* Wait for oscillator startup timer after reset */
641 mdelay(MCP251X_OST_DELAY_MS);
643 /* Wait for reset to finish */
644 timeout = jiffies + HZ;
645 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) !=
646 CANCTRL_REQOP_CONF) {
647 usleep_range(MCP251X_OST_DELAY_MS * 1000,
648 MCP251X_OST_DELAY_MS * 1000 * 2);
650 if (time_after(jiffies, timeout)) {
651 dev_err(&spi->dev,
652 "MCP251x didn't enter in conf mode after reset\n");
653 return -EBUSY;
656 return 0;
659 static int mcp251x_hw_probe(struct spi_device *spi)
661 u8 ctrl;
662 int ret;
664 ret = mcp251x_hw_reset(spi);
665 if (ret)
666 return ret;
668 ctrl = mcp251x_read_reg(spi, CANCTRL);
670 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
672 /* Check for power up default value */
673 if ((ctrl & 0x17) != 0x07)
674 return -ENODEV;
676 return 0;
679 static int mcp251x_power_enable(struct regulator *reg, int enable)
681 if (IS_ERR_OR_NULL(reg))
682 return 0;
684 if (enable)
685 return regulator_enable(reg);
686 else
687 return regulator_disable(reg);
690 static int mcp251x_stop(struct net_device *net)
692 struct mcp251x_priv *priv = netdev_priv(net);
693 struct spi_device *spi = priv->spi;
695 close_candev(net);
697 priv->force_quit = 1;
698 free_irq(spi->irq, priv);
699 destroy_workqueue(priv->wq);
700 priv->wq = NULL;
702 mutex_lock(&priv->mcp_lock);
704 /* Disable and clear pending interrupts */
705 mcp251x_write_reg(spi, CANINTE, 0x00);
706 mcp251x_write_reg(spi, CANINTF, 0x00);
708 mcp251x_write_reg(spi, TXBCTRL(0), 0);
709 mcp251x_clean(net);
711 mcp251x_hw_sleep(spi);
713 mcp251x_power_enable(priv->transceiver, 0);
715 priv->can.state = CAN_STATE_STOPPED;
717 mutex_unlock(&priv->mcp_lock);
719 can_led_event(net, CAN_LED_EVENT_STOP);
721 return 0;
724 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
726 struct sk_buff *skb;
727 struct can_frame *frame;
729 skb = alloc_can_err_skb(net, &frame);
730 if (skb) {
731 frame->can_id |= can_id;
732 frame->data[1] = data1;
733 netif_rx_ni(skb);
734 } else {
735 netdev_err(net, "cannot allocate error skb\n");
739 static void mcp251x_tx_work_handler(struct work_struct *ws)
741 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
742 tx_work);
743 struct spi_device *spi = priv->spi;
744 struct net_device *net = priv->net;
745 struct can_frame *frame;
747 mutex_lock(&priv->mcp_lock);
748 if (priv->tx_skb) {
749 if (priv->can.state == CAN_STATE_BUS_OFF) {
750 mcp251x_clean(net);
751 } else {
752 frame = (struct can_frame *)priv->tx_skb->data;
754 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
755 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
756 mcp251x_hw_tx(spi, frame, 0);
757 priv->tx_len = 1 + frame->can_dlc;
758 can_put_echo_skb(priv->tx_skb, net, 0);
759 priv->tx_skb = NULL;
762 mutex_unlock(&priv->mcp_lock);
765 static void mcp251x_restart_work_handler(struct work_struct *ws)
767 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
768 restart_work);
769 struct spi_device *spi = priv->spi;
770 struct net_device *net = priv->net;
772 mutex_lock(&priv->mcp_lock);
773 if (priv->after_suspend) {
774 mcp251x_hw_reset(spi);
775 mcp251x_setup(net, spi);
776 priv->force_quit = 0;
777 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
778 mcp251x_set_normal_mode(spi);
779 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
780 netif_device_attach(net);
781 mcp251x_clean(net);
782 mcp251x_set_normal_mode(spi);
783 netif_wake_queue(net);
784 } else {
785 mcp251x_hw_sleep(spi);
787 priv->after_suspend = 0;
790 if (priv->restart_tx) {
791 priv->restart_tx = 0;
792 mcp251x_write_reg(spi, TXBCTRL(0), 0);
793 mcp251x_clean(net);
794 netif_wake_queue(net);
795 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
797 mutex_unlock(&priv->mcp_lock);
800 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
802 struct mcp251x_priv *priv = dev_id;
803 struct spi_device *spi = priv->spi;
804 struct net_device *net = priv->net;
806 mutex_lock(&priv->mcp_lock);
807 while (!priv->force_quit) {
808 enum can_state new_state;
809 u8 intf, eflag;
810 u8 clear_intf = 0;
811 int can_id = 0, data1 = 0;
813 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
815 /* mask out flags we don't care about */
816 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
818 /* receive buffer 0 */
819 if (intf & CANINTF_RX0IF) {
820 mcp251x_hw_rx(spi, 0);
821 /* Free one buffer ASAP
822 * (The MCP2515/25625 does this automatically.)
824 if (mcp251x_is_2510(spi))
825 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00);
828 /* receive buffer 1 */
829 if (intf & CANINTF_RX1IF) {
830 mcp251x_hw_rx(spi, 1);
831 /* The MCP2515/25625 does this automatically. */
832 if (mcp251x_is_2510(spi))
833 clear_intf |= CANINTF_RX1IF;
836 /* any error or tx interrupt we need to clear? */
837 if (intf & (CANINTF_ERR | CANINTF_TX))
838 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
839 if (clear_intf)
840 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
842 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
843 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
845 /* Update can state */
846 if (eflag & EFLG_TXBO) {
847 new_state = CAN_STATE_BUS_OFF;
848 can_id |= CAN_ERR_BUSOFF;
849 } else if (eflag & EFLG_TXEP) {
850 new_state = CAN_STATE_ERROR_PASSIVE;
851 can_id |= CAN_ERR_CRTL;
852 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
853 } else if (eflag & EFLG_RXEP) {
854 new_state = CAN_STATE_ERROR_PASSIVE;
855 can_id |= CAN_ERR_CRTL;
856 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
857 } else if (eflag & EFLG_TXWAR) {
858 new_state = CAN_STATE_ERROR_WARNING;
859 can_id |= CAN_ERR_CRTL;
860 data1 |= CAN_ERR_CRTL_TX_WARNING;
861 } else if (eflag & EFLG_RXWAR) {
862 new_state = CAN_STATE_ERROR_WARNING;
863 can_id |= CAN_ERR_CRTL;
864 data1 |= CAN_ERR_CRTL_RX_WARNING;
865 } else {
866 new_state = CAN_STATE_ERROR_ACTIVE;
869 /* Update can state statistics */
870 switch (priv->can.state) {
871 case CAN_STATE_ERROR_ACTIVE:
872 if (new_state >= CAN_STATE_ERROR_WARNING &&
873 new_state <= CAN_STATE_BUS_OFF)
874 priv->can.can_stats.error_warning++;
875 case CAN_STATE_ERROR_WARNING: /* fallthrough */
876 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
877 new_state <= CAN_STATE_BUS_OFF)
878 priv->can.can_stats.error_passive++;
879 break;
880 default:
881 break;
883 priv->can.state = new_state;
885 if (intf & CANINTF_ERRIF) {
886 /* Handle overflow counters */
887 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
888 if (eflag & EFLG_RX0OVR) {
889 net->stats.rx_over_errors++;
890 net->stats.rx_errors++;
892 if (eflag & EFLG_RX1OVR) {
893 net->stats.rx_over_errors++;
894 net->stats.rx_errors++;
896 can_id |= CAN_ERR_CRTL;
897 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
899 mcp251x_error_skb(net, can_id, data1);
902 if (priv->can.state == CAN_STATE_BUS_OFF) {
903 if (priv->can.restart_ms == 0) {
904 priv->force_quit = 1;
905 priv->can.can_stats.bus_off++;
906 can_bus_off(net);
907 mcp251x_hw_sleep(spi);
908 break;
912 if (intf == 0)
913 break;
915 if (intf & CANINTF_TX) {
916 net->stats.tx_packets++;
917 net->stats.tx_bytes += priv->tx_len - 1;
918 can_led_event(net, CAN_LED_EVENT_TX);
919 if (priv->tx_len) {
920 can_get_echo_skb(net, 0);
921 priv->tx_len = 0;
923 netif_wake_queue(net);
927 mutex_unlock(&priv->mcp_lock);
928 return IRQ_HANDLED;
931 static int mcp251x_open(struct net_device *net)
933 struct mcp251x_priv *priv = netdev_priv(net);
934 struct spi_device *spi = priv->spi;
935 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING;
936 int ret;
938 ret = open_candev(net);
939 if (ret) {
940 dev_err(&spi->dev, "unable to set initial baudrate!\n");
941 return ret;
944 mutex_lock(&priv->mcp_lock);
945 mcp251x_power_enable(priv->transceiver, 1);
947 priv->force_quit = 0;
948 priv->tx_skb = NULL;
949 priv->tx_len = 0;
951 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
952 flags | IRQF_ONESHOT, DEVICE_NAME, priv);
953 if (ret) {
954 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
955 goto out_close;
958 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
960 if (!priv->wq) {
961 ret = -ENOMEM;
962 goto out_clean;
964 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
965 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
967 ret = mcp251x_hw_reset(spi);
968 if (ret)
969 goto out_free_wq;
970 ret = mcp251x_setup(net, spi);
971 if (ret)
972 goto out_free_wq;
973 ret = mcp251x_set_normal_mode(spi);
974 if (ret)
975 goto out_free_wq;
977 can_led_event(net, CAN_LED_EVENT_OPEN);
979 netif_wake_queue(net);
980 mutex_unlock(&priv->mcp_lock);
982 return 0;
984 out_free_wq:
985 destroy_workqueue(priv->wq);
986 out_clean:
987 free_irq(spi->irq, priv);
988 mcp251x_hw_sleep(spi);
989 out_close:
990 mcp251x_power_enable(priv->transceiver, 0);
991 close_candev(net);
992 mutex_unlock(&priv->mcp_lock);
993 return ret;
996 static const struct net_device_ops mcp251x_netdev_ops = {
997 .ndo_open = mcp251x_open,
998 .ndo_stop = mcp251x_stop,
999 .ndo_start_xmit = mcp251x_hard_start_xmit,
1000 .ndo_change_mtu = can_change_mtu,
1003 static const struct of_device_id mcp251x_of_match[] = {
1005 .compatible = "microchip,mcp2510",
1006 .data = (void *)CAN_MCP251X_MCP2510,
1009 .compatible = "microchip,mcp2515",
1010 .data = (void *)CAN_MCP251X_MCP2515,
1013 .compatible = "microchip,mcp25625",
1014 .data = (void *)CAN_MCP251X_MCP25625,
1018 MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1020 static const struct spi_device_id mcp251x_id_table[] = {
1022 .name = "mcp2510",
1023 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1026 .name = "mcp2515",
1027 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1030 .name = "mcp25625",
1031 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
1035 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1037 static int mcp251x_can_probe(struct spi_device *spi)
1039 const struct of_device_id *of_id = of_match_device(mcp251x_of_match,
1040 &spi->dev);
1041 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev);
1042 struct net_device *net;
1043 struct mcp251x_priv *priv;
1044 struct clk *clk;
1045 int freq, ret;
1047 clk = devm_clk_get(&spi->dev, NULL);
1048 if (IS_ERR(clk)) {
1049 if (pdata)
1050 freq = pdata->oscillator_frequency;
1051 else
1052 return PTR_ERR(clk);
1053 } else {
1054 freq = clk_get_rate(clk);
1057 /* Sanity check */
1058 if (freq < 1000000 || freq > 25000000)
1059 return -ERANGE;
1061 /* Allocate can/net device */
1062 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1063 if (!net)
1064 return -ENOMEM;
1066 if (!IS_ERR(clk)) {
1067 ret = clk_prepare_enable(clk);
1068 if (ret)
1069 goto out_free;
1072 net->netdev_ops = &mcp251x_netdev_ops;
1073 net->flags |= IFF_ECHO;
1075 priv = netdev_priv(net);
1076 priv->can.bittiming_const = &mcp251x_bittiming_const;
1077 priv->can.do_set_mode = mcp251x_do_set_mode;
1078 priv->can.clock.freq = freq / 2;
1079 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1080 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1081 if (of_id)
1082 priv->model = (enum mcp251x_model)of_id->data;
1083 else
1084 priv->model = spi_get_device_id(spi)->driver_data;
1085 priv->net = net;
1086 priv->clk = clk;
1088 spi_set_drvdata(spi, priv);
1090 /* Configure the SPI bus */
1091 spi->bits_per_word = 8;
1092 if (mcp251x_is_2510(spi))
1093 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1094 else
1095 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1096 ret = spi_setup(spi);
1097 if (ret)
1098 goto out_clk;
1100 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1101 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1102 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1103 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1104 ret = -EPROBE_DEFER;
1105 goto out_clk;
1108 ret = mcp251x_power_enable(priv->power, 1);
1109 if (ret)
1110 goto out_clk;
1112 priv->spi = spi;
1113 mutex_init(&priv->mcp_lock);
1115 /* If requested, allocate DMA buffers */
1116 if (mcp251x_enable_dma) {
1117 spi->dev.coherent_dma_mask = ~0;
1120 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1121 * that much and share it between Tx and Rx DMA buffers.
1123 priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev,
1124 PAGE_SIZE,
1125 &priv->spi_tx_dma,
1126 GFP_DMA);
1128 if (priv->spi_tx_buf) {
1129 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
1130 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1131 (PAGE_SIZE / 2));
1132 } else {
1133 /* Fall back to non-DMA */
1134 mcp251x_enable_dma = 0;
1138 /* Allocate non-DMA buffers */
1139 if (!mcp251x_enable_dma) {
1140 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1141 GFP_KERNEL);
1142 if (!priv->spi_tx_buf) {
1143 ret = -ENOMEM;
1144 goto error_probe;
1146 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1147 GFP_KERNEL);
1148 if (!priv->spi_rx_buf) {
1149 ret = -ENOMEM;
1150 goto error_probe;
1154 SET_NETDEV_DEV(net, &spi->dev);
1156 /* Here is OK to not lock the MCP, no one knows about it yet */
1157 ret = mcp251x_hw_probe(spi);
1158 if (ret) {
1159 if (ret == -ENODEV)
1160 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n", priv->model);
1161 goto error_probe;
1164 mcp251x_hw_sleep(spi);
1166 ret = register_candev(net);
1167 if (ret)
1168 goto error_probe;
1170 devm_can_led_init(net);
1172 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1173 return 0;
1175 error_probe:
1176 mcp251x_power_enable(priv->power, 0);
1178 out_clk:
1179 if (!IS_ERR(clk))
1180 clk_disable_unprepare(clk);
1182 out_free:
1183 free_candev(net);
1185 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1186 return ret;
1189 static int mcp251x_can_remove(struct spi_device *spi)
1191 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1192 struct net_device *net = priv->net;
1194 unregister_candev(net);
1196 mcp251x_power_enable(priv->power, 0);
1198 if (!IS_ERR(priv->clk))
1199 clk_disable_unprepare(priv->clk);
1201 free_candev(net);
1203 return 0;
1206 static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1208 struct spi_device *spi = to_spi_device(dev);
1209 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1210 struct net_device *net = priv->net;
1212 priv->force_quit = 1;
1213 disable_irq(spi->irq);
1215 * Note: at this point neither IST nor workqueues are running.
1216 * open/stop cannot be called anyway so locking is not needed
1218 if (netif_running(net)) {
1219 netif_device_detach(net);
1221 mcp251x_hw_sleep(spi);
1222 mcp251x_power_enable(priv->transceiver, 0);
1223 priv->after_suspend = AFTER_SUSPEND_UP;
1224 } else {
1225 priv->after_suspend = AFTER_SUSPEND_DOWN;
1228 if (!IS_ERR_OR_NULL(priv->power)) {
1229 regulator_disable(priv->power);
1230 priv->after_suspend |= AFTER_SUSPEND_POWER;
1233 return 0;
1236 static int __maybe_unused mcp251x_can_resume(struct device *dev)
1238 struct spi_device *spi = to_spi_device(dev);
1239 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1241 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1242 mcp251x_power_enable(priv->power, 1);
1244 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1245 mcp251x_power_enable(priv->transceiver, 1);
1246 queue_work(priv->wq, &priv->restart_work);
1247 } else {
1248 priv->after_suspend = 0;
1251 priv->force_quit = 0;
1252 enable_irq(spi->irq);
1253 return 0;
1256 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1257 mcp251x_can_resume);
1259 static struct spi_driver mcp251x_can_driver = {
1260 .driver = {
1261 .name = DEVICE_NAME,
1262 .of_match_table = mcp251x_of_match,
1263 .pm = &mcp251x_can_pm_ops,
1265 .id_table = mcp251x_id_table,
1266 .probe = mcp251x_can_probe,
1267 .remove = mcp251x_can_remove,
1269 module_spi_driver(mcp251x_can_driver);
1271 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1272 "Christian Pellegrin <chripell@evolware.org>");
1273 MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
1274 MODULE_LICENSE("GPL v2");