Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / dsa / mv88e6060.c
blob0b3e51f248c21a2477c9b1736b0f06b80e350e29
1 /*
2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
3 * Copyright (c) 2008-2009 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
11 #include <linux/delay.h>
12 #include <linux/etherdevice.h>
13 #include <linux/jiffies.h>
14 #include <linux/list.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/phy.h>
18 #include <net/dsa.h>
19 #include "mv88e6060.h"
21 static int reg_read(struct dsa_switch *ds, int addr, int reg)
23 struct mv88e6060_priv *priv = ds->priv;
25 return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg);
28 #define REG_READ(addr, reg) \
29 ({ \
30 int __ret; \
32 __ret = reg_read(ds, addr, reg); \
33 if (__ret < 0) \
34 return __ret; \
35 __ret; \
39 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
41 struct mv88e6060_priv *priv = ds->priv;
43 return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val);
46 #define REG_WRITE(addr, reg, val) \
47 ({ \
48 int __ret; \
50 __ret = reg_write(ds, addr, reg, val); \
51 if (__ret < 0) \
52 return __ret; \
55 static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr)
57 int ret;
59 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
60 if (ret >= 0) {
61 if (ret == PORT_SWITCH_ID_6060)
62 return "Marvell 88E6060 (A0)";
63 if (ret == PORT_SWITCH_ID_6060_R1 ||
64 ret == PORT_SWITCH_ID_6060_R2)
65 return "Marvell 88E6060 (B0)";
66 if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
67 return "Marvell 88E6060";
70 return NULL;
73 static enum dsa_tag_protocol mv88e6060_get_tag_protocol(struct dsa_switch *ds,
74 int port)
76 return DSA_TAG_PROTO_TRAILER;
79 static const char *mv88e6060_drv_probe(struct device *dsa_dev,
80 struct device *host_dev, int sw_addr,
81 void **_priv)
83 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
84 struct mv88e6060_priv *priv;
85 const char *name;
87 name = mv88e6060_get_name(bus, sw_addr);
88 if (name) {
89 priv = devm_kzalloc(dsa_dev, sizeof(*priv), GFP_KERNEL);
90 if (!priv)
91 return NULL;
92 *_priv = priv;
93 priv->bus = bus;
94 priv->sw_addr = sw_addr;
97 return name;
100 static int mv88e6060_switch_reset(struct dsa_switch *ds)
102 int i;
103 int ret;
104 unsigned long timeout;
106 /* Set all ports to the disabled state. */
107 for (i = 0; i < MV88E6060_PORTS; i++) {
108 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
109 REG_WRITE(REG_PORT(i), PORT_CONTROL,
110 ret & ~PORT_CONTROL_STATE_MASK);
113 /* Wait for transmit queues to drain. */
114 usleep_range(2000, 4000);
116 /* Reset the switch. */
117 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
118 GLOBAL_ATU_CONTROL_SWRESET |
119 GLOBAL_ATU_CONTROL_LEARNDIS);
121 /* Wait up to one second for reset to complete. */
122 timeout = jiffies + 1 * HZ;
123 while (time_before(jiffies, timeout)) {
124 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
125 if (ret & GLOBAL_STATUS_INIT_READY)
126 break;
128 usleep_range(1000, 2000);
130 if (time_after(jiffies, timeout))
131 return -ETIMEDOUT;
133 return 0;
136 static int mv88e6060_setup_global(struct dsa_switch *ds)
138 /* Disable discarding of frames with excessive collisions,
139 * set the maximum frame size to 1536 bytes, and mask all
140 * interrupt sources.
142 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
144 /* Disable automatic address learning.
146 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
147 GLOBAL_ATU_CONTROL_LEARNDIS);
149 return 0;
152 static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
154 int addr = REG_PORT(p);
156 /* Do not force flow control, disable Ingress and Egress
157 * Header tagging, disable VLAN tunneling, and set the port
158 * state to Forwarding. Additionally, if this is the CPU
159 * port, enable Ingress and Egress Trailer tagging mode.
161 REG_WRITE(addr, PORT_CONTROL,
162 dsa_is_cpu_port(ds, p) ?
163 PORT_CONTROL_TRAILER |
164 PORT_CONTROL_INGRESS_MODE |
165 PORT_CONTROL_STATE_FORWARDING :
166 PORT_CONTROL_STATE_FORWARDING);
168 /* Port based VLAN map: give each port its own address
169 * database, allow the CPU port to talk to each of the 'real'
170 * ports, and allow each of the 'real' ports to only talk to
171 * the CPU port.
173 REG_WRITE(addr, PORT_VLAN_MAP,
174 ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
175 (dsa_is_cpu_port(ds, p) ? dsa_user_ports(ds) :
176 BIT(dsa_to_port(ds, p)->cpu_dp->index)));
178 /* Port Association Vector: when learning source addresses
179 * of packets, add the address to the address database using
180 * a port bitmap that has only the bit for this port set and
181 * the other bits clear.
183 REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
185 return 0;
188 static int mv88e6060_setup_addr(struct dsa_switch *ds)
190 u8 addr[ETH_ALEN];
191 u16 val;
193 eth_random_addr(addr);
195 val = addr[0] << 8 | addr[1];
197 /* The multicast bit is always transmitted as a zero, so the switch uses
198 * bit 8 for "DiffAddr", where 0 means all ports transmit the same SA.
200 val &= 0xfeff;
202 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, val);
203 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
204 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
206 return 0;
209 static int mv88e6060_setup(struct dsa_switch *ds)
211 int ret;
212 int i;
214 ret = mv88e6060_switch_reset(ds);
215 if (ret < 0)
216 return ret;
218 /* @@@ initialise atu */
220 ret = mv88e6060_setup_global(ds);
221 if (ret < 0)
222 return ret;
224 ret = mv88e6060_setup_addr(ds);
225 if (ret < 0)
226 return ret;
228 for (i = 0; i < MV88E6060_PORTS; i++) {
229 ret = mv88e6060_setup_port(ds, i);
230 if (ret < 0)
231 return ret;
234 return 0;
237 static int mv88e6060_port_to_phy_addr(int port)
239 if (port >= 0 && port < MV88E6060_PORTS)
240 return port;
241 return -1;
244 static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
246 int addr;
248 addr = mv88e6060_port_to_phy_addr(port);
249 if (addr == -1)
250 return 0xffff;
252 return reg_read(ds, addr, regnum);
255 static int
256 mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
258 int addr;
260 addr = mv88e6060_port_to_phy_addr(port);
261 if (addr == -1)
262 return 0xffff;
264 return reg_write(ds, addr, regnum, val);
267 static const struct dsa_switch_ops mv88e6060_switch_ops = {
268 .get_tag_protocol = mv88e6060_get_tag_protocol,
269 .probe = mv88e6060_drv_probe,
270 .setup = mv88e6060_setup,
271 .phy_read = mv88e6060_phy_read,
272 .phy_write = mv88e6060_phy_write,
275 static struct dsa_switch_driver mv88e6060_switch_drv = {
276 .ops = &mv88e6060_switch_ops,
279 static int __init mv88e6060_init(void)
281 register_switch_driver(&mv88e6060_switch_drv);
282 return 0;
284 module_init(mv88e6060_init);
286 static void __exit mv88e6060_cleanup(void)
288 unregister_switch_driver(&mv88e6060_switch_drv);
290 module_exit(mv88e6060_cleanup);
292 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
293 MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
294 MODULE_LICENSE("GPL");
295 MODULE_ALIAS("platform:mv88e6060");