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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / altera / altera_tse_main.c
blobc3c1195021a2b72101f9a8aaa0fd0f58a15e561c
1 /* Altera Triple-Speed Ethernet MAC driver
2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
3 *
4 * Contributors:
5 * Dalon Westergreen
6 * Thomas Chou
7 * Ian Abbott
8 * Yuriy Kozlov
9 * Tobias Klauser
10 * Andriy Smolskyy
11 * Roman Bulgakov
12 * Dmytro Mytarchuk
13 * Matthew Gerlach
14 *
15 * Original driver contributed by SLS.
16 * Major updates contributed by GlobalLogic
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2, as published by the Free Software Foundation.
21 *
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
25 * more details.
26 *
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
29 */
30
31 #include <linux/atomic.h>
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/if_vlan.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/io.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/mii.h>
41 #include <linux/netdevice.h>
42 #include <linux/of_device.h>
43 #include <linux/of_mdio.h>
44 #include <linux/of_net.h>
45 #include <linux/of_platform.h>
46 #include <linux/phy.h>
47 #include <linux/platform_device.h>
48 #include <linux/skbuff.h>
49 #include <asm/cacheflush.h>
50
51 #include "altera_utils.h"
52 #include "altera_tse.h"
53 #include "altera_sgdma.h"
54 #include "altera_msgdma.h"
55
56 static atomic_t instance_count = ATOMIC_INIT(~0);
57 /* Module parameters */
58 static int debug = -1;
59 module_param(debug, int, 0644);
60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
61
62 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
63 NETIF_MSG_LINK | NETIF_MSG_IFUP |
64 NETIF_MSG_IFDOWN);
65
66 #define RX_DESCRIPTORS 64
67 static int dma_rx_num = RX_DESCRIPTORS;
68 module_param(dma_rx_num, int, 0644);
69 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
70
71 #define TX_DESCRIPTORS 64
72 static int dma_tx_num = TX_DESCRIPTORS;
73 module_param(dma_tx_num, int, 0644);
74 MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list");
75
76
77 #define POLL_PHY (-1)
78
79 /* Make sure DMA buffer size is larger than the max frame size
80 * plus some alignment offset and a VLAN header. If the max frame size is
81 * 1518, a VLAN header would be additional 4 bytes and additional
82 * headroom for alignment is 2 bytes, 2048 is just fine.
83 */
84 #define ALTERA_RXDMABUFFER_SIZE 2048
85
86 /* Allow network stack to resume queueing packets after we've
87 * finished transmitting at least 1/4 of the packets in the queue.
88 */
89 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
90
91 #define TXQUEUESTOP_THRESHHOLD 2
92
93 static const struct of_device_id altera_tse_ids[];
94
95 static inline u32 tse_tx_avail(struct altera_tse_private *priv)
96 {
97 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1;
98 }
99
100 /* PCS Register read/write functions
101 */
102 static u16 sgmii_pcs_read(struct altera_tse_private *priv, int regnum)
103 {
104 return csrrd32(priv->mac_dev,
105 tse_csroffs(mdio_phy0) + regnum * 4) & 0xffff;
106 }
107
108 static void sgmii_pcs_write(struct altera_tse_private *priv, int regnum,
109 u16 value)
110 {
111 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy0) + regnum * 4);
112 }
113
114 /* Check PCS scratch memory */
115 static int sgmii_pcs_scratch_test(struct altera_tse_private *priv, u16 value)
116 {
117 sgmii_pcs_write(priv, SGMII_PCS_SCRATCH, value);
118 return (sgmii_pcs_read(priv, SGMII_PCS_SCRATCH) == value);
119 }
120
121 /* MDIO specific functions
122 */
123 static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
124 {
125 struct net_device *ndev = bus->priv;
126 struct altera_tse_private *priv = netdev_priv(ndev);
127
128 /* set MDIO address */
129 csrwr32((mii_id & 0x1f), priv->mac_dev,
130 tse_csroffs(mdio_phy1_addr));
131
132 /* get the data */
133 return csrrd32(priv->mac_dev,
134 tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff;
135 }
136
137 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
138 u16 value)
139 {
140 struct net_device *ndev = bus->priv;
141 struct altera_tse_private *priv = netdev_priv(ndev);
142
143 /* set MDIO address */
144 csrwr32((mii_id & 0x1f), priv->mac_dev,
145 tse_csroffs(mdio_phy1_addr));
146
147 /* write the data */
148 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
149 return 0;
150 }
151
152 static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
153 {
154 struct altera_tse_private *priv = netdev_priv(dev);
155 int ret;
156 struct device_node *mdio_node = NULL;
157 struct mii_bus *mdio = NULL;
158 struct device_node *child_node = NULL;
159
160 for_each_child_of_node(priv->device->of_node, child_node) {
161 if (of_device_is_compatible(child_node, "altr,tse-mdio")) {
162 mdio_node = child_node;
163 break;
164 }
165 }
166
167 if (mdio_node) {
168 netdev_dbg(dev, "FOUND MDIO subnode\n");
169 } else {
170 netdev_dbg(dev, "NO MDIO subnode\n");
171 return 0;
172 }
173
174 mdio = mdiobus_alloc();
175 if (mdio == NULL) {
176 netdev_err(dev, "Error allocating MDIO bus\n");
177 return -ENOMEM;
178 }
179
180 mdio->name = ALTERA_TSE_RESOURCE_NAME;
181 mdio->read = &altera_tse_mdio_read;
182 mdio->write = &altera_tse_mdio_write;
183 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id);
184
185 mdio->priv = dev;
186 mdio->parent = priv->device;
187
188 ret = of_mdiobus_register(mdio, mdio_node);
189 if (ret != 0) {
190 netdev_err(dev, "Cannot register MDIO bus %s\n",
191 mdio->id);
192 goto out_free_mdio;
193 }
194
195 if (netif_msg_drv(priv))
196 netdev_info(dev, "MDIO bus %s: created\n", mdio->id);
197
198 priv->mdio = mdio;
199 return 0;
200 out_free_mdio:
201 mdiobus_free(mdio);
202 mdio = NULL;
203 return ret;
204 }
205
206 static void altera_tse_mdio_destroy(struct net_device *dev)
207 {
208 struct altera_tse_private *priv = netdev_priv(dev);
209
210 if (priv->mdio == NULL)
211 return;
212
213 if (netif_msg_drv(priv))
214 netdev_info(dev, "MDIO bus %s: removed\n",
215 priv->mdio->id);
216
217 mdiobus_unregister(priv->mdio);
218 mdiobus_free(priv->mdio);
219 priv->mdio = NULL;
220 }
221
222 static int tse_init_rx_buffer(struct altera_tse_private *priv,
223 struct tse_buffer *rxbuffer, int len)
224 {
225 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len);
226 if (!rxbuffer->skb)
227 return -ENOMEM;
228
229 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data,
230 len,
231 DMA_FROM_DEVICE);
232
233 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) {
234 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
235 dev_kfree_skb_any(rxbuffer->skb);
236 return -EINVAL;
237 }
238 rxbuffer->dma_addr &= (dma_addr_t)~3;
239 rxbuffer->len = len;
240 return 0;
241 }
242
243 static void tse_free_rx_buffer(struct altera_tse_private *priv,
244 struct tse_buffer *rxbuffer)
245 {
246 struct sk_buff *skb = rxbuffer->skb;
247 dma_addr_t dma_addr = rxbuffer->dma_addr;
248
249 if (skb != NULL) {
250 if (dma_addr)
251 dma_unmap_single(priv->device, dma_addr,
252 rxbuffer->len,
253 DMA_FROM_DEVICE);
254 dev_kfree_skb_any(skb);
255 rxbuffer->skb = NULL;
256 rxbuffer->dma_addr = 0;
257 }
258 }
259
260 /* Unmap and free Tx buffer resources
261 */
262 static void tse_free_tx_buffer(struct altera_tse_private *priv,
263 struct tse_buffer *buffer)
264 {
265 if (buffer->dma_addr) {
266 if (buffer->mapped_as_page)
267 dma_unmap_page(priv->device, buffer->dma_addr,
268 buffer->len, DMA_TO_DEVICE);
269 else
270 dma_unmap_single(priv->device, buffer->dma_addr,
271 buffer->len, DMA_TO_DEVICE);
272 buffer->dma_addr = 0;
273 }
274 if (buffer->skb) {
275 dev_kfree_skb_any(buffer->skb);
276 buffer->skb = NULL;
277 }
278 }
279
280 static int alloc_init_skbufs(struct altera_tse_private *priv)
281 {
282 unsigned int rx_descs = priv->rx_ring_size;
283 unsigned int tx_descs = priv->tx_ring_size;
284 int ret = -ENOMEM;
285 int i;
286
287 /* Create Rx ring buffer */
288 priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer),
289 GFP_KERNEL);
290 if (!priv->rx_ring)
291 goto err_rx_ring;
292
293 /* Create Tx ring buffer */
294 priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer),
295 GFP_KERNEL);
296 if (!priv->tx_ring)
297 goto err_tx_ring;
298
299 priv->tx_cons = 0;
300 priv->tx_prod = 0;
301
302 /* Init Rx ring */
303 for (i = 0; i < rx_descs; i++) {
304 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i],
305 priv->rx_dma_buf_sz);
306 if (ret)
307 goto err_init_rx_buffers;
308 }
309
310 priv->rx_cons = 0;
311 priv->rx_prod = 0;
312
313 return 0;
314 err_init_rx_buffers:
315 while (--i >= 0)
316 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
317 kfree(priv->tx_ring);
318 err_tx_ring:
319 kfree(priv->rx_ring);
320 err_rx_ring:
321 return ret;
322 }
323
324 static void free_skbufs(struct net_device *dev)
325 {
326 struct altera_tse_private *priv = netdev_priv(dev);
327 unsigned int rx_descs = priv->rx_ring_size;
328 unsigned int tx_descs = priv->tx_ring_size;
329 int i;
330
331 /* Release the DMA TX/RX socket buffers */
332 for (i = 0; i < rx_descs; i++)
333 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
334 for (i = 0; i < tx_descs; i++)
335 tse_free_tx_buffer(priv, &priv->tx_ring[i]);
336
337
338 kfree(priv->tx_ring);
339 }
340
341 /* Reallocate the skb for the reception process
342 */
343 static inline void tse_rx_refill(struct altera_tse_private *priv)
344 {
345 unsigned int rxsize = priv->rx_ring_size;
346 unsigned int entry;
347 int ret;
348
349 for (; priv->rx_cons - priv->rx_prod > 0;
350 priv->rx_prod++) {
351 entry = priv->rx_prod % rxsize;
352 if (likely(priv->rx_ring[entry].skb == NULL)) {
353 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry],
354 priv->rx_dma_buf_sz);
355 if (unlikely(ret != 0))
356 break;
357 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]);
358 }
359 }
360 }
361
362 /* Pull out the VLAN tag and fix up the packet
363 */
364 static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb)
365 {
366 struct ethhdr *eth_hdr;
367 u16 vid;
368 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
369 !__vlan_get_tag(skb, &vid)) {
370 eth_hdr = (struct ethhdr *)skb->data;
371 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
372 skb_pull(skb, VLAN_HLEN);
373 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
374 }
375 }
376
377 /* Receive a packet: retrieve and pass over to upper levels
378 */
379 static int tse_rx(struct altera_tse_private *priv, int limit)
380 {
381 unsigned int count = 0;
382 unsigned int next_entry;
383 struct sk_buff *skb;
384 unsigned int entry = priv->rx_cons % priv->rx_ring_size;
385 u32 rxstatus;
386 u16 pktlength;
387 u16 pktstatus;
388
389 /* Check for count < limit first as get_rx_status is changing
390 * the response-fifo so we must process the next packet
391 * after calling get_rx_status if a response is pending.
392 * (reading the last byte of the response pops the value from the fifo.)
393 */
394 while ((count < limit) &&
395 ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0)) {
396 pktstatus = rxstatus >> 16;
397 pktlength = rxstatus & 0xffff;
398
399 if ((pktstatus & 0xFF) || (pktlength == 0))
400 netdev_err(priv->dev,
401 "RCV pktstatus %08X pktlength %08X\n",
402 pktstatus, pktlength);
403
404 /* DMA trasfer from TSE starts with 2 aditional bytes for
405 * IP payload alignment. Status returned by get_rx_status()
406 * contains DMA transfer length. Packet is 2 bytes shorter.
407 */
408 pktlength -= 2;
409
410 count++;
411 next_entry = (++priv->rx_cons) % priv->rx_ring_size;
412
413 skb = priv->rx_ring[entry].skb;
414 if (unlikely(!skb)) {
415 netdev_err(priv->dev,
416 "%s: Inconsistent Rx descriptor chain\n",
417 __func__);
418 priv->dev->stats.rx_dropped++;
419 break;
420 }
421 priv->rx_ring[entry].skb = NULL;
422
423 skb_put(skb, pktlength);
424
425 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr,
426 priv->rx_ring[entry].len, DMA_FROM_DEVICE);
427
428 if (netif_msg_pktdata(priv)) {
429 netdev_info(priv->dev, "frame received %d bytes\n",
430 pktlength);
431 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET,
432 16, 1, skb->data, pktlength, true);
433 }
434
435 tse_rx_vlan(priv->dev, skb);
436
437 skb->protocol = eth_type_trans(skb, priv->dev);
438 skb_checksum_none_assert(skb);
439
440 napi_gro_receive(&priv->napi, skb);
441
442 priv->dev->stats.rx_packets++;
443 priv->dev->stats.rx_bytes += pktlength;
444
445 entry = next_entry;
446
447 tse_rx_refill(priv);
448 }
449
450 return count;
451 }
452
453 /* Reclaim resources after transmission completes
454 */
455 static int tse_tx_complete(struct altera_tse_private *priv)
456 {
457 unsigned int txsize = priv->tx_ring_size;
458 u32 ready;
459 unsigned int entry;
460 struct tse_buffer *tx_buff;
461 int txcomplete = 0;
462
463 spin_lock(&priv->tx_lock);
464
465 ready = priv->dmaops->tx_completions(priv);
466
467 /* Free sent buffers */
468 while (ready && (priv->tx_cons != priv->tx_prod)) {
469 entry = priv->tx_cons % txsize;
470 tx_buff = &priv->tx_ring[entry];
471
472 if (netif_msg_tx_done(priv))
473 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n",
474 __func__, priv->tx_prod, priv->tx_cons);
475
476 if (likely(tx_buff->skb))
477 priv->dev->stats.tx_packets++;
478
479 tse_free_tx_buffer(priv, tx_buff);
480 priv->tx_cons++;
481
482 txcomplete++;
483 ready--;
484 }
485
486 if (unlikely(netif_queue_stopped(priv->dev) &&
487 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) {
488 if (netif_queue_stopped(priv->dev) &&
489 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) {
490 if (netif_msg_tx_done(priv))
491 netdev_dbg(priv->dev, "%s: restart transmit\n",
492 __func__);
493 netif_wake_queue(priv->dev);
494 }
495 }
496
497 spin_unlock(&priv->tx_lock);
498 return txcomplete;
499 }
500
501 /* NAPI polling function
502 */
503 static int tse_poll(struct napi_struct *napi, int budget)
504 {
505 struct altera_tse_private *priv =
506 container_of(napi, struct altera_tse_private, napi);
507 int rxcomplete = 0;
508 unsigned long int flags;
509
510 tse_tx_complete(priv);
511
512 rxcomplete = tse_rx(priv, budget);
513
514 if (rxcomplete < budget) {
515
516 napi_complete_done(napi, rxcomplete);
517
518 netdev_dbg(priv->dev,
519 "NAPI Complete, did %d packets with budget %d\n",
520 rxcomplete, budget);
521
522 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
523 priv->dmaops->enable_rxirq(priv);
524 priv->dmaops->enable_txirq(priv);
525 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
526 }
527 return rxcomplete;
528 }
529
530 /* DMA TX & RX FIFO interrupt routing
531 */
532 static irqreturn_t altera_isr(int irq, void *dev_id)
533 {
534 struct net_device *dev = dev_id;
535 struct altera_tse_private *priv;
536
537 if (unlikely(!dev)) {
538 pr_err("%s: invalid dev pointer\n", __func__);
539 return IRQ_NONE;
540 }
541 priv = netdev_priv(dev);
542
543 spin_lock(&priv->rxdma_irq_lock);
544 /* reset IRQs */
545 priv->dmaops->clear_rxirq(priv);
546 priv->dmaops->clear_txirq(priv);
547 spin_unlock(&priv->rxdma_irq_lock);
548
549 if (likely(napi_schedule_prep(&priv->napi))) {
550 spin_lock(&priv->rxdma_irq_lock);
551 priv->dmaops->disable_rxirq(priv);
552 priv->dmaops->disable_txirq(priv);
553 spin_unlock(&priv->rxdma_irq_lock);
554 __napi_schedule(&priv->napi);
555 }
556
557
558 return IRQ_HANDLED;
559 }
560
561 /* Transmit a packet (called by the kernel). Dispatches
562 * either the SGDMA method for transmitting or the
563 * MSGDMA method, assumes no scatter/gather support,
564 * implying an assumption that there's only one
565 * physically contiguous fragment starting at
566 * skb->data, for length of skb_headlen(skb).
567 */
568 static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
569 {
570 struct altera_tse_private *priv = netdev_priv(dev);
571 unsigned int txsize = priv->tx_ring_size;
572 unsigned int entry;
573 struct tse_buffer *buffer = NULL;
574 int nfrags = skb_shinfo(skb)->nr_frags;
575 unsigned int nopaged_len = skb_headlen(skb);
576 enum netdev_tx ret = NETDEV_TX_OK;
577 dma_addr_t dma_addr;
578
579 spin_lock_bh(&priv->tx_lock);
580
581 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) {
582 if (!netif_queue_stopped(dev)) {
583 netif_stop_queue(dev);
584 /* This is a hard error, log it. */
585 netdev_err(priv->dev,
586 "%s: Tx list full when queue awake\n",
587 __func__);
588 }
589 ret = NETDEV_TX_BUSY;
590 goto out;
591 }
592
593 /* Map the first skb fragment */
594 entry = priv->tx_prod % txsize;
595 buffer = &priv->tx_ring[entry];
596
597 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len,
598 DMA_TO_DEVICE);
599 if (dma_mapping_error(priv->device, dma_addr)) {
600 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
601 ret = NETDEV_TX_OK;
602 goto out;
603 }
604
605 buffer->skb = skb;
606 buffer->dma_addr = dma_addr;
607 buffer->len = nopaged_len;
608
609 priv->dmaops->tx_buffer(priv, buffer);
610
611 skb_tx_timestamp(skb);
612
613 priv->tx_prod++;
614 dev->stats.tx_bytes += skb->len;
615
616 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) {
617 if (netif_msg_hw(priv))
618 netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
619 __func__);
620 netif_stop_queue(dev);
621 }
622
623 out:
624 spin_unlock_bh(&priv->tx_lock);
625
626 return ret;
627 }
628
629 /* Called every time the controller might need to be made
630 * aware of new link state. The PHY code conveys this
631 * information through variables in the phydev structure, and this
632 * function converts those variables into the appropriate
633 * register values, and can bring down the device if needed.
634 */
635 static void altera_tse_adjust_link(struct net_device *dev)
636 {
637 struct altera_tse_private *priv = netdev_priv(dev);
638 struct phy_device *phydev = dev->phydev;
639 int new_state = 0;
640
641 /* only change config if there is a link */
642 spin_lock(&priv->mac_cfg_lock);
643 if (phydev->link) {
644 /* Read old config */
645 u32 cfg_reg = ioread32(&priv->mac_dev->command_config);
646
647 /* Check duplex */
648 if (phydev->duplex != priv->oldduplex) {
649 new_state = 1;
650 if (!(phydev->duplex))
651 cfg_reg |= MAC_CMDCFG_HD_ENA;
652 else
653 cfg_reg &= ~MAC_CMDCFG_HD_ENA;
654
655 netdev_dbg(priv->dev, "%s: Link duplex = 0x%x\n",
656 dev->name, phydev->duplex);
657
658 priv->oldduplex = phydev->duplex;
659 }
660
661 /* Check speed */
662 if (phydev->speed != priv->oldspeed) {
663 new_state = 1;
664 switch (phydev->speed) {
665 case 1000:
666 cfg_reg |= MAC_CMDCFG_ETH_SPEED;
667 cfg_reg &= ~MAC_CMDCFG_ENA_10;
668 break;
669 case 100:
670 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
671 cfg_reg &= ~MAC_CMDCFG_ENA_10;
672 break;
673 case 10:
674 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
675 cfg_reg |= MAC_CMDCFG_ENA_10;
676 break;
677 default:
678 if (netif_msg_link(priv))
679 netdev_warn(dev, "Speed (%d) is not 10/100/1000!\n",
680 phydev->speed);
681 break;
682 }
683 priv->oldspeed = phydev->speed;
684 }
685 iowrite32(cfg_reg, &priv->mac_dev->command_config);
686
687 if (!priv->oldlink) {
688 new_state = 1;
689 priv->oldlink = 1;
690 }
691 } else if (priv->oldlink) {
692 new_state = 1;
693 priv->oldlink = 0;
694 priv->oldspeed = 0;
695 priv->oldduplex = -1;
696 }
697
698 if (new_state && netif_msg_link(priv))
699 phy_print_status(phydev);
700
701 spin_unlock(&priv->mac_cfg_lock);
702 }
703 static struct phy_device *connect_local_phy(struct net_device *dev)
704 {
705 struct altera_tse_private *priv = netdev_priv(dev);
706 struct phy_device *phydev = NULL;
707 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
708
709 if (priv->phy_addr != POLL_PHY) {
710 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
711 priv->mdio->id, priv->phy_addr);
712
713 netdev_dbg(dev, "trying to attach to %s\n", phy_id_fmt);
714
715 phydev = phy_connect(dev, phy_id_fmt, &altera_tse_adjust_link,
716 priv->phy_iface);
717 if (IS_ERR(phydev)) {
718 netdev_err(dev, "Could not attach to PHY\n");
719 phydev = NULL;
720 }
721
722 } else {
723 int ret;
724 phydev = phy_find_first(priv->mdio);
725 if (phydev == NULL) {
726 netdev_err(dev, "No PHY found\n");
727 return phydev;
728 }
729
730 ret = phy_connect_direct(dev, phydev, &altera_tse_adjust_link,
731 priv->phy_iface);
732 if (ret != 0) {
733 netdev_err(dev, "Could not attach to PHY\n");
734 phydev = NULL;
735 }
736 }
737 return phydev;
738 }
739
740 static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev)
741 {
742 struct altera_tse_private *priv = netdev_priv(dev);
743 struct device_node *np = priv->device->of_node;
744 int ret = 0;
745
746 priv->phy_iface = of_get_phy_mode(np);
747
748 /* Avoid get phy addr and create mdio if no phy is present */
749 if (!priv->phy_iface)
750 return 0;
751
752 /* try to get PHY address from device tree, use PHY autodetection if
753 * no valid address is given
754 */
755
756 if (of_property_read_u32(priv->device->of_node, "phy-addr",
757 &priv->phy_addr)) {
758 priv->phy_addr = POLL_PHY;
759 }
760
761 if (!((priv->phy_addr == POLL_PHY) ||
762 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) {
763 netdev_err(dev, "invalid phy-addr specified %d\n",
764 priv->phy_addr);
765 return -ENODEV;
766 }
767
768 /* Create/attach to MDIO bus */
769 ret = altera_tse_mdio_create(dev,
770 atomic_add_return(1, &instance_count));
771
772 if (ret)
773 return -ENODEV;
774
775 return 0;
776 }
777
778 /* Initialize driver's PHY state, and attach to the PHY
779 */
780 static int init_phy(struct net_device *dev)
781 {
782 struct altera_tse_private *priv = netdev_priv(dev);
783 struct phy_device *phydev;
784 struct device_node *phynode;
785 bool fixed_link = false;
786 int rc = 0;
787
788 /* Avoid init phy in case of no phy present */
789 if (!priv->phy_iface)
790 return 0;
791
792 priv->oldlink = 0;
793 priv->oldspeed = 0;
794 priv->oldduplex = -1;
795
796 phynode = of_parse_phandle(priv->device->of_node, "phy-handle", 0);
797
798 if (!phynode) {
799 /* check if a fixed-link is defined in device-tree */
800 if (of_phy_is_fixed_link(priv->device->of_node)) {
801 rc = of_phy_register_fixed_link(priv->device->of_node);
802 if (rc < 0) {
803 netdev_err(dev, "cannot register fixed PHY\n");
804 return rc;
805 }
806
807 /* In the case of a fixed PHY, the DT node associated
808 * to the PHY is the Ethernet MAC DT node.
809 */
810 phynode = of_node_get(priv->device->of_node);
811 fixed_link = true;
812
813 netdev_dbg(dev, "fixed-link detected\n");
814 phydev = of_phy_connect(dev, phynode,
815 &altera_tse_adjust_link,
816 0, priv->phy_iface);
817 } else {
818 netdev_dbg(dev, "no phy-handle found\n");
819 if (!priv->mdio) {
820 netdev_err(dev, "No phy-handle nor local mdio specified\n");
821 return -ENODEV;
822 }
823 phydev = connect_local_phy(dev);
824 }
825 } else {
826 netdev_dbg(dev, "phy-handle found\n");
827 phydev = of_phy_connect(dev, phynode,
828 &altera_tse_adjust_link, 0, priv->phy_iface);
829 }
830 of_node_put(phynode);
831
832 if (!phydev) {
833 netdev_err(dev, "Could not find the PHY\n");
834 if (fixed_link)
835 of_phy_deregister_fixed_link(priv->device->of_node);
836 return -ENODEV;
837 }
838
839 /* Stop Advertising 1000BASE Capability if interface is not GMII
840 * Note: Checkpatch throws CHECKs for the camel case defines below,
841 * it's ok to ignore.
842 */
843 if ((priv->phy_iface == PHY_INTERFACE_MODE_MII) ||
844 (priv->phy_iface == PHY_INTERFACE_MODE_RMII))
845 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
846 SUPPORTED_1000baseT_Full);
847
848 /* Broken HW is sometimes missing the pull-up resistor on the
849 * MDIO line, which results in reads to non-existent devices returning
850 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
851 * device as well. If a fixed-link is used the phy_id is always 0.
852 * Note: phydev->phy_id is the result of reading the UID PHY registers.
853 */
854 if ((phydev->phy_id == 0) && !fixed_link) {
855 netdev_err(dev, "Bad PHY UID 0x%08x\n", phydev->phy_id);
856 phy_disconnect(phydev);
857 return -ENODEV;
858 }
859
860 netdev_dbg(dev, "attached to PHY %d UID 0x%08x Link = %d\n",
861 phydev->mdio.addr, phydev->phy_id, phydev->link);
862
863 return 0;
864 }
865
866 static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr)
867 {
868 u32 msb;
869 u32 lsb;
870
871 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
872 lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
873
874 /* Set primary MAC address */
875 csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0));
876 csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1));
877 }
878
879 /* MAC software reset.
880 * When reset is triggered, the MAC function completes the current
881 * transmission or reception, and subsequently disables the transmit and
882 * receive logic, flushes the receive FIFO buffer, and resets the statistics
883 * counters.
884 */
885 static int reset_mac(struct altera_tse_private *priv)
886 {
887 int counter;
888 u32 dat;
889
890 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
891 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
892 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
893 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
894
895 counter = 0;
896 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
897 if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config),
898 MAC_CMDCFG_SW_RESET))
899 break;
900 udelay(1);
901 }
902
903 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
904 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
905 dat &= ~MAC_CMDCFG_SW_RESET;
906 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
907 return -1;
908 }
909 return 0;
910 }
911
912 /* Initialize MAC core registers
913 */
914 static int init_mac(struct altera_tse_private *priv)
915 {
916 unsigned int cmd = 0;
917 u32 frm_length;
918
919 /* Setup Rx FIFO */
920 csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
921 priv->mac_dev, tse_csroffs(rx_section_empty));
922
923 csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev,
924 tse_csroffs(rx_section_full));
925
926 csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev,
927 tse_csroffs(rx_almost_empty));
928
929 csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev,
930 tse_csroffs(rx_almost_full));
931
932 /* Setup Tx FIFO */
933 csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
934 priv->mac_dev, tse_csroffs(tx_section_empty));
935
936 csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev,
937 tse_csroffs(tx_section_full));
938
939 csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev,
940 tse_csroffs(tx_almost_empty));
941
942 csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev,
943 tse_csroffs(tx_almost_full));
944
945 /* MAC Address Configuration */
946 tse_update_mac_addr(priv, priv->dev->dev_addr);
947
948 /* MAC Function Configuration */
949 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
950 csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length));
951
952 csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev,
953 tse_csroffs(tx_ipg_length));
954
955 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
956 * start address
957 */
958 tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat),
959 ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
960
961 tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat),
962 ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
963 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
964
965 /* Set the MAC options */
966 cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config));
967 cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */
968 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */
969 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames
970 * with CRC errors
971 */
972 cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
973 cmd &= ~MAC_CMDCFG_TX_ENA;
974 cmd &= ~MAC_CMDCFG_RX_ENA;
975
976 /* Default speed and duplex setting, full/100 */
977 cmd &= ~MAC_CMDCFG_HD_ENA;
978 cmd &= ~MAC_CMDCFG_ETH_SPEED;
979 cmd &= ~MAC_CMDCFG_ENA_10;
980
981 csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config));
982
983 csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev,
984 tse_csroffs(pause_quanta));
985
986 if (netif_msg_hw(priv))
987 dev_dbg(priv->device,
988 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd);
989
990 return 0;
991 }
992
993 /* Start/stop MAC transmission logic
994 */
995 static void tse_set_mac(struct altera_tse_private *priv, bool enable)
996 {
997 u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config));
998
999 if (enable)
1000 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
1001 else
1002 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
1003
1004 csrwr32(value, priv->mac_dev, tse_csroffs(command_config));
1005 }
1006
1007 /* Change the MTU
1008 */
1009 static int tse_change_mtu(struct net_device *dev, int new_mtu)
1010 {
1011 if (netif_running(dev)) {
1012 netdev_err(dev, "must be stopped to change its MTU\n");
1013 return -EBUSY;
1014 }
1015
1016 dev->mtu = new_mtu;
1017 netdev_update_features(dev);
1018
1019 return 0;
1020 }
1021
1022 static void altera_tse_set_mcfilter(struct net_device *dev)
1023 {
1024 struct altera_tse_private *priv = netdev_priv(dev);
1025 int i;
1026 struct netdev_hw_addr *ha;
1027
1028 /* clear the hash filter */
1029 for (i = 0; i < 64; i++)
1030 csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1031
1032 netdev_for_each_mc_addr(ha, dev) {
1033 unsigned int hash = 0;
1034 int mac_octet;
1035
1036 for (mac_octet = 5; mac_octet >= 0; mac_octet--) {
1037 unsigned char xor_bit = 0;
1038 unsigned char octet = ha->addr[mac_octet];
1039 unsigned int bitshift;
1040
1041 for (bitshift = 0; bitshift < 8; bitshift++)
1042 xor_bit ^= ((octet >> bitshift) & 0x01);
1043
1044 hash = (hash << 1) | xor_bit;
1045 }
1046 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4);
1047 }
1048 }
1049
1050
1051 static void altera_tse_set_mcfilterall(struct net_device *dev)
1052 {
1053 struct altera_tse_private *priv = netdev_priv(dev);
1054 int i;
1055
1056 /* set the hash filter */
1057 for (i = 0; i < 64; i++)
1058 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1059 }
1060
1061 /* Set or clear the multicast filter for this adaptor
1062 */
1063 static void tse_set_rx_mode_hashfilter(struct net_device *dev)
1064 {
1065 struct altera_tse_private *priv = netdev_priv(dev);
1066
1067 spin_lock(&priv->mac_cfg_lock);
1068
1069 if (dev->flags & IFF_PROMISC)
1070 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1071 MAC_CMDCFG_PROMIS_EN);
1072
1073 if (dev->flags & IFF_ALLMULTI)
1074 altera_tse_set_mcfilterall(dev);
1075 else
1076 altera_tse_set_mcfilter(dev);
1077
1078 spin_unlock(&priv->mac_cfg_lock);
1079 }
1080
1081 /* Set or clear the multicast filter for this adaptor
1082 */
1083 static void tse_set_rx_mode(struct net_device *dev)
1084 {
1085 struct altera_tse_private *priv = netdev_priv(dev);
1086
1087 spin_lock(&priv->mac_cfg_lock);
1088
1089 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
1090 !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
1091 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1092 MAC_CMDCFG_PROMIS_EN);
1093 else
1094 tse_clear_bit(priv->mac_dev, tse_csroffs(command_config),
1095 MAC_CMDCFG_PROMIS_EN);
1096
1097 spin_unlock(&priv->mac_cfg_lock);
1098 }
1099
1100 /* Initialise (if necessary) the SGMII PCS component
1101 */
1102 static int init_sgmii_pcs(struct net_device *dev)
1103 {
1104 struct altera_tse_private *priv = netdev_priv(dev);
1105 int n;
1106 unsigned int tmp_reg = 0;
1107
1108 if (priv->phy_iface != PHY_INTERFACE_MODE_SGMII)
1109 return 0; /* Nothing to do, not in SGMII mode */
1110
1111 /* The TSE SGMII PCS block looks a little like a PHY, it is
1112 * mapped into the zeroth MDIO space of the MAC and it has
1113 * ID registers like a PHY would. Sadly this is often
1114 * configured to zeroes, so don't be surprised if it does
1115 * show 0x00000000.
1116 */
1117
1118 if (sgmii_pcs_scratch_test(priv, 0x0000) &&
1119 sgmii_pcs_scratch_test(priv, 0xffff) &&
1120 sgmii_pcs_scratch_test(priv, 0xa5a5) &&
1121 sgmii_pcs_scratch_test(priv, 0x5a5a)) {
1122 netdev_info(dev, "PCS PHY ID: 0x%04x%04x\n",
1123 sgmii_pcs_read(priv, MII_PHYSID1),
1124 sgmii_pcs_read(priv, MII_PHYSID2));
1125 } else {
1126 netdev_err(dev, "SGMII PCS Scratch memory test failed.\n");
1127 return -ENOMEM;
1128 }
1129
1130 /* Starting on page 5-29 of the MegaCore Function User Guide
1131 * Set SGMII Link timer to 1.6ms
1132 */
1133 sgmii_pcs_write(priv, SGMII_PCS_LINK_TIMER_0, 0x0D40);
1134 sgmii_pcs_write(priv, SGMII_PCS_LINK_TIMER_1, 0x03);
1135
1136 /* Enable SGMII Interface and Enable SGMII Auto Negotiation */
1137 sgmii_pcs_write(priv, SGMII_PCS_IF_MODE, 0x3);
1138
1139 /* Enable Autonegotiation */
1140 tmp_reg = sgmii_pcs_read(priv, MII_BMCR);
1141 tmp_reg |= (BMCR_SPEED1000 | BMCR_FULLDPLX | BMCR_ANENABLE);
1142 sgmii_pcs_write(priv, MII_BMCR, tmp_reg);
1143
1144 /* Reset PCS block */
1145 tmp_reg |= BMCR_RESET;
1146 sgmii_pcs_write(priv, MII_BMCR, tmp_reg);
1147 for (n = 0; n < SGMII_PCS_SW_RESET_TIMEOUT; n++) {
1148 if (!(sgmii_pcs_read(priv, MII_BMCR) & BMCR_RESET)) {
1149 netdev_info(dev, "SGMII PCS block initialised OK\n");
1150 return 0;
1151 }
1152 udelay(1);
1153 }
1154
1155 /* We failed to reset the block, return a timeout */
1156 netdev_err(dev, "SGMII PCS block reset failed.\n");
1157 return -ETIMEDOUT;
1158 }
1159
1160 /* Open and initialize the interface
1161 */
1162 static int tse_open(struct net_device *dev)
1163 {
1164 struct altera_tse_private *priv = netdev_priv(dev);
1165 int ret = 0;
1166 int i;
1167 unsigned long int flags;
1168
1169 /* Reset and configure TSE MAC and probe associated PHY */
1170 ret = priv->dmaops->init_dma(priv);
1171 if (ret != 0) {
1172 netdev_err(dev, "Cannot initialize DMA\n");
1173 goto phy_error;
1174 }
1175
1176 if (netif_msg_ifup(priv))
1177 netdev_warn(dev, "device MAC address %pM\n",
1178 dev->dev_addr);
1179
1180 if ((priv->revision < 0xd00) || (priv->revision > 0xe00))
1181 netdev_warn(dev, "TSE revision %x\n", priv->revision);
1182
1183 spin_lock(&priv->mac_cfg_lock);
1184 /* no-op if MAC not operating in SGMII mode*/
1185 ret = init_sgmii_pcs(dev);
1186 if (ret) {
1187 netdev_err(dev,
1188 "Cannot init the SGMII PCS (error: %d)\n", ret);
1189 spin_unlock(&priv->mac_cfg_lock);
1190 goto phy_error;
1191 }
1192
1193 ret = reset_mac(priv);
1194 /* Note that reset_mac will fail if the clocks are gated by the PHY
1195 * due to the PHY being put into isolation or power down mode.
1196 * This is not an error if reset fails due to no clock.
1197 */
1198 if (ret)
1199 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1200
1201 ret = init_mac(priv);
1202 spin_unlock(&priv->mac_cfg_lock);
1203 if (ret) {
1204 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret);
1205 goto alloc_skbuf_error;
1206 }
1207
1208 priv->dmaops->reset_dma(priv);
1209
1210 /* Create and initialize the TX/RX descriptors chains. */
1211 priv->rx_ring_size = dma_rx_num;
1212 priv->tx_ring_size = dma_tx_num;
1213 ret = alloc_init_skbufs(priv);
1214 if (ret) {
1215 netdev_err(dev, "DMA descriptors initialization failed\n");
1216 goto alloc_skbuf_error;
1217 }
1218
1219
1220 /* Register RX interrupt */
1221 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED,
1222 dev->name, dev);
1223 if (ret) {
1224 netdev_err(dev, "Unable to register RX interrupt %d\n",
1225 priv->rx_irq);
1226 goto init_error;
1227 }
1228
1229 /* Register TX interrupt */
1230 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED,
1231 dev->name, dev);
1232 if (ret) {
1233 netdev_err(dev, "Unable to register TX interrupt %d\n",
1234 priv->tx_irq);
1235 goto tx_request_irq_error;
1236 }
1237
1238 /* Enable DMA interrupts */
1239 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1240 priv->dmaops->enable_rxirq(priv);
1241 priv->dmaops->enable_txirq(priv);
1242
1243 /* Setup RX descriptor chain */
1244 for (i = 0; i < priv->rx_ring_size; i++)
1245 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]);
1246
1247 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1248
1249 if (dev->phydev)
1250 phy_start(dev->phydev);
1251
1252 napi_enable(&priv->napi);
1253 netif_start_queue(dev);
1254
1255 priv->dmaops->start_rxdma(priv);
1256
1257 /* Start MAC Rx/Tx */
1258 spin_lock(&priv->mac_cfg_lock);
1259 tse_set_mac(priv, true);
1260 spin_unlock(&priv->mac_cfg_lock);
1261
1262 return 0;
1263
1264 tx_request_irq_error:
1265 free_irq(priv->rx_irq, dev);
1266 init_error:
1267 free_skbufs(dev);
1268 alloc_skbuf_error:
1269 phy_error:
1270 return ret;
1271 }
1272
1273 /* Stop TSE MAC interface and put the device in an inactive state
1274 */
1275 static int tse_shutdown(struct net_device *dev)
1276 {
1277 struct altera_tse_private *priv = netdev_priv(dev);
1278 int ret;
1279 unsigned long int flags;
1280
1281 /* Stop the PHY */
1282 if (dev->phydev)
1283 phy_stop(dev->phydev);
1284
1285 netif_stop_queue(dev);
1286 napi_disable(&priv->napi);
1287
1288 /* Disable DMA interrupts */
1289 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1290 priv->dmaops->disable_rxirq(priv);
1291 priv->dmaops->disable_txirq(priv);
1292 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1293
1294 /* Free the IRQ lines */
1295 free_irq(priv->rx_irq, dev);
1296 free_irq(priv->tx_irq, dev);
1297
1298 /* disable and reset the MAC, empties fifo */
1299 spin_lock(&priv->mac_cfg_lock);
1300 spin_lock(&priv->tx_lock);
1301
1302 ret = reset_mac(priv);
1303 /* Note that reset_mac will fail if the clocks are gated by the PHY
1304 * due to the PHY being put into isolation or power down mode.
1305 * This is not an error if reset fails due to no clock.
1306 */
1307 if (ret)
1308 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1309 priv->dmaops->reset_dma(priv);
1310 free_skbufs(dev);
1311
1312 spin_unlock(&priv->tx_lock);
1313 spin_unlock(&priv->mac_cfg_lock);
1314
1315 priv->dmaops->uninit_dma(priv);
1316
1317 return 0;
1318 }
1319
1320 static struct net_device_ops altera_tse_netdev_ops = {
1321 .ndo_open = tse_open,
1322 .ndo_stop = tse_shutdown,
1323 .ndo_start_xmit = tse_start_xmit,
1324 .ndo_set_mac_address = eth_mac_addr,
1325 .ndo_set_rx_mode = tse_set_rx_mode,
1326 .ndo_change_mtu = tse_change_mtu,
1327 .ndo_validate_addr = eth_validate_addr,
1328 };
1329
1330 static int request_and_map(struct platform_device *pdev, const char *name,
1331 struct resource **res, void __iomem **ptr)
1332 {
1333 struct resource *region;
1334 struct device *device = &pdev->dev;
1335
1336 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
1337 if (*res == NULL) {
1338 dev_err(device, "resource %s not defined\n", name);
1339 return -ENODEV;
1340 }
1341
1342 region = devm_request_mem_region(device, (*res)->start,
1343 resource_size(*res), dev_name(device));
1344 if (region == NULL) {
1345 dev_err(device, "unable to request %s\n", name);
1346 return -EBUSY;
1347 }
1348
1349 *ptr = devm_ioremap_nocache(device, region->start,
1350 resource_size(region));
1351 if (*ptr == NULL) {
1352 dev_err(device, "ioremap_nocache of %s failed!", name);
1353 return -ENOMEM;
1354 }
1355
1356 return 0;
1357 }
1358
1359 /* Probe Altera TSE MAC device
1360 */
1361 static int altera_tse_probe(struct platform_device *pdev)
1362 {
1363 struct net_device *ndev;
1364 int ret = -ENODEV;
1365 struct resource *control_port;
1366 struct resource *dma_res;
1367 struct altera_tse_private *priv;
1368 const unsigned char *macaddr;
1369 void __iomem *descmap;
1370 const struct of_device_id *of_id = NULL;
1371
1372 ndev = alloc_etherdev(sizeof(struct altera_tse_private));
1373 if (!ndev) {
1374 dev_err(&pdev->dev, "Could not allocate network device\n");
1375 return -ENODEV;
1376 }
1377
1378 SET_NETDEV_DEV(ndev, &pdev->dev);
1379
1380 priv = netdev_priv(ndev);
1381 priv->device = &pdev->dev;
1382 priv->dev = ndev;
1383 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1384
1385 of_id = of_match_device(altera_tse_ids, &pdev->dev);
1386
1387 if (of_id)
1388 priv->dmaops = (struct altera_dmaops *)of_id->data;
1389
1390
1391 if (priv->dmaops &&
1392 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) {
1393 /* Get the mapped address to the SGDMA descriptor memory */
1394 ret = request_and_map(pdev, "s1", &dma_res, &descmap);
1395 if (ret)
1396 goto err_free_netdev;
1397
1398 /* Start of that memory is for transmit descriptors */
1399 priv->tx_dma_desc = descmap;
1400
1401 /* First half is for tx descriptors, other half for tx */
1402 priv->txdescmem = resource_size(dma_res)/2;
1403
1404 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start;
1405
1406 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap +
1407 priv->txdescmem));
1408 priv->rxdescmem = resource_size(dma_res)/2;
1409 priv->rxdescmem_busaddr = dma_res->start;
1410 priv->rxdescmem_busaddr += priv->txdescmem;
1411
1412 if (upper_32_bits(priv->rxdescmem_busaddr)) {
1413 dev_dbg(priv->device,
1414 "SGDMA bus addresses greater than 32-bits\n");
1415 ret = -EINVAL;
1416 goto err_free_netdev;
1417 }
1418 if (upper_32_bits(priv->txdescmem_busaddr)) {
1419 dev_dbg(priv->device,
1420 "SGDMA bus addresses greater than 32-bits\n");
1421 ret = -EINVAL;
1422 goto err_free_netdev;
1423 }
1424 } else if (priv->dmaops &&
1425 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) {
1426 ret = request_and_map(pdev, "rx_resp", &dma_res,
1427 &priv->rx_dma_resp);
1428 if (ret)
1429 goto err_free_netdev;
1430
1431 ret = request_and_map(pdev, "tx_desc", &dma_res,
1432 &priv->tx_dma_desc);
1433 if (ret)
1434 goto err_free_netdev;
1435
1436 priv->txdescmem = resource_size(dma_res);
1437 priv->txdescmem_busaddr = dma_res->start;
1438
1439 ret = request_and_map(pdev, "rx_desc", &dma_res,
1440 &priv->rx_dma_desc);
1441 if (ret)
1442 goto err_free_netdev;
1443
1444 priv->rxdescmem = resource_size(dma_res);
1445 priv->rxdescmem_busaddr = dma_res->start;
1446
1447 } else {
1448 goto err_free_netdev;
1449 }
1450
1451 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask)))
1452 dma_set_coherent_mask(priv->device,
1453 DMA_BIT_MASK(priv->dmaops->dmamask));
1454 else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32)))
1455 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32));
1456 else
1457 goto err_free_netdev;
1458
1459 /* MAC address space */
1460 ret = request_and_map(pdev, "control_port", &control_port,
1461 (void __iomem **)&priv->mac_dev);
1462 if (ret)
1463 goto err_free_netdev;
1464
1465 /* xSGDMA Rx Dispatcher address space */
1466 ret = request_and_map(pdev, "rx_csr", &dma_res,
1467 &priv->rx_dma_csr);
1468 if (ret)
1469 goto err_free_netdev;
1470
1471
1472 /* xSGDMA Tx Dispatcher address space */
1473 ret = request_and_map(pdev, "tx_csr", &dma_res,
1474 &priv->tx_dma_csr);
1475 if (ret)
1476 goto err_free_netdev;
1477
1478
1479 /* Rx IRQ */
1480 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq");
1481 if (priv->rx_irq == -ENXIO) {
1482 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n");
1483 ret = -ENXIO;
1484 goto err_free_netdev;
1485 }
1486
1487 /* Tx IRQ */
1488 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq");
1489 if (priv->tx_irq == -ENXIO) {
1490 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n");
1491 ret = -ENXIO;
1492 goto err_free_netdev;
1493 }
1494
1495 /* get FIFO depths from device tree */
1496 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1497 &priv->rx_fifo_depth)) {
1498 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n");
1499 ret = -ENXIO;
1500 goto err_free_netdev;
1501 }
1502
1503 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1504 &priv->tx_fifo_depth)) {
1505 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n");
1506 ret = -ENXIO;
1507 goto err_free_netdev;
1508 }
1509
1510 /* get hash filter settings for this instance */
1511 priv->hash_filter =
1512 of_property_read_bool(pdev->dev.of_node,
1513 "altr,has-hash-multicast-filter");
1514
1515 /* Set hash filter to not set for now until the
1516 * multicast filter receive issue is debugged
1517 */
1518 priv->hash_filter = 0;
1519
1520 /* get supplemental address settings for this instance */
1521 priv->added_unicast =
1522 of_property_read_bool(pdev->dev.of_node,
1523 "altr,has-supplementary-unicast");
1524
1525 priv->dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN;
1526 /* Max MTU is 1500, ETH_DATA_LEN */
1527 priv->dev->max_mtu = ETH_DATA_LEN;
1528
1529 /* Get the max mtu from the device tree. Note that the
1530 * "max-frame-size" parameter is actually max mtu. Definition
1531 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1532 */
1533 of_property_read_u32(pdev->dev.of_node, "max-frame-size",
1534 &priv->dev->max_mtu);
1535
1536 /* The DMA buffer size already accounts for an alignment bias
1537 * to avoid unaligned access exceptions for the NIOS processor,
1538 */
1539 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;
1540
1541 /* get default MAC address from device tree */
1542 macaddr = of_get_mac_address(pdev->dev.of_node);
1543 if (macaddr)
1544 ether_addr_copy(ndev->dev_addr, macaddr);
1545 else
1546 eth_hw_addr_random(ndev);
1547
1548 /* get phy addr and create mdio */
1549 ret = altera_tse_phy_get_addr_mdio_create(ndev);
1550
1551 if (ret)
1552 goto err_free_netdev;
1553
1554 /* initialize netdev */
1555 ndev->mem_start = control_port->start;
1556 ndev->mem_end = control_port->end;
1557 ndev->netdev_ops = &altera_tse_netdev_ops;
1558 altera_tse_set_ethtool_ops(ndev);
1559
1560 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode;
1561
1562 if (priv->hash_filter)
1563 altera_tse_netdev_ops.ndo_set_rx_mode =
1564 tse_set_rx_mode_hashfilter;
1565
1566 /* Scatter/gather IO is not supported,
1567 * so it is turned off
1568 */
1569 ndev->hw_features &= ~NETIF_F_SG;
1570 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1571
1572 /* VLAN offloading of tagging, stripping and filtering is not
1573 * supported by hardware, but driver will accommodate the
1574 * extra 4-byte VLAN tag for processing by upper layers
1575 */
1576 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1577
1578 /* setup NAPI interface */
1579 netif_napi_add(ndev, &priv->napi, tse_poll, NAPI_POLL_WEIGHT);
1580
1581 spin_lock_init(&priv->mac_cfg_lock);
1582 spin_lock_init(&priv->tx_lock);
1583 spin_lock_init(&priv->rxdma_irq_lock);
1584
1585 netif_carrier_off(ndev);
1586 ret = register_netdev(ndev);
1587 if (ret) {
1588 dev_err(&pdev->dev, "failed to register TSE net device\n");
1589 goto err_register_netdev;
1590 }
1591
1592 platform_set_drvdata(pdev, ndev);
1593
1594 priv->revision = ioread32(&priv->mac_dev->megacore_revision);
1595
1596 if (netif_msg_probe(priv))
1597 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1598 (priv->revision >> 8) & 0xff,
1599 priv->revision & 0xff,
1600 (unsigned long) control_port->start, priv->rx_irq,
1601 priv->tx_irq);
1602
1603 ret = init_phy(ndev);
1604 if (ret != 0) {
1605 netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret);
1606 goto err_init_phy;
1607 }
1608 return 0;
1609
1610 err_init_phy:
1611 unregister_netdev(ndev);
1612 err_register_netdev:
1613 netif_napi_del(&priv->napi);
1614 altera_tse_mdio_destroy(ndev);
1615 err_free_netdev:
1616 free_netdev(ndev);
1617 return ret;
1618 }
1619
1620 /* Remove Altera TSE MAC device
1621 */
1622 static int altera_tse_remove(struct platform_device *pdev)
1623 {
1624 struct net_device *ndev = platform_get_drvdata(pdev);
1625 struct altera_tse_private *priv = netdev_priv(ndev);
1626
1627 if (ndev->phydev) {
1628 phy_disconnect(ndev->phydev);
1629
1630 if (of_phy_is_fixed_link(priv->device->of_node))
1631 of_phy_deregister_fixed_link(priv->device->of_node);
1632 }
1633
1634 platform_set_drvdata(pdev, NULL);
1635 altera_tse_mdio_destroy(ndev);
1636 unregister_netdev(ndev);
1637 free_netdev(ndev);
1638
1639 return 0;
1640 }
1641
1642 static const struct altera_dmaops altera_dtype_sgdma = {
1643 .altera_dtype = ALTERA_DTYPE_SGDMA,
1644 .dmamask = 32,
1645 .reset_dma = sgdma_reset,
1646 .enable_txirq = sgdma_enable_txirq,
1647 .enable_rxirq = sgdma_enable_rxirq,
1648 .disable_txirq = sgdma_disable_txirq,
1649 .disable_rxirq = sgdma_disable_rxirq,
1650 .clear_txirq = sgdma_clear_txirq,
1651 .clear_rxirq = sgdma_clear_rxirq,
1652 .tx_buffer = sgdma_tx_buffer,
1653 .tx_completions = sgdma_tx_completions,
1654 .add_rx_desc = sgdma_add_rx_desc,
1655 .get_rx_status = sgdma_rx_status,
1656 .init_dma = sgdma_initialize,
1657 .uninit_dma = sgdma_uninitialize,
1658 .start_rxdma = sgdma_start_rxdma,
1659 };
1660
1661 static const struct altera_dmaops altera_dtype_msgdma = {
1662 .altera_dtype = ALTERA_DTYPE_MSGDMA,
1663 .dmamask = 64,
1664 .reset_dma = msgdma_reset,
1665 .enable_txirq = msgdma_enable_txirq,
1666 .enable_rxirq = msgdma_enable_rxirq,
1667 .disable_txirq = msgdma_disable_txirq,
1668 .disable_rxirq = msgdma_disable_rxirq,
1669 .clear_txirq = msgdma_clear_txirq,
1670 .clear_rxirq = msgdma_clear_rxirq,
1671 .tx_buffer = msgdma_tx_buffer,
1672 .tx_completions = msgdma_tx_completions,
1673 .add_rx_desc = msgdma_add_rx_desc,
1674 .get_rx_status = msgdma_rx_status,
1675 .init_dma = msgdma_initialize,
1676 .uninit_dma = msgdma_uninitialize,
1677 .start_rxdma = msgdma_start_rxdma,
1678 };
1679
1680 static const struct of_device_id altera_tse_ids[] = {
1681 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
1682 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
1683 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
1684 {},
1685 };
1686 MODULE_DEVICE_TABLE(of, altera_tse_ids);
1687
1688 static struct platform_driver altera_tse_driver = {
1689 .probe = altera_tse_probe,
1690 .remove = altera_tse_remove,
1691 .suspend = NULL,
1692 .resume = NULL,
1693 .driver = {
1694 .name = ALTERA_TSE_RESOURCE_NAME,
1695 .of_match_table = altera_tse_ids,
1696 },
1697 };
1698
1699 module_platform_driver(altera_tse_driver);
1700
1701 MODULE_AUTHOR("Altera Corporation");
1702 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1703 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support