drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h

   1 /* bnx2x_cmn.h: QLogic Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12  * Written by: Eliezer Tamir
  13  * Based on code from Michael Chan's bnx2 driver
  14  * UDP CSUM errata workaround by Arik Gendelman
  15  * Slowpath and fastpath rework by Vladislav Zolotarov
  16  * Statistics and Link management by Yitchak Gertner
  17  *
  18  */
  19 #ifndef BNX2X_CMN_H
  20 #define BNX2X_CMN_H
  21
  22 #include <linux/types.h>
  23 #include <linux/pci.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/irq.h>
  27
  28 #include "bnx2x.h"
  29 #include "bnx2x_sriov.h"
  30
  31 /* This is used as a replacement for an MCP if it's not present */
  32 extern int bnx2x_load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */
  33 extern int bnx2x_num_queues;
  34
  35 /************************ Macros ********************************/
  36 #define BNX2X_PCI_FREE(x, y, size) \
  37         do { \
  38                 if (x) { \
  39                         dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
  40                         x = NULL; \
  41                         y = 0; \
  42                 } \
  43         } while (0)
  44
  45 #define BNX2X_FREE(x) \
  46         do { \
  47                 if (x) { \
  48                         kfree((void *)x); \
  49                         x = NULL; \
  50                 } \
  51         } while (0)
  52
  53 #define BNX2X_PCI_ALLOC(y, size)                                        \
  54 ({                                                                      \
  55         void *x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
  56         if (x)                                                          \
  57                 DP(NETIF_MSG_HW,                                        \
  58                    "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n",        \
  59                    (unsigned long long)(*y), x);                        \
  60         x;                                                              \
  61 })
  62 #define BNX2X_PCI_FALLOC(y, size)                                       \
  63 ({                                                                      \
  64         void *x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
  65         if (x) {                                                        \
  66                 memset(x, 0xff, size);                                  \
  67                 DP(NETIF_MSG_HW,                                        \
  68                    "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n",       \
  69                    (unsigned long long)(*y), x);                        \
  70         }                                                               \
  71         x;                                                              \
  72 })
  73
  74 /*********************** Interfaces ****************************
  75  *  Functions that need to be implemented by each driver version
  76  */
  77 /* Init */
  78
  79 /**
  80  * bnx2x_send_unload_req - request unload mode from the MCP.
  81  *
  82  * @bp:                 driver handle
  83  * @unload_mode:        requested function's unload mode
  84  *
  85  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
  86  */
  87 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
  88
  89 /**
  90  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
  91  *
  92  * @bp:         driver handle
  93  * @keep_link:          true iff link should be kept up
  94  */
  95 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link);
  96
  97 /**
  98  * bnx2x_config_rss_pf - configure RSS parameters in a PF.
  99  *
 100  * @bp:                 driver handle
 101  * @rss_obj:            RSS object to use
 102  * @ind_table:          indirection table to configure
 103  * @config_hash:        re-configure RSS hash keys configuration
 104  * @enable:             enabled or disabled configuration
 105  */
 106 int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
 107               bool config_hash, bool enable);
 108
 109 /**
 110  * bnx2x__init_func_obj - init function object
 111  *
 112  * @bp:                 driver handle
 113  *
 114  * Initializes the Function Object with the appropriate
 115  * parameters which include a function slow path driver
 116  * interface.
 117  */
 118 void bnx2x__init_func_obj(struct bnx2x *bp);
 119
 120 /**
 121  * bnx2x_setup_queue - setup eth queue.
 122  *
 123  * @bp:         driver handle
 124  * @fp:         pointer to the fastpath structure
 125  * @leading:    boolean
 126  *
 127  */
 128 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
 129                        bool leading);
 130
 131 /**
 132  * bnx2x_setup_leading - bring up a leading eth queue.
 133  *
 134  * @bp:         driver handle
 135  */
 136 int bnx2x_setup_leading(struct bnx2x *bp);
 137
 138 /**
 139  * bnx2x_fw_command - send the MCP a request
 140  *
 141  * @bp:         driver handle
 142  * @command:    request
 143  * @param:      request's parameter
 144  *
 145  * block until there is a reply
 146  */
 147 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
 148
 149 /**
 150  * bnx2x_initial_phy_init - initialize link parameters structure variables.
 151  *
 152  * @bp:         driver handle
 153  * @load_mode:  current mode
 154  */
 155 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
 156
 157 /**
 158  * bnx2x_link_set - configure hw according to link parameters structure.
 159  *
 160  * @bp:         driver handle
 161  */
 162 void bnx2x_link_set(struct bnx2x *bp);
 163
 164 /**
 165  * bnx2x_force_link_reset - Forces link reset, and put the PHY
 166  * in reset as well.
 167  *
 168  * @bp:         driver handle
 169  */
 170 void bnx2x_force_link_reset(struct bnx2x *bp);
 171
 172 /**
 173  * bnx2x_link_test - query link status.
 174  *
 175  * @bp:         driver handle
 176  * @is_serdes:  bool
 177  *
 178  * Returns 0 if link is UP.
 179  */
 180 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
 181
 182 /**
 183  * bnx2x_drv_pulse - write driver pulse to shmem
 184  *
 185  * @bp:         driver handle
 186  *
 187  * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox
 188  * in the shmem.
 189  */
 190 void bnx2x_drv_pulse(struct bnx2x *bp);
 191
 192 /**
 193  * bnx2x_igu_ack_sb - update IGU with current SB value
 194  *
 195  * @bp:         driver handle
 196  * @igu_sb_id:  SB id
 197  * @segment:    SB segment
 198  * @index:      SB index
 199  * @op:         SB operation
 200  * @update:     is HW update required
 201  */
 202 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
 203                       u16 index, u8 op, u8 update);
 204
 205 /* Disable transactions from chip to host */
 206 void bnx2x_pf_disable(struct bnx2x *bp);
 207 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
 208
 209 /**
 210  * bnx2x__link_status_update - handles link status change.
 211  *
 212  * @bp:         driver handle
 213  */
 214 void bnx2x__link_status_update(struct bnx2x *bp);
 215
 216 /**
 217  * bnx2x_link_report - report link status to upper layer.
 218  *
 219  * @bp:         driver handle
 220  */
 221 void bnx2x_link_report(struct bnx2x *bp);
 222
 223 /* None-atomic version of bnx2x_link_report() */
 224 void __bnx2x_link_report(struct bnx2x *bp);
 225
 226 /**
 227  * bnx2x_get_mf_speed - calculate MF speed.
 228  *
 229  * @bp:         driver handle
 230  *
 231  * Takes into account current linespeed and MF configuration.
 232  */
 233 u16 bnx2x_get_mf_speed(struct bnx2x *bp);
 234
 235 /**
 236  * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
 237  *
 238  * @irq:                irq number
 239  * @dev_instance:       private instance
 240  */
 241 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
 242
 243 /**
 244  * bnx2x_interrupt - non MSI-X interrupt handler
 245  *
 246  * @irq:                irq number
 247  * @dev_instance:       private instance
 248  */
 249 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
 250
 251 /**
 252  * bnx2x_cnic_notify - send command to cnic driver
 253  *
 254  * @bp:         driver handle
 255  * @cmd:        command
 256  */
 257 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
 258
 259 /**
 260  * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
 261  *
 262  * @bp:         driver handle
 263  */
 264 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
 265
 266 /**
 267  * bnx2x_setup_cnic_info - provides cnic with updated info
 268  *
 269  * @bp:         driver handle
 270  */
 271 void bnx2x_setup_cnic_info(struct bnx2x *bp);
 272
 273 /**
 274  * bnx2x_int_enable - enable HW interrupts.
 275  *
 276  * @bp:         driver handle
 277  */
 278 void bnx2x_int_enable(struct bnx2x *bp);
 279
 280 /**
 281  * bnx2x_int_disable_sync - disable interrupts.
 282  *
 283  * @bp:         driver handle
 284  * @disable_hw: true, disable HW interrupts.
 285  *
 286  * This function ensures that there are no
 287  * ISRs or SP DPCs (sp_task) are running after it returns.
 288  */
 289 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
 290
 291 /**
 292  * bnx2x_nic_init_cnic - init driver internals for cnic.
 293  *
 294  * @bp:         driver handle
 295  * @load_code:  COMMON, PORT or FUNCTION
 296  *
 297  * Initializes:
 298  *  - rings
 299  *  - status blocks
 300  *  - etc.
 301  */
 302 void bnx2x_nic_init_cnic(struct bnx2x *bp);
 303
 304 /**
 305  * bnx2x_preirq_nic_init - init driver internals.
 306  *
 307  * @bp:         driver handle
 308  *
 309  * Initializes:
 310  *  - fastpath object
 311  *  - fastpath rings
 312  *  etc.
 313  */
 314 void bnx2x_pre_irq_nic_init(struct bnx2x *bp);
 315
 316 /**
 317  * bnx2x_postirq_nic_init - init driver internals.
 318  *
 319  * @bp:         driver handle
 320  * @load_code:  COMMON, PORT or FUNCTION
 321  *
 322  * Initializes:
 323  *  - status blocks
 324  *  - slowpath rings
 325  *  - etc.
 326  */
 327 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code);
 328 /**
 329  * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic.
 330  *
 331  * @bp:         driver handle
 332  */
 333 int bnx2x_alloc_mem_cnic(struct bnx2x *bp);
 334 /**
 335  * bnx2x_alloc_mem - allocate driver's memory.
 336  *
 337  * @bp:         driver handle
 338  */
 339 int bnx2x_alloc_mem(struct bnx2x *bp);
 340
 341 /**
 342  * bnx2x_free_mem_cnic - release driver's memory for cnic.
 343  *
 344  * @bp:         driver handle
 345  */
 346 void bnx2x_free_mem_cnic(struct bnx2x *bp);
 347 /**
 348  * bnx2x_free_mem - release driver's memory.
 349  *
 350  * @bp:         driver handle
 351  */
 352 void bnx2x_free_mem(struct bnx2x *bp);
 353
 354 /**
 355  * bnx2x_set_num_queues - set number of queues according to mode.
 356  *
 357  * @bp:         driver handle
 358  */
 359 void bnx2x_set_num_queues(struct bnx2x *bp);
 360
 361 /**
 362  * bnx2x_chip_cleanup - cleanup chip internals.
 363  *
 364  * @bp:                 driver handle
 365  * @unload_mode:        COMMON, PORT, FUNCTION
 366  * @keep_link:          true iff link should be kept up.
 367  *
 368  * - Cleanup MAC configuration.
 369  * - Closes clients.
 370  * - etc.
 371  */
 372 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link);
 373
 374 /**
 375  * bnx2x_acquire_hw_lock - acquire HW lock.
 376  *
 377  * @bp:         driver handle
 378  * @resource:   resource bit which was locked
 379  */
 380 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
 381
 382 /**
 383  * bnx2x_release_hw_lock - release HW lock.
 384  *
 385  * @bp:         driver handle
 386  * @resource:   resource bit which was locked
 387  */
 388 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
 389
 390 /**
 391  * bnx2x_release_leader_lock - release recovery leader lock
 392  *
 393  * @bp:         driver handle
 394  */
 395 int bnx2x_release_leader_lock(struct bnx2x *bp);
 396
 397 /**
 398  * bnx2x_set_eth_mac - configure eth MAC address in the HW
 399  *
 400  * @bp:         driver handle
 401  * @set:        set or clear
 402  *
 403  * Configures according to the value in netdev->dev_addr.
 404  */
 405 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set);
 406
 407 /**
 408  * bnx2x_set_rx_mode - set MAC filtering configurations.
 409  *
 410  * @dev:        netdevice
 411  *
 412  * called with netif_tx_lock from dev_mcast.c
 413  * If bp->state is OPEN, should be called with
 414  * netif_addr_lock_bh()
 415  */
 416 void bnx2x_set_rx_mode_inner(struct bnx2x *bp);
 417
 418 /* Parity errors related */
 419 void bnx2x_set_pf_load(struct bnx2x *bp);
 420 bool bnx2x_clear_pf_load(struct bnx2x *bp);
 421 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
 422 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
 423 void bnx2x_set_reset_in_progress(struct bnx2x *bp);
 424 void bnx2x_set_reset_global(struct bnx2x *bp);
 425 void bnx2x_disable_close_the_gate(struct bnx2x *bp);
 426 int bnx2x_init_hw_func_cnic(struct bnx2x *bp);
 427
 428 void bnx2x_clear_vlan_info(struct bnx2x *bp);
 429
 430 /**
 431  * bnx2x_sp_event - handle ramrods completion.
 432  *
 433  * @fp:         fastpath handle for the event
 434  * @rr_cqe:     eth_rx_cqe
 435  */
 436 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
 437
 438 /**
 439  * bnx2x_ilt_set_info - prepare ILT configurations.
 440  *
 441  * @bp:         driver handle
 442  */
 443 void bnx2x_ilt_set_info(struct bnx2x *bp);
 444
 445 /**
 446  * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC
 447  * and TM.
 448  *
 449  * @bp:         driver handle
 450  */
 451 void bnx2x_ilt_set_info_cnic(struct bnx2x *bp);
 452
 453 /**
 454  * bnx2x_dcbx_init - initialize dcbx protocol.
 455  *
 456  * @bp:         driver handle
 457  */
 458 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem);
 459
 460 /**
 461  * bnx2x_set_power_state - set power state to the requested value.
 462  *
 463  * @bp:         driver handle
 464  * @state:      required state D0 or D3hot
 465  *
 466  * Currently only D0 and D3hot are supported.
 467  */
 468 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
 469
 470 /**
 471  * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
 472  *
 473  * @bp:         driver handle
 474  * @value:      new value
 475  */
 476 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
 477 /* Error handling */
 478 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
 479
 480 /* dev_close main block */
 481 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link);
 482
 483 /* dev_open main block */
 484 int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
 485
 486 /* hard_xmit callback */
 487 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
 488
 489 /* setup_tc callback */
 490 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc);
 491 int __bnx2x_setup_tc(struct net_device *dev, enum tc_setup_type type,
 492                      void *type_data);
 493
 494 int bnx2x_get_vf_config(struct net_device *dev, int vf,
 495                         struct ifla_vf_info *ivi);
 496 int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac);
 497 int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos,
 498                       __be16 vlan_proto);
 499
 500 /* select_queue callback */
 501 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb,
 502                        struct net_device *sb_dev,
 503                        select_queue_fallback_t fallback);
 504
 505 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
 506                                         struct bnx2x_fastpath *fp,
 507                                         u16 bd_prod, u16 rx_comp_prod,
 508                                         u16 rx_sge_prod)
 509 {
 510         struct ustorm_eth_rx_producers rx_prods = {0};
 511         u32 i;
 512
 513         /* Update producers */
 514         rx_prods.bd_prod = bd_prod;
 515         rx_prods.cqe_prod = rx_comp_prod;
 516         rx_prods.sge_prod = rx_sge_prod;
 517
 518         /* Make sure that the BD and SGE data is updated before updating the
 519          * producers since FW might read the BD/SGE right after the producer
 520          * is updated.
 521          * This is only applicable for weak-ordered memory model archs such
 522          * as IA-64. The following barrier is also mandatory since FW will
 523          * assumes BDs must have buffers.
 524          */
 525         wmb();
 526
 527         for (i = 0; i < sizeof(rx_prods)/4; i++)
 528                 REG_WR_RELAXED(bp, fp->ustorm_rx_prods_offset + i * 4,
 529                                ((u32 *)&rx_prods)[i]);
 530
 531         mmiowb(); /* keep prod updates ordered */
 532
 533         DP(NETIF_MSG_RX_STATUS,
 534            "queue[%d]:  wrote  bd_prod %u  cqe_prod %u  sge_prod %u\n",
 535            fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
 536 }
 537
 538 /* reload helper */
 539 int bnx2x_reload_if_running(struct net_device *dev);
 540
 541 int bnx2x_change_mac_addr(struct net_device *dev, void *p);
 542
 543 /* NAPI poll Tx part */
 544 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata);
 545
 546 /* suspend/resume callbacks */
 547 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
 548 int bnx2x_resume(struct pci_dev *pdev);
 549
 550 /* Release IRQ vectors */
 551 void bnx2x_free_irq(struct bnx2x *bp);
 552
 553 void bnx2x_free_fp_mem(struct bnx2x *bp);
 554 void bnx2x_init_rx_rings(struct bnx2x *bp);
 555 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp);
 556 void bnx2x_free_skbs(struct bnx2x *bp);
 557 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
 558 void bnx2x_netif_start(struct bnx2x *bp);
 559 int bnx2x_load_cnic(struct bnx2x *bp);
 560
 561 /**
 562  * bnx2x_enable_msix - set msix configuration.
 563  *
 564  * @bp:         driver handle
 565  *
 566  * fills msix_table, requests vectors, updates num_queues
 567  * according to number of available vectors.
 568  */
 569 int bnx2x_enable_msix(struct bnx2x *bp);
 570
 571 /**
 572  * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
 573  *
 574  * @bp:         driver handle
 575  */
 576 int bnx2x_enable_msi(struct bnx2x *bp);
 577
 578 /**
 579  * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
 580  *
 581  * @bp:         driver handle
 582  */
 583 int bnx2x_alloc_mem_bp(struct bnx2x *bp);
 584
 585 /**
 586  * bnx2x_free_mem_bp - release memories outsize main driver structure
 587  *
 588  * @bp:         driver handle
 589  */
 590 void bnx2x_free_mem_bp(struct bnx2x *bp);
 591
 592 /**
 593  * bnx2x_change_mtu - change mtu netdev callback
 594  *
 595  * @dev:        net device
 596  * @new_mtu:    requested mtu
 597  *
 598  */
 599 int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
 600
 601 #ifdef NETDEV_FCOE_WWNN
 602 /**
 603  * bnx2x_fcoe_get_wwn - return the requested WWN value for this port
 604  *
 605  * @dev:        net_device
 606  * @wwn:        output buffer
 607  * @type:       WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port)
 608  *
 609  */
 610 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type);
 611 #endif
 612
 613 netdev_features_t bnx2x_fix_features(struct net_device *dev,
 614                                      netdev_features_t features);
 615 int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
 616
 617 /**
 618  * bnx2x_tx_timeout - tx timeout netdev callback
 619  *
 620  * @dev:        net device
 621  */
 622 void bnx2x_tx_timeout(struct net_device *dev);
 623
 624 /** bnx2x_get_c2s_mapping - read inner-to-outer vlan configuration
 625  * c2s_map should have BNX2X_MAX_PRIORITY entries.
 626  * @bp:                 driver handle
 627  * @c2s_map:            should have BNX2X_MAX_PRIORITY entries for mapping
 628  * @c2s_default:        entry for non-tagged configuration
 629  */
 630 void bnx2x_get_c2s_mapping(struct bnx2x *bp, u8 *c2s_map, u8 *c2s_default);
 631
 632 /*********************** Inlines **********************************/
 633 /*********************** Fast path ********************************/
 634 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
 635 {
 636         barrier(); /* status block is written to by the chip */
 637         fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
 638 }
 639
 640 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
 641                                         u8 segment, u16 index, u8 op,
 642                                         u8 update, u32 igu_addr)
 643 {
 644         struct igu_regular cmd_data = {0};
 645
 646         cmd_data.sb_id_and_flags =
 647                         ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
 648                          (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
 649                          (update << IGU_REGULAR_BUPDATE_SHIFT) |
 650                          (op << IGU_REGULAR_ENABLE_INT_SHIFT));
 651
 652         DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
 653            cmd_data.sb_id_and_flags, igu_addr);
 654         REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
 655
 656         /* Make sure that ACK is written */
 657         mmiowb();
 658         barrier();
 659 }
 660
 661 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
 662                                    u8 storm, u16 index, u8 op, u8 update)
 663 {
 664         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
 665                        COMMAND_REG_INT_ACK);
 666         struct igu_ack_register igu_ack;
 667
 668         igu_ack.status_block_index = index;
 669         igu_ack.sb_id_and_flags =
 670                         ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
 671                          (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
 672                          (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
 673                          (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
 674
 675         REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
 676
 677         /* Make sure that ACK is written */
 678         mmiowb();
 679         barrier();
 680 }
 681
 682 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
 683                                 u16 index, u8 op, u8 update)
 684 {
 685         if (bp->common.int_block == INT_BLOCK_HC)
 686                 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
 687         else {
 688                 u8 segment;
 689
 690                 if (CHIP_INT_MODE_IS_BC(bp))
 691                         segment = storm;
 692                 else if (igu_sb_id != bp->igu_dsb_id)
 693                         segment = IGU_SEG_ACCESS_DEF;
 694                 else if (storm == ATTENTION_ID)
 695                         segment = IGU_SEG_ACCESS_ATTN;
 696                 else
 697                         segment = IGU_SEG_ACCESS_DEF;
 698                 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
 699         }
 700 }
 701
 702 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
 703 {
 704         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
 705                        COMMAND_REG_SIMD_MASK);
 706         u32 result = REG_RD(bp, hc_addr);
 707
 708         barrier();
 709         return result;
 710 }
 711
 712 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
 713 {
 714         u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
 715         u32 result = REG_RD(bp, igu_addr);
 716
 717         DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
 718            result, igu_addr);
 719
 720         barrier();
 721         return result;
 722 }
 723
 724 static inline u16 bnx2x_ack_int(struct bnx2x *bp)
 725 {
 726         barrier();
 727         if (bp->common.int_block == INT_BLOCK_HC)
 728                 return bnx2x_hc_ack_int(bp);
 729         else
 730                 return bnx2x_igu_ack_int(bp);
 731 }
 732
 733 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
 734 {
 735         /* Tell compiler that consumer and producer can change */
 736         barrier();
 737         return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
 738 }
 739
 740 static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
 741                                  struct bnx2x_fp_txdata *txdata)
 742 {
 743         s16 used;
 744         u16 prod;
 745         u16 cons;
 746
 747         prod = txdata->tx_bd_prod;
 748         cons = txdata->tx_bd_cons;
 749
 750         used = SUB_S16(prod, cons);
 751
 752 #ifdef BNX2X_STOP_ON_ERROR
 753         WARN_ON(used < 0);
 754         WARN_ON(used > txdata->tx_ring_size);
 755         WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL);
 756 #endif
 757
 758         return (s16)(txdata->tx_ring_size) - used;
 759 }
 760
 761 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
 762 {
 763         u16 hw_cons;
 764
 765         /* Tell compiler that status block fields can change */
 766         barrier();
 767         hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
 768         return hw_cons != txdata->tx_pkt_cons;
 769 }
 770
 771 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
 772 {
 773         u8 cos;
 774         for_each_cos_in_tx_queue(fp, cos)
 775                 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
 776                         return true;
 777         return false;
 778 }
 779
 780 #define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0)
 781 #define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF)
 782 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
 783 {
 784         u16 cons;
 785         union eth_rx_cqe *cqe;
 786         struct eth_fast_path_rx_cqe *cqe_fp;
 787
 788         cons = RCQ_BD(fp->rx_comp_cons);
 789         cqe = &fp->rx_comp_ring[cons];
 790         cqe_fp = &cqe->fast_path_cqe;
 791         return BNX2X_IS_CQE_COMPLETED(cqe_fp);
 792 }
 793
 794 /**
 795  * bnx2x_tx_disable - disables tx from stack point of view
 796  *
 797  * @bp:         driver handle
 798  */
 799 static inline void bnx2x_tx_disable(struct bnx2x *bp)
 800 {
 801         netif_tx_disable(bp->dev);
 802         netif_carrier_off(bp->dev);
 803 }
 804
 805 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
 806                                      struct bnx2x_fastpath *fp, u16 index)
 807 {
 808         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
 809         struct page *page = sw_buf->page;
 810         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
 811
 812         /* Skip "next page" elements */
 813         if (!page)
 814                 return;
 815
 816         /* Since many fragments can share the same page, make sure to
 817          * only unmap and free the page once.
 818          */
 819         dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
 820                        SGE_PAGE_SIZE, DMA_FROM_DEVICE);
 821
 822         put_page(page);
 823
 824         sw_buf->page = NULL;
 825         sge->addr_hi = 0;
 826         sge->addr_lo = 0;
 827 }
 828
 829 static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp)
 830 {
 831         int i;
 832
 833         for_each_rx_queue_cnic(bp, i) {
 834                 napi_hash_del(&bnx2x_fp(bp, i, napi));
 835                 netif_napi_del(&bnx2x_fp(bp, i, napi));
 836         }
 837 }
 838
 839 static inline void bnx2x_del_all_napi(struct bnx2x *bp)
 840 {
 841         int i;
 842
 843         for_each_eth_queue(bp, i) {
 844                 napi_hash_del(&bnx2x_fp(bp, i, napi));
 845                 netif_napi_del(&bnx2x_fp(bp, i, napi));
 846         }
 847 }
 848
 849 int bnx2x_set_int_mode(struct bnx2x *bp);
 850
 851 static inline void bnx2x_disable_msi(struct bnx2x *bp)
 852 {
 853         if (bp->flags & USING_MSIX_FLAG) {
 854                 pci_disable_msix(bp->pdev);
 855                 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG);
 856         } else if (bp->flags & USING_MSI_FLAG) {
 857                 pci_disable_msi(bp->pdev);
 858                 bp->flags &= ~USING_MSI_FLAG;
 859         }
 860 }
 861
 862 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
 863 {
 864         int i, j;
 865
 866         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
 867                 int idx = RX_SGE_CNT * i - 1;
 868
 869                 for (j = 0; j < 2; j++) {
 870                         BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
 871                         idx--;
 872                 }
 873         }
 874 }
 875
 876 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
 877 {
 878         /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
 879         memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
 880
 881         /* Clear the two last indices in the page to 1:
 882            these are the indices that correspond to the "next" element,
 883            hence will never be indicated and should be removed from
 884            the calculations. */
 885         bnx2x_clear_sge_mask_next_elems(fp);
 886 }
 887
 888 /* note that we are not allocating a new buffer,
 889  * we are just moving one from cons to prod
 890  * we are not creating a new mapping,
 891  * so there is no need to check for dma_mapping_error().
 892  */
 893 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
 894                                       u16 cons, u16 prod)
 895 {
 896         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
 897         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
 898         struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
 899         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
 900
 901         dma_unmap_addr_set(prod_rx_buf, mapping,
 902                            dma_unmap_addr(cons_rx_buf, mapping));
 903         prod_rx_buf->data = cons_rx_buf->data;
 904         *prod_bd = *cons_bd;
 905 }
 906
 907 /************************* Init ******************************************/
 908
 909 /* returns func by VN for current port */
 910 static inline int func_by_vn(struct bnx2x *bp, int vn)
 911 {
 912         return 2 * vn + BP_PORT(bp);
 913 }
 914
 915 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash)
 916 {
 917         return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true);
 918 }
 919
 920 /**
 921  * bnx2x_func_start - init function
 922  *
 923  * @bp:         driver handle
 924  *
 925  * Must be called before sending CLIENT_SETUP for the first client.
 926  */
 927 static inline int bnx2x_func_start(struct bnx2x *bp)
 928 {
 929         struct bnx2x_func_state_params func_params = {NULL};
 930         struct bnx2x_func_start_params *start_params =
 931                 &func_params.params.start;
 932         u16 port;
 933
 934         /* Prepare parameters for function state transitions */
 935         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
 936
 937         func_params.f_obj = &bp->func_obj;
 938         func_params.cmd = BNX2X_F_CMD_START;
 939
 940         /* Function parameters */
 941         start_params->mf_mode = bp->mf_mode;
 942         start_params->sd_vlan_tag = bp->mf_ov;
 943
 944         /* Configure Ethertype for BD mode */
 945         if (IS_MF_BD(bp)) {
 946                 DP(NETIF_MSG_IFUP, "Configuring ethertype 0x88a8 for BD\n");
 947                 start_params->sd_vlan_eth_type = ETH_P_8021AD;
 948                 REG_WR(bp, PRS_REG_VLAN_TYPE_0, ETH_P_8021AD);
 949                 REG_WR(bp, PBF_REG_VLAN_TYPE_0, ETH_P_8021AD);
 950                 REG_WR(bp, NIG_REG_LLH_E1HOV_TYPE_1, ETH_P_8021AD);
 951
 952                 bnx2x_get_c2s_mapping(bp, start_params->c2s_pri,
 953                                       &start_params->c2s_pri_default);
 954                 start_params->c2s_pri_valid = 1;
 955
 956                 DP(NETIF_MSG_IFUP,
 957                    "Inner-to-Outer priority: %02x %02x %02x %02x %02x %02x %02x %02x [Default %02x]\n",
 958                    start_params->c2s_pri[0], start_params->c2s_pri[1],
 959                    start_params->c2s_pri[2], start_params->c2s_pri[3],
 960                    start_params->c2s_pri[4], start_params->c2s_pri[5],
 961                    start_params->c2s_pri[6], start_params->c2s_pri[7],
 962                    start_params->c2s_pri_default);
 963         }
 964
 965         if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
 966                 start_params->network_cos_mode = STATIC_COS;
 967         else /* CHIP_IS_E1X */
 968                 start_params->network_cos_mode = FW_WRR;
 969         if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
 970                 port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].dst_port;
 971                 start_params->vxlan_dst_port = port;
 972         }
 973         if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
 974                 port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].dst_port;
 975                 start_params->geneve_dst_port = port;
 976         }
 977
 978         start_params->inner_rss = 1;
 979
 980         if (IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
 981                 start_params->class_fail_ethtype = ETH_P_FIP;
 982                 start_params->class_fail = 1;
 983                 start_params->no_added_tags = 1;
 984         }
 985
 986         return bnx2x_func_state_change(bp, &func_params);
 987 }
 988
 989 /**
 990  * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
 991  *
 992  * @fw_hi:      pointer to upper part
 993  * @fw_mid:     pointer to middle part
 994  * @fw_lo:      pointer to lower part
 995  * @mac:        pointer to MAC address
 996  */
 997 static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
 998                                          __le16 *fw_lo, u8 *mac)
 999 {
1000         ((u8 *)fw_hi)[0]  = mac[1];
1001         ((u8 *)fw_hi)[1]  = mac[0];
1002         ((u8 *)fw_mid)[0] = mac[3];
1003         ((u8 *)fw_mid)[1] = mac[2];
1004         ((u8 *)fw_lo)[0]  = mac[5];
1005         ((u8 *)fw_lo)[1]  = mac[4];
1006 }
1007
1008 static inline void bnx2x_free_rx_mem_pool(struct bnx2x *bp,
1009                                           struct bnx2x_alloc_pool *pool)
1010 {
1011         if (!pool->page)
1012                 return;
1013
1014         put_page(pool->page);
1015
1016         pool->page = NULL;
1017 }
1018
1019 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
1020                                            struct bnx2x_fastpath *fp, int last)
1021 {
1022         int i;
1023
1024         if (fp->mode == TPA_MODE_DISABLED)
1025                 return;
1026
1027         for (i = 0; i < last; i++)
1028                 bnx2x_free_rx_sge(bp, fp, i);
1029
1030         bnx2x_free_rx_mem_pool(bp, &fp->page_pool);
1031 }
1032
1033 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
1034 {
1035         int i;
1036
1037         for (i = 1; i <= NUM_RX_RINGS; i++) {
1038                 struct eth_rx_bd *rx_bd;
1039
1040                 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
1041                 rx_bd->addr_hi =
1042                         cpu_to_le32(U64_HI(fp->rx_desc_mapping +
1043                                     BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1044                 rx_bd->addr_lo =
1045                         cpu_to_le32(U64_LO(fp->rx_desc_mapping +
1046                                     BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1047         }
1048 }
1049
1050 /* Statistics ID are global per chip/path, while Client IDs for E1x are per
1051  * port.
1052  */
1053 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1054 {
1055         struct bnx2x *bp = fp->bp;
1056         if (!CHIP_IS_E1x(bp)) {
1057                 /* there are special statistics counters for FCoE 136..140 */
1058                 if (IS_FCOE_FP(fp))
1059                         return bp->cnic_base_cl_id + (bp->pf_num >> 1);
1060                 return fp->cl_id;
1061         }
1062         return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x;
1063 }
1064
1065 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
1066                                                bnx2x_obj_type obj_type)
1067 {
1068         struct bnx2x *bp = fp->bp;
1069
1070         /* Configure classification DBs */
1071         bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id,
1072                            fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata),
1073                            bnx2x_sp_mapping(bp, mac_rdata),
1074                            BNX2X_FILTER_MAC_PENDING,
1075                            &bp->sp_state, obj_type,
1076                            &bp->macs_pool);
1077
1078         if (!CHIP_IS_E1x(bp))
1079                 bnx2x_init_vlan_obj(bp, &bnx2x_sp_obj(bp, fp).vlan_obj,
1080                                     fp->cl_id, fp->cid, BP_FUNC(bp),
1081                                     bnx2x_sp(bp, vlan_rdata),
1082                                     bnx2x_sp_mapping(bp, vlan_rdata),
1083                                     BNX2X_FILTER_VLAN_PENDING,
1084                                     &bp->sp_state, obj_type,
1085                                     &bp->vlans_pool);
1086 }
1087
1088 /**
1089  * bnx2x_get_path_func_num - get number of active functions
1090  *
1091  * @bp:         driver handle
1092  *
1093  * Calculates the number of active (not hidden) functions on the
1094  * current path.
1095  */
1096 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
1097 {
1098         u8 func_num = 0, i;
1099
1100         /* 57710 has only one function per-port */
1101         if (CHIP_IS_E1(bp))
1102                 return 1;
1103
1104         /* Calculate a number of functions enabled on the current
1105          * PATH/PORT.
1106          */
1107         if (CHIP_REV_IS_SLOW(bp)) {
1108                 if (IS_MF(bp))
1109                         func_num = 4;
1110                 else
1111                         func_num = 2;
1112         } else {
1113                 for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
1114                         u32 func_config =
1115                                 MF_CFG_RD(bp,
1116                                           func_mf_config[BP_PATH(bp) + 2 * i].
1117                                           config);
1118                         func_num +=
1119                                 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1);
1120                 }
1121         }
1122
1123         WARN_ON(!func_num);
1124
1125         return func_num;
1126 }
1127
1128 static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
1129 {
1130         /* RX_MODE controlling object */
1131         bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj);
1132
1133         /* multicast configuration controlling object */
1134         bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid,
1135                              BP_FUNC(bp), BP_FUNC(bp),
1136                              bnx2x_sp(bp, mcast_rdata),
1137                              bnx2x_sp_mapping(bp, mcast_rdata),
1138                              BNX2X_FILTER_MCAST_PENDING, &bp->sp_state,
1139                              BNX2X_OBJ_TYPE_RX);
1140
1141         /* Setup CAM credit pools */
1142         bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),
1143                                    bnx2x_get_path_func_num(bp));
1144
1145         bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_FUNC(bp),
1146                                     bnx2x_get_path_func_num(bp));
1147
1148         /* RSS configuration object */
1149         bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,
1150                                   bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),
1151                                   bnx2x_sp(bp, rss_rdata),
1152                                   bnx2x_sp_mapping(bp, rss_rdata),
1153                                   BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state,
1154                                   BNX2X_OBJ_TYPE_RX);
1155
1156         bp->vlan_credit = PF_VLAN_CREDIT_E2(bp, bnx2x_get_path_func_num(bp));
1157 }
1158
1159 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
1160 {
1161         if (CHIP_IS_E1x(fp->bp))
1162                 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
1163         else
1164                 return fp->cl_id;
1165 }
1166
1167 static inline void bnx2x_init_txdata(struct bnx2x *bp,
1168                                      struct bnx2x_fp_txdata *txdata, u32 cid,
1169                                      int txq_index, __le16 *tx_cons_sb,
1170                                      struct bnx2x_fastpath *fp)
1171 {
1172         txdata->cid = cid;
1173         txdata->txq_index = txq_index;
1174         txdata->tx_cons_sb = tx_cons_sb;
1175         txdata->parent_fp = fp;
1176         txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size;
1177
1178         DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1179            txdata->cid, txdata->txq_index);
1180 }
1181
1182 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
1183 {
1184         return bp->cnic_base_cl_id + cl_idx +
1185                 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
1186 }
1187
1188 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
1189 {
1190         /* the 'first' id is allocated for the cnic */
1191         return bp->base_fw_ndsb;
1192 }
1193
1194 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
1195 {
1196         return bp->igu_base_sb;
1197 }
1198
1199 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
1200                                        struct bnx2x_fp_txdata *txdata)
1201 {
1202         int cnt = 1000;
1203
1204         while (bnx2x_has_tx_work_unload(txdata)) {
1205                 if (!cnt) {
1206                         BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1207                                   txdata->txq_index, txdata->tx_pkt_prod,
1208                                   txdata->tx_pkt_cons);
1209 #ifdef BNX2X_STOP_ON_ERROR
1210                         bnx2x_panic();
1211                         return -EBUSY;
1212 #else
1213                         break;
1214 #endif
1215                 }
1216                 cnt--;
1217                 usleep_range(1000, 2000);
1218         }
1219
1220         return 0;
1221 }
1222
1223 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1224
1225 static inline void __storm_memset_struct(struct bnx2x *bp,
1226                                          u32 addr, size_t size, u32 *data)
1227 {
1228         int i;
1229         for (i = 0; i < size/4; i++)
1230                 REG_WR(bp, addr + (i * 4), data[i]);
1231 }
1232
1233 /**
1234  * bnx2x_wait_sp_comp - wait for the outstanding SP commands.
1235  *
1236  * @bp:         driver handle
1237  * @mask:       bits that need to be cleared
1238  */
1239 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
1240 {
1241         int tout = 5000; /* Wait for 5 secs tops */
1242
1243         while (tout--) {
1244                 smp_mb();
1245                 netif_addr_lock_bh(bp->dev);
1246                 if (!(bp->sp_state & mask)) {
1247                         netif_addr_unlock_bh(bp->dev);
1248                         return true;
1249                 }
1250                 netif_addr_unlock_bh(bp->dev);
1251
1252                 usleep_range(1000, 2000);
1253         }
1254
1255         smp_mb();
1256
1257         netif_addr_lock_bh(bp->dev);
1258         if (bp->sp_state & mask) {
1259                 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n",
1260                           bp->sp_state, mask);
1261                 netif_addr_unlock_bh(bp->dev);
1262                 return false;
1263         }
1264         netif_addr_unlock_bh(bp->dev);
1265
1266         return true;
1267 }
1268
1269 /**
1270  * bnx2x_set_ctx_validation - set CDU context validation values
1271  *
1272  * @bp:         driver handle
1273  * @cxt:        context of the connection on the host memory
1274  * @cid:        SW CID of the connection to be configured
1275  */
1276 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
1277                               u32 cid);
1278
1279 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
1280                                     u8 sb_index, u8 disable, u16 usec);
1281 void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1282 void bnx2x_release_phy_lock(struct bnx2x *bp);
1283
1284 /**
1285  * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
1286  *
1287  * @bp:         driver handle
1288  * @mf_cfg:     MF configuration
1289  *
1290  */
1291 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
1292 {
1293         u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1294                               FUNC_MF_CFG_MAX_BW_SHIFT;
1295         if (!max_cfg) {
1296                 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1297                    "Max BW configured to 0 - using 100 instead\n");
1298                 max_cfg = 100;
1299         }
1300         return max_cfg;
1301 }
1302
1303 /* checks if HW supports GRO for given MTU */
1304 static inline bool bnx2x_mtu_allows_gro(int mtu)
1305 {
1306         /* gro frags per page */
1307         int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE);
1308
1309         /*
1310          * 1. Number of frags should not grow above MAX_SKB_FRAGS
1311          * 2. Frag must fit the page
1312          */
1313         return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS;
1314 }
1315
1316 /**
1317  * bnx2x_get_iscsi_info - update iSCSI params according to licensing info.
1318  *
1319  * @bp:         driver handle
1320  *
1321  */
1322 void bnx2x_get_iscsi_info(struct bnx2x *bp);
1323
1324 /**
1325  * bnx2x_link_sync_notify - send notification to other functions.
1326  *
1327  * @bp:         driver handle
1328  *
1329  */
1330 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
1331 {
1332         int func;
1333         int vn;
1334
1335         /* Set the attention towards other drivers on the same port */
1336         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
1337                 if (vn == BP_VN(bp))
1338                         continue;
1339
1340                 func = func_by_vn(bp, vn);
1341                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1342                        (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1343         }
1344 }
1345
1346 /**
1347  * bnx2x_update_drv_flags - update flags in shmem
1348  *
1349  * @bp:         driver handle
1350  * @flags:      flags to update
1351  * @set:        set or clear
1352  *
1353  */
1354 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
1355 {
1356         if (SHMEM2_HAS(bp, drv_flags)) {
1357                 u32 drv_flags;
1358                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1359                 drv_flags = SHMEM2_RD(bp, drv_flags);
1360
1361                 if (set)
1362                         SET_FLAGS(drv_flags, flags);
1363                 else
1364                         RESET_FLAGS(drv_flags, flags);
1365
1366                 SHMEM2_WR(bp, drv_flags, drv_flags);
1367                 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
1368                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1369         }
1370 }
1371
1372
1373
1374 /**
1375  * bnx2x_fill_fw_str - Fill buffer with FW version string
1376  *
1377  * @bp:        driver handle
1378  * @buf:       character buffer to fill with the fw name
1379  * @buf_len:   length of the above buffer
1380  *
1381  */
1382 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len);
1383
1384 int bnx2x_drain_tx_queues(struct bnx2x *bp);
1385 void bnx2x_squeeze_objects(struct bnx2x *bp);
1386
1387 void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag,
1388                             u32 verbose);
1389
1390 /**
1391  * bnx2x_set_os_driver_state - write driver state for management FW usage
1392  *
1393  * @bp:         driver handle
1394  * @state:      OS_DRIVER_STATE_* value reflecting current driver state
1395  */
1396 void bnx2x_set_os_driver_state(struct bnx2x *bp, u32 state);
1397
1398 /**
1399  * bnx2x_nvram_read - reads data from nvram [might sleep]
1400  *
1401  * @bp:         driver handle
1402  * @offset:     byte offset in nvram
1403  * @ret_buf:    pointer to buffer where data is to be stored
1404  * @buf_size:   Length of 'ret_buf' in bytes
1405  */
1406 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1407                      int buf_size);
1408
1409 #endif /* BNX2X_CMN_H */