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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
blobab4d1dacb5854ece9294b3c68335a35429ffe4de
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
31 #include <asm/page.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/if.h>
35 #include <linux/if_vlan.h>
36 #include <linux/if_bridge.h>
37 #include <linux/rtc.h>
38 #include <linux/bpf.h>
39 #include <net/ip.h>
40 #include <net/tcp.h>
41 #include <net/udp.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <net/udp_tunnel.h>
45 #include <linux/workqueue.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/log2.h>
49 #include <linux/aer.h>
50 #include <linux/bitmap.h>
51 #include <linux/cpu_rmap.h>
52 #include <linux/cpumask.h>
53 #include <net/pkt_cls.h>
54 #include <linux/hwmon.h>
55 #include <linux/hwmon-sysfs.h>
56
57 #include "bnxt_hsi.h"
58 #include "bnxt.h"
59 #include "bnxt_ulp.h"
60 #include "bnxt_sriov.h"
61 #include "bnxt_ethtool.h"
62 #include "bnxt_dcb.h"
63 #include "bnxt_xdp.h"
64 #include "bnxt_vfr.h"
65 #include "bnxt_tc.h"
66 #include "bnxt_devlink.h"
67 #include "bnxt_debugfs.h"
68
69 #define BNXT_TX_TIMEOUT (5 * HZ)
70
71 static const char version[] =
72 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
73
74 MODULE_LICENSE("GPL");
75 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
76 MODULE_VERSION(DRV_MODULE_VERSION);
77
78 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
79 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
80 #define BNXT_RX_COPY_THRESH 256
81
82 #define BNXT_TX_PUSH_THRESH 164
83
84 enum board_idx {
85 BCM57301,
86 BCM57302,
87 BCM57304,
88 BCM57417_NPAR,
89 BCM58700,
90 BCM57311,
91 BCM57312,
92 BCM57402,
93 BCM57404,
94 BCM57406,
95 BCM57402_NPAR,
96 BCM57407,
97 BCM57412,
98 BCM57414,
99 BCM57416,
100 BCM57417,
101 BCM57412_NPAR,
102 BCM57314,
103 BCM57417_SFP,
104 BCM57416_SFP,
105 BCM57404_NPAR,
106 BCM57406_NPAR,
107 BCM57407_SFP,
108 BCM57407_NPAR,
109 BCM57414_NPAR,
110 BCM57416_NPAR,
111 BCM57452,
112 BCM57454,
113 BCM5745x_NPAR,
114 BCM58802,
115 BCM58804,
116 BCM58808,
117 NETXTREME_E_VF,
118 NETXTREME_C_VF,
119 NETXTREME_S_VF,
120 };
121
122 /* indexed by enum above */
123 static const struct {
124 char *name;
125 } board_info[] = {
126 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
127 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
128 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
129 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
130 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
131 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
132 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
133 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
134 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
135 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
136 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
137 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
138 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
139 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
140 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
141 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
142 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
143 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
144 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
145 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
146 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
147 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
148 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
149 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
150 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
151 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
152 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
153 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
154 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
155 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
156 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
157 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
158 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
159 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
160 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
161 };
162
163 static const struct pci_device_id bnxt_pci_tbl[] = {
164 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
165 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
166 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
167 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
168 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
169 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
170 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
171 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
172 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
173 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
174 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
175 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
176 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
177 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
178 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
179 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
180 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
181 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
182 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
183 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
184 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
185 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
186 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
187 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
188 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
189 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
190 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
191 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
192 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
193 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
194 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
195 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
196 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
197 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
198 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
199 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
200 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
201 #ifdef CONFIG_BNXT_SRIOV
202 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
203 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
204 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
205 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
206 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
207 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
208 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
209 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
210 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
211 #endif
212 { 0 }
213 };
214
215 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
216
217 static const u16 bnxt_vf_req_snif[] = {
218 HWRM_FUNC_CFG,
219 HWRM_FUNC_VF_CFG,
220 HWRM_PORT_PHY_QCFG,
221 HWRM_CFA_L2_FILTER_ALLOC,
222 };
223
224 static const u16 bnxt_async_events_arr[] = {
225 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
226 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
227 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
228 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
229 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
230 };
231
232 static struct workqueue_struct *bnxt_pf_wq;
233
234 static bool bnxt_vf_pciid(enum board_idx idx)
235 {
236 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
237 idx == NETXTREME_S_VF);
238 }
239
240 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
241 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
242 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
243
244 #define BNXT_CP_DB_REARM(db, raw_cons) \
245 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
246
247 #define BNXT_CP_DB(db, raw_cons) \
248 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
249
250 #define BNXT_CP_DB_IRQ_DIS(db) \
251 writel(DB_CP_IRQ_DIS_FLAGS, db)
252
253 const u16 bnxt_lhint_arr[] = {
254 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
255 TX_BD_FLAGS_LHINT_512_TO_1023,
256 TX_BD_FLAGS_LHINT_1024_TO_2047,
257 TX_BD_FLAGS_LHINT_1024_TO_2047,
258 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
259 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
260 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
261 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
262 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
263 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
264 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
265 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
266 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
267 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
268 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
269 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
270 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
271 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
272 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
273 };
274
275 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
276 {
277 struct metadata_dst *md_dst = skb_metadata_dst(skb);
278
279 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
280 return 0;
281
282 return md_dst->u.port_info.port_id;
283 }
284
285 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
286 {
287 struct bnxt *bp = netdev_priv(dev);
288 struct tx_bd *txbd;
289 struct tx_bd_ext *txbd1;
290 struct netdev_queue *txq;
291 int i;
292 dma_addr_t mapping;
293 unsigned int length, pad = 0;
294 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
295 u16 prod, last_frag;
296 struct pci_dev *pdev = bp->pdev;
297 struct bnxt_tx_ring_info *txr;
298 struct bnxt_sw_tx_bd *tx_buf;
299
300 i = skb_get_queue_mapping(skb);
301 if (unlikely(i >= bp->tx_nr_rings)) {
302 dev_kfree_skb_any(skb);
303 return NETDEV_TX_OK;
304 }
305
306 txq = netdev_get_tx_queue(dev, i);
307 txr = &bp->tx_ring[bp->tx_ring_map[i]];
308 prod = txr->tx_prod;
309
310 free_size = bnxt_tx_avail(bp, txr);
311 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
312 netif_tx_stop_queue(txq);
313 return NETDEV_TX_BUSY;
314 }
315
316 length = skb->len;
317 len = skb_headlen(skb);
318 last_frag = skb_shinfo(skb)->nr_frags;
319
320 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
321
322 txbd->tx_bd_opaque = prod;
323
324 tx_buf = &txr->tx_buf_ring[prod];
325 tx_buf->skb = skb;
326 tx_buf->nr_frags = last_frag;
327
328 vlan_tag_flags = 0;
329 cfa_action = bnxt_xmit_get_cfa_action(skb);
330 if (skb_vlan_tag_present(skb)) {
331 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
332 skb_vlan_tag_get(skb);
333 /* Currently supports 8021Q, 8021AD vlan offloads
334 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
335 */
336 if (skb->vlan_proto == htons(ETH_P_8021Q))
337 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
338 }
339
340 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
341 struct tx_push_buffer *tx_push_buf = txr->tx_push;
342 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
343 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
344 void *pdata = tx_push_buf->data;
345 u64 *end;
346 int j, push_len;
347
348 /* Set COAL_NOW to be ready quickly for the next push */
349 tx_push->tx_bd_len_flags_type =
350 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
351 TX_BD_TYPE_LONG_TX_BD |
352 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
353 TX_BD_FLAGS_COAL_NOW |
354 TX_BD_FLAGS_PACKET_END |
355 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
356
357 if (skb->ip_summed == CHECKSUM_PARTIAL)
358 tx_push1->tx_bd_hsize_lflags =
359 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
360 else
361 tx_push1->tx_bd_hsize_lflags = 0;
362
363 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
364 tx_push1->tx_bd_cfa_action =
365 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
366
367 end = pdata + length;
368 end = PTR_ALIGN(end, 8) - 1;
369 *end = 0;
370
371 skb_copy_from_linear_data(skb, pdata, len);
372 pdata += len;
373 for (j = 0; j < last_frag; j++) {
374 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
375 void *fptr;
376
377 fptr = skb_frag_address_safe(frag);
378 if (!fptr)
379 goto normal_tx;
380
381 memcpy(pdata, fptr, skb_frag_size(frag));
382 pdata += skb_frag_size(frag);
383 }
384
385 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
386 txbd->tx_bd_haddr = txr->data_mapping;
387 prod = NEXT_TX(prod);
388 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
389 memcpy(txbd, tx_push1, sizeof(*txbd));
390 prod = NEXT_TX(prod);
391 tx_push->doorbell =
392 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
393 txr->tx_prod = prod;
394
395 tx_buf->is_push = 1;
396 netdev_tx_sent_queue(txq, skb->len);
397 wmb(); /* Sync is_push and byte queue before pushing data */
398
399 push_len = (length + sizeof(*tx_push) + 7) / 8;
400 if (push_len > 16) {
401 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
402 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
403 (push_len - 16) << 1);
404 } else {
405 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
406 push_len);
407 }
408
409 goto tx_done;
410 }
411
412 normal_tx:
413 if (length < BNXT_MIN_PKT_SIZE) {
414 pad = BNXT_MIN_PKT_SIZE - length;
415 if (skb_pad(skb, pad)) {
416 /* SKB already freed. */
417 tx_buf->skb = NULL;
418 return NETDEV_TX_OK;
419 }
420 length = BNXT_MIN_PKT_SIZE;
421 }
422
423 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
424
425 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
426 dev_kfree_skb_any(skb);
427 tx_buf->skb = NULL;
428 return NETDEV_TX_OK;
429 }
430
431 dma_unmap_addr_set(tx_buf, mapping, mapping);
432 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
433 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
434
435 txbd->tx_bd_haddr = cpu_to_le64(mapping);
436
437 prod = NEXT_TX(prod);
438 txbd1 = (struct tx_bd_ext *)
439 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
440
441 txbd1->tx_bd_hsize_lflags = 0;
442 if (skb_is_gso(skb)) {
443 u32 hdr_len;
444
445 if (skb->encapsulation)
446 hdr_len = skb_inner_network_offset(skb) +
447 skb_inner_network_header_len(skb) +
448 inner_tcp_hdrlen(skb);
449 else
450 hdr_len = skb_transport_offset(skb) +
451 tcp_hdrlen(skb);
452
453 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
454 TX_BD_FLAGS_T_IPID |
455 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
456 length = skb_shinfo(skb)->gso_size;
457 txbd1->tx_bd_mss = cpu_to_le32(length);
458 length += hdr_len;
459 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
460 txbd1->tx_bd_hsize_lflags =
461 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
462 txbd1->tx_bd_mss = 0;
463 }
464
465 length >>= 9;
466 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
467 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
468 skb->len);
469 i = 0;
470 goto tx_dma_error;
471 }
472 flags |= bnxt_lhint_arr[length];
473 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
474
475 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
476 txbd1->tx_bd_cfa_action =
477 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
478 for (i = 0; i < last_frag; i++) {
479 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
480
481 prod = NEXT_TX(prod);
482 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
483
484 len = skb_frag_size(frag);
485 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
486 DMA_TO_DEVICE);
487
488 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
489 goto tx_dma_error;
490
491 tx_buf = &txr->tx_buf_ring[prod];
492 dma_unmap_addr_set(tx_buf, mapping, mapping);
493
494 txbd->tx_bd_haddr = cpu_to_le64(mapping);
495
496 flags = len << TX_BD_LEN_SHIFT;
497 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
498 }
499
500 flags &= ~TX_BD_LEN;
501 txbd->tx_bd_len_flags_type =
502 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
503 TX_BD_FLAGS_PACKET_END);
504
505 netdev_tx_sent_queue(txq, skb->len);
506
507 /* Sync BD data before updating doorbell */
508 wmb();
509
510 prod = NEXT_TX(prod);
511 txr->tx_prod = prod;
512
513 if (!skb->xmit_more || netif_xmit_stopped(txq))
514 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
515
516 tx_done:
517
518 mmiowb();
519
520 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
521 if (skb->xmit_more && !tx_buf->is_push)
522 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
523
524 netif_tx_stop_queue(txq);
525
526 /* netif_tx_stop_queue() must be done before checking
527 * tx index in bnxt_tx_avail() below, because in
528 * bnxt_tx_int(), we update tx index before checking for
529 * netif_tx_queue_stopped().
530 */
531 smp_mb();
532 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
533 netif_tx_wake_queue(txq);
534 }
535 return NETDEV_TX_OK;
536
537 tx_dma_error:
538 last_frag = i;
539
540 /* start back at beginning and unmap skb */
541 prod = txr->tx_prod;
542 tx_buf = &txr->tx_buf_ring[prod];
543 tx_buf->skb = NULL;
544 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
545 skb_headlen(skb), PCI_DMA_TODEVICE);
546 prod = NEXT_TX(prod);
547
548 /* unmap remaining mapped pages */
549 for (i = 0; i < last_frag; i++) {
550 prod = NEXT_TX(prod);
551 tx_buf = &txr->tx_buf_ring[prod];
552 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
553 skb_frag_size(&skb_shinfo(skb)->frags[i]),
554 PCI_DMA_TODEVICE);
555 }
556
557 dev_kfree_skb_any(skb);
558 return NETDEV_TX_OK;
559 }
560
561 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
562 {
563 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
564 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
565 u16 cons = txr->tx_cons;
566 struct pci_dev *pdev = bp->pdev;
567 int i;
568 unsigned int tx_bytes = 0;
569
570 for (i = 0; i < nr_pkts; i++) {
571 struct bnxt_sw_tx_bd *tx_buf;
572 struct sk_buff *skb;
573 int j, last;
574
575 tx_buf = &txr->tx_buf_ring[cons];
576 cons = NEXT_TX(cons);
577 skb = tx_buf->skb;
578 tx_buf->skb = NULL;
579
580 if (tx_buf->is_push) {
581 tx_buf->is_push = 0;
582 goto next_tx_int;
583 }
584
585 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
586 skb_headlen(skb), PCI_DMA_TODEVICE);
587 last = tx_buf->nr_frags;
588
589 for (j = 0; j < last; j++) {
590 cons = NEXT_TX(cons);
591 tx_buf = &txr->tx_buf_ring[cons];
592 dma_unmap_page(
593 &pdev->dev,
594 dma_unmap_addr(tx_buf, mapping),
595 skb_frag_size(&skb_shinfo(skb)->frags[j]),
596 PCI_DMA_TODEVICE);
597 }
598
599 next_tx_int:
600 cons = NEXT_TX(cons);
601
602 tx_bytes += skb->len;
603 dev_kfree_skb_any(skb);
604 }
605
606 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
607 txr->tx_cons = cons;
608
609 /* Need to make the tx_cons update visible to bnxt_start_xmit()
610 * before checking for netif_tx_queue_stopped(). Without the
611 * memory barrier, there is a small possibility that bnxt_start_xmit()
612 * will miss it and cause the queue to be stopped forever.
613 */
614 smp_mb();
615
616 if (unlikely(netif_tx_queue_stopped(txq)) &&
617 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
618 __netif_tx_lock(txq, smp_processor_id());
619 if (netif_tx_queue_stopped(txq) &&
620 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
621 txr->dev_state != BNXT_DEV_STATE_CLOSING)
622 netif_tx_wake_queue(txq);
623 __netif_tx_unlock(txq);
624 }
625 }
626
627 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
628 gfp_t gfp)
629 {
630 struct device *dev = &bp->pdev->dev;
631 struct page *page;
632
633 page = alloc_page(gfp);
634 if (!page)
635 return NULL;
636
637 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
638 DMA_ATTR_WEAK_ORDERING);
639 if (dma_mapping_error(dev, *mapping)) {
640 __free_page(page);
641 return NULL;
642 }
643 *mapping += bp->rx_dma_offset;
644 return page;
645 }
646
647 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
648 gfp_t gfp)
649 {
650 u8 *data;
651 struct pci_dev *pdev = bp->pdev;
652
653 data = kmalloc(bp->rx_buf_size, gfp);
654 if (!data)
655 return NULL;
656
657 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
658 bp->rx_buf_use_size, bp->rx_dir,
659 DMA_ATTR_WEAK_ORDERING);
660
661 if (dma_mapping_error(&pdev->dev, *mapping)) {
662 kfree(data);
663 data = NULL;
664 }
665 return data;
666 }
667
668 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
669 u16 prod, gfp_t gfp)
670 {
671 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
672 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
673 dma_addr_t mapping;
674
675 if (BNXT_RX_PAGE_MODE(bp)) {
676 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
677
678 if (!page)
679 return -ENOMEM;
680
681 rx_buf->data = page;
682 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
683 } else {
684 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
685
686 if (!data)
687 return -ENOMEM;
688
689 rx_buf->data = data;
690 rx_buf->data_ptr = data + bp->rx_offset;
691 }
692 rx_buf->mapping = mapping;
693
694 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
695 return 0;
696 }
697
698 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
699 {
700 u16 prod = rxr->rx_prod;
701 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
702 struct rx_bd *cons_bd, *prod_bd;
703
704 prod_rx_buf = &rxr->rx_buf_ring[prod];
705 cons_rx_buf = &rxr->rx_buf_ring[cons];
706
707 prod_rx_buf->data = data;
708 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
709
710 prod_rx_buf->mapping = cons_rx_buf->mapping;
711
712 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
713 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
714
715 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
716 }
717
718 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
719 {
720 u16 next, max = rxr->rx_agg_bmap_size;
721
722 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
723 if (next >= max)
724 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
725 return next;
726 }
727
728 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
729 struct bnxt_rx_ring_info *rxr,
730 u16 prod, gfp_t gfp)
731 {
732 struct rx_bd *rxbd =
733 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
734 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
735 struct pci_dev *pdev = bp->pdev;
736 struct page *page;
737 dma_addr_t mapping;
738 u16 sw_prod = rxr->rx_sw_agg_prod;
739 unsigned int offset = 0;
740
741 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
742 page = rxr->rx_page;
743 if (!page) {
744 page = alloc_page(gfp);
745 if (!page)
746 return -ENOMEM;
747 rxr->rx_page = page;
748 rxr->rx_page_offset = 0;
749 }
750 offset = rxr->rx_page_offset;
751 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
752 if (rxr->rx_page_offset == PAGE_SIZE)
753 rxr->rx_page = NULL;
754 else
755 get_page(page);
756 } else {
757 page = alloc_page(gfp);
758 if (!page)
759 return -ENOMEM;
760 }
761
762 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
763 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
764 DMA_ATTR_WEAK_ORDERING);
765 if (dma_mapping_error(&pdev->dev, mapping)) {
766 __free_page(page);
767 return -EIO;
768 }
769
770 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
771 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
772
773 __set_bit(sw_prod, rxr->rx_agg_bmap);
774 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
775 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
776
777 rx_agg_buf->page = page;
778 rx_agg_buf->offset = offset;
779 rx_agg_buf->mapping = mapping;
780 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
781 rxbd->rx_bd_opaque = sw_prod;
782 return 0;
783 }
784
785 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
786 u32 agg_bufs)
787 {
788 struct bnxt *bp = bnapi->bp;
789 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
790 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
791 u16 prod = rxr->rx_agg_prod;
792 u16 sw_prod = rxr->rx_sw_agg_prod;
793 u32 i;
794
795 for (i = 0; i < agg_bufs; i++) {
796 u16 cons;
797 struct rx_agg_cmp *agg;
798 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
799 struct rx_bd *prod_bd;
800 struct page *page;
801
802 agg = (struct rx_agg_cmp *)
803 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
804 cons = agg->rx_agg_cmp_opaque;
805 __clear_bit(cons, rxr->rx_agg_bmap);
806
807 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
808 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
809
810 __set_bit(sw_prod, rxr->rx_agg_bmap);
811 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
812 cons_rx_buf = &rxr->rx_agg_ring[cons];
813
814 /* It is possible for sw_prod to be equal to cons, so
815 * set cons_rx_buf->page to NULL first.
816 */
817 page = cons_rx_buf->page;
818 cons_rx_buf->page = NULL;
819 prod_rx_buf->page = page;
820 prod_rx_buf->offset = cons_rx_buf->offset;
821
822 prod_rx_buf->mapping = cons_rx_buf->mapping;
823
824 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
825
826 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
827 prod_bd->rx_bd_opaque = sw_prod;
828
829 prod = NEXT_RX_AGG(prod);
830 sw_prod = NEXT_RX_AGG(sw_prod);
831 cp_cons = NEXT_CMP(cp_cons);
832 }
833 rxr->rx_agg_prod = prod;
834 rxr->rx_sw_agg_prod = sw_prod;
835 }
836
837 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
838 struct bnxt_rx_ring_info *rxr,
839 u16 cons, void *data, u8 *data_ptr,
840 dma_addr_t dma_addr,
841 unsigned int offset_and_len)
842 {
843 unsigned int payload = offset_and_len >> 16;
844 unsigned int len = offset_and_len & 0xffff;
845 struct skb_frag_struct *frag;
846 struct page *page = data;
847 u16 prod = rxr->rx_prod;
848 struct sk_buff *skb;
849 int off, err;
850
851 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
852 if (unlikely(err)) {
853 bnxt_reuse_rx_data(rxr, cons, data);
854 return NULL;
855 }
856 dma_addr -= bp->rx_dma_offset;
857 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
858 DMA_ATTR_WEAK_ORDERING);
859
860 if (unlikely(!payload))
861 payload = eth_get_headlen(data_ptr, len);
862
863 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
864 if (!skb) {
865 __free_page(page);
866 return NULL;
867 }
868
869 off = (void *)data_ptr - page_address(page);
870 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
871 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
872 payload + NET_IP_ALIGN);
873
874 frag = &skb_shinfo(skb)->frags[0];
875 skb_frag_size_sub(frag, payload);
876 frag->page_offset += payload;
877 skb->data_len -= payload;
878 skb->tail += payload;
879
880 return skb;
881 }
882
883 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
884 struct bnxt_rx_ring_info *rxr, u16 cons,
885 void *data, u8 *data_ptr,
886 dma_addr_t dma_addr,
887 unsigned int offset_and_len)
888 {
889 u16 prod = rxr->rx_prod;
890 struct sk_buff *skb;
891 int err;
892
893 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
894 if (unlikely(err)) {
895 bnxt_reuse_rx_data(rxr, cons, data);
896 return NULL;
897 }
898
899 skb = build_skb(data, 0);
900 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
901 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
902 if (!skb) {
903 kfree(data);
904 return NULL;
905 }
906
907 skb_reserve(skb, bp->rx_offset);
908 skb_put(skb, offset_and_len & 0xffff);
909 return skb;
910 }
911
912 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
913 struct sk_buff *skb, u16 cp_cons,
914 u32 agg_bufs)
915 {
916 struct pci_dev *pdev = bp->pdev;
917 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
918 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
919 u16 prod = rxr->rx_agg_prod;
920 u32 i;
921
922 for (i = 0; i < agg_bufs; i++) {
923 u16 cons, frag_len;
924 struct rx_agg_cmp *agg;
925 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
926 struct page *page;
927 dma_addr_t mapping;
928
929 agg = (struct rx_agg_cmp *)
930 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
931 cons = agg->rx_agg_cmp_opaque;
932 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
933 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
934
935 cons_rx_buf = &rxr->rx_agg_ring[cons];
936 skb_fill_page_desc(skb, i, cons_rx_buf->page,
937 cons_rx_buf->offset, frag_len);
938 __clear_bit(cons, rxr->rx_agg_bmap);
939
940 /* It is possible for bnxt_alloc_rx_page() to allocate
941 * a sw_prod index that equals the cons index, so we
942 * need to clear the cons entry now.
943 */
944 mapping = cons_rx_buf->mapping;
945 page = cons_rx_buf->page;
946 cons_rx_buf->page = NULL;
947
948 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
949 struct skb_shared_info *shinfo;
950 unsigned int nr_frags;
951
952 shinfo = skb_shinfo(skb);
953 nr_frags = --shinfo->nr_frags;
954 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
955
956 dev_kfree_skb(skb);
957
958 cons_rx_buf->page = page;
959
960 /* Update prod since possibly some pages have been
961 * allocated already.
962 */
963 rxr->rx_agg_prod = prod;
964 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
965 return NULL;
966 }
967
968 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
969 PCI_DMA_FROMDEVICE,
970 DMA_ATTR_WEAK_ORDERING);
971
972 skb->data_len += frag_len;
973 skb->len += frag_len;
974 skb->truesize += PAGE_SIZE;
975
976 prod = NEXT_RX_AGG(prod);
977 cp_cons = NEXT_CMP(cp_cons);
978 }
979 rxr->rx_agg_prod = prod;
980 return skb;
981 }
982
983 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
984 u8 agg_bufs, u32 *raw_cons)
985 {
986 u16 last;
987 struct rx_agg_cmp *agg;
988
989 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
990 last = RING_CMP(*raw_cons);
991 agg = (struct rx_agg_cmp *)
992 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
993 return RX_AGG_CMP_VALID(agg, *raw_cons);
994 }
995
996 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
997 unsigned int len,
998 dma_addr_t mapping)
999 {
1000 struct bnxt *bp = bnapi->bp;
1001 struct pci_dev *pdev = bp->pdev;
1002 struct sk_buff *skb;
1003
1004 skb = napi_alloc_skb(&bnapi->napi, len);
1005 if (!skb)
1006 return NULL;
1007
1008 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1009 bp->rx_dir);
1010
1011 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1012 len + NET_IP_ALIGN);
1013
1014 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1015 bp->rx_dir);
1016
1017 skb_put(skb, len);
1018 return skb;
1019 }
1020
1021 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1022 u32 *raw_cons, void *cmp)
1023 {
1024 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1025 struct rx_cmp *rxcmp = cmp;
1026 u32 tmp_raw_cons = *raw_cons;
1027 u8 cmp_type, agg_bufs = 0;
1028
1029 cmp_type = RX_CMP_TYPE(rxcmp);
1030
1031 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1032 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1033 RX_CMP_AGG_BUFS) >>
1034 RX_CMP_AGG_BUFS_SHIFT;
1035 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1036 struct rx_tpa_end_cmp *tpa_end = cmp;
1037
1038 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1039 RX_TPA_END_CMP_AGG_BUFS) >>
1040 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1041 }
1042
1043 if (agg_bufs) {
1044 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1045 return -EBUSY;
1046 }
1047 *raw_cons = tmp_raw_cons;
1048 return 0;
1049 }
1050
1051 static void bnxt_queue_sp_work(struct bnxt *bp)
1052 {
1053 if (BNXT_PF(bp))
1054 queue_work(bnxt_pf_wq, &bp->sp_task);
1055 else
1056 schedule_work(&bp->sp_task);
1057 }
1058
1059 static void bnxt_cancel_sp_work(struct bnxt *bp)
1060 {
1061 if (BNXT_PF(bp))
1062 flush_workqueue(bnxt_pf_wq);
1063 else
1064 cancel_work_sync(&bp->sp_task);
1065 }
1066
1067 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1068 {
1069 if (!rxr->bnapi->in_reset) {
1070 rxr->bnapi->in_reset = true;
1071 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1072 bnxt_queue_sp_work(bp);
1073 }
1074 rxr->rx_next_cons = 0xffff;
1075 }
1076
1077 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1078 struct rx_tpa_start_cmp *tpa_start,
1079 struct rx_tpa_start_cmp_ext *tpa_start1)
1080 {
1081 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1082 u16 cons, prod;
1083 struct bnxt_tpa_info *tpa_info;
1084 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1085 struct rx_bd *prod_bd;
1086 dma_addr_t mapping;
1087
1088 cons = tpa_start->rx_tpa_start_cmp_opaque;
1089 prod = rxr->rx_prod;
1090 cons_rx_buf = &rxr->rx_buf_ring[cons];
1091 prod_rx_buf = &rxr->rx_buf_ring[prod];
1092 tpa_info = &rxr->rx_tpa[agg_id];
1093
1094 if (unlikely(cons != rxr->rx_next_cons)) {
1095 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n",
1096 cons, rxr->rx_next_cons);
1097 bnxt_sched_reset(bp, rxr);
1098 return;
1099 }
1100 /* Store cfa_code in tpa_info to use in tpa_end
1101 * completion processing.
1102 */
1103 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1104 prod_rx_buf->data = tpa_info->data;
1105 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1106
1107 mapping = tpa_info->mapping;
1108 prod_rx_buf->mapping = mapping;
1109
1110 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1111
1112 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1113
1114 tpa_info->data = cons_rx_buf->data;
1115 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1116 cons_rx_buf->data = NULL;
1117 tpa_info->mapping = cons_rx_buf->mapping;
1118
1119 tpa_info->len =
1120 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1121 RX_TPA_START_CMP_LEN_SHIFT;
1122 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1123 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1124
1125 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1126 tpa_info->gso_type = SKB_GSO_TCPV4;
1127 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1128 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1129 tpa_info->gso_type = SKB_GSO_TCPV6;
1130 tpa_info->rss_hash =
1131 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1132 } else {
1133 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1134 tpa_info->gso_type = 0;
1135 if (netif_msg_rx_err(bp))
1136 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1137 }
1138 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1139 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1140 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1141
1142 rxr->rx_prod = NEXT_RX(prod);
1143 cons = NEXT_RX(cons);
1144 rxr->rx_next_cons = NEXT_RX(cons);
1145 cons_rx_buf = &rxr->rx_buf_ring[cons];
1146
1147 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1148 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1149 cons_rx_buf->data = NULL;
1150 }
1151
1152 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1153 u16 cp_cons, u32 agg_bufs)
1154 {
1155 if (agg_bufs)
1156 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1157 }
1158
1159 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1160 int payload_off, int tcp_ts,
1161 struct sk_buff *skb)
1162 {
1163 #ifdef CONFIG_INET
1164 struct tcphdr *th;
1165 int len, nw_off;
1166 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1167 u32 hdr_info = tpa_info->hdr_info;
1168 bool loopback = false;
1169
1170 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1171 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1172 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1173
1174 /* If the packet is an internal loopback packet, the offsets will
1175 * have an extra 4 bytes.
1176 */
1177 if (inner_mac_off == 4) {
1178 loopback = true;
1179 } else if (inner_mac_off > 4) {
1180 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1181 ETH_HLEN - 2));
1182
1183 /* We only support inner iPv4/ipv6. If we don't see the
1184 * correct protocol ID, it must be a loopback packet where
1185 * the offsets are off by 4.
1186 */
1187 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1188 loopback = true;
1189 }
1190 if (loopback) {
1191 /* internal loopback packet, subtract all offsets by 4 */
1192 inner_ip_off -= 4;
1193 inner_mac_off -= 4;
1194 outer_ip_off -= 4;
1195 }
1196
1197 nw_off = inner_ip_off - ETH_HLEN;
1198 skb_set_network_header(skb, nw_off);
1199 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1200 struct ipv6hdr *iph = ipv6_hdr(skb);
1201
1202 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1203 len = skb->len - skb_transport_offset(skb);
1204 th = tcp_hdr(skb);
1205 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1206 } else {
1207 struct iphdr *iph = ip_hdr(skb);
1208
1209 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1210 len = skb->len - skb_transport_offset(skb);
1211 th = tcp_hdr(skb);
1212 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1213 }
1214
1215 if (inner_mac_off) { /* tunnel */
1216 struct udphdr *uh = NULL;
1217 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1218 ETH_HLEN - 2));
1219
1220 if (proto == htons(ETH_P_IP)) {
1221 struct iphdr *iph = (struct iphdr *)skb->data;
1222
1223 if (iph->protocol == IPPROTO_UDP)
1224 uh = (struct udphdr *)(iph + 1);
1225 } else {
1226 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1227
1228 if (iph->nexthdr == IPPROTO_UDP)
1229 uh = (struct udphdr *)(iph + 1);
1230 }
1231 if (uh) {
1232 if (uh->check)
1233 skb_shinfo(skb)->gso_type |=
1234 SKB_GSO_UDP_TUNNEL_CSUM;
1235 else
1236 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1237 }
1238 }
1239 #endif
1240 return skb;
1241 }
1242
1243 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1244 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1245
1246 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1247 int payload_off, int tcp_ts,
1248 struct sk_buff *skb)
1249 {
1250 #ifdef CONFIG_INET
1251 struct tcphdr *th;
1252 int len, nw_off, tcp_opt_len = 0;
1253
1254 if (tcp_ts)
1255 tcp_opt_len = 12;
1256
1257 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1258 struct iphdr *iph;
1259
1260 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1261 ETH_HLEN;
1262 skb_set_network_header(skb, nw_off);
1263 iph = ip_hdr(skb);
1264 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1265 len = skb->len - skb_transport_offset(skb);
1266 th = tcp_hdr(skb);
1267 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1268 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1269 struct ipv6hdr *iph;
1270
1271 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1272 ETH_HLEN;
1273 skb_set_network_header(skb, nw_off);
1274 iph = ipv6_hdr(skb);
1275 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1276 len = skb->len - skb_transport_offset(skb);
1277 th = tcp_hdr(skb);
1278 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1279 } else {
1280 dev_kfree_skb_any(skb);
1281 return NULL;
1282 }
1283
1284 if (nw_off) { /* tunnel */
1285 struct udphdr *uh = NULL;
1286
1287 if (skb->protocol == htons(ETH_P_IP)) {
1288 struct iphdr *iph = (struct iphdr *)skb->data;
1289
1290 if (iph->protocol == IPPROTO_UDP)
1291 uh = (struct udphdr *)(iph + 1);
1292 } else {
1293 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1294
1295 if (iph->nexthdr == IPPROTO_UDP)
1296 uh = (struct udphdr *)(iph + 1);
1297 }
1298 if (uh) {
1299 if (uh->check)
1300 skb_shinfo(skb)->gso_type |=
1301 SKB_GSO_UDP_TUNNEL_CSUM;
1302 else
1303 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1304 }
1305 }
1306 #endif
1307 return skb;
1308 }
1309
1310 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1311 struct bnxt_tpa_info *tpa_info,
1312 struct rx_tpa_end_cmp *tpa_end,
1313 struct rx_tpa_end_cmp_ext *tpa_end1,
1314 struct sk_buff *skb)
1315 {
1316 #ifdef CONFIG_INET
1317 int payload_off;
1318 u16 segs;
1319
1320 segs = TPA_END_TPA_SEGS(tpa_end);
1321 if (segs == 1)
1322 return skb;
1323
1324 NAPI_GRO_CB(skb)->count = segs;
1325 skb_shinfo(skb)->gso_size =
1326 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1327 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1328 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1329 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1330 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1331 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1332 if (likely(skb))
1333 tcp_gro_complete(skb);
1334 #endif
1335 return skb;
1336 }
1337
1338 /* Given the cfa_code of a received packet determine which
1339 * netdev (vf-rep or PF) the packet is destined to.
1340 */
1341 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1342 {
1343 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1344
1345 /* if vf-rep dev is NULL, the must belongs to the PF */
1346 return dev ? dev : bp->dev;
1347 }
1348
1349 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1350 struct bnxt_napi *bnapi,
1351 u32 *raw_cons,
1352 struct rx_tpa_end_cmp *tpa_end,
1353 struct rx_tpa_end_cmp_ext *tpa_end1,
1354 u8 *event)
1355 {
1356 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1357 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1358 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1359 u8 *data_ptr, agg_bufs;
1360 u16 cp_cons = RING_CMP(*raw_cons);
1361 unsigned int len;
1362 struct bnxt_tpa_info *tpa_info;
1363 dma_addr_t mapping;
1364 struct sk_buff *skb;
1365 void *data;
1366
1367 if (unlikely(bnapi->in_reset)) {
1368 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1369
1370 if (rc < 0)
1371 return ERR_PTR(-EBUSY);
1372 return NULL;
1373 }
1374
1375 tpa_info = &rxr->rx_tpa[agg_id];
1376 data = tpa_info->data;
1377 data_ptr = tpa_info->data_ptr;
1378 prefetch(data_ptr);
1379 len = tpa_info->len;
1380 mapping = tpa_info->mapping;
1381
1382 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1383 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1384
1385 if (agg_bufs) {
1386 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1387 return ERR_PTR(-EBUSY);
1388
1389 *event |= BNXT_AGG_EVENT;
1390 cp_cons = NEXT_CMP(cp_cons);
1391 }
1392
1393 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1394 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1395 if (agg_bufs > MAX_SKB_FRAGS)
1396 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1397 agg_bufs, (int)MAX_SKB_FRAGS);
1398 return NULL;
1399 }
1400
1401 if (len <= bp->rx_copy_thresh) {
1402 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1403 if (!skb) {
1404 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1405 return NULL;
1406 }
1407 } else {
1408 u8 *new_data;
1409 dma_addr_t new_mapping;
1410
1411 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1412 if (!new_data) {
1413 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1414 return NULL;
1415 }
1416
1417 tpa_info->data = new_data;
1418 tpa_info->data_ptr = new_data + bp->rx_offset;
1419 tpa_info->mapping = new_mapping;
1420
1421 skb = build_skb(data, 0);
1422 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1423 bp->rx_buf_use_size, bp->rx_dir,
1424 DMA_ATTR_WEAK_ORDERING);
1425
1426 if (!skb) {
1427 kfree(data);
1428 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1429 return NULL;
1430 }
1431 skb_reserve(skb, bp->rx_offset);
1432 skb_put(skb, len);
1433 }
1434
1435 if (agg_bufs) {
1436 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1437 if (!skb) {
1438 /* Page reuse already handled by bnxt_rx_pages(). */
1439 return NULL;
1440 }
1441 }
1442
1443 skb->protocol =
1444 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1445
1446 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1447 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1448
1449 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1450 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1451 u16 vlan_proto = tpa_info->metadata >>
1452 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1453 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1454
1455 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1456 }
1457
1458 skb_checksum_none_assert(skb);
1459 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1460 skb->ip_summed = CHECKSUM_UNNECESSARY;
1461 skb->csum_level =
1462 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1463 }
1464
1465 if (TPA_END_GRO(tpa_end))
1466 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1467
1468 return skb;
1469 }
1470
1471 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1472 struct sk_buff *skb)
1473 {
1474 if (skb->dev != bp->dev) {
1475 /* this packet belongs to a vf-rep */
1476 bnxt_vf_rep_rx(bp, skb);
1477 return;
1478 }
1479 skb_record_rx_queue(skb, bnapi->index);
1480 napi_gro_receive(&bnapi->napi, skb);
1481 }
1482
1483 /* returns the following:
1484 * 1 - 1 packet successfully received
1485 * 0 - successful TPA_START, packet not completed yet
1486 * -EBUSY - completion ring does not have all the agg buffers yet
1487 * -ENOMEM - packet aborted due to out of memory
1488 * -EIO - packet aborted due to hw error indicated in BD
1489 */
1490 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1491 u8 *event)
1492 {
1493 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1494 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1495 struct net_device *dev = bp->dev;
1496 struct rx_cmp *rxcmp;
1497 struct rx_cmp_ext *rxcmp1;
1498 u32 tmp_raw_cons = *raw_cons;
1499 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1500 struct bnxt_sw_rx_bd *rx_buf;
1501 unsigned int len;
1502 u8 *data_ptr, agg_bufs, cmp_type;
1503 dma_addr_t dma_addr;
1504 struct sk_buff *skb;
1505 void *data;
1506 int rc = 0;
1507 u32 misc;
1508
1509 rxcmp = (struct rx_cmp *)
1510 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1511
1512 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1513 cp_cons = RING_CMP(tmp_raw_cons);
1514 rxcmp1 = (struct rx_cmp_ext *)
1515 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1516
1517 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1518 return -EBUSY;
1519
1520 cmp_type = RX_CMP_TYPE(rxcmp);
1521
1522 prod = rxr->rx_prod;
1523
1524 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1525 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1526 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1527
1528 *event |= BNXT_RX_EVENT;
1529 goto next_rx_no_prod_no_len;
1530
1531 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1532 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1533 (struct rx_tpa_end_cmp *)rxcmp,
1534 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1535
1536 if (IS_ERR(skb))
1537 return -EBUSY;
1538
1539 rc = -ENOMEM;
1540 if (likely(skb)) {
1541 bnxt_deliver_skb(bp, bnapi, skb);
1542 rc = 1;
1543 }
1544 *event |= BNXT_RX_EVENT;
1545 goto next_rx_no_prod_no_len;
1546 }
1547
1548 cons = rxcmp->rx_cmp_opaque;
1549 if (unlikely(cons != rxr->rx_next_cons)) {
1550 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1551
1552 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1553 cons, rxr->rx_next_cons);
1554 bnxt_sched_reset(bp, rxr);
1555 return rc1;
1556 }
1557 rx_buf = &rxr->rx_buf_ring[cons];
1558 data = rx_buf->data;
1559 data_ptr = rx_buf->data_ptr;
1560 prefetch(data_ptr);
1561
1562 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1563 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1564
1565 if (agg_bufs) {
1566 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1567 return -EBUSY;
1568
1569 cp_cons = NEXT_CMP(cp_cons);
1570 *event |= BNXT_AGG_EVENT;
1571 }
1572 *event |= BNXT_RX_EVENT;
1573
1574 rx_buf->data = NULL;
1575 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1576 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1577
1578 bnxt_reuse_rx_data(rxr, cons, data);
1579 if (agg_bufs)
1580 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1581
1582 rc = -EIO;
1583 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1584 netdev_warn(bp->dev, "RX buffer error %x\n", rx_err);
1585 bnxt_sched_reset(bp, rxr);
1586 }
1587 goto next_rx_no_len;
1588 }
1589
1590 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1591 dma_addr = rx_buf->mapping;
1592
1593 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1594 rc = 1;
1595 goto next_rx;
1596 }
1597
1598 if (len <= bp->rx_copy_thresh) {
1599 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1600 bnxt_reuse_rx_data(rxr, cons, data);
1601 if (!skb) {
1602 if (agg_bufs)
1603 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1604 rc = -ENOMEM;
1605 goto next_rx;
1606 }
1607 } else {
1608 u32 payload;
1609
1610 if (rx_buf->data_ptr == data_ptr)
1611 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1612 else
1613 payload = 0;
1614 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1615 payload | len);
1616 if (!skb) {
1617 rc = -ENOMEM;
1618 goto next_rx;
1619 }
1620 }
1621
1622 if (agg_bufs) {
1623 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1624 if (!skb) {
1625 rc = -ENOMEM;
1626 goto next_rx;
1627 }
1628 }
1629
1630 if (RX_CMP_HASH_VALID(rxcmp)) {
1631 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1632 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1633
1634 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1635 if (hash_type != 1 && hash_type != 3)
1636 type = PKT_HASH_TYPE_L3;
1637 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1638 }
1639
1640 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1641 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1642
1643 if ((rxcmp1->rx_cmp_flags2 &
1644 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1645 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1646 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1647 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1648 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1649
1650 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1651 }
1652
1653 skb_checksum_none_assert(skb);
1654 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1655 if (dev->features & NETIF_F_RXCSUM) {
1656 skb->ip_summed = CHECKSUM_UNNECESSARY;
1657 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1658 }
1659 } else {
1660 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1661 if (dev->features & NETIF_F_RXCSUM)
1662 cpr->rx_l4_csum_errors++;
1663 }
1664 }
1665
1666 bnxt_deliver_skb(bp, bnapi, skb);
1667 rc = 1;
1668
1669 next_rx:
1670 cpr->rx_packets += 1;
1671 cpr->rx_bytes += len;
1672
1673 next_rx_no_len:
1674 rxr->rx_prod = NEXT_RX(prod);
1675 rxr->rx_next_cons = NEXT_RX(cons);
1676
1677 next_rx_no_prod_no_len:
1678 *raw_cons = tmp_raw_cons;
1679
1680 return rc;
1681 }
1682
1683 /* In netpoll mode, if we are using a combined completion ring, we need to
1684 * discard the rx packets and recycle the buffers.
1685 */
1686 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1687 u32 *raw_cons, u8 *event)
1688 {
1689 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1690 u32 tmp_raw_cons = *raw_cons;
1691 struct rx_cmp_ext *rxcmp1;
1692 struct rx_cmp *rxcmp;
1693 u16 cp_cons;
1694 u8 cmp_type;
1695
1696 cp_cons = RING_CMP(tmp_raw_cons);
1697 rxcmp = (struct rx_cmp *)
1698 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1699
1700 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1701 cp_cons = RING_CMP(tmp_raw_cons);
1702 rxcmp1 = (struct rx_cmp_ext *)
1703 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1704
1705 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1706 return -EBUSY;
1707
1708 cmp_type = RX_CMP_TYPE(rxcmp);
1709 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1710 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1711 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1712 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1713 struct rx_tpa_end_cmp_ext *tpa_end1;
1714
1715 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1716 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1717 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1718 }
1719 return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1720 }
1721
1722 #define BNXT_GET_EVENT_PORT(data) \
1723 ((data) & \
1724 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1725
1726 static int bnxt_async_event_process(struct bnxt *bp,
1727 struct hwrm_async_event_cmpl *cmpl)
1728 {
1729 u16 event_id = le16_to_cpu(cmpl->event_id);
1730
1731 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1732 switch (event_id) {
1733 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1734 u32 data1 = le32_to_cpu(cmpl->event_data1);
1735 struct bnxt_link_info *link_info = &bp->link_info;
1736
1737 if (BNXT_VF(bp))
1738 goto async_event_process_exit;
1739
1740 /* print unsupported speed warning in forced speed mode only */
1741 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1742 (data1 & 0x20000)) {
1743 u16 fw_speed = link_info->force_link_speed;
1744 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1745
1746 if (speed != SPEED_UNKNOWN)
1747 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1748 speed);
1749 }
1750 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1751 }
1752 /* fall through */
1753 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1754 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1755 break;
1756 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1757 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1758 break;
1759 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1760 u32 data1 = le32_to_cpu(cmpl->event_data1);
1761 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1762
1763 if (BNXT_VF(bp))
1764 break;
1765
1766 if (bp->pf.port_id != port_id)
1767 break;
1768
1769 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1770 break;
1771 }
1772 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1773 if (BNXT_PF(bp))
1774 goto async_event_process_exit;
1775 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1776 break;
1777 default:
1778 goto async_event_process_exit;
1779 }
1780 bnxt_queue_sp_work(bp);
1781 async_event_process_exit:
1782 bnxt_ulp_async_events(bp, cmpl);
1783 return 0;
1784 }
1785
1786 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1787 {
1788 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1789 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1790 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1791 (struct hwrm_fwd_req_cmpl *)txcmp;
1792
1793 switch (cmpl_type) {
1794 case CMPL_BASE_TYPE_HWRM_DONE:
1795 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1796 if (seq_id == bp->hwrm_intr_seq_id)
1797 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1798 else
1799 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1800 break;
1801
1802 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1803 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1804
1805 if ((vf_id < bp->pf.first_vf_id) ||
1806 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1807 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1808 vf_id);
1809 return -EINVAL;
1810 }
1811
1812 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1813 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1814 bnxt_queue_sp_work(bp);
1815 break;
1816
1817 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1818 bnxt_async_event_process(bp,
1819 (struct hwrm_async_event_cmpl *)txcmp);
1820
1821 default:
1822 break;
1823 }
1824
1825 return 0;
1826 }
1827
1828 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1829 {
1830 struct bnxt_napi *bnapi = dev_instance;
1831 struct bnxt *bp = bnapi->bp;
1832 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1833 u32 cons = RING_CMP(cpr->cp_raw_cons);
1834
1835 cpr->event_ctr++;
1836 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1837 napi_schedule(&bnapi->napi);
1838 return IRQ_HANDLED;
1839 }
1840
1841 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1842 {
1843 u32 raw_cons = cpr->cp_raw_cons;
1844 u16 cons = RING_CMP(raw_cons);
1845 struct tx_cmp *txcmp;
1846
1847 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1848
1849 return TX_CMP_VALID(txcmp, raw_cons);
1850 }
1851
1852 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1853 {
1854 struct bnxt_napi *bnapi = dev_instance;
1855 struct bnxt *bp = bnapi->bp;
1856 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1857 u32 cons = RING_CMP(cpr->cp_raw_cons);
1858 u32 int_status;
1859
1860 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1861
1862 if (!bnxt_has_work(bp, cpr)) {
1863 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1864 /* return if erroneous interrupt */
1865 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1866 return IRQ_NONE;
1867 }
1868
1869 /* disable ring IRQ */
1870 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1871
1872 /* Return here if interrupt is shared and is disabled. */
1873 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1874 return IRQ_HANDLED;
1875
1876 napi_schedule(&bnapi->napi);
1877 return IRQ_HANDLED;
1878 }
1879
1880 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1881 {
1882 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1883 u32 raw_cons = cpr->cp_raw_cons;
1884 u32 cons;
1885 int tx_pkts = 0;
1886 int rx_pkts = 0;
1887 u8 event = 0;
1888 struct tx_cmp *txcmp;
1889
1890 while (1) {
1891 int rc;
1892
1893 cons = RING_CMP(raw_cons);
1894 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1895
1896 if (!TX_CMP_VALID(txcmp, raw_cons))
1897 break;
1898
1899 /* The valid test of the entry must be done first before
1900 * reading any further.
1901 */
1902 dma_rmb();
1903 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1904 tx_pkts++;
1905 /* return full budget so NAPI will complete. */
1906 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1907 rx_pkts = budget;
1908 raw_cons = NEXT_RAW_CMP(raw_cons);
1909 break;
1910 }
1911 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1912 if (likely(budget))
1913 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1914 else
1915 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1916 &event);
1917 if (likely(rc >= 0))
1918 rx_pkts += rc;
1919 /* Increment rx_pkts when rc is -ENOMEM to count towards
1920 * the NAPI budget. Otherwise, we may potentially loop
1921 * here forever if we consistently cannot allocate
1922 * buffers.
1923 */
1924 else if (rc == -ENOMEM && budget)
1925 rx_pkts++;
1926 else if (rc == -EBUSY) /* partial completion */
1927 break;
1928 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1929 CMPL_BASE_TYPE_HWRM_DONE) ||
1930 (TX_CMP_TYPE(txcmp) ==
1931 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1932 (TX_CMP_TYPE(txcmp) ==
1933 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1934 bnxt_hwrm_handler(bp, txcmp);
1935 }
1936 raw_cons = NEXT_RAW_CMP(raw_cons);
1937
1938 if (rx_pkts && rx_pkts == budget)
1939 break;
1940 }
1941
1942 if (event & BNXT_TX_EVENT) {
1943 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1944 void __iomem *db = txr->tx_doorbell;
1945 u16 prod = txr->tx_prod;
1946
1947 /* Sync BD data before updating doorbell */
1948 wmb();
1949
1950 bnxt_db_write_relaxed(bp, db, DB_KEY_TX | prod);
1951 }
1952
1953 cpr->cp_raw_cons = raw_cons;
1954 /* ACK completion ring before freeing tx ring and producing new
1955 * buffers in rx/agg rings to prevent overflowing the completion
1956 * ring.
1957 */
1958 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1959
1960 if (tx_pkts)
1961 bnapi->tx_int(bp, bnapi, tx_pkts);
1962
1963 if (event & BNXT_RX_EVENT) {
1964 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1965
1966 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1967 if (event & BNXT_AGG_EVENT)
1968 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1969 DB_KEY_RX | rxr->rx_agg_prod);
1970 }
1971 return rx_pkts;
1972 }
1973
1974 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1975 {
1976 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1977 struct bnxt *bp = bnapi->bp;
1978 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1979 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1980 struct tx_cmp *txcmp;
1981 struct rx_cmp_ext *rxcmp1;
1982 u32 cp_cons, tmp_raw_cons;
1983 u32 raw_cons = cpr->cp_raw_cons;
1984 u32 rx_pkts = 0;
1985 u8 event = 0;
1986
1987 while (1) {
1988 int rc;
1989
1990 cp_cons = RING_CMP(raw_cons);
1991 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1992
1993 if (!TX_CMP_VALID(txcmp, raw_cons))
1994 break;
1995
1996 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1997 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1998 cp_cons = RING_CMP(tmp_raw_cons);
1999 rxcmp1 = (struct rx_cmp_ext *)
2000 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2001
2002 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2003 break;
2004
2005 /* force an error to recycle the buffer */
2006 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2007 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2008
2009 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
2010 if (likely(rc == -EIO) && budget)
2011 rx_pkts++;
2012 else if (rc == -EBUSY) /* partial completion */
2013 break;
2014 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2015 CMPL_BASE_TYPE_HWRM_DONE)) {
2016 bnxt_hwrm_handler(bp, txcmp);
2017 } else {
2018 netdev_err(bp->dev,
2019 "Invalid completion received on special ring\n");
2020 }
2021 raw_cons = NEXT_RAW_CMP(raw_cons);
2022
2023 if (rx_pkts == budget)
2024 break;
2025 }
2026
2027 cpr->cp_raw_cons = raw_cons;
2028 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
2029 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
2030
2031 if (event & BNXT_AGG_EVENT)
2032 bnxt_db_write(bp, rxr->rx_agg_doorbell,
2033 DB_KEY_RX | rxr->rx_agg_prod);
2034
2035 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2036 napi_complete_done(napi, rx_pkts);
2037 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2038 }
2039 return rx_pkts;
2040 }
2041
2042 static int bnxt_poll(struct napi_struct *napi, int budget)
2043 {
2044 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2045 struct bnxt *bp = bnapi->bp;
2046 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2047 int work_done = 0;
2048
2049 while (1) {
2050 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2051
2052 if (work_done >= budget) {
2053 if (!budget)
2054 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2055 cpr->cp_raw_cons);
2056 break;
2057 }
2058
2059 if (!bnxt_has_work(bp, cpr)) {
2060 if (napi_complete_done(napi, work_done))
2061 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2062 cpr->cp_raw_cons);
2063 break;
2064 }
2065 }
2066 if (bp->flags & BNXT_FLAG_DIM) {
2067 struct net_dim_sample dim_sample;
2068
2069 net_dim_sample(cpr->event_ctr,
2070 cpr->rx_packets,
2071 cpr->rx_bytes,
2072 &dim_sample);
2073 net_dim(&cpr->dim, dim_sample);
2074 }
2075 mmiowb();
2076 return work_done;
2077 }
2078
2079 static void bnxt_free_tx_skbs(struct bnxt *bp)
2080 {
2081 int i, max_idx;
2082 struct pci_dev *pdev = bp->pdev;
2083
2084 if (!bp->tx_ring)
2085 return;
2086
2087 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2088 for (i = 0; i < bp->tx_nr_rings; i++) {
2089 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2090 int j;
2091
2092 for (j = 0; j < max_idx;) {
2093 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2094 struct sk_buff *skb = tx_buf->skb;
2095 int k, last;
2096
2097 if (!skb) {
2098 j++;
2099 continue;
2100 }
2101
2102 tx_buf->skb = NULL;
2103
2104 if (tx_buf->is_push) {
2105 dev_kfree_skb(skb);
2106 j += 2;
2107 continue;
2108 }
2109
2110 dma_unmap_single(&pdev->dev,
2111 dma_unmap_addr(tx_buf, mapping),
2112 skb_headlen(skb),
2113 PCI_DMA_TODEVICE);
2114
2115 last = tx_buf->nr_frags;
2116 j += 2;
2117 for (k = 0; k < last; k++, j++) {
2118 int ring_idx = j & bp->tx_ring_mask;
2119 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2120
2121 tx_buf = &txr->tx_buf_ring[ring_idx];
2122 dma_unmap_page(
2123 &pdev->dev,
2124 dma_unmap_addr(tx_buf, mapping),
2125 skb_frag_size(frag), PCI_DMA_TODEVICE);
2126 }
2127 dev_kfree_skb(skb);
2128 }
2129 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2130 }
2131 }
2132
2133 static void bnxt_free_rx_skbs(struct bnxt *bp)
2134 {
2135 int i, max_idx, max_agg_idx;
2136 struct pci_dev *pdev = bp->pdev;
2137
2138 if (!bp->rx_ring)
2139 return;
2140
2141 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2142 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2143 for (i = 0; i < bp->rx_nr_rings; i++) {
2144 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2145 int j;
2146
2147 if (rxr->rx_tpa) {
2148 for (j = 0; j < MAX_TPA; j++) {
2149 struct bnxt_tpa_info *tpa_info =
2150 &rxr->rx_tpa[j];
2151 u8 *data = tpa_info->data;
2152
2153 if (!data)
2154 continue;
2155
2156 dma_unmap_single_attrs(&pdev->dev,
2157 tpa_info->mapping,
2158 bp->rx_buf_use_size,
2159 bp->rx_dir,
2160 DMA_ATTR_WEAK_ORDERING);
2161
2162 tpa_info->data = NULL;
2163
2164 kfree(data);
2165 }
2166 }
2167
2168 for (j = 0; j < max_idx; j++) {
2169 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2170 dma_addr_t mapping = rx_buf->mapping;
2171 void *data = rx_buf->data;
2172
2173 if (!data)
2174 continue;
2175
2176 rx_buf->data = NULL;
2177
2178 if (BNXT_RX_PAGE_MODE(bp)) {
2179 mapping -= bp->rx_dma_offset;
2180 dma_unmap_page_attrs(&pdev->dev, mapping,
2181 PAGE_SIZE, bp->rx_dir,
2182 DMA_ATTR_WEAK_ORDERING);
2183 __free_page(data);
2184 } else {
2185 dma_unmap_single_attrs(&pdev->dev, mapping,
2186 bp->rx_buf_use_size,
2187 bp->rx_dir,
2188 DMA_ATTR_WEAK_ORDERING);
2189 kfree(data);
2190 }
2191 }
2192
2193 for (j = 0; j < max_agg_idx; j++) {
2194 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2195 &rxr->rx_agg_ring[j];
2196 struct page *page = rx_agg_buf->page;
2197
2198 if (!page)
2199 continue;
2200
2201 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2202 BNXT_RX_PAGE_SIZE,
2203 PCI_DMA_FROMDEVICE,
2204 DMA_ATTR_WEAK_ORDERING);
2205
2206 rx_agg_buf->page = NULL;
2207 __clear_bit(j, rxr->rx_agg_bmap);
2208
2209 __free_page(page);
2210 }
2211 if (rxr->rx_page) {
2212 __free_page(rxr->rx_page);
2213 rxr->rx_page = NULL;
2214 }
2215 }
2216 }
2217
2218 static void bnxt_free_skbs(struct bnxt *bp)
2219 {
2220 bnxt_free_tx_skbs(bp);
2221 bnxt_free_rx_skbs(bp);
2222 }
2223
2224 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2225 {
2226 struct pci_dev *pdev = bp->pdev;
2227 int i;
2228
2229 for (i = 0; i < ring->nr_pages; i++) {
2230 if (!ring->pg_arr[i])
2231 continue;
2232
2233 dma_free_coherent(&pdev->dev, ring->page_size,
2234 ring->pg_arr[i], ring->dma_arr[i]);
2235
2236 ring->pg_arr[i] = NULL;
2237 }
2238 if (ring->pg_tbl) {
2239 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2240 ring->pg_tbl, ring->pg_tbl_map);
2241 ring->pg_tbl = NULL;
2242 }
2243 if (ring->vmem_size && *ring->vmem) {
2244 vfree(*ring->vmem);
2245 *ring->vmem = NULL;
2246 }
2247 }
2248
2249 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2250 {
2251 int i;
2252 struct pci_dev *pdev = bp->pdev;
2253
2254 if (ring->nr_pages > 1) {
2255 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2256 ring->nr_pages * 8,
2257 &ring->pg_tbl_map,
2258 GFP_KERNEL);
2259 if (!ring->pg_tbl)
2260 return -ENOMEM;
2261 }
2262
2263 for (i = 0; i < ring->nr_pages; i++) {
2264 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2265 ring->page_size,
2266 &ring->dma_arr[i],
2267 GFP_KERNEL);
2268 if (!ring->pg_arr[i])
2269 return -ENOMEM;
2270
2271 if (ring->nr_pages > 1)
2272 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2273 }
2274
2275 if (ring->vmem_size) {
2276 *ring->vmem = vzalloc(ring->vmem_size);
2277 if (!(*ring->vmem))
2278 return -ENOMEM;
2279 }
2280 return 0;
2281 }
2282
2283 static void bnxt_free_rx_rings(struct bnxt *bp)
2284 {
2285 int i;
2286
2287 if (!bp->rx_ring)
2288 return;
2289
2290 for (i = 0; i < bp->rx_nr_rings; i++) {
2291 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2292 struct bnxt_ring_struct *ring;
2293
2294 if (rxr->xdp_prog)
2295 bpf_prog_put(rxr->xdp_prog);
2296
2297 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2298 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2299
2300 kfree(rxr->rx_tpa);
2301 rxr->rx_tpa = NULL;
2302
2303 kfree(rxr->rx_agg_bmap);
2304 rxr->rx_agg_bmap = NULL;
2305
2306 ring = &rxr->rx_ring_struct;
2307 bnxt_free_ring(bp, ring);
2308
2309 ring = &rxr->rx_agg_ring_struct;
2310 bnxt_free_ring(bp, ring);
2311 }
2312 }
2313
2314 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2315 {
2316 int i, rc, agg_rings = 0, tpa_rings = 0;
2317
2318 if (!bp->rx_ring)
2319 return -ENOMEM;
2320
2321 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2322 agg_rings = 1;
2323
2324 if (bp->flags & BNXT_FLAG_TPA)
2325 tpa_rings = 1;
2326
2327 for (i = 0; i < bp->rx_nr_rings; i++) {
2328 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2329 struct bnxt_ring_struct *ring;
2330
2331 ring = &rxr->rx_ring_struct;
2332
2333 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2334 if (rc < 0)
2335 return rc;
2336
2337 rc = bnxt_alloc_ring(bp, ring);
2338 if (rc)
2339 return rc;
2340
2341 if (agg_rings) {
2342 u16 mem_size;
2343
2344 ring = &rxr->rx_agg_ring_struct;
2345 rc = bnxt_alloc_ring(bp, ring);
2346 if (rc)
2347 return rc;
2348
2349 ring->grp_idx = i;
2350 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2351 mem_size = rxr->rx_agg_bmap_size / 8;
2352 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2353 if (!rxr->rx_agg_bmap)
2354 return -ENOMEM;
2355
2356 if (tpa_rings) {
2357 rxr->rx_tpa = kcalloc(MAX_TPA,
2358 sizeof(struct bnxt_tpa_info),
2359 GFP_KERNEL);
2360 if (!rxr->rx_tpa)
2361 return -ENOMEM;
2362 }
2363 }
2364 }
2365 return 0;
2366 }
2367
2368 static void bnxt_free_tx_rings(struct bnxt *bp)
2369 {
2370 int i;
2371 struct pci_dev *pdev = bp->pdev;
2372
2373 if (!bp->tx_ring)
2374 return;
2375
2376 for (i = 0; i < bp->tx_nr_rings; i++) {
2377 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2378 struct bnxt_ring_struct *ring;
2379
2380 if (txr->tx_push) {
2381 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2382 txr->tx_push, txr->tx_push_mapping);
2383 txr->tx_push = NULL;
2384 }
2385
2386 ring = &txr->tx_ring_struct;
2387
2388 bnxt_free_ring(bp, ring);
2389 }
2390 }
2391
2392 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2393 {
2394 int i, j, rc;
2395 struct pci_dev *pdev = bp->pdev;
2396
2397 bp->tx_push_size = 0;
2398 if (bp->tx_push_thresh) {
2399 int push_size;
2400
2401 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2402 bp->tx_push_thresh);
2403
2404 if (push_size > 256) {
2405 push_size = 0;
2406 bp->tx_push_thresh = 0;
2407 }
2408
2409 bp->tx_push_size = push_size;
2410 }
2411
2412 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2413 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2414 struct bnxt_ring_struct *ring;
2415 u8 qidx;
2416
2417 ring = &txr->tx_ring_struct;
2418
2419 rc = bnxt_alloc_ring(bp, ring);
2420 if (rc)
2421 return rc;
2422
2423 ring->grp_idx = txr->bnapi->index;
2424 if (bp->tx_push_size) {
2425 dma_addr_t mapping;
2426
2427 /* One pre-allocated DMA buffer to backup
2428 * TX push operation
2429 */
2430 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2431 bp->tx_push_size,
2432 &txr->tx_push_mapping,
2433 GFP_KERNEL);
2434
2435 if (!txr->tx_push)
2436 return -ENOMEM;
2437
2438 mapping = txr->tx_push_mapping +
2439 sizeof(struct tx_push_bd);
2440 txr->data_mapping = cpu_to_le64(mapping);
2441
2442 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2443 }
2444 qidx = bp->tc_to_qidx[j];
2445 ring->queue_id = bp->q_info[qidx].queue_id;
2446 if (i < bp->tx_nr_rings_xdp)
2447 continue;
2448 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2449 j++;
2450 }
2451 return 0;
2452 }
2453
2454 static void bnxt_free_cp_rings(struct bnxt *bp)
2455 {
2456 int i;
2457
2458 if (!bp->bnapi)
2459 return;
2460
2461 for (i = 0; i < bp->cp_nr_rings; i++) {
2462 struct bnxt_napi *bnapi = bp->bnapi[i];
2463 struct bnxt_cp_ring_info *cpr;
2464 struct bnxt_ring_struct *ring;
2465
2466 if (!bnapi)
2467 continue;
2468
2469 cpr = &bnapi->cp_ring;
2470 ring = &cpr->cp_ring_struct;
2471
2472 bnxt_free_ring(bp, ring);
2473 }
2474 }
2475
2476 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2477 {
2478 int i, rc, ulp_base_vec, ulp_msix;
2479
2480 ulp_msix = bnxt_get_ulp_msix_num(bp);
2481 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2482 for (i = 0; i < bp->cp_nr_rings; i++) {
2483 struct bnxt_napi *bnapi = bp->bnapi[i];
2484 struct bnxt_cp_ring_info *cpr;
2485 struct bnxt_ring_struct *ring;
2486
2487 if (!bnapi)
2488 continue;
2489
2490 cpr = &bnapi->cp_ring;
2491 ring = &cpr->cp_ring_struct;
2492
2493 rc = bnxt_alloc_ring(bp, ring);
2494 if (rc)
2495 return rc;
2496
2497 if (ulp_msix && i >= ulp_base_vec)
2498 ring->map_idx = i + ulp_msix;
2499 else
2500 ring->map_idx = i;
2501 }
2502 return 0;
2503 }
2504
2505 static void bnxt_init_ring_struct(struct bnxt *bp)
2506 {
2507 int i;
2508
2509 for (i = 0; i < bp->cp_nr_rings; i++) {
2510 struct bnxt_napi *bnapi = bp->bnapi[i];
2511 struct bnxt_cp_ring_info *cpr;
2512 struct bnxt_rx_ring_info *rxr;
2513 struct bnxt_tx_ring_info *txr;
2514 struct bnxt_ring_struct *ring;
2515
2516 if (!bnapi)
2517 continue;
2518
2519 cpr = &bnapi->cp_ring;
2520 ring = &cpr->cp_ring_struct;
2521 ring->nr_pages = bp->cp_nr_pages;
2522 ring->page_size = HW_CMPD_RING_SIZE;
2523 ring->pg_arr = (void **)cpr->cp_desc_ring;
2524 ring->dma_arr = cpr->cp_desc_mapping;
2525 ring->vmem_size = 0;
2526
2527 rxr = bnapi->rx_ring;
2528 if (!rxr)
2529 goto skip_rx;
2530
2531 ring = &rxr->rx_ring_struct;
2532 ring->nr_pages = bp->rx_nr_pages;
2533 ring->page_size = HW_RXBD_RING_SIZE;
2534 ring->pg_arr = (void **)rxr->rx_desc_ring;
2535 ring->dma_arr = rxr->rx_desc_mapping;
2536 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2537 ring->vmem = (void **)&rxr->rx_buf_ring;
2538
2539 ring = &rxr->rx_agg_ring_struct;
2540 ring->nr_pages = bp->rx_agg_nr_pages;
2541 ring->page_size = HW_RXBD_RING_SIZE;
2542 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2543 ring->dma_arr = rxr->rx_agg_desc_mapping;
2544 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2545 ring->vmem = (void **)&rxr->rx_agg_ring;
2546
2547 skip_rx:
2548 txr = bnapi->tx_ring;
2549 if (!txr)
2550 continue;
2551
2552 ring = &txr->tx_ring_struct;
2553 ring->nr_pages = bp->tx_nr_pages;
2554 ring->page_size = HW_RXBD_RING_SIZE;
2555 ring->pg_arr = (void **)txr->tx_desc_ring;
2556 ring->dma_arr = txr->tx_desc_mapping;
2557 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2558 ring->vmem = (void **)&txr->tx_buf_ring;
2559 }
2560 }
2561
2562 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2563 {
2564 int i;
2565 u32 prod;
2566 struct rx_bd **rx_buf_ring;
2567
2568 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2569 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2570 int j;
2571 struct rx_bd *rxbd;
2572
2573 rxbd = rx_buf_ring[i];
2574 if (!rxbd)
2575 continue;
2576
2577 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2578 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2579 rxbd->rx_bd_opaque = prod;
2580 }
2581 }
2582 }
2583
2584 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2585 {
2586 struct net_device *dev = bp->dev;
2587 struct bnxt_rx_ring_info *rxr;
2588 struct bnxt_ring_struct *ring;
2589 u32 prod, type;
2590 int i;
2591
2592 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2593 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2594
2595 if (NET_IP_ALIGN == 2)
2596 type |= RX_BD_FLAGS_SOP;
2597
2598 rxr = &bp->rx_ring[ring_nr];
2599 ring = &rxr->rx_ring_struct;
2600 bnxt_init_rxbd_pages(ring, type);
2601
2602 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2603 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2604 if (IS_ERR(rxr->xdp_prog)) {
2605 int rc = PTR_ERR(rxr->xdp_prog);
2606
2607 rxr->xdp_prog = NULL;
2608 return rc;
2609 }
2610 }
2611 prod = rxr->rx_prod;
2612 for (i = 0; i < bp->rx_ring_size; i++) {
2613 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2614 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2615 ring_nr, i, bp->rx_ring_size);
2616 break;
2617 }
2618 prod = NEXT_RX(prod);
2619 }
2620 rxr->rx_prod = prod;
2621 ring->fw_ring_id = INVALID_HW_RING_ID;
2622
2623 ring = &rxr->rx_agg_ring_struct;
2624 ring->fw_ring_id = INVALID_HW_RING_ID;
2625
2626 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2627 return 0;
2628
2629 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2630 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2631
2632 bnxt_init_rxbd_pages(ring, type);
2633
2634 prod = rxr->rx_agg_prod;
2635 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2636 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2637 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2638 ring_nr, i, bp->rx_ring_size);
2639 break;
2640 }
2641 prod = NEXT_RX_AGG(prod);
2642 }
2643 rxr->rx_agg_prod = prod;
2644
2645 if (bp->flags & BNXT_FLAG_TPA) {
2646 if (rxr->rx_tpa) {
2647 u8 *data;
2648 dma_addr_t mapping;
2649
2650 for (i = 0; i < MAX_TPA; i++) {
2651 data = __bnxt_alloc_rx_data(bp, &mapping,
2652 GFP_KERNEL);
2653 if (!data)
2654 return -ENOMEM;
2655
2656 rxr->rx_tpa[i].data = data;
2657 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2658 rxr->rx_tpa[i].mapping = mapping;
2659 }
2660 } else {
2661 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2662 return -ENOMEM;
2663 }
2664 }
2665
2666 return 0;
2667 }
2668
2669 static void bnxt_init_cp_rings(struct bnxt *bp)
2670 {
2671 int i;
2672
2673 for (i = 0; i < bp->cp_nr_rings; i++) {
2674 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2675 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2676
2677 ring->fw_ring_id = INVALID_HW_RING_ID;
2678 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2679 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2680 }
2681 }
2682
2683 static int bnxt_init_rx_rings(struct bnxt *bp)
2684 {
2685 int i, rc = 0;
2686
2687 if (BNXT_RX_PAGE_MODE(bp)) {
2688 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2689 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2690 } else {
2691 bp->rx_offset = BNXT_RX_OFFSET;
2692 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2693 }
2694
2695 for (i = 0; i < bp->rx_nr_rings; i++) {
2696 rc = bnxt_init_one_rx_ring(bp, i);
2697 if (rc)
2698 break;
2699 }
2700
2701 return rc;
2702 }
2703
2704 static int bnxt_init_tx_rings(struct bnxt *bp)
2705 {
2706 u16 i;
2707
2708 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2709 MAX_SKB_FRAGS + 1);
2710
2711 for (i = 0; i < bp->tx_nr_rings; i++) {
2712 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2713 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2714
2715 ring->fw_ring_id = INVALID_HW_RING_ID;
2716 }
2717
2718 return 0;
2719 }
2720
2721 static void bnxt_free_ring_grps(struct bnxt *bp)
2722 {
2723 kfree(bp->grp_info);
2724 bp->grp_info = NULL;
2725 }
2726
2727 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2728 {
2729 int i;
2730
2731 if (irq_re_init) {
2732 bp->grp_info = kcalloc(bp->cp_nr_rings,
2733 sizeof(struct bnxt_ring_grp_info),
2734 GFP_KERNEL);
2735 if (!bp->grp_info)
2736 return -ENOMEM;
2737 }
2738 for (i = 0; i < bp->cp_nr_rings; i++) {
2739 if (irq_re_init)
2740 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2741 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2742 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2743 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2744 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2745 }
2746 return 0;
2747 }
2748
2749 static void bnxt_free_vnics(struct bnxt *bp)
2750 {
2751 kfree(bp->vnic_info);
2752 bp->vnic_info = NULL;
2753 bp->nr_vnics = 0;
2754 }
2755
2756 static int bnxt_alloc_vnics(struct bnxt *bp)
2757 {
2758 int num_vnics = 1;
2759
2760 #ifdef CONFIG_RFS_ACCEL
2761 if (bp->flags & BNXT_FLAG_RFS)
2762 num_vnics += bp->rx_nr_rings;
2763 #endif
2764
2765 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2766 num_vnics++;
2767
2768 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2769 GFP_KERNEL);
2770 if (!bp->vnic_info)
2771 return -ENOMEM;
2772
2773 bp->nr_vnics = num_vnics;
2774 return 0;
2775 }
2776
2777 static void bnxt_init_vnics(struct bnxt *bp)
2778 {
2779 int i;
2780
2781 for (i = 0; i < bp->nr_vnics; i++) {
2782 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2783
2784 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2785 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2786 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2787 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2788
2789 if (bp->vnic_info[i].rss_hash_key) {
2790 if (i == 0)
2791 prandom_bytes(vnic->rss_hash_key,
2792 HW_HASH_KEY_SIZE);
2793 else
2794 memcpy(vnic->rss_hash_key,
2795 bp->vnic_info[0].rss_hash_key,
2796 HW_HASH_KEY_SIZE);
2797 }
2798 }
2799 }
2800
2801 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2802 {
2803 int pages;
2804
2805 pages = ring_size / desc_per_pg;
2806
2807 if (!pages)
2808 return 1;
2809
2810 pages++;
2811
2812 while (pages & (pages - 1))
2813 pages++;
2814
2815 return pages;
2816 }
2817
2818 void bnxt_set_tpa_flags(struct bnxt *bp)
2819 {
2820 bp->flags &= ~BNXT_FLAG_TPA;
2821 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2822 return;
2823 if (bp->dev->features & NETIF_F_LRO)
2824 bp->flags |= BNXT_FLAG_LRO;
2825 else if (bp->dev->features & NETIF_F_GRO_HW)
2826 bp->flags |= BNXT_FLAG_GRO;
2827 }
2828
2829 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2830 * be set on entry.
2831 */
2832 void bnxt_set_ring_params(struct bnxt *bp)
2833 {
2834 u32 ring_size, rx_size, rx_space;
2835 u32 agg_factor = 0, agg_ring_size = 0;
2836
2837 /* 8 for CRC and VLAN */
2838 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2839
2840 rx_space = rx_size + NET_SKB_PAD +
2841 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2842
2843 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2844 ring_size = bp->rx_ring_size;
2845 bp->rx_agg_ring_size = 0;
2846 bp->rx_agg_nr_pages = 0;
2847
2848 if (bp->flags & BNXT_FLAG_TPA)
2849 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2850
2851 bp->flags &= ~BNXT_FLAG_JUMBO;
2852 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2853 u32 jumbo_factor;
2854
2855 bp->flags |= BNXT_FLAG_JUMBO;
2856 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2857 if (jumbo_factor > agg_factor)
2858 agg_factor = jumbo_factor;
2859 }
2860 agg_ring_size = ring_size * agg_factor;
2861
2862 if (agg_ring_size) {
2863 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2864 RX_DESC_CNT);
2865 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2866 u32 tmp = agg_ring_size;
2867
2868 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2869 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2870 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2871 tmp, agg_ring_size);
2872 }
2873 bp->rx_agg_ring_size = agg_ring_size;
2874 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2875 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2876 rx_space = rx_size + NET_SKB_PAD +
2877 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2878 }
2879
2880 bp->rx_buf_use_size = rx_size;
2881 bp->rx_buf_size = rx_space;
2882
2883 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2884 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2885
2886 ring_size = bp->tx_ring_size;
2887 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2888 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2889
2890 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2891 bp->cp_ring_size = ring_size;
2892
2893 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2894 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2895 bp->cp_nr_pages = MAX_CP_PAGES;
2896 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2897 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2898 ring_size, bp->cp_ring_size);
2899 }
2900 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2901 bp->cp_ring_mask = bp->cp_bit - 1;
2902 }
2903
2904 /* Changing allocation mode of RX rings.
2905 * TODO: Update when extending xdp_rxq_info to support allocation modes.
2906 */
2907 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2908 {
2909 if (page_mode) {
2910 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2911 return -EOPNOTSUPP;
2912 bp->dev->max_mtu =
2913 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
2914 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2915 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2916 bp->rx_dir = DMA_BIDIRECTIONAL;
2917 bp->rx_skb_func = bnxt_rx_page_skb;
2918 /* Disable LRO or GRO_HW */
2919 netdev_update_features(bp->dev);
2920 } else {
2921 bp->dev->max_mtu = bp->max_mtu;
2922 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2923 bp->rx_dir = DMA_FROM_DEVICE;
2924 bp->rx_skb_func = bnxt_rx_skb;
2925 }
2926 return 0;
2927 }
2928
2929 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2930 {
2931 int i;
2932 struct bnxt_vnic_info *vnic;
2933 struct pci_dev *pdev = bp->pdev;
2934
2935 if (!bp->vnic_info)
2936 return;
2937
2938 for (i = 0; i < bp->nr_vnics; i++) {
2939 vnic = &bp->vnic_info[i];
2940
2941 kfree(vnic->fw_grp_ids);
2942 vnic->fw_grp_ids = NULL;
2943
2944 kfree(vnic->uc_list);
2945 vnic->uc_list = NULL;
2946
2947 if (vnic->mc_list) {
2948 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2949 vnic->mc_list, vnic->mc_list_mapping);
2950 vnic->mc_list = NULL;
2951 }
2952
2953 if (vnic->rss_table) {
2954 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2955 vnic->rss_table,
2956 vnic->rss_table_dma_addr);
2957 vnic->rss_table = NULL;
2958 }
2959
2960 vnic->rss_hash_key = NULL;
2961 vnic->flags = 0;
2962 }
2963 }
2964
2965 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2966 {
2967 int i, rc = 0, size;
2968 struct bnxt_vnic_info *vnic;
2969 struct pci_dev *pdev = bp->pdev;
2970 int max_rings;
2971
2972 for (i = 0; i < bp->nr_vnics; i++) {
2973 vnic = &bp->vnic_info[i];
2974
2975 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2976 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2977
2978 if (mem_size > 0) {
2979 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2980 if (!vnic->uc_list) {
2981 rc = -ENOMEM;
2982 goto out;
2983 }
2984 }
2985 }
2986
2987 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2988 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2989 vnic->mc_list =
2990 dma_alloc_coherent(&pdev->dev,
2991 vnic->mc_list_size,
2992 &vnic->mc_list_mapping,
2993 GFP_KERNEL);
2994 if (!vnic->mc_list) {
2995 rc = -ENOMEM;
2996 goto out;
2997 }
2998 }
2999
3000 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3001 max_rings = bp->rx_nr_rings;
3002 else
3003 max_rings = 1;
3004
3005 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3006 if (!vnic->fw_grp_ids) {
3007 rc = -ENOMEM;
3008 goto out;
3009 }
3010
3011 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3012 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3013 continue;
3014
3015 /* Allocate rss table and hash key */
3016 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3017 &vnic->rss_table_dma_addr,
3018 GFP_KERNEL);
3019 if (!vnic->rss_table) {
3020 rc = -ENOMEM;
3021 goto out;
3022 }
3023
3024 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3025
3026 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3027 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3028 }
3029 return 0;
3030
3031 out:
3032 return rc;
3033 }
3034
3035 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3036 {
3037 struct pci_dev *pdev = bp->pdev;
3038
3039 if (bp->hwrm_cmd_resp_addr) {
3040 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3041 bp->hwrm_cmd_resp_dma_addr);
3042 bp->hwrm_cmd_resp_addr = NULL;
3043 }
3044 }
3045
3046 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3047 {
3048 struct pci_dev *pdev = bp->pdev;
3049
3050 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3051 &bp->hwrm_cmd_resp_dma_addr,
3052 GFP_KERNEL);
3053 if (!bp->hwrm_cmd_resp_addr)
3054 return -ENOMEM;
3055
3056 return 0;
3057 }
3058
3059 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3060 {
3061 if (bp->hwrm_short_cmd_req_addr) {
3062 struct pci_dev *pdev = bp->pdev;
3063
3064 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3065 bp->hwrm_short_cmd_req_addr,
3066 bp->hwrm_short_cmd_req_dma_addr);
3067 bp->hwrm_short_cmd_req_addr = NULL;
3068 }
3069 }
3070
3071 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3072 {
3073 struct pci_dev *pdev = bp->pdev;
3074
3075 bp->hwrm_short_cmd_req_addr =
3076 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3077 &bp->hwrm_short_cmd_req_dma_addr,
3078 GFP_KERNEL);
3079 if (!bp->hwrm_short_cmd_req_addr)
3080 return -ENOMEM;
3081
3082 return 0;
3083 }
3084
3085 static void bnxt_free_stats(struct bnxt *bp)
3086 {
3087 u32 size, i;
3088 struct pci_dev *pdev = bp->pdev;
3089
3090 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3091 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3092
3093 if (bp->hw_rx_port_stats) {
3094 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3095 bp->hw_rx_port_stats,
3096 bp->hw_rx_port_stats_map);
3097 bp->hw_rx_port_stats = NULL;
3098 }
3099
3100 if (bp->hw_rx_port_stats_ext) {
3101 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3102 bp->hw_rx_port_stats_ext,
3103 bp->hw_rx_port_stats_ext_map);
3104 bp->hw_rx_port_stats_ext = NULL;
3105 }
3106
3107 if (!bp->bnapi)
3108 return;
3109
3110 size = sizeof(struct ctx_hw_stats);
3111
3112 for (i = 0; i < bp->cp_nr_rings; i++) {
3113 struct bnxt_napi *bnapi = bp->bnapi[i];
3114 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3115
3116 if (cpr->hw_stats) {
3117 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3118 cpr->hw_stats_map);
3119 cpr->hw_stats = NULL;
3120 }
3121 }
3122 }
3123
3124 static int bnxt_alloc_stats(struct bnxt *bp)
3125 {
3126 u32 size, i;
3127 struct pci_dev *pdev = bp->pdev;
3128
3129 size = sizeof(struct ctx_hw_stats);
3130
3131 for (i = 0; i < bp->cp_nr_rings; i++) {
3132 struct bnxt_napi *bnapi = bp->bnapi[i];
3133 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3134
3135 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3136 &cpr->hw_stats_map,
3137 GFP_KERNEL);
3138 if (!cpr->hw_stats)
3139 return -ENOMEM;
3140
3141 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3142 }
3143
3144 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3145 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3146 sizeof(struct tx_port_stats) + 1024;
3147
3148 bp->hw_rx_port_stats =
3149 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3150 &bp->hw_rx_port_stats_map,
3151 GFP_KERNEL);
3152 if (!bp->hw_rx_port_stats)
3153 return -ENOMEM;
3154
3155 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3156 512;
3157 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3158 sizeof(struct rx_port_stats) + 512;
3159 bp->flags |= BNXT_FLAG_PORT_STATS;
3160
3161 /* Display extended statistics only if FW supports it */
3162 if (bp->hwrm_spec_code < 0x10804 ||
3163 bp->hwrm_spec_code == 0x10900)
3164 return 0;
3165
3166 bp->hw_rx_port_stats_ext =
3167 dma_zalloc_coherent(&pdev->dev,
3168 sizeof(struct rx_port_stats_ext),
3169 &bp->hw_rx_port_stats_ext_map,
3170 GFP_KERNEL);
3171 if (!bp->hw_rx_port_stats_ext)
3172 return 0;
3173
3174 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3175 }
3176 return 0;
3177 }
3178
3179 static void bnxt_clear_ring_indices(struct bnxt *bp)
3180 {
3181 int i;
3182
3183 if (!bp->bnapi)
3184 return;
3185
3186 for (i = 0; i < bp->cp_nr_rings; i++) {
3187 struct bnxt_napi *bnapi = bp->bnapi[i];
3188 struct bnxt_cp_ring_info *cpr;
3189 struct bnxt_rx_ring_info *rxr;
3190 struct bnxt_tx_ring_info *txr;
3191
3192 if (!bnapi)
3193 continue;
3194
3195 cpr = &bnapi->cp_ring;
3196 cpr->cp_raw_cons = 0;
3197
3198 txr = bnapi->tx_ring;
3199 if (txr) {
3200 txr->tx_prod = 0;
3201 txr->tx_cons = 0;
3202 }
3203
3204 rxr = bnapi->rx_ring;
3205 if (rxr) {
3206 rxr->rx_prod = 0;
3207 rxr->rx_agg_prod = 0;
3208 rxr->rx_sw_agg_prod = 0;
3209 rxr->rx_next_cons = 0;
3210 }
3211 }
3212 }
3213
3214 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3215 {
3216 #ifdef CONFIG_RFS_ACCEL
3217 int i;
3218
3219 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3220 * safe to delete the hash table.
3221 */
3222 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3223 struct hlist_head *head;
3224 struct hlist_node *tmp;
3225 struct bnxt_ntuple_filter *fltr;
3226
3227 head = &bp->ntp_fltr_hash_tbl[i];
3228 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3229 hlist_del(&fltr->hash);
3230 kfree(fltr);
3231 }
3232 }
3233 if (irq_reinit) {
3234 kfree(bp->ntp_fltr_bmap);
3235 bp->ntp_fltr_bmap = NULL;
3236 }
3237 bp->ntp_fltr_count = 0;
3238 #endif
3239 }
3240
3241 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3242 {
3243 #ifdef CONFIG_RFS_ACCEL
3244 int i, rc = 0;
3245
3246 if (!(bp->flags & BNXT_FLAG_RFS))
3247 return 0;
3248
3249 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3250 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3251
3252 bp->ntp_fltr_count = 0;
3253 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3254 sizeof(long),
3255 GFP_KERNEL);
3256
3257 if (!bp->ntp_fltr_bmap)
3258 rc = -ENOMEM;
3259
3260 return rc;
3261 #else
3262 return 0;
3263 #endif
3264 }
3265
3266 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3267 {
3268 bnxt_free_vnic_attributes(bp);
3269 bnxt_free_tx_rings(bp);
3270 bnxt_free_rx_rings(bp);
3271 bnxt_free_cp_rings(bp);
3272 bnxt_free_ntp_fltrs(bp, irq_re_init);
3273 if (irq_re_init) {
3274 bnxt_free_stats(bp);
3275 bnxt_free_ring_grps(bp);
3276 bnxt_free_vnics(bp);
3277 kfree(bp->tx_ring_map);
3278 bp->tx_ring_map = NULL;
3279 kfree(bp->tx_ring);
3280 bp->tx_ring = NULL;
3281 kfree(bp->rx_ring);
3282 bp->rx_ring = NULL;
3283 kfree(bp->bnapi);
3284 bp->bnapi = NULL;
3285 } else {
3286 bnxt_clear_ring_indices(bp);
3287 }
3288 }
3289
3290 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3291 {
3292 int i, j, rc, size, arr_size;
3293 void *bnapi;
3294
3295 if (irq_re_init) {
3296 /* Allocate bnapi mem pointer array and mem block for
3297 * all queues
3298 */
3299 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3300 bp->cp_nr_rings);
3301 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3302 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3303 if (!bnapi)
3304 return -ENOMEM;
3305
3306 bp->bnapi = bnapi;
3307 bnapi += arr_size;
3308 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3309 bp->bnapi[i] = bnapi;
3310 bp->bnapi[i]->index = i;
3311 bp->bnapi[i]->bp = bp;
3312 }
3313
3314 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3315 sizeof(struct bnxt_rx_ring_info),
3316 GFP_KERNEL);
3317 if (!bp->rx_ring)
3318 return -ENOMEM;
3319
3320 for (i = 0; i < bp->rx_nr_rings; i++) {
3321 bp->rx_ring[i].bnapi = bp->bnapi[i];
3322 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3323 }
3324
3325 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3326 sizeof(struct bnxt_tx_ring_info),
3327 GFP_KERNEL);
3328 if (!bp->tx_ring)
3329 return -ENOMEM;
3330
3331 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3332 GFP_KERNEL);
3333
3334 if (!bp->tx_ring_map)
3335 return -ENOMEM;
3336
3337 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3338 j = 0;
3339 else
3340 j = bp->rx_nr_rings;
3341
3342 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3343 bp->tx_ring[i].bnapi = bp->bnapi[j];
3344 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3345 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3346 if (i >= bp->tx_nr_rings_xdp) {
3347 bp->tx_ring[i].txq_index = i -
3348 bp->tx_nr_rings_xdp;
3349 bp->bnapi[j]->tx_int = bnxt_tx_int;
3350 } else {
3351 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3352 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3353 }
3354 }
3355
3356 rc = bnxt_alloc_stats(bp);
3357 if (rc)
3358 goto alloc_mem_err;
3359
3360 rc = bnxt_alloc_ntp_fltrs(bp);
3361 if (rc)
3362 goto alloc_mem_err;
3363
3364 rc = bnxt_alloc_vnics(bp);
3365 if (rc)
3366 goto alloc_mem_err;
3367 }
3368
3369 bnxt_init_ring_struct(bp);
3370
3371 rc = bnxt_alloc_rx_rings(bp);
3372 if (rc)
3373 goto alloc_mem_err;
3374
3375 rc = bnxt_alloc_tx_rings(bp);
3376 if (rc)
3377 goto alloc_mem_err;
3378
3379 rc = bnxt_alloc_cp_rings(bp);
3380 if (rc)
3381 goto alloc_mem_err;
3382
3383 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3384 BNXT_VNIC_UCAST_FLAG;
3385 rc = bnxt_alloc_vnic_attributes(bp);
3386 if (rc)
3387 goto alloc_mem_err;
3388 return 0;
3389
3390 alloc_mem_err:
3391 bnxt_free_mem(bp, true);
3392 return rc;
3393 }
3394
3395 static void bnxt_disable_int(struct bnxt *bp)
3396 {
3397 int i;
3398
3399 if (!bp->bnapi)
3400 return;
3401
3402 for (i = 0; i < bp->cp_nr_rings; i++) {
3403 struct bnxt_napi *bnapi = bp->bnapi[i];
3404 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3405 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3406
3407 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3408 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3409 }
3410 }
3411
3412 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3413 {
3414 struct bnxt_napi *bnapi = bp->bnapi[n];
3415 struct bnxt_cp_ring_info *cpr;
3416
3417 cpr = &bnapi->cp_ring;
3418 return cpr->cp_ring_struct.map_idx;
3419 }
3420
3421 static void bnxt_disable_int_sync(struct bnxt *bp)
3422 {
3423 int i;
3424
3425 atomic_inc(&bp->intr_sem);
3426
3427 bnxt_disable_int(bp);
3428 for (i = 0; i < bp->cp_nr_rings; i++) {
3429 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3430
3431 synchronize_irq(bp->irq_tbl[map_idx].vector);
3432 }
3433 }
3434
3435 static void bnxt_enable_int(struct bnxt *bp)
3436 {
3437 int i;
3438
3439 atomic_set(&bp->intr_sem, 0);
3440 for (i = 0; i < bp->cp_nr_rings; i++) {
3441 struct bnxt_napi *bnapi = bp->bnapi[i];
3442 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3443
3444 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3445 }
3446 }
3447
3448 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3449 u16 cmpl_ring, u16 target_id)
3450 {
3451 struct input *req = request;
3452
3453 req->req_type = cpu_to_le16(req_type);
3454 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3455 req->target_id = cpu_to_le16(target_id);
3456 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3457 }
3458
3459 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3460 int timeout, bool silent)
3461 {
3462 int i, intr_process, rc, tmo_count;
3463 struct input *req = msg;
3464 u32 *data = msg;
3465 __le32 *resp_len;
3466 u8 *valid;
3467 u16 cp_ring_id, len = 0;
3468 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3469 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3470 struct hwrm_short_input short_input = {0};
3471
3472 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3473 memset(resp, 0, PAGE_SIZE);
3474 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3475 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3476
3477 if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) {
3478 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3479
3480 memcpy(short_cmd_req, req, msg_len);
3481 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3482 msg_len);
3483
3484 short_input.req_type = req->req_type;
3485 short_input.signature =
3486 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3487 short_input.size = cpu_to_le16(msg_len);
3488 short_input.req_addr =
3489 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3490
3491 data = (u32 *)&short_input;
3492 msg_len = sizeof(short_input);
3493
3494 /* Sync memory write before updating doorbell */
3495 wmb();
3496
3497 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3498 }
3499
3500 /* Write request msg to hwrm channel */
3501 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3502
3503 for (i = msg_len; i < max_req_len; i += 4)
3504 writel(0, bp->bar0 + i);
3505
3506 /* currently supports only one outstanding message */
3507 if (intr_process)
3508 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3509
3510 /* Ring channel doorbell */
3511 writel(1, bp->bar0 + 0x100);
3512
3513 if (!timeout)
3514 timeout = DFLT_HWRM_CMD_TIMEOUT;
3515 /* convert timeout to usec */
3516 timeout *= 1000;
3517
3518 i = 0;
3519 /* Short timeout for the first few iterations:
3520 * number of loops = number of loops for short timeout +
3521 * number of loops for standard timeout.
3522 */
3523 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3524 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3525 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3526 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3527 if (intr_process) {
3528 /* Wait until hwrm response cmpl interrupt is processed */
3529 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3530 i++ < tmo_count) {
3531 /* on first few passes, just barely sleep */
3532 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3533 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3534 HWRM_SHORT_MAX_TIMEOUT);
3535 else
3536 usleep_range(HWRM_MIN_TIMEOUT,
3537 HWRM_MAX_TIMEOUT);
3538 }
3539
3540 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3541 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3542 le16_to_cpu(req->req_type));
3543 return -1;
3544 }
3545 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3546 HWRM_RESP_LEN_SFT;
3547 valid = bp->hwrm_cmd_resp_addr + len - 1;
3548 } else {
3549 int j;
3550
3551 /* Check if response len is updated */
3552 for (i = 0; i < tmo_count; i++) {
3553 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3554 HWRM_RESP_LEN_SFT;
3555 if (len)
3556 break;
3557 /* on first few passes, just barely sleep */
3558 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3559 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3560 HWRM_SHORT_MAX_TIMEOUT);
3561 else
3562 usleep_range(HWRM_MIN_TIMEOUT,
3563 HWRM_MAX_TIMEOUT);
3564 }
3565
3566 if (i >= tmo_count) {
3567 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3568 HWRM_TOTAL_TIMEOUT(i),
3569 le16_to_cpu(req->req_type),
3570 le16_to_cpu(req->seq_id), len);
3571 return -1;
3572 }
3573
3574 /* Last byte of resp contains valid bit */
3575 valid = bp->hwrm_cmd_resp_addr + len - 1;
3576 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3577 /* make sure we read from updated DMA memory */
3578 dma_rmb();
3579 if (*valid)
3580 break;
3581 usleep_range(1, 5);
3582 }
3583
3584 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3585 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3586 HWRM_TOTAL_TIMEOUT(i),
3587 le16_to_cpu(req->req_type),
3588 le16_to_cpu(req->seq_id), len, *valid);
3589 return -1;
3590 }
3591 }
3592
3593 /* Zero valid bit for compatibility. Valid bit in an older spec
3594 * may become a new field in a newer spec. We must make sure that
3595 * a new field not implemented by old spec will read zero.
3596 */
3597 *valid = 0;
3598 rc = le16_to_cpu(resp->error_code);
3599 if (rc && !silent)
3600 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3601 le16_to_cpu(resp->req_type),
3602 le16_to_cpu(resp->seq_id), rc);
3603 return rc;
3604 }
3605
3606 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3607 {
3608 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3609 }
3610
3611 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3612 int timeout)
3613 {
3614 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3615 }
3616
3617 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3618 {
3619 int rc;
3620
3621 mutex_lock(&bp->hwrm_cmd_lock);
3622 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3623 mutex_unlock(&bp->hwrm_cmd_lock);
3624 return rc;
3625 }
3626
3627 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3628 int timeout)
3629 {
3630 int rc;
3631
3632 mutex_lock(&bp->hwrm_cmd_lock);
3633 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3634 mutex_unlock(&bp->hwrm_cmd_lock);
3635 return rc;
3636 }
3637
3638 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3639 int bmap_size)
3640 {
3641 struct hwrm_func_drv_rgtr_input req = {0};
3642 DECLARE_BITMAP(async_events_bmap, 256);
3643 u32 *events = (u32 *)async_events_bmap;
3644 int i;
3645
3646 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3647
3648 req.enables =
3649 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3650
3651 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3652 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3653 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3654
3655 if (bmap && bmap_size) {
3656 for (i = 0; i < bmap_size; i++) {
3657 if (test_bit(i, bmap))
3658 __set_bit(i, async_events_bmap);
3659 }
3660 }
3661
3662 for (i = 0; i < 8; i++)
3663 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3664
3665 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3666 }
3667
3668 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3669 {
3670 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3671 struct hwrm_func_drv_rgtr_input req = {0};
3672 int rc;
3673
3674 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3675
3676 req.enables =
3677 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3678 FUNC_DRV_RGTR_REQ_ENABLES_VER);
3679
3680 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3681 req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
3682 req.ver_maj_8b = DRV_VER_MAJ;
3683 req.ver_min_8b = DRV_VER_MIN;
3684 req.ver_upd_8b = DRV_VER_UPD;
3685 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
3686 req.ver_min = cpu_to_le16(DRV_VER_MIN);
3687 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
3688
3689 if (BNXT_PF(bp)) {
3690 u32 data[8];
3691 int i;
3692
3693 memset(data, 0, sizeof(data));
3694 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3695 u16 cmd = bnxt_vf_req_snif[i];
3696 unsigned int bit, idx;
3697
3698 idx = cmd / 32;
3699 bit = cmd % 32;
3700 data[idx] |= 1 << bit;
3701 }
3702
3703 for (i = 0; i < 8; i++)
3704 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3705
3706 req.enables |=
3707 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3708 }
3709
3710 mutex_lock(&bp->hwrm_cmd_lock);
3711 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3712 if (rc)
3713 rc = -EIO;
3714 else if (resp->flags &
3715 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
3716 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
3717 mutex_unlock(&bp->hwrm_cmd_lock);
3718 return rc;
3719 }
3720
3721 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3722 {
3723 struct hwrm_func_drv_unrgtr_input req = {0};
3724
3725 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3726 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3727 }
3728
3729 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3730 {
3731 u32 rc = 0;
3732 struct hwrm_tunnel_dst_port_free_input req = {0};
3733
3734 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3735 req.tunnel_type = tunnel_type;
3736
3737 switch (tunnel_type) {
3738 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3739 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3740 break;
3741 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3742 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3743 break;
3744 default:
3745 break;
3746 }
3747
3748 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3749 if (rc)
3750 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3751 rc);
3752 return rc;
3753 }
3754
3755 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3756 u8 tunnel_type)
3757 {
3758 u32 rc = 0;
3759 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3760 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3761
3762 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3763
3764 req.tunnel_type = tunnel_type;
3765 req.tunnel_dst_port_val = port;
3766
3767 mutex_lock(&bp->hwrm_cmd_lock);
3768 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3769 if (rc) {
3770 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3771 rc);
3772 goto err_out;
3773 }
3774
3775 switch (tunnel_type) {
3776 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3777 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3778 break;
3779 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3780 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3781 break;
3782 default:
3783 break;
3784 }
3785
3786 err_out:
3787 mutex_unlock(&bp->hwrm_cmd_lock);
3788 return rc;
3789 }
3790
3791 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3792 {
3793 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3794 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3795
3796 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3797 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3798
3799 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3800 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3801 req.mask = cpu_to_le32(vnic->rx_mask);
3802 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3803 }
3804
3805 #ifdef CONFIG_RFS_ACCEL
3806 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3807 struct bnxt_ntuple_filter *fltr)
3808 {
3809 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3810
3811 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3812 req.ntuple_filter_id = fltr->filter_id;
3813 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3814 }
3815
3816 #define BNXT_NTP_FLTR_FLAGS \
3817 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3818 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3819 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3820 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3821 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3822 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3823 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3824 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3825 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3826 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3827 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3828 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3829 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3830 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3831
3832 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
3833 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3834
3835 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3836 struct bnxt_ntuple_filter *fltr)
3837 {
3838 int rc = 0;
3839 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3840 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3841 bp->hwrm_cmd_resp_addr;
3842 struct flow_keys *keys = &fltr->fkeys;
3843 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3844
3845 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3846 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3847
3848 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3849
3850 req.ethertype = htons(ETH_P_IP);
3851 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3852 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3853 req.ip_protocol = keys->basic.ip_proto;
3854
3855 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3856 int i;
3857
3858 req.ethertype = htons(ETH_P_IPV6);
3859 req.ip_addr_type =
3860 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3861 *(struct in6_addr *)&req.src_ipaddr[0] =
3862 keys->addrs.v6addrs.src;
3863 *(struct in6_addr *)&req.dst_ipaddr[0] =
3864 keys->addrs.v6addrs.dst;
3865 for (i = 0; i < 4; i++) {
3866 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3867 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3868 }
3869 } else {
3870 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3871 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3872 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3873 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3874 }
3875 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3876 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3877 req.tunnel_type =
3878 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3879 }
3880
3881 req.src_port = keys->ports.src;
3882 req.src_port_mask = cpu_to_be16(0xffff);
3883 req.dst_port = keys->ports.dst;
3884 req.dst_port_mask = cpu_to_be16(0xffff);
3885
3886 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3887 mutex_lock(&bp->hwrm_cmd_lock);
3888 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3889 if (!rc)
3890 fltr->filter_id = resp->ntuple_filter_id;
3891 mutex_unlock(&bp->hwrm_cmd_lock);
3892 return rc;
3893 }
3894 #endif
3895
3896 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3897 u8 *mac_addr)
3898 {
3899 u32 rc = 0;
3900 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3901 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3902
3903 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3904 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3905 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3906 req.flags |=
3907 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3908 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3909 req.enables =
3910 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3911 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3912 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3913 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3914 req.l2_addr_mask[0] = 0xff;
3915 req.l2_addr_mask[1] = 0xff;
3916 req.l2_addr_mask[2] = 0xff;
3917 req.l2_addr_mask[3] = 0xff;
3918 req.l2_addr_mask[4] = 0xff;
3919 req.l2_addr_mask[5] = 0xff;
3920
3921 mutex_lock(&bp->hwrm_cmd_lock);
3922 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3923 if (!rc)
3924 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3925 resp->l2_filter_id;
3926 mutex_unlock(&bp->hwrm_cmd_lock);
3927 return rc;
3928 }
3929
3930 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3931 {
3932 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3933 int rc = 0;
3934
3935 /* Any associated ntuple filters will also be cleared by firmware. */
3936 mutex_lock(&bp->hwrm_cmd_lock);
3937 for (i = 0; i < num_of_vnics; i++) {
3938 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3939
3940 for (j = 0; j < vnic->uc_filter_count; j++) {
3941 struct hwrm_cfa_l2_filter_free_input req = {0};
3942
3943 bnxt_hwrm_cmd_hdr_init(bp, &req,
3944 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3945
3946 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3947
3948 rc = _hwrm_send_message(bp, &req, sizeof(req),
3949 HWRM_CMD_TIMEOUT);
3950 }
3951 vnic->uc_filter_count = 0;
3952 }
3953 mutex_unlock(&bp->hwrm_cmd_lock);
3954
3955 return rc;
3956 }
3957
3958 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3959 {
3960 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3961 struct hwrm_vnic_tpa_cfg_input req = {0};
3962
3963 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
3964 return 0;
3965
3966 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3967
3968 if (tpa_flags) {
3969 u16 mss = bp->dev->mtu - 40;
3970 u32 nsegs, n, segs = 0, flags;
3971
3972 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3973 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3974 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3975 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3976 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3977 if (tpa_flags & BNXT_FLAG_GRO)
3978 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3979
3980 req.flags = cpu_to_le32(flags);
3981
3982 req.enables =
3983 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3984 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3985 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3986
3987 /* Number of segs are log2 units, and first packet is not
3988 * included as part of this units.
3989 */
3990 if (mss <= BNXT_RX_PAGE_SIZE) {
3991 n = BNXT_RX_PAGE_SIZE / mss;
3992 nsegs = (MAX_SKB_FRAGS - 1) * n;
3993 } else {
3994 n = mss / BNXT_RX_PAGE_SIZE;
3995 if (mss & (BNXT_RX_PAGE_SIZE - 1))
3996 n++;
3997 nsegs = (MAX_SKB_FRAGS - n) / n;
3998 }
3999
4000 segs = ilog2(nsegs);
4001 req.max_agg_segs = cpu_to_le16(segs);
4002 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4003
4004 req.min_agg_len = cpu_to_le32(512);
4005 }
4006 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4007
4008 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4009 }
4010
4011 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4012 {
4013 u32 i, j, max_rings;
4014 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4015 struct hwrm_vnic_rss_cfg_input req = {0};
4016
4017 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4018 return 0;
4019
4020 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4021 if (set_rss) {
4022 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4023 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4024 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4025 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4026 max_rings = bp->rx_nr_rings - 1;
4027 else
4028 max_rings = bp->rx_nr_rings;
4029 } else {
4030 max_rings = 1;
4031 }
4032
4033 /* Fill the RSS indirection table with ring group ids */
4034 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4035 if (j == max_rings)
4036 j = 0;
4037 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4038 }
4039
4040 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4041 req.hash_key_tbl_addr =
4042 cpu_to_le64(vnic->rss_hash_key_dma_addr);
4043 }
4044 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4045 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4046 }
4047
4048 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4049 {
4050 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4051 struct hwrm_vnic_plcmodes_cfg_input req = {0};
4052
4053 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4054 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4055 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4056 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4057 req.enables =
4058 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4059 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4060 /* thresholds not implemented in firmware yet */
4061 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4062 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4063 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4064 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4065 }
4066
4067 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4068 u16 ctx_idx)
4069 {
4070 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4071
4072 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4073 req.rss_cos_lb_ctx_id =
4074 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4075
4076 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4077 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4078 }
4079
4080 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4081 {
4082 int i, j;
4083
4084 for (i = 0; i < bp->nr_vnics; i++) {
4085 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4086
4087 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4088 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4089 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4090 }
4091 }
4092 bp->rsscos_nr_ctxs = 0;
4093 }
4094
4095 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4096 {
4097 int rc;
4098 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4099 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4100 bp->hwrm_cmd_resp_addr;
4101
4102 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4103 -1);
4104
4105 mutex_lock(&bp->hwrm_cmd_lock);
4106 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4107 if (!rc)
4108 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4109 le16_to_cpu(resp->rss_cos_lb_ctx_id);
4110 mutex_unlock(&bp->hwrm_cmd_lock);
4111
4112 return rc;
4113 }
4114
4115 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4116 {
4117 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4118 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4119 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4120 }
4121
4122 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4123 {
4124 unsigned int ring = 0, grp_idx;
4125 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4126 struct hwrm_vnic_cfg_input req = {0};
4127 u16 def_vlan = 0;
4128
4129 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4130
4131 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4132 /* Only RSS support for now TBD: COS & LB */
4133 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4134 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4135 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4136 VNIC_CFG_REQ_ENABLES_MRU);
4137 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4138 req.rss_rule =
4139 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4140 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4141 VNIC_CFG_REQ_ENABLES_MRU);
4142 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4143 } else {
4144 req.rss_rule = cpu_to_le16(0xffff);
4145 }
4146
4147 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4148 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4149 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4150 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4151 } else {
4152 req.cos_rule = cpu_to_le16(0xffff);
4153 }
4154
4155 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4156 ring = 0;
4157 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4158 ring = vnic_id - 1;
4159 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4160 ring = bp->rx_nr_rings - 1;
4161
4162 grp_idx = bp->rx_ring[ring].bnapi->index;
4163 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4164 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4165
4166 req.lb_rule = cpu_to_le16(0xffff);
4167 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4168 VLAN_HLEN);
4169
4170 #ifdef CONFIG_BNXT_SRIOV
4171 if (BNXT_VF(bp))
4172 def_vlan = bp->vf.vlan;
4173 #endif
4174 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4175 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4176 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4177 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4178
4179 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4180 }
4181
4182 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4183 {
4184 u32 rc = 0;
4185
4186 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4187 struct hwrm_vnic_free_input req = {0};
4188
4189 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4190 req.vnic_id =
4191 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4192
4193 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4194 if (rc)
4195 return rc;
4196 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4197 }
4198 return rc;
4199 }
4200
4201 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4202 {
4203 u16 i;
4204
4205 for (i = 0; i < bp->nr_vnics; i++)
4206 bnxt_hwrm_vnic_free_one(bp, i);
4207 }
4208
4209 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4210 unsigned int start_rx_ring_idx,
4211 unsigned int nr_rings)
4212 {
4213 int rc = 0;
4214 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4215 struct hwrm_vnic_alloc_input req = {0};
4216 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4217
4218 /* map ring groups to this vnic */
4219 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4220 grp_idx = bp->rx_ring[i].bnapi->index;
4221 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4222 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4223 j, nr_rings);
4224 break;
4225 }
4226 bp->vnic_info[vnic_id].fw_grp_ids[j] =
4227 bp->grp_info[grp_idx].fw_grp_id;
4228 }
4229
4230 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4231 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
4232 if (vnic_id == 0)
4233 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4234
4235 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4236
4237 mutex_lock(&bp->hwrm_cmd_lock);
4238 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4239 if (!rc)
4240 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4241 mutex_unlock(&bp->hwrm_cmd_lock);
4242 return rc;
4243 }
4244
4245 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4246 {
4247 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4248 struct hwrm_vnic_qcaps_input req = {0};
4249 int rc;
4250
4251 if (bp->hwrm_spec_code < 0x10600)
4252 return 0;
4253
4254 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4255 mutex_lock(&bp->hwrm_cmd_lock);
4256 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4257 if (!rc) {
4258 u32 flags = le32_to_cpu(resp->flags);
4259
4260 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)
4261 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4262 if (flags &
4263 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4264 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4265 }
4266 mutex_unlock(&bp->hwrm_cmd_lock);
4267 return rc;
4268 }
4269
4270 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4271 {
4272 u16 i;
4273 u32 rc = 0;
4274
4275 mutex_lock(&bp->hwrm_cmd_lock);
4276 for (i = 0; i < bp->rx_nr_rings; i++) {
4277 struct hwrm_ring_grp_alloc_input req = {0};
4278 struct hwrm_ring_grp_alloc_output *resp =
4279 bp->hwrm_cmd_resp_addr;
4280 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4281
4282 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4283
4284 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4285 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4286 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4287 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4288
4289 rc = _hwrm_send_message(bp, &req, sizeof(req),
4290 HWRM_CMD_TIMEOUT);
4291 if (rc)
4292 break;
4293
4294 bp->grp_info[grp_idx].fw_grp_id =
4295 le32_to_cpu(resp->ring_group_id);
4296 }
4297 mutex_unlock(&bp->hwrm_cmd_lock);
4298 return rc;
4299 }
4300
4301 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4302 {
4303 u16 i;
4304 u32 rc = 0;
4305 struct hwrm_ring_grp_free_input req = {0};
4306
4307 if (!bp->grp_info)
4308 return 0;
4309
4310 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4311
4312 mutex_lock(&bp->hwrm_cmd_lock);
4313 for (i = 0; i < bp->cp_nr_rings; i++) {
4314 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4315 continue;
4316 req.ring_group_id =
4317 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4318
4319 rc = _hwrm_send_message(bp, &req, sizeof(req),
4320 HWRM_CMD_TIMEOUT);
4321 if (rc)
4322 break;
4323 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4324 }
4325 mutex_unlock(&bp->hwrm_cmd_lock);
4326 return rc;
4327 }
4328
4329 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4330 struct bnxt_ring_struct *ring,
4331 u32 ring_type, u32 map_index)
4332 {
4333 int rc = 0, err = 0;
4334 struct hwrm_ring_alloc_input req = {0};
4335 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4336 struct bnxt_ring_grp_info *grp_info;
4337 u16 ring_id;
4338
4339 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4340
4341 req.enables = 0;
4342 if (ring->nr_pages > 1) {
4343 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4344 /* Page size is in log2 units */
4345 req.page_size = BNXT_PAGE_SHIFT;
4346 req.page_tbl_depth = 1;
4347 } else {
4348 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
4349 }
4350 req.fbo = 0;
4351 /* Association of ring index with doorbell index and MSIX number */
4352 req.logical_id = cpu_to_le16(map_index);
4353
4354 switch (ring_type) {
4355 case HWRM_RING_ALLOC_TX:
4356 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4357 /* Association of transmit ring with completion ring */
4358 grp_info = &bp->grp_info[ring->grp_idx];
4359 req.cmpl_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4360 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4361 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4362 req.queue_id = cpu_to_le16(ring->queue_id);
4363 break;
4364 case HWRM_RING_ALLOC_RX:
4365 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4366 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4367 break;
4368 case HWRM_RING_ALLOC_AGG:
4369 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4370 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4371 break;
4372 case HWRM_RING_ALLOC_CMPL:
4373 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4374 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4375 if (bp->flags & BNXT_FLAG_USING_MSIX)
4376 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4377 break;
4378 default:
4379 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4380 ring_type);
4381 return -1;
4382 }
4383
4384 mutex_lock(&bp->hwrm_cmd_lock);
4385 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4386 err = le16_to_cpu(resp->error_code);
4387 ring_id = le16_to_cpu(resp->ring_id);
4388 mutex_unlock(&bp->hwrm_cmd_lock);
4389
4390 if (rc || err) {
4391 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4392 ring_type, rc, err);
4393 return -EIO;
4394 }
4395 ring->fw_ring_id = ring_id;
4396 return rc;
4397 }
4398
4399 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4400 {
4401 int rc;
4402
4403 if (BNXT_PF(bp)) {
4404 struct hwrm_func_cfg_input req = {0};
4405
4406 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4407 req.fid = cpu_to_le16(0xffff);
4408 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4409 req.async_event_cr = cpu_to_le16(idx);
4410 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4411 } else {
4412 struct hwrm_func_vf_cfg_input req = {0};
4413
4414 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4415 req.enables =
4416 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4417 req.async_event_cr = cpu_to_le16(idx);
4418 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4419 }
4420 return rc;
4421 }
4422
4423 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4424 {
4425 int i, rc = 0;
4426
4427 for (i = 0; i < bp->cp_nr_rings; i++) {
4428 struct bnxt_napi *bnapi = bp->bnapi[i];
4429 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4430 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4431 u32 map_idx = ring->map_idx;
4432
4433 cpr->cp_doorbell = bp->bar1 + map_idx * 0x80;
4434 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL,
4435 map_idx);
4436 if (rc)
4437 goto err_out;
4438 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4439 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4440
4441 if (!i) {
4442 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4443 if (rc)
4444 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4445 }
4446 }
4447
4448 for (i = 0; i < bp->tx_nr_rings; i++) {
4449 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4450 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4451 u32 map_idx = i;
4452
4453 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4454 map_idx);
4455 if (rc)
4456 goto err_out;
4457 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4458 }
4459
4460 for (i = 0; i < bp->rx_nr_rings; i++) {
4461 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4462 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4463 u32 map_idx = rxr->bnapi->index;
4464
4465 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4466 map_idx);
4467 if (rc)
4468 goto err_out;
4469 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4470 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4471 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4472 }
4473
4474 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4475 for (i = 0; i < bp->rx_nr_rings; i++) {
4476 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4477 struct bnxt_ring_struct *ring =
4478 &rxr->rx_agg_ring_struct;
4479 u32 grp_idx = ring->grp_idx;
4480 u32 map_idx = grp_idx + bp->rx_nr_rings;
4481
4482 rc = hwrm_ring_alloc_send_msg(bp, ring,
4483 HWRM_RING_ALLOC_AGG,
4484 map_idx);
4485 if (rc)
4486 goto err_out;
4487
4488 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4489 writel(DB_KEY_RX | rxr->rx_agg_prod,
4490 rxr->rx_agg_doorbell);
4491 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4492 }
4493 }
4494 err_out:
4495 return rc;
4496 }
4497
4498 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4499 struct bnxt_ring_struct *ring,
4500 u32 ring_type, int cmpl_ring_id)
4501 {
4502 int rc;
4503 struct hwrm_ring_free_input req = {0};
4504 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4505 u16 error_code;
4506
4507 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4508 req.ring_type = ring_type;
4509 req.ring_id = cpu_to_le16(ring->fw_ring_id);
4510
4511 mutex_lock(&bp->hwrm_cmd_lock);
4512 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4513 error_code = le16_to_cpu(resp->error_code);
4514 mutex_unlock(&bp->hwrm_cmd_lock);
4515
4516 if (rc || error_code) {
4517 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
4518 ring_type, rc, error_code);
4519 return -EIO;
4520 }
4521 return 0;
4522 }
4523
4524 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4525 {
4526 int i;
4527
4528 if (!bp->bnapi)
4529 return;
4530
4531 for (i = 0; i < bp->tx_nr_rings; i++) {
4532 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4533 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4534 u32 grp_idx = txr->bnapi->index;
4535 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4536
4537 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4538 hwrm_ring_free_send_msg(bp, ring,
4539 RING_FREE_REQ_RING_TYPE_TX,
4540 close_path ? cmpl_ring_id :
4541 INVALID_HW_RING_ID);
4542 ring->fw_ring_id = INVALID_HW_RING_ID;
4543 }
4544 }
4545
4546 for (i = 0; i < bp->rx_nr_rings; i++) {
4547 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4548 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4549 u32 grp_idx = rxr->bnapi->index;
4550 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4551
4552 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4553 hwrm_ring_free_send_msg(bp, ring,
4554 RING_FREE_REQ_RING_TYPE_RX,
4555 close_path ? cmpl_ring_id :
4556 INVALID_HW_RING_ID);
4557 ring->fw_ring_id = INVALID_HW_RING_ID;
4558 bp->grp_info[grp_idx].rx_fw_ring_id =
4559 INVALID_HW_RING_ID;
4560 }
4561 }
4562
4563 for (i = 0; i < bp->rx_nr_rings; i++) {
4564 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4565 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4566 u32 grp_idx = rxr->bnapi->index;
4567 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4568
4569 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4570 hwrm_ring_free_send_msg(bp, ring,
4571 RING_FREE_REQ_RING_TYPE_RX,
4572 close_path ? cmpl_ring_id :
4573 INVALID_HW_RING_ID);
4574 ring->fw_ring_id = INVALID_HW_RING_ID;
4575 bp->grp_info[grp_idx].agg_fw_ring_id =
4576 INVALID_HW_RING_ID;
4577 }
4578 }
4579
4580 /* The completion rings are about to be freed. After that the
4581 * IRQ doorbell will not work anymore. So we need to disable
4582 * IRQ here.
4583 */
4584 bnxt_disable_int_sync(bp);
4585
4586 for (i = 0; i < bp->cp_nr_rings; i++) {
4587 struct bnxt_napi *bnapi = bp->bnapi[i];
4588 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4589 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4590
4591 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4592 hwrm_ring_free_send_msg(bp, ring,
4593 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4594 INVALID_HW_RING_ID);
4595 ring->fw_ring_id = INVALID_HW_RING_ID;
4596 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4597 }
4598 }
4599 }
4600
4601 static int bnxt_hwrm_get_rings(struct bnxt *bp)
4602 {
4603 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4604 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4605 struct hwrm_func_qcfg_input req = {0};
4606 int rc;
4607
4608 if (bp->hwrm_spec_code < 0x10601)
4609 return 0;
4610
4611 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4612 req.fid = cpu_to_le16(0xffff);
4613 mutex_lock(&bp->hwrm_cmd_lock);
4614 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4615 if (rc) {
4616 mutex_unlock(&bp->hwrm_cmd_lock);
4617 return -EIO;
4618 }
4619
4620 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4621 if (BNXT_NEW_RM(bp)) {
4622 u16 cp, stats;
4623
4624 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
4625 hw_resc->resv_hw_ring_grps =
4626 le32_to_cpu(resp->alloc_hw_ring_grps);
4627 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
4628 cp = le16_to_cpu(resp->alloc_cmpl_rings);
4629 stats = le16_to_cpu(resp->alloc_stat_ctx);
4630 cp = min_t(u16, cp, stats);
4631 hw_resc->resv_cp_rings = cp;
4632 }
4633 mutex_unlock(&bp->hwrm_cmd_lock);
4634 return 0;
4635 }
4636
4637 /* Caller must hold bp->hwrm_cmd_lock */
4638 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4639 {
4640 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4641 struct hwrm_func_qcfg_input req = {0};
4642 int rc;
4643
4644 if (bp->hwrm_spec_code < 0x10601)
4645 return 0;
4646
4647 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4648 req.fid = cpu_to_le16(fid);
4649 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4650 if (!rc)
4651 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4652
4653 return rc;
4654 }
4655
4656 static void
4657 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
4658 int tx_rings, int rx_rings, int ring_grps,
4659 int cp_rings, int vnics)
4660 {
4661 u32 enables = 0;
4662
4663 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
4664 req->fid = cpu_to_le16(0xffff);
4665 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4666 req->num_tx_rings = cpu_to_le16(tx_rings);
4667 if (BNXT_NEW_RM(bp)) {
4668 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4669 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4670 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4671 enables |= ring_grps ?
4672 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4673 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
4674
4675 req->num_rx_rings = cpu_to_le16(rx_rings);
4676 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4677 req->num_cmpl_rings = cpu_to_le16(cp_rings);
4678 req->num_stat_ctxs = req->num_cmpl_rings;
4679 req->num_vnics = cpu_to_le16(vnics);
4680 }
4681 req->enables = cpu_to_le32(enables);
4682 }
4683
4684 static void
4685 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
4686 struct hwrm_func_vf_cfg_input *req, int tx_rings,
4687 int rx_rings, int ring_grps, int cp_rings,
4688 int vnics)
4689 {
4690 u32 enables = 0;
4691
4692 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
4693 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4694 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4695 enables |= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4696 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4697 enables |= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4698 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4699
4700 req->num_tx_rings = cpu_to_le16(tx_rings);
4701 req->num_rx_rings = cpu_to_le16(rx_rings);
4702 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4703 req->num_cmpl_rings = cpu_to_le16(cp_rings);
4704 req->num_stat_ctxs = req->num_cmpl_rings;
4705 req->num_vnics = cpu_to_le16(vnics);
4706
4707 req->enables = cpu_to_le32(enables);
4708 }
4709
4710 static int
4711 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4712 int ring_grps, int cp_rings, int vnics)
4713 {
4714 struct hwrm_func_cfg_input req = {0};
4715 int rc;
4716
4717 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4718 cp_rings, vnics);
4719 if (!req.enables)
4720 return 0;
4721
4722 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4723 if (rc)
4724 return -ENOMEM;
4725
4726 if (bp->hwrm_spec_code < 0x10601)
4727 bp->hw_resc.resv_tx_rings = tx_rings;
4728
4729 rc = bnxt_hwrm_get_rings(bp);
4730 return rc;
4731 }
4732
4733 static int
4734 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4735 int ring_grps, int cp_rings, int vnics)
4736 {
4737 struct hwrm_func_vf_cfg_input req = {0};
4738 int rc;
4739
4740 if (!BNXT_NEW_RM(bp)) {
4741 bp->hw_resc.resv_tx_rings = tx_rings;
4742 return 0;
4743 }
4744
4745 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4746 cp_rings, vnics);
4747 req.enables |= cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS |
4748 FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS);
4749 req.num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
4750 req.num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
4751 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4752 if (rc)
4753 return -ENOMEM;
4754
4755 rc = bnxt_hwrm_get_rings(bp);
4756 return rc;
4757 }
4758
4759 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
4760 int cp, int vnic)
4761 {
4762 if (BNXT_PF(bp))
4763 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic);
4764 else
4765 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic);
4766 }
4767
4768 static int bnxt_cp_rings_in_use(struct bnxt *bp)
4769 {
4770 int cp = bp->cp_nr_rings;
4771 int ulp_msix, ulp_base;
4772
4773 ulp_msix = bnxt_get_ulp_msix_num(bp);
4774 if (ulp_msix) {
4775 ulp_base = bnxt_get_ulp_msix_base(bp);
4776 cp += ulp_msix;
4777 if ((ulp_base + ulp_msix) > cp)
4778 cp = ulp_base + ulp_msix;
4779 }
4780 return cp;
4781 }
4782
4783 static bool bnxt_need_reserve_rings(struct bnxt *bp)
4784 {
4785 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4786 int cp = bnxt_cp_rings_in_use(bp);
4787 int rx = bp->rx_nr_rings;
4788 int vnic = 1, grp = rx;
4789
4790 if (bp->hwrm_spec_code < 0x10601)
4791 return false;
4792
4793 if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
4794 return true;
4795
4796 if (bp->flags & BNXT_FLAG_RFS)
4797 vnic = rx + 1;
4798 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4799 rx <<= 1;
4800 if (BNXT_NEW_RM(bp) &&
4801 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
4802 hw_resc->resv_hw_ring_grps != grp || hw_resc->resv_vnics != vnic))
4803 return true;
4804 return false;
4805 }
4806
4807 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4808 bool shared);
4809
4810 static int __bnxt_reserve_rings(struct bnxt *bp)
4811 {
4812 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4813 int cp = bnxt_cp_rings_in_use(bp);
4814 int tx = bp->tx_nr_rings;
4815 int rx = bp->rx_nr_rings;
4816 int grp, rx_rings, rc;
4817 bool sh = false;
4818 int vnic = 1;
4819
4820 if (!bnxt_need_reserve_rings(bp))
4821 return 0;
4822
4823 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4824 sh = true;
4825 if (bp->flags & BNXT_FLAG_RFS)
4826 vnic = rx + 1;
4827 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4828 rx <<= 1;
4829 grp = bp->rx_nr_rings;
4830
4831 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic);
4832 if (rc)
4833 return rc;
4834
4835 tx = hw_resc->resv_tx_rings;
4836 if (BNXT_NEW_RM(bp)) {
4837 rx = hw_resc->resv_rx_rings;
4838 cp = hw_resc->resv_cp_rings;
4839 grp = hw_resc->resv_hw_ring_grps;
4840 vnic = hw_resc->resv_vnics;
4841 }
4842
4843 rx_rings = rx;
4844 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4845 if (rx >= 2) {
4846 rx_rings = rx >> 1;
4847 } else {
4848 if (netif_running(bp->dev))
4849 return -ENOMEM;
4850
4851 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
4852 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4853 bp->dev->hw_features &= ~NETIF_F_LRO;
4854 bp->dev->features &= ~NETIF_F_LRO;
4855 bnxt_set_ring_params(bp);
4856 }
4857 }
4858 rx_rings = min_t(int, rx_rings, grp);
4859 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
4860 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4861 rx = rx_rings << 1;
4862 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
4863 bp->tx_nr_rings = tx;
4864 bp->rx_nr_rings = rx_rings;
4865 bp->cp_nr_rings = cp;
4866
4867 if (!tx || !rx || !cp || !grp || !vnic)
4868 return -ENOMEM;
4869
4870 return rc;
4871 }
4872
4873 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4874 int ring_grps, int cp_rings, int vnics)
4875 {
4876 struct hwrm_func_vf_cfg_input req = {0};
4877 u32 flags;
4878 int rc;
4879
4880 if (!BNXT_NEW_RM(bp))
4881 return 0;
4882
4883 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4884 cp_rings, vnics);
4885 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
4886 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4887 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4888 FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4889 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4890 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4891
4892 req.flags = cpu_to_le32(flags);
4893 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4894 if (rc)
4895 return -ENOMEM;
4896 return 0;
4897 }
4898
4899 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4900 int ring_grps, int cp_rings, int vnics)
4901 {
4902 struct hwrm_func_cfg_input req = {0};
4903 u32 flags;
4904 int rc;
4905
4906 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4907 cp_rings, vnics);
4908 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
4909 if (BNXT_NEW_RM(bp))
4910 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4911 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4912 FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4913 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4914 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4915
4916 req.flags = cpu_to_le32(flags);
4917 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4918 if (rc)
4919 return -ENOMEM;
4920 return 0;
4921 }
4922
4923 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4924 int ring_grps, int cp_rings, int vnics)
4925 {
4926 if (bp->hwrm_spec_code < 0x10801)
4927 return 0;
4928
4929 if (BNXT_PF(bp))
4930 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
4931 ring_grps, cp_rings, vnics);
4932
4933 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
4934 cp_rings, vnics);
4935 }
4936
4937 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4938 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4939 {
4940 u16 val, tmr, max, flags;
4941
4942 max = hw_coal->bufs_per_record * 128;
4943 if (hw_coal->budget)
4944 max = hw_coal->bufs_per_record * hw_coal->budget;
4945
4946 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
4947 req->num_cmpl_aggr_int = cpu_to_le16(val);
4948
4949 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4950 val = min_t(u16, val, 63);
4951 req->num_cmpl_dma_aggr = cpu_to_le16(val);
4952
4953 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4954 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
4955 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
4956
4957 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);
4958 tmr = max_t(u16, tmr, 1);
4959 req->int_lat_tmr_max = cpu_to_le16(tmr);
4960
4961 /* min timer set to 1/2 of interrupt timer */
4962 val = tmr / 2;
4963 req->int_lat_tmr_min = cpu_to_le16(val);
4964
4965 /* buf timer set to 1/4 of interrupt timer */
4966 val = max_t(u16, tmr / 4, 1);
4967 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
4968
4969 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq);
4970 tmr = max_t(u16, tmr, 1);
4971 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
4972
4973 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4974 if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
4975 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4976 req->flags = cpu_to_le16(flags);
4977 }
4978
4979 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
4980 {
4981 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
4982 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4983 struct bnxt_coal coal;
4984 unsigned int grp_idx;
4985
4986 /* Tick values in micro seconds.
4987 * 1 coal_buf x bufs_per_record = 1 completion record.
4988 */
4989 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
4990
4991 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
4992 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
4993
4994 if (!bnapi->rx_ring)
4995 return -ENODEV;
4996
4997 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4998 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4999
5000 bnxt_hwrm_set_coal_params(&coal, &req_rx);
5001
5002 grp_idx = bnapi->index;
5003 req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
5004
5005 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5006 HWRM_CMD_TIMEOUT);
5007 }
5008
5009 int bnxt_hwrm_set_coal(struct bnxt *bp)
5010 {
5011 int i, rc = 0;
5012 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5013 req_tx = {0}, *req;
5014
5015 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5016 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5017 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5018 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5019
5020 bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx);
5021 bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx);
5022
5023 mutex_lock(&bp->hwrm_cmd_lock);
5024 for (i = 0; i < bp->cp_nr_rings; i++) {
5025 struct bnxt_napi *bnapi = bp->bnapi[i];
5026
5027 req = &req_rx;
5028 if (!bnapi->rx_ring)
5029 req = &req_tx;
5030 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
5031
5032 rc = _hwrm_send_message(bp, req, sizeof(*req),
5033 HWRM_CMD_TIMEOUT);
5034 if (rc)
5035 break;
5036 }
5037 mutex_unlock(&bp->hwrm_cmd_lock);
5038 return rc;
5039 }
5040
5041 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5042 {
5043 int rc = 0, i;
5044 struct hwrm_stat_ctx_free_input req = {0};
5045
5046 if (!bp->bnapi)
5047 return 0;
5048
5049 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5050 return 0;
5051
5052 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5053
5054 mutex_lock(&bp->hwrm_cmd_lock);
5055 for (i = 0; i < bp->cp_nr_rings; i++) {
5056 struct bnxt_napi *bnapi = bp->bnapi[i];
5057 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5058
5059 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5060 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5061
5062 rc = _hwrm_send_message(bp, &req, sizeof(req),
5063 HWRM_CMD_TIMEOUT);
5064 if (rc)
5065 break;
5066
5067 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5068 }
5069 }
5070 mutex_unlock(&bp->hwrm_cmd_lock);
5071 return rc;
5072 }
5073
5074 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5075 {
5076 int rc = 0, i;
5077 struct hwrm_stat_ctx_alloc_input req = {0};
5078 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5079
5080 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5081 return 0;
5082
5083 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5084
5085 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5086
5087 mutex_lock(&bp->hwrm_cmd_lock);
5088 for (i = 0; i < bp->cp_nr_rings; i++) {
5089 struct bnxt_napi *bnapi = bp->bnapi[i];
5090 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5091
5092 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5093
5094 rc = _hwrm_send_message(bp, &req, sizeof(req),
5095 HWRM_CMD_TIMEOUT);
5096 if (rc)
5097 break;
5098
5099 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5100
5101 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5102 }
5103 mutex_unlock(&bp->hwrm_cmd_lock);
5104 return rc;
5105 }
5106
5107 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5108 {
5109 struct hwrm_func_qcfg_input req = {0};
5110 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5111 u16 flags;
5112 int rc;
5113
5114 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5115 req.fid = cpu_to_le16(0xffff);
5116 mutex_lock(&bp->hwrm_cmd_lock);
5117 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5118 if (rc)
5119 goto func_qcfg_exit;
5120
5121 #ifdef CONFIG_BNXT_SRIOV
5122 if (BNXT_VF(bp)) {
5123 struct bnxt_vf_info *vf = &bp->vf;
5124
5125 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5126 }
5127 #endif
5128 flags = le16_to_cpu(resp->flags);
5129 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5130 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5131 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
5132 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5133 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
5134 }
5135 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5136 bp->flags |= BNXT_FLAG_MULTI_HOST;
5137
5138 switch (resp->port_partition_type) {
5139 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5140 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5141 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5142 bp->port_partition_type = resp->port_partition_type;
5143 break;
5144 }
5145 if (bp->hwrm_spec_code < 0x10707 ||
5146 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5147 bp->br_mode = BRIDGE_MODE_VEB;
5148 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5149 bp->br_mode = BRIDGE_MODE_VEPA;
5150 else
5151 bp->br_mode = BRIDGE_MODE_UNDEF;
5152
5153 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5154 if (!bp->max_mtu)
5155 bp->max_mtu = BNXT_MAX_MTU;
5156
5157 func_qcfg_exit:
5158 mutex_unlock(&bp->hwrm_cmd_lock);
5159 return rc;
5160 }
5161
5162 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
5163 {
5164 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5165 struct hwrm_func_resource_qcaps_input req = {0};
5166 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5167 int rc;
5168
5169 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
5170 req.fid = cpu_to_le16(0xffff);
5171
5172 mutex_lock(&bp->hwrm_cmd_lock);
5173 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5174 if (rc) {
5175 rc = -EIO;
5176 goto hwrm_func_resc_qcaps_exit;
5177 }
5178
5179 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
5180 if (!all)
5181 goto hwrm_func_resc_qcaps_exit;
5182
5183 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
5184 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5185 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
5186 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5187 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
5188 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5189 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
5190 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5191 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
5192 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
5193 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
5194 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5195 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
5196 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5197 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
5198 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5199
5200 if (BNXT_PF(bp)) {
5201 struct bnxt_pf_info *pf = &bp->pf;
5202
5203 pf->vf_resv_strategy =
5204 le16_to_cpu(resp->vf_reservation_strategy);
5205 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
5206 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
5207 }
5208 hwrm_func_resc_qcaps_exit:
5209 mutex_unlock(&bp->hwrm_cmd_lock);
5210 return rc;
5211 }
5212
5213 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
5214 {
5215 int rc = 0;
5216 struct hwrm_func_qcaps_input req = {0};
5217 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5218 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5219 u32 flags;
5220
5221 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
5222 req.fid = cpu_to_le16(0xffff);
5223
5224 mutex_lock(&bp->hwrm_cmd_lock);
5225 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5226 if (rc)
5227 goto hwrm_func_qcaps_exit;
5228
5229 flags = le32_to_cpu(resp->flags);
5230 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
5231 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
5232 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
5233 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
5234
5235 bp->tx_push_thresh = 0;
5236 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
5237 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
5238
5239 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5240 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5241 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5242 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5243 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
5244 if (!hw_resc->max_hw_ring_grps)
5245 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
5246 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5247 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5248 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5249
5250 if (BNXT_PF(bp)) {
5251 struct bnxt_pf_info *pf = &bp->pf;
5252
5253 pf->fw_fid = le16_to_cpu(resp->fid);
5254 pf->port_id = le16_to_cpu(resp->port_id);
5255 bp->dev->dev_port = pf->port_id;
5256 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
5257 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
5258 pf->max_vfs = le16_to_cpu(resp->max_vfs);
5259 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
5260 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
5261 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
5262 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
5263 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
5264 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
5265 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
5266 bp->flags |= BNXT_FLAG_WOL_CAP;
5267 } else {
5268 #ifdef CONFIG_BNXT_SRIOV
5269 struct bnxt_vf_info *vf = &bp->vf;
5270
5271 vf->fw_fid = le16_to_cpu(resp->fid);
5272 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
5273 #endif
5274 }
5275
5276 hwrm_func_qcaps_exit:
5277 mutex_unlock(&bp->hwrm_cmd_lock);
5278 return rc;
5279 }
5280
5281 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
5282 {
5283 int rc;
5284
5285 rc = __bnxt_hwrm_func_qcaps(bp);
5286 if (rc)
5287 return rc;
5288 if (bp->hwrm_spec_code >= 0x10803) {
5289 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
5290 if (!rc)
5291 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
5292 }
5293 return 0;
5294 }
5295
5296 static int bnxt_hwrm_func_reset(struct bnxt *bp)
5297 {
5298 struct hwrm_func_reset_input req = {0};
5299
5300 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
5301 req.enables = 0;
5302
5303 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
5304 }
5305
5306 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
5307 {
5308 int rc = 0;
5309 struct hwrm_queue_qportcfg_input req = {0};
5310 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
5311 u8 i, j, *qptr;
5312 bool no_rdma;
5313
5314 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
5315
5316 mutex_lock(&bp->hwrm_cmd_lock);
5317 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5318 if (rc)
5319 goto qportcfg_exit;
5320
5321 if (!resp->max_configurable_queues) {
5322 rc = -EINVAL;
5323 goto qportcfg_exit;
5324 }
5325 bp->max_tc = resp->max_configurable_queues;
5326 bp->max_lltc = resp->max_configurable_lossless_queues;
5327 if (bp->max_tc > BNXT_MAX_QUEUE)
5328 bp->max_tc = BNXT_MAX_QUEUE;
5329
5330 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
5331 qptr = &resp->queue_id0;
5332 for (i = 0, j = 0; i < bp->max_tc; i++) {
5333 bp->q_info[j].queue_id = *qptr++;
5334 bp->q_info[j].queue_profile = *qptr++;
5335 bp->tc_to_qidx[j] = j;
5336 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
5337 (no_rdma && BNXT_PF(bp)))
5338 j++;
5339 }
5340 bp->max_tc = max_t(u8, j, 1);
5341
5342 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
5343 bp->max_tc = 1;
5344
5345 if (bp->max_lltc > bp->max_tc)
5346 bp->max_lltc = bp->max_tc;
5347
5348 qportcfg_exit:
5349 mutex_unlock(&bp->hwrm_cmd_lock);
5350 return rc;
5351 }
5352
5353 static int bnxt_hwrm_ver_get(struct bnxt *bp)
5354 {
5355 int rc;
5356 struct hwrm_ver_get_input req = {0};
5357 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
5358 u32 dev_caps_cfg;
5359
5360 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
5361 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
5362 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
5363 req.hwrm_intf_min = HWRM_VERSION_MINOR;
5364 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
5365 mutex_lock(&bp->hwrm_cmd_lock);
5366 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5367 if (rc)
5368 goto hwrm_ver_get_exit;
5369
5370 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
5371
5372 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
5373 resp->hwrm_intf_min_8b << 8 |
5374 resp->hwrm_intf_upd_8b;
5375 if (resp->hwrm_intf_maj_8b < 1) {
5376 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
5377 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
5378 resp->hwrm_intf_upd_8b);
5379 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
5380 }
5381 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
5382 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
5383 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
5384
5385 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
5386 if (!bp->hwrm_cmd_timeout)
5387 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
5388
5389 if (resp->hwrm_intf_maj_8b >= 1)
5390 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
5391
5392 bp->chip_num = le16_to_cpu(resp->chip_num);
5393 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
5394 !resp->chip_metal)
5395 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
5396
5397 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
5398 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
5399 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
5400 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
5401
5402 hwrm_ver_get_exit:
5403 mutex_unlock(&bp->hwrm_cmd_lock);
5404 return rc;
5405 }
5406
5407 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
5408 {
5409 struct hwrm_fw_set_time_input req = {0};
5410 struct tm tm;
5411 time64_t now = ktime_get_real_seconds();
5412
5413 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
5414 bp->hwrm_spec_code < 0x10400)
5415 return -EOPNOTSUPP;
5416
5417 time64_to_tm(now, 0, &tm);
5418 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
5419 req.year = cpu_to_le16(1900 + tm.tm_year);
5420 req.month = 1 + tm.tm_mon;
5421 req.day = tm.tm_mday;
5422 req.hour = tm.tm_hour;
5423 req.minute = tm.tm_min;
5424 req.second = tm.tm_sec;
5425 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5426 }
5427
5428 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
5429 {
5430 int rc;
5431 struct bnxt_pf_info *pf = &bp->pf;
5432 struct hwrm_port_qstats_input req = {0};
5433
5434 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
5435 return 0;
5436
5437 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
5438 req.port_id = cpu_to_le16(pf->port_id);
5439 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
5440 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
5441 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5442 return rc;
5443 }
5444
5445 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
5446 {
5447 struct hwrm_port_qstats_ext_input req = {0};
5448 struct bnxt_pf_info *pf = &bp->pf;
5449
5450 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5451 return 0;
5452
5453 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
5454 req.port_id = cpu_to_le16(pf->port_id);
5455 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
5456 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
5457 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5458 }
5459
5460 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
5461 {
5462 if (bp->vxlan_port_cnt) {
5463 bnxt_hwrm_tunnel_dst_port_free(
5464 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5465 }
5466 bp->vxlan_port_cnt = 0;
5467 if (bp->nge_port_cnt) {
5468 bnxt_hwrm_tunnel_dst_port_free(
5469 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5470 }
5471 bp->nge_port_cnt = 0;
5472 }
5473
5474 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
5475 {
5476 int rc, i;
5477 u32 tpa_flags = 0;
5478
5479 if (set_tpa)
5480 tpa_flags = bp->flags & BNXT_FLAG_TPA;
5481 for (i = 0; i < bp->nr_vnics; i++) {
5482 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
5483 if (rc) {
5484 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
5485 i, rc);
5486 return rc;
5487 }
5488 }
5489 return 0;
5490 }
5491
5492 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
5493 {
5494 int i;
5495
5496 for (i = 0; i < bp->nr_vnics; i++)
5497 bnxt_hwrm_vnic_set_rss(bp, i, false);
5498 }
5499
5500 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
5501 bool irq_re_init)
5502 {
5503 if (bp->vnic_info) {
5504 bnxt_hwrm_clear_vnic_filter(bp);
5505 /* clear all RSS setting before free vnic ctx */
5506 bnxt_hwrm_clear_vnic_rss(bp);
5507 bnxt_hwrm_vnic_ctx_free(bp);
5508 /* before free the vnic, undo the vnic tpa settings */
5509 if (bp->flags & BNXT_FLAG_TPA)
5510 bnxt_set_tpa(bp, false);
5511 bnxt_hwrm_vnic_free(bp);
5512 }
5513 bnxt_hwrm_ring_free(bp, close_path);
5514 bnxt_hwrm_ring_grp_free(bp);
5515 if (irq_re_init) {
5516 bnxt_hwrm_stat_ctx_free(bp);
5517 bnxt_hwrm_free_tunnel_ports(bp);
5518 }
5519 }
5520
5521 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5522 {
5523 struct hwrm_func_cfg_input req = {0};
5524 int rc;
5525
5526 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5527 req.fid = cpu_to_le16(0xffff);
5528 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5529 if (br_mode == BRIDGE_MODE_VEB)
5530 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5531 else if (br_mode == BRIDGE_MODE_VEPA)
5532 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5533 else
5534 return -EINVAL;
5535 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5536 if (rc)
5537 rc = -EIO;
5538 return rc;
5539 }
5540
5541 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
5542 {
5543 struct hwrm_func_cfg_input req = {0};
5544 int rc;
5545
5546 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
5547 return 0;
5548
5549 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5550 req.fid = cpu_to_le16(0xffff);
5551 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
5552 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
5553 if (size == 128)
5554 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
5555
5556 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5557 if (rc)
5558 rc = -EIO;
5559 return rc;
5560 }
5561
5562 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5563 {
5564 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5565 int rc;
5566
5567 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5568 goto skip_rss_ctx;
5569
5570 /* allocate context for vnic */
5571 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
5572 if (rc) {
5573 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5574 vnic_id, rc);
5575 goto vnic_setup_err;
5576 }
5577 bp->rsscos_nr_ctxs++;
5578
5579 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5580 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5581 if (rc) {
5582 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5583 vnic_id, rc);
5584 goto vnic_setup_err;
5585 }
5586 bp->rsscos_nr_ctxs++;
5587 }
5588
5589 skip_rss_ctx:
5590 /* configure default vnic, ring grp */
5591 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5592 if (rc) {
5593 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5594 vnic_id, rc);
5595 goto vnic_setup_err;
5596 }
5597
5598 /* Enable RSS hashing on vnic */
5599 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5600 if (rc) {
5601 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5602 vnic_id, rc);
5603 goto vnic_setup_err;
5604 }
5605
5606 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5607 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5608 if (rc) {
5609 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5610 vnic_id, rc);
5611 }
5612 }
5613
5614 vnic_setup_err:
5615 return rc;
5616 }
5617
5618 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5619 {
5620 #ifdef CONFIG_RFS_ACCEL
5621 int i, rc = 0;
5622
5623 for (i = 0; i < bp->rx_nr_rings; i++) {
5624 struct bnxt_vnic_info *vnic;
5625 u16 vnic_id = i + 1;
5626 u16 ring_id = i;
5627
5628 if (vnic_id >= bp->nr_vnics)
5629 break;
5630
5631 vnic = &bp->vnic_info[vnic_id];
5632 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5633 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5634 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
5635 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
5636 if (rc) {
5637 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5638 vnic_id, rc);
5639 break;
5640 }
5641 rc = bnxt_setup_vnic(bp, vnic_id);
5642 if (rc)
5643 break;
5644 }
5645 return rc;
5646 #else
5647 return 0;
5648 #endif
5649 }
5650
5651 /* Allow PF and VF with default VLAN to be in promiscuous mode */
5652 static bool bnxt_promisc_ok(struct bnxt *bp)
5653 {
5654 #ifdef CONFIG_BNXT_SRIOV
5655 if (BNXT_VF(bp) && !bp->vf.vlan)
5656 return false;
5657 #endif
5658 return true;
5659 }
5660
5661 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5662 {
5663 unsigned int rc = 0;
5664
5665 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5666 if (rc) {
5667 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5668 rc);
5669 return rc;
5670 }
5671
5672 rc = bnxt_hwrm_vnic_cfg(bp, 1);
5673 if (rc) {
5674 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5675 rc);
5676 return rc;
5677 }
5678 return rc;
5679 }
5680
5681 static int bnxt_cfg_rx_mode(struct bnxt *);
5682 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
5683
5684 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5685 {
5686 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5687 int rc = 0;
5688 unsigned int rx_nr_rings = bp->rx_nr_rings;
5689
5690 if (irq_re_init) {
5691 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5692 if (rc) {
5693 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5694 rc);
5695 goto err_out;
5696 }
5697 }
5698
5699 rc = bnxt_hwrm_ring_alloc(bp);
5700 if (rc) {
5701 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5702 goto err_out;
5703 }
5704
5705 rc = bnxt_hwrm_ring_grp_alloc(bp);
5706 if (rc) {
5707 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5708 goto err_out;
5709 }
5710
5711 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5712 rx_nr_rings--;
5713
5714 /* default vnic 0 */
5715 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
5716 if (rc) {
5717 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5718 goto err_out;
5719 }
5720
5721 rc = bnxt_setup_vnic(bp, 0);
5722 if (rc)
5723 goto err_out;
5724
5725 if (bp->flags & BNXT_FLAG_RFS) {
5726 rc = bnxt_alloc_rfs_vnics(bp);
5727 if (rc)
5728 goto err_out;
5729 }
5730
5731 if (bp->flags & BNXT_FLAG_TPA) {
5732 rc = bnxt_set_tpa(bp, true);
5733 if (rc)
5734 goto err_out;
5735 }
5736
5737 if (BNXT_VF(bp))
5738 bnxt_update_vf_mac(bp);
5739
5740 /* Filter for default vnic 0 */
5741 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5742 if (rc) {
5743 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5744 goto err_out;
5745 }
5746 vnic->uc_filter_count = 1;
5747
5748 vnic->rx_mask = 0;
5749 if (bp->dev->flags & IFF_BROADCAST)
5750 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
5751
5752 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5753 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5754
5755 if (bp->dev->flags & IFF_ALLMULTI) {
5756 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5757 vnic->mc_list_count = 0;
5758 } else {
5759 u32 mask = 0;
5760
5761 bnxt_mc_list_updated(bp, &mask);
5762 vnic->rx_mask |= mask;
5763 }
5764
5765 rc = bnxt_cfg_rx_mode(bp);
5766 if (rc)
5767 goto err_out;
5768
5769 rc = bnxt_hwrm_set_coal(bp);
5770 if (rc)
5771 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5772 rc);
5773
5774 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5775 rc = bnxt_setup_nitroa0_vnic(bp);
5776 if (rc)
5777 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5778 rc);
5779 }
5780
5781 if (BNXT_VF(bp)) {
5782 bnxt_hwrm_func_qcfg(bp);
5783 netdev_update_features(bp->dev);
5784 }
5785
5786 return 0;
5787
5788 err_out:
5789 bnxt_hwrm_resource_free(bp, 0, true);
5790
5791 return rc;
5792 }
5793
5794 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5795 {
5796 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5797 return 0;
5798 }
5799
5800 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5801 {
5802 bnxt_init_cp_rings(bp);
5803 bnxt_init_rx_rings(bp);
5804 bnxt_init_tx_rings(bp);
5805 bnxt_init_ring_grps(bp, irq_re_init);
5806 bnxt_init_vnics(bp);
5807
5808 return bnxt_init_chip(bp, irq_re_init);
5809 }
5810
5811 static int bnxt_set_real_num_queues(struct bnxt *bp)
5812 {
5813 int rc;
5814 struct net_device *dev = bp->dev;
5815
5816 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5817 bp->tx_nr_rings_xdp);
5818 if (rc)
5819 return rc;
5820
5821 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5822 if (rc)
5823 return rc;
5824
5825 #ifdef CONFIG_RFS_ACCEL
5826 if (bp->flags & BNXT_FLAG_RFS)
5827 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5828 #endif
5829
5830 return rc;
5831 }
5832
5833 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5834 bool shared)
5835 {
5836 int _rx = *rx, _tx = *tx;
5837
5838 if (shared) {
5839 *rx = min_t(int, _rx, max);
5840 *tx = min_t(int, _tx, max);
5841 } else {
5842 if (max < 2)
5843 return -ENOMEM;
5844
5845 while (_rx + _tx > max) {
5846 if (_rx > _tx && _rx > 1)
5847 _rx--;
5848 else if (_tx > 1)
5849 _tx--;
5850 }
5851 *rx = _rx;
5852 *tx = _tx;
5853 }
5854 return 0;
5855 }
5856
5857 static void bnxt_setup_msix(struct bnxt *bp)
5858 {
5859 const int len = sizeof(bp->irq_tbl[0].name);
5860 struct net_device *dev = bp->dev;
5861 int tcs, i;
5862
5863 tcs = netdev_get_num_tc(dev);
5864 if (tcs) {
5865 int i, off, count;
5866
5867 for (i = 0; i < tcs; i++) {
5868 count = bp->tx_nr_rings_per_tc;
5869 off = i * count;
5870 netdev_set_tc_queue(dev, i, count, off);
5871 }
5872 }
5873
5874 for (i = 0; i < bp->cp_nr_rings; i++) {
5875 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
5876 char *attr;
5877
5878 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5879 attr = "TxRx";
5880 else if (i < bp->rx_nr_rings)
5881 attr = "rx";
5882 else
5883 attr = "tx";
5884
5885 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
5886 attr, i);
5887 bp->irq_tbl[map_idx].handler = bnxt_msix;
5888 }
5889 }
5890
5891 static void bnxt_setup_inta(struct bnxt *bp)
5892 {
5893 const int len = sizeof(bp->irq_tbl[0].name);
5894
5895 if (netdev_get_num_tc(bp->dev))
5896 netdev_reset_tc(bp->dev);
5897
5898 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5899 0);
5900 bp->irq_tbl[0].handler = bnxt_inta;
5901 }
5902
5903 static int bnxt_setup_int_mode(struct bnxt *bp)
5904 {
5905 int rc;
5906
5907 if (bp->flags & BNXT_FLAG_USING_MSIX)
5908 bnxt_setup_msix(bp);
5909 else
5910 bnxt_setup_inta(bp);
5911
5912 rc = bnxt_set_real_num_queues(bp);
5913 return rc;
5914 }
5915
5916 #ifdef CONFIG_RFS_ACCEL
5917 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5918 {
5919 return bp->hw_resc.max_rsscos_ctxs;
5920 }
5921
5922 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5923 {
5924 return bp->hw_resc.max_vnics;
5925 }
5926 #endif
5927
5928 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5929 {
5930 return bp->hw_resc.max_stat_ctxs;
5931 }
5932
5933 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5934 {
5935 bp->hw_resc.max_stat_ctxs = max;
5936 }
5937
5938 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5939 {
5940 return bp->hw_resc.max_cp_rings;
5941 }
5942
5943 unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
5944 {
5945 return bp->hw_resc.max_cp_rings - bnxt_get_ulp_msix_num(bp);
5946 }
5947
5948 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5949 {
5950 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5951
5952 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
5953 }
5954
5955 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5956 {
5957 bp->hw_resc.max_irqs = max_irqs;
5958 }
5959
5960 int bnxt_get_avail_msix(struct bnxt *bp, int num)
5961 {
5962 int max_cp = bnxt_get_max_func_cp_rings(bp);
5963 int max_irq = bnxt_get_max_func_irqs(bp);
5964 int total_req = bp->cp_nr_rings + num;
5965 int max_idx, avail_msix;
5966
5967 max_idx = min_t(int, bp->total_irqs, max_cp);
5968 avail_msix = max_idx - bp->cp_nr_rings;
5969 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
5970 return avail_msix;
5971
5972 if (max_irq < total_req) {
5973 num = max_irq - bp->cp_nr_rings;
5974 if (num <= 0)
5975 return 0;
5976 }
5977 return num;
5978 }
5979
5980 static int bnxt_get_num_msix(struct bnxt *bp)
5981 {
5982 if (!BNXT_NEW_RM(bp))
5983 return bnxt_get_max_func_irqs(bp);
5984
5985 return bnxt_cp_rings_in_use(bp);
5986 }
5987
5988 static int bnxt_init_msix(struct bnxt *bp)
5989 {
5990 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
5991 struct msix_entry *msix_ent;
5992
5993 total_vecs = bnxt_get_num_msix(bp);
5994 max = bnxt_get_max_func_irqs(bp);
5995 if (total_vecs > max)
5996 total_vecs = max;
5997
5998 if (!total_vecs)
5999 return 0;
6000
6001 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
6002 if (!msix_ent)
6003 return -ENOMEM;
6004
6005 for (i = 0; i < total_vecs; i++) {
6006 msix_ent[i].entry = i;
6007 msix_ent[i].vector = 0;
6008 }
6009
6010 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
6011 min = 2;
6012
6013 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
6014 ulp_msix = bnxt_get_ulp_msix_num(bp);
6015 if (total_vecs < 0 || total_vecs < ulp_msix) {
6016 rc = -ENODEV;
6017 goto msix_setup_exit;
6018 }
6019
6020 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
6021 if (bp->irq_tbl) {
6022 for (i = 0; i < total_vecs; i++)
6023 bp->irq_tbl[i].vector = msix_ent[i].vector;
6024
6025 bp->total_irqs = total_vecs;
6026 /* Trim rings based upon num of vectors allocated */
6027 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
6028 total_vecs - ulp_msix, min == 1);
6029 if (rc)
6030 goto msix_setup_exit;
6031
6032 bp->cp_nr_rings = (min == 1) ?
6033 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6034 bp->tx_nr_rings + bp->rx_nr_rings;
6035
6036 } else {
6037 rc = -ENOMEM;
6038 goto msix_setup_exit;
6039 }
6040 bp->flags |= BNXT_FLAG_USING_MSIX;
6041 kfree(msix_ent);
6042 return 0;
6043
6044 msix_setup_exit:
6045 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
6046 kfree(bp->irq_tbl);
6047 bp->irq_tbl = NULL;
6048 pci_disable_msix(bp->pdev);
6049 kfree(msix_ent);
6050 return rc;
6051 }
6052
6053 static int bnxt_init_inta(struct bnxt *bp)
6054 {
6055 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
6056 if (!bp->irq_tbl)
6057 return -ENOMEM;
6058
6059 bp->total_irqs = 1;
6060 bp->rx_nr_rings = 1;
6061 bp->tx_nr_rings = 1;
6062 bp->cp_nr_rings = 1;
6063 bp->flags |= BNXT_FLAG_SHARED_RINGS;
6064 bp->irq_tbl[0].vector = bp->pdev->irq;
6065 return 0;
6066 }
6067
6068 static int bnxt_init_int_mode(struct bnxt *bp)
6069 {
6070 int rc = 0;
6071
6072 if (bp->flags & BNXT_FLAG_MSIX_CAP)
6073 rc = bnxt_init_msix(bp);
6074
6075 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
6076 /* fallback to INTA */
6077 rc = bnxt_init_inta(bp);
6078 }
6079 return rc;
6080 }
6081
6082 static void bnxt_clear_int_mode(struct bnxt *bp)
6083 {
6084 if (bp->flags & BNXT_FLAG_USING_MSIX)
6085 pci_disable_msix(bp->pdev);
6086
6087 kfree(bp->irq_tbl);
6088 bp->irq_tbl = NULL;
6089 bp->flags &= ~BNXT_FLAG_USING_MSIX;
6090 }
6091
6092 int bnxt_reserve_rings(struct bnxt *bp)
6093 {
6094 int tcs = netdev_get_num_tc(bp->dev);
6095 bool reinit_irq = false;
6096 int rc;
6097
6098 if (!bnxt_need_reserve_rings(bp))
6099 return 0;
6100
6101 if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
6102 bnxt_ulp_irq_stop(bp);
6103 bnxt_clear_int_mode(bp);
6104 reinit_irq = true;
6105 }
6106 rc = __bnxt_reserve_rings(bp);
6107 if (reinit_irq) {
6108 if (!rc)
6109 rc = bnxt_init_int_mode(bp);
6110 bnxt_ulp_irq_restart(bp, rc);
6111 }
6112 if (rc) {
6113 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
6114 return rc;
6115 }
6116 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
6117 netdev_err(bp->dev, "tx ring reservation failure\n");
6118 netdev_reset_tc(bp->dev);
6119 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
6120 return -ENOMEM;
6121 }
6122 bp->num_stat_ctxs = bp->cp_nr_rings;
6123 return 0;
6124 }
6125
6126 static void bnxt_free_irq(struct bnxt *bp)
6127 {
6128 struct bnxt_irq *irq;
6129 int i;
6130
6131 #ifdef CONFIG_RFS_ACCEL
6132 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
6133 bp->dev->rx_cpu_rmap = NULL;
6134 #endif
6135 if (!bp->irq_tbl || !bp->bnapi)
6136 return;
6137
6138 for (i = 0; i < bp->cp_nr_rings; i++) {
6139 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6140
6141 irq = &bp->irq_tbl[map_idx];
6142 if (irq->requested) {
6143 if (irq->have_cpumask) {
6144 irq_set_affinity_hint(irq->vector, NULL);
6145 free_cpumask_var(irq->cpu_mask);
6146 irq->have_cpumask = 0;
6147 }
6148 free_irq(irq->vector, bp->bnapi[i]);
6149 }
6150
6151 irq->requested = 0;
6152 }
6153 }
6154
6155 static int bnxt_request_irq(struct bnxt *bp)
6156 {
6157 int i, j, rc = 0;
6158 unsigned long flags = 0;
6159 #ifdef CONFIG_RFS_ACCEL
6160 struct cpu_rmap *rmap;
6161 #endif
6162
6163 rc = bnxt_setup_int_mode(bp);
6164 if (rc) {
6165 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6166 rc);
6167 return rc;
6168 }
6169 #ifdef CONFIG_RFS_ACCEL
6170 rmap = bp->dev->rx_cpu_rmap;
6171 #endif
6172 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
6173 flags = IRQF_SHARED;
6174
6175 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
6176 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6177 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
6178
6179 #ifdef CONFIG_RFS_ACCEL
6180 if (rmap && bp->bnapi[i]->rx_ring) {
6181 rc = irq_cpu_rmap_add(rmap, irq->vector);
6182 if (rc)
6183 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
6184 j);
6185 j++;
6186 }
6187 #endif
6188 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6189 bp->bnapi[i]);
6190 if (rc)
6191 break;
6192
6193 irq->requested = 1;
6194
6195 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
6196 int numa_node = dev_to_node(&bp->pdev->dev);
6197
6198 irq->have_cpumask = 1;
6199 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
6200 irq->cpu_mask);
6201 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
6202 if (rc) {
6203 netdev_warn(bp->dev,
6204 "Set affinity failed, IRQ = %d\n",
6205 irq->vector);
6206 break;
6207 }
6208 }
6209 }
6210 return rc;
6211 }
6212
6213 static void bnxt_del_napi(struct bnxt *bp)
6214 {
6215 int i;
6216
6217 if (!bp->bnapi)
6218 return;
6219
6220 for (i = 0; i < bp->cp_nr_rings; i++) {
6221 struct bnxt_napi *bnapi = bp->bnapi[i];
6222
6223 napi_hash_del(&bnapi->napi);
6224 netif_napi_del(&bnapi->napi);
6225 }
6226 /* We called napi_hash_del() before netif_napi_del(), we need
6227 * to respect an RCU grace period before freeing napi structures.
6228 */
6229 synchronize_net();
6230 }
6231
6232 static void bnxt_init_napi(struct bnxt *bp)
6233 {
6234 int i;
6235 unsigned int cp_nr_rings = bp->cp_nr_rings;
6236 struct bnxt_napi *bnapi;
6237
6238 if (bp->flags & BNXT_FLAG_USING_MSIX) {
6239 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6240 cp_nr_rings--;
6241 for (i = 0; i < cp_nr_rings; i++) {
6242 bnapi = bp->bnapi[i];
6243 netif_napi_add(bp->dev, &bnapi->napi,
6244 bnxt_poll, 64);
6245 }
6246 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6247 bnapi = bp->bnapi[cp_nr_rings];
6248 netif_napi_add(bp->dev, &bnapi->napi,
6249 bnxt_poll_nitroa0, 64);
6250 }
6251 } else {
6252 bnapi = bp->bnapi[0];
6253 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
6254 }
6255 }
6256
6257 static void bnxt_disable_napi(struct bnxt *bp)
6258 {
6259 int i;
6260
6261 if (!bp->bnapi)
6262 return;
6263
6264 for (i = 0; i < bp->cp_nr_rings; i++) {
6265 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6266
6267 if (bp->bnapi[i]->rx_ring)
6268 cancel_work_sync(&cpr->dim.work);
6269
6270 napi_disable(&bp->bnapi[i]->napi);
6271 }
6272 }
6273
6274 static void bnxt_enable_napi(struct bnxt *bp)
6275 {
6276 int i;
6277
6278 for (i = 0; i < bp->cp_nr_rings; i++) {
6279 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6280 bp->bnapi[i]->in_reset = false;
6281
6282 if (bp->bnapi[i]->rx_ring) {
6283 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
6284 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
6285 }
6286 napi_enable(&bp->bnapi[i]->napi);
6287 }
6288 }
6289
6290 void bnxt_tx_disable(struct bnxt *bp)
6291 {
6292 int i;
6293 struct bnxt_tx_ring_info *txr;
6294
6295 if (bp->tx_ring) {
6296 for (i = 0; i < bp->tx_nr_rings; i++) {
6297 txr = &bp->tx_ring[i];
6298 txr->dev_state = BNXT_DEV_STATE_CLOSING;
6299 }
6300 }
6301 /* Stop all TX queues */
6302 netif_tx_disable(bp->dev);
6303 netif_carrier_off(bp->dev);
6304 }
6305
6306 void bnxt_tx_enable(struct bnxt *bp)
6307 {
6308 int i;
6309 struct bnxt_tx_ring_info *txr;
6310
6311 for (i = 0; i < bp->tx_nr_rings; i++) {
6312 txr = &bp->tx_ring[i];
6313 txr->dev_state = 0;
6314 }
6315 netif_tx_wake_all_queues(bp->dev);
6316 if (bp->link_info.link_up)
6317 netif_carrier_on(bp->dev);
6318 }
6319
6320 static void bnxt_report_link(struct bnxt *bp)
6321 {
6322 if (bp->link_info.link_up) {
6323 const char *duplex;
6324 const char *flow_ctrl;
6325 u32 speed;
6326 u16 fec;
6327
6328 netif_carrier_on(bp->dev);
6329 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
6330 duplex = "full";
6331 else
6332 duplex = "half";
6333 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
6334 flow_ctrl = "ON - receive & transmit";
6335 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
6336 flow_ctrl = "ON - transmit";
6337 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
6338 flow_ctrl = "ON - receive";
6339 else
6340 flow_ctrl = "none";
6341 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
6342 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
6343 speed, duplex, flow_ctrl);
6344 if (bp->flags & BNXT_FLAG_EEE_CAP)
6345 netdev_info(bp->dev, "EEE is %s\n",
6346 bp->eee.eee_active ? "active" :
6347 "not active");
6348 fec = bp->link_info.fec_cfg;
6349 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
6350 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
6351 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
6352 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
6353 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
6354 } else {
6355 netif_carrier_off(bp->dev);
6356 netdev_err(bp->dev, "NIC Link is Down\n");
6357 }
6358 }
6359
6360 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
6361 {
6362 int rc = 0;
6363 struct hwrm_port_phy_qcaps_input req = {0};
6364 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6365 struct bnxt_link_info *link_info = &bp->link_info;
6366
6367 if (bp->hwrm_spec_code < 0x10201)
6368 return 0;
6369
6370 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
6371
6372 mutex_lock(&bp->hwrm_cmd_lock);
6373 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6374 if (rc)
6375 goto hwrm_phy_qcaps_exit;
6376
6377 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
6378 struct ethtool_eee *eee = &bp->eee;
6379 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
6380
6381 bp->flags |= BNXT_FLAG_EEE_CAP;
6382 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6383 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
6384 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
6385 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
6386 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
6387 }
6388 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
6389 if (bp->test_info)
6390 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
6391 }
6392 if (resp->supported_speeds_auto_mode)
6393 link_info->support_auto_speeds =
6394 le16_to_cpu(resp->supported_speeds_auto_mode);
6395
6396 bp->port_count = resp->port_cnt;
6397
6398 hwrm_phy_qcaps_exit:
6399 mutex_unlock(&bp->hwrm_cmd_lock);
6400 return rc;
6401 }
6402
6403 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
6404 {
6405 int rc = 0;
6406 struct bnxt_link_info *link_info = &bp->link_info;
6407 struct hwrm_port_phy_qcfg_input req = {0};
6408 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6409 u8 link_up = link_info->link_up;
6410 u16 diff;
6411
6412 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
6413
6414 mutex_lock(&bp->hwrm_cmd_lock);
6415 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6416 if (rc) {
6417 mutex_unlock(&bp->hwrm_cmd_lock);
6418 return rc;
6419 }
6420
6421 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
6422 link_info->phy_link_status = resp->link;
6423 link_info->duplex = resp->duplex_cfg;
6424 if (bp->hwrm_spec_code >= 0x10800)
6425 link_info->duplex = resp->duplex_state;
6426 link_info->pause = resp->pause;
6427 link_info->auto_mode = resp->auto_mode;
6428 link_info->auto_pause_setting = resp->auto_pause;
6429 link_info->lp_pause = resp->link_partner_adv_pause;
6430 link_info->force_pause_setting = resp->force_pause;
6431 link_info->duplex_setting = resp->duplex_cfg;
6432 if (link_info->phy_link_status == BNXT_LINK_LINK)
6433 link_info->link_speed = le16_to_cpu(resp->link_speed);
6434 else
6435 link_info->link_speed = 0;
6436 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
6437 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
6438 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
6439 link_info->lp_auto_link_speeds =
6440 le16_to_cpu(resp->link_partner_adv_speeds);
6441 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
6442 link_info->phy_ver[0] = resp->phy_maj;
6443 link_info->phy_ver[1] = resp->phy_min;
6444 link_info->phy_ver[2] = resp->phy_bld;
6445 link_info->media_type = resp->media_type;
6446 link_info->phy_type = resp->phy_type;
6447 link_info->transceiver = resp->xcvr_pkg_type;
6448 link_info->phy_addr = resp->eee_config_phy_addr &
6449 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
6450 link_info->module_status = resp->module_status;
6451
6452 if (bp->flags & BNXT_FLAG_EEE_CAP) {
6453 struct ethtool_eee *eee = &bp->eee;
6454 u16 fw_speeds;
6455
6456 eee->eee_active = 0;
6457 if (resp->eee_config_phy_addr &
6458 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
6459 eee->eee_active = 1;
6460 fw_speeds = le16_to_cpu(
6461 resp->link_partner_adv_eee_link_speed_mask);
6462 eee->lp_advertised =
6463 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6464 }
6465
6466 /* Pull initial EEE config */
6467 if (!chng_link_state) {
6468 if (resp->eee_config_phy_addr &
6469 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
6470 eee->eee_enabled = 1;
6471
6472 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
6473 eee->advertised =
6474 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6475
6476 if (resp->eee_config_phy_addr &
6477 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
6478 __le32 tmr;
6479
6480 eee->tx_lpi_enabled = 1;
6481 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
6482 eee->tx_lpi_timer = le32_to_cpu(tmr) &
6483 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
6484 }
6485 }
6486 }
6487
6488 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
6489 if (bp->hwrm_spec_code >= 0x10504)
6490 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
6491
6492 /* TODO: need to add more logic to report VF link */
6493 if (chng_link_state) {
6494 if (link_info->phy_link_status == BNXT_LINK_LINK)
6495 link_info->link_up = 1;
6496 else
6497 link_info->link_up = 0;
6498 if (link_up != link_info->link_up)
6499 bnxt_report_link(bp);
6500 } else {
6501 /* alwasy link down if not require to update link state */
6502 link_info->link_up = 0;
6503 }
6504 mutex_unlock(&bp->hwrm_cmd_lock);
6505
6506 if (!BNXT_SINGLE_PF(bp))
6507 return 0;
6508
6509 diff = link_info->support_auto_speeds ^ link_info->advertising;
6510 if ((link_info->support_auto_speeds | diff) !=
6511 link_info->support_auto_speeds) {
6512 /* An advertised speed is no longer supported, so we need to
6513 * update the advertisement settings. Caller holds RTNL
6514 * so we can modify link settings.
6515 */
6516 link_info->advertising = link_info->support_auto_speeds;
6517 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
6518 bnxt_hwrm_set_link_setting(bp, true, false);
6519 }
6520 return 0;
6521 }
6522
6523 static void bnxt_get_port_module_status(struct bnxt *bp)
6524 {
6525 struct bnxt_link_info *link_info = &bp->link_info;
6526 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
6527 u8 module_status;
6528
6529 if (bnxt_update_link(bp, true))
6530 return;
6531
6532 module_status = link_info->module_status;
6533 switch (module_status) {
6534 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
6535 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
6536 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
6537 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
6538 bp->pf.port_id);
6539 if (bp->hwrm_spec_code >= 0x10201) {
6540 netdev_warn(bp->dev, "Module part number %s\n",
6541 resp->phy_vendor_partnumber);
6542 }
6543 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
6544 netdev_warn(bp->dev, "TX is disabled\n");
6545 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
6546 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
6547 }
6548 }
6549
6550 static void
6551 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
6552 {
6553 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
6554 if (bp->hwrm_spec_code >= 0x10201)
6555 req->auto_pause =
6556 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
6557 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6558 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
6559 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6560 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
6561 req->enables |=
6562 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6563 } else {
6564 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6565 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
6566 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6567 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
6568 req->enables |=
6569 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
6570 if (bp->hwrm_spec_code >= 0x10201) {
6571 req->auto_pause = req->force_pause;
6572 req->enables |= cpu_to_le32(
6573 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6574 }
6575 }
6576 }
6577
6578 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
6579 struct hwrm_port_phy_cfg_input *req)
6580 {
6581 u8 autoneg = bp->link_info.autoneg;
6582 u16 fw_link_speed = bp->link_info.req_link_speed;
6583 u16 advertising = bp->link_info.advertising;
6584
6585 if (autoneg & BNXT_AUTONEG_SPEED) {
6586 req->auto_mode |=
6587 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
6588
6589 req->enables |= cpu_to_le32(
6590 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6591 req->auto_link_speed_mask = cpu_to_le16(advertising);
6592
6593 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6594 req->flags |=
6595 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6596 } else {
6597 req->force_link_speed = cpu_to_le16(fw_link_speed);
6598 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6599 }
6600
6601 /* tell chimp that the setting takes effect immediately */
6602 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6603 }
6604
6605 int bnxt_hwrm_set_pause(struct bnxt *bp)
6606 {
6607 struct hwrm_port_phy_cfg_input req = {0};
6608 int rc;
6609
6610 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6611 bnxt_hwrm_set_pause_common(bp, &req);
6612
6613 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6614 bp->link_info.force_link_chng)
6615 bnxt_hwrm_set_link_common(bp, &req);
6616
6617 mutex_lock(&bp->hwrm_cmd_lock);
6618 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6619 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6620 /* since changing of pause setting doesn't trigger any link
6621 * change event, the driver needs to update the current pause
6622 * result upon successfully return of the phy_cfg command
6623 */
6624 bp->link_info.pause =
6625 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6626 bp->link_info.auto_pause_setting = 0;
6627 if (!bp->link_info.force_link_chng)
6628 bnxt_report_link(bp);
6629 }
6630 bp->link_info.force_link_chng = false;
6631 mutex_unlock(&bp->hwrm_cmd_lock);
6632 return rc;
6633 }
6634
6635 static void bnxt_hwrm_set_eee(struct bnxt *bp,
6636 struct hwrm_port_phy_cfg_input *req)
6637 {
6638 struct ethtool_eee *eee = &bp->eee;
6639
6640 if (eee->eee_enabled) {
6641 u16 eee_speeds;
6642 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6643
6644 if (eee->tx_lpi_enabled)
6645 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6646 else
6647 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6648
6649 req->flags |= cpu_to_le32(flags);
6650 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6651 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6652 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6653 } else {
6654 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6655 }
6656 }
6657
6658 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
6659 {
6660 struct hwrm_port_phy_cfg_input req = {0};
6661
6662 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6663 if (set_pause)
6664 bnxt_hwrm_set_pause_common(bp, &req);
6665
6666 bnxt_hwrm_set_link_common(bp, &req);
6667
6668 if (set_eee)
6669 bnxt_hwrm_set_eee(bp, &req);
6670 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6671 }
6672
6673 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6674 {
6675 struct hwrm_port_phy_cfg_input req = {0};
6676
6677 if (!BNXT_SINGLE_PF(bp))
6678 return 0;
6679
6680 if (pci_num_vf(bp->pdev))
6681 return 0;
6682
6683 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6684 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
6685 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6686 }
6687
6688 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
6689 {
6690 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
6691 struct hwrm_func_drv_if_change_input req = {0};
6692 bool resc_reinit = false;
6693 int rc;
6694
6695 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
6696 return 0;
6697
6698 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
6699 if (up)
6700 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
6701 mutex_lock(&bp->hwrm_cmd_lock);
6702 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6703 if (!rc && (resp->flags &
6704 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
6705 resc_reinit = true;
6706 mutex_unlock(&bp->hwrm_cmd_lock);
6707
6708 if (up && resc_reinit && BNXT_NEW_RM(bp)) {
6709 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6710
6711 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6712 hw_resc->resv_cp_rings = 0;
6713 hw_resc->resv_tx_rings = 0;
6714 hw_resc->resv_rx_rings = 0;
6715 hw_resc->resv_hw_ring_grps = 0;
6716 hw_resc->resv_vnics = 0;
6717 bp->tx_nr_rings = 0;
6718 bp->rx_nr_rings = 0;
6719 }
6720 return rc;
6721 }
6722
6723 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6724 {
6725 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6726 struct hwrm_port_led_qcaps_input req = {0};
6727 struct bnxt_pf_info *pf = &bp->pf;
6728 int rc;
6729
6730 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6731 return 0;
6732
6733 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6734 req.port_id = cpu_to_le16(pf->port_id);
6735 mutex_lock(&bp->hwrm_cmd_lock);
6736 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6737 if (rc) {
6738 mutex_unlock(&bp->hwrm_cmd_lock);
6739 return rc;
6740 }
6741 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6742 int i;
6743
6744 bp->num_leds = resp->num_leds;
6745 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6746 bp->num_leds);
6747 for (i = 0; i < bp->num_leds; i++) {
6748 struct bnxt_led_info *led = &bp->leds[i];
6749 __le16 caps = led->led_state_caps;
6750
6751 if (!led->led_group_id ||
6752 !BNXT_LED_ALT_BLINK_CAP(caps)) {
6753 bp->num_leds = 0;
6754 break;
6755 }
6756 }
6757 }
6758 mutex_unlock(&bp->hwrm_cmd_lock);
6759 return 0;
6760 }
6761
6762 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6763 {
6764 struct hwrm_wol_filter_alloc_input req = {0};
6765 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6766 int rc;
6767
6768 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6769 req.port_id = cpu_to_le16(bp->pf.port_id);
6770 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6771 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6772 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6773 mutex_lock(&bp->hwrm_cmd_lock);
6774 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6775 if (!rc)
6776 bp->wol_filter_id = resp->wol_filter_id;
6777 mutex_unlock(&bp->hwrm_cmd_lock);
6778 return rc;
6779 }
6780
6781 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6782 {
6783 struct hwrm_wol_filter_free_input req = {0};
6784 int rc;
6785
6786 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6787 req.port_id = cpu_to_le16(bp->pf.port_id);
6788 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6789 req.wol_filter_id = bp->wol_filter_id;
6790 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6791 return rc;
6792 }
6793
6794 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6795 {
6796 struct hwrm_wol_filter_qcfg_input req = {0};
6797 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6798 u16 next_handle = 0;
6799 int rc;
6800
6801 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6802 req.port_id = cpu_to_le16(bp->pf.port_id);
6803 req.handle = cpu_to_le16(handle);
6804 mutex_lock(&bp->hwrm_cmd_lock);
6805 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6806 if (!rc) {
6807 next_handle = le16_to_cpu(resp->next_handle);
6808 if (next_handle != 0) {
6809 if (resp->wol_type ==
6810 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6811 bp->wol = 1;
6812 bp->wol_filter_id = resp->wol_filter_id;
6813 }
6814 }
6815 }
6816 mutex_unlock(&bp->hwrm_cmd_lock);
6817 return next_handle;
6818 }
6819
6820 static void bnxt_get_wol_settings(struct bnxt *bp)
6821 {
6822 u16 handle = 0;
6823
6824 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6825 return;
6826
6827 do {
6828 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6829 } while (handle && handle != 0xffff);
6830 }
6831
6832 #ifdef CONFIG_BNXT_HWMON
6833 static ssize_t bnxt_show_temp(struct device *dev,
6834 struct device_attribute *devattr, char *buf)
6835 {
6836 struct hwrm_temp_monitor_query_input req = {0};
6837 struct hwrm_temp_monitor_query_output *resp;
6838 struct bnxt *bp = dev_get_drvdata(dev);
6839 u32 temp = 0;
6840
6841 resp = bp->hwrm_cmd_resp_addr;
6842 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
6843 mutex_lock(&bp->hwrm_cmd_lock);
6844 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
6845 temp = resp->temp * 1000; /* display millidegree */
6846 mutex_unlock(&bp->hwrm_cmd_lock);
6847
6848 return sprintf(buf, "%u\n", temp);
6849 }
6850 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
6851
6852 static struct attribute *bnxt_attrs[] = {
6853 &sensor_dev_attr_temp1_input.dev_attr.attr,
6854 NULL
6855 };
6856 ATTRIBUTE_GROUPS(bnxt);
6857
6858 static void bnxt_hwmon_close(struct bnxt *bp)
6859 {
6860 if (bp->hwmon_dev) {
6861 hwmon_device_unregister(bp->hwmon_dev);
6862 bp->hwmon_dev = NULL;
6863 }
6864 }
6865
6866 static void bnxt_hwmon_open(struct bnxt *bp)
6867 {
6868 struct pci_dev *pdev = bp->pdev;
6869
6870 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
6871 DRV_MODULE_NAME, bp,
6872 bnxt_groups);
6873 if (IS_ERR(bp->hwmon_dev)) {
6874 bp->hwmon_dev = NULL;
6875 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
6876 }
6877 }
6878 #else
6879 static void bnxt_hwmon_close(struct bnxt *bp)
6880 {
6881 }
6882
6883 static void bnxt_hwmon_open(struct bnxt *bp)
6884 {
6885 }
6886 #endif
6887
6888 static bool bnxt_eee_config_ok(struct bnxt *bp)
6889 {
6890 struct ethtool_eee *eee = &bp->eee;
6891 struct bnxt_link_info *link_info = &bp->link_info;
6892
6893 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6894 return true;
6895
6896 if (eee->eee_enabled) {
6897 u32 advertising =
6898 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6899
6900 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6901 eee->eee_enabled = 0;
6902 return false;
6903 }
6904 if (eee->advertised & ~advertising) {
6905 eee->advertised = advertising & eee->supported;
6906 return false;
6907 }
6908 }
6909 return true;
6910 }
6911
6912 static int bnxt_update_phy_setting(struct bnxt *bp)
6913 {
6914 int rc;
6915 bool update_link = false;
6916 bool update_pause = false;
6917 bool update_eee = false;
6918 struct bnxt_link_info *link_info = &bp->link_info;
6919
6920 rc = bnxt_update_link(bp, true);
6921 if (rc) {
6922 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6923 rc);
6924 return rc;
6925 }
6926 if (!BNXT_SINGLE_PF(bp))
6927 return 0;
6928
6929 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6930 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6931 link_info->req_flow_ctrl)
6932 update_pause = true;
6933 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6934 link_info->force_pause_setting != link_info->req_flow_ctrl)
6935 update_pause = true;
6936 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6937 if (BNXT_AUTO_MODE(link_info->auto_mode))
6938 update_link = true;
6939 if (link_info->req_link_speed != link_info->force_link_speed)
6940 update_link = true;
6941 if (link_info->req_duplex != link_info->duplex_setting)
6942 update_link = true;
6943 } else {
6944 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6945 update_link = true;
6946 if (link_info->advertising != link_info->auto_link_speeds)
6947 update_link = true;
6948 }
6949
6950 /* The last close may have shutdown the link, so need to call
6951 * PHY_CFG to bring it back up.
6952 */
6953 if (!netif_carrier_ok(bp->dev))
6954 update_link = true;
6955
6956 if (!bnxt_eee_config_ok(bp))
6957 update_eee = true;
6958
6959 if (update_link)
6960 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6961 else if (update_pause)
6962 rc = bnxt_hwrm_set_pause(bp);
6963 if (rc) {
6964 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6965 rc);
6966 return rc;
6967 }
6968
6969 return rc;
6970 }
6971
6972 /* Common routine to pre-map certain register block to different GRC window.
6973 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6974 * in PF and 3 windows in VF that can be customized to map in different
6975 * register blocks.
6976 */
6977 static void bnxt_preset_reg_win(struct bnxt *bp)
6978 {
6979 if (BNXT_PF(bp)) {
6980 /* CAG registers map to GRC window #4 */
6981 writel(BNXT_CAG_REG_BASE,
6982 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6983 }
6984 }
6985
6986 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
6987
6988 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6989 {
6990 int rc = 0;
6991
6992 bnxt_preset_reg_win(bp);
6993 netif_carrier_off(bp->dev);
6994 if (irq_re_init) {
6995 /* Reserve rings now if none were reserved at driver probe. */
6996 rc = bnxt_init_dflt_ring_mode(bp);
6997 if (rc) {
6998 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
6999 return rc;
7000 }
7001 rc = bnxt_reserve_rings(bp);
7002 if (rc)
7003 return rc;
7004 }
7005 if ((bp->flags & BNXT_FLAG_RFS) &&
7006 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
7007 /* disable RFS if falling back to INTA */
7008 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
7009 bp->flags &= ~BNXT_FLAG_RFS;
7010 }
7011
7012 rc = bnxt_alloc_mem(bp, irq_re_init);
7013 if (rc) {
7014 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
7015 goto open_err_free_mem;
7016 }
7017
7018 if (irq_re_init) {
7019 bnxt_init_napi(bp);
7020 rc = bnxt_request_irq(bp);
7021 if (rc) {
7022 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
7023 goto open_err_irq;
7024 }
7025 }
7026
7027 bnxt_enable_napi(bp);
7028 bnxt_debug_dev_init(bp);
7029
7030 rc = bnxt_init_nic(bp, irq_re_init);
7031 if (rc) {
7032 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
7033 goto open_err;
7034 }
7035
7036 if (link_re_init) {
7037 mutex_lock(&bp->link_lock);
7038 rc = bnxt_update_phy_setting(bp);
7039 mutex_unlock(&bp->link_lock);
7040 if (rc) {
7041 netdev_warn(bp->dev, "failed to update phy settings\n");
7042 if (BNXT_SINGLE_PF(bp)) {
7043 bp->link_info.phy_retry = true;
7044 bp->link_info.phy_retry_expires =
7045 jiffies + 5 * HZ;
7046 }
7047 }
7048 }
7049
7050 if (irq_re_init)
7051 udp_tunnel_get_rx_info(bp->dev);
7052
7053 set_bit(BNXT_STATE_OPEN, &bp->state);
7054 bnxt_enable_int(bp);
7055 /* Enable TX queues */
7056 bnxt_tx_enable(bp);
7057 mod_timer(&bp->timer, jiffies + bp->current_interval);
7058 /* Poll link status and check for SFP+ module status */
7059 bnxt_get_port_module_status(bp);
7060
7061 /* VF-reps may need to be re-opened after the PF is re-opened */
7062 if (BNXT_PF(bp))
7063 bnxt_vf_reps_open(bp);
7064 return 0;
7065
7066 open_err:
7067 bnxt_debug_dev_exit(bp);
7068 bnxt_disable_napi(bp);
7069
7070 open_err_irq:
7071 bnxt_del_napi(bp);
7072
7073 open_err_free_mem:
7074 bnxt_free_skbs(bp);
7075 bnxt_free_irq(bp);
7076 bnxt_free_mem(bp, true);
7077 return rc;
7078 }
7079
7080 /* rtnl_lock held */
7081 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7082 {
7083 int rc = 0;
7084
7085 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
7086 if (rc) {
7087 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
7088 dev_close(bp->dev);
7089 }
7090 return rc;
7091 }
7092
7093 /* rtnl_lock held, open the NIC half way by allocating all resources, but
7094 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
7095 * self tests.
7096 */
7097 int bnxt_half_open_nic(struct bnxt *bp)
7098 {
7099 int rc = 0;
7100
7101 rc = bnxt_alloc_mem(bp, false);
7102 if (rc) {
7103 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
7104 goto half_open_err;
7105 }
7106 rc = bnxt_init_nic(bp, false);
7107 if (rc) {
7108 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
7109 goto half_open_err;
7110 }
7111 return 0;
7112
7113 half_open_err:
7114 bnxt_free_skbs(bp);
7115 bnxt_free_mem(bp, false);
7116 dev_close(bp->dev);
7117 return rc;
7118 }
7119
7120 /* rtnl_lock held, this call can only be made after a previous successful
7121 * call to bnxt_half_open_nic().
7122 */
7123 void bnxt_half_close_nic(struct bnxt *bp)
7124 {
7125 bnxt_hwrm_resource_free(bp, false, false);
7126 bnxt_free_skbs(bp);
7127 bnxt_free_mem(bp, false);
7128 }
7129
7130 static int bnxt_open(struct net_device *dev)
7131 {
7132 struct bnxt *bp = netdev_priv(dev);
7133 int rc;
7134
7135 bnxt_hwrm_if_change(bp, true);
7136 rc = __bnxt_open_nic(bp, true, true);
7137 if (rc)
7138 bnxt_hwrm_if_change(bp, false);
7139
7140 bnxt_hwmon_open(bp);
7141
7142 return rc;
7143 }
7144
7145 static bool bnxt_drv_busy(struct bnxt *bp)
7146 {
7147 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
7148 test_bit(BNXT_STATE_READ_STATS, &bp->state));
7149 }
7150
7151 static void bnxt_get_ring_stats(struct bnxt *bp,
7152 struct rtnl_link_stats64 *stats);
7153
7154 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
7155 bool link_re_init)
7156 {
7157 /* Close the VF-reps before closing PF */
7158 if (BNXT_PF(bp))
7159 bnxt_vf_reps_close(bp);
7160
7161 /* Change device state to avoid TX queue wake up's */
7162 bnxt_tx_disable(bp);
7163
7164 clear_bit(BNXT_STATE_OPEN, &bp->state);
7165 smp_mb__after_atomic();
7166 while (bnxt_drv_busy(bp))
7167 msleep(20);
7168
7169 /* Flush rings and and disable interrupts */
7170 bnxt_shutdown_nic(bp, irq_re_init);
7171
7172 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
7173
7174 bnxt_debug_dev_exit(bp);
7175 bnxt_disable_napi(bp);
7176 del_timer_sync(&bp->timer);
7177 bnxt_free_skbs(bp);
7178
7179 /* Save ring stats before shutdown */
7180 if (bp->bnapi && irq_re_init)
7181 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
7182 if (irq_re_init) {
7183 bnxt_free_irq(bp);
7184 bnxt_del_napi(bp);
7185 }
7186 bnxt_free_mem(bp, irq_re_init);
7187 }
7188
7189 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7190 {
7191 int rc = 0;
7192
7193 #ifdef CONFIG_BNXT_SRIOV
7194 if (bp->sriov_cfg) {
7195 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
7196 !bp->sriov_cfg,
7197 BNXT_SRIOV_CFG_WAIT_TMO);
7198 if (rc)
7199 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
7200 }
7201 #endif
7202 __bnxt_close_nic(bp, irq_re_init, link_re_init);
7203 return rc;
7204 }
7205
7206 static int bnxt_close(struct net_device *dev)
7207 {
7208 struct bnxt *bp = netdev_priv(dev);
7209
7210 bnxt_hwmon_close(bp);
7211 bnxt_close_nic(bp, true, true);
7212 bnxt_hwrm_shutdown_link(bp);
7213 bnxt_hwrm_if_change(bp, false);
7214 return 0;
7215 }
7216
7217 /* rtnl_lock held */
7218 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7219 {
7220 switch (cmd) {
7221 case SIOCGMIIPHY:
7222 /* fallthru */
7223 case SIOCGMIIREG: {
7224 if (!netif_running(dev))
7225 return -EAGAIN;
7226
7227 return 0;
7228 }
7229
7230 case SIOCSMIIREG:
7231 if (!netif_running(dev))
7232 return -EAGAIN;
7233
7234 return 0;
7235
7236 default:
7237 /* do nothing */
7238 break;
7239 }
7240 return -EOPNOTSUPP;
7241 }
7242
7243 static void bnxt_get_ring_stats(struct bnxt *bp,
7244 struct rtnl_link_stats64 *stats)
7245 {
7246 int i;
7247
7248
7249 for (i = 0; i < bp->cp_nr_rings; i++) {
7250 struct bnxt_napi *bnapi = bp->bnapi[i];
7251 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7252 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
7253
7254 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
7255 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
7256 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
7257
7258 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
7259 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
7260 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
7261
7262 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
7263 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
7264 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
7265
7266 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
7267 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
7268 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
7269
7270 stats->rx_missed_errors +=
7271 le64_to_cpu(hw_stats->rx_discard_pkts);
7272
7273 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
7274
7275 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
7276 }
7277 }
7278
7279 static void bnxt_add_prev_stats(struct bnxt *bp,
7280 struct rtnl_link_stats64 *stats)
7281 {
7282 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
7283
7284 stats->rx_packets += prev_stats->rx_packets;
7285 stats->tx_packets += prev_stats->tx_packets;
7286 stats->rx_bytes += prev_stats->rx_bytes;
7287 stats->tx_bytes += prev_stats->tx_bytes;
7288 stats->rx_missed_errors += prev_stats->rx_missed_errors;
7289 stats->multicast += prev_stats->multicast;
7290 stats->tx_dropped += prev_stats->tx_dropped;
7291 }
7292
7293 static void
7294 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7295 {
7296 struct bnxt *bp = netdev_priv(dev);
7297
7298 set_bit(BNXT_STATE_READ_STATS, &bp->state);
7299 /* Make sure bnxt_close_nic() sees that we are reading stats before
7300 * we check the BNXT_STATE_OPEN flag.
7301 */
7302 smp_mb__after_atomic();
7303 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7304 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7305 *stats = bp->net_stats_prev;
7306 return;
7307 }
7308
7309 bnxt_get_ring_stats(bp, stats);
7310 bnxt_add_prev_stats(bp, stats);
7311
7312 if (bp->flags & BNXT_FLAG_PORT_STATS) {
7313 struct rx_port_stats *rx = bp->hw_rx_port_stats;
7314 struct tx_port_stats *tx = bp->hw_tx_port_stats;
7315
7316 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
7317 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
7318 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
7319 le64_to_cpu(rx->rx_ovrsz_frames) +
7320 le64_to_cpu(rx->rx_runt_frames);
7321 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
7322 le64_to_cpu(rx->rx_jbr_frames);
7323 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
7324 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
7325 stats->tx_errors = le64_to_cpu(tx->tx_err);
7326 }
7327 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7328 }
7329
7330 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
7331 {
7332 struct net_device *dev = bp->dev;
7333 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7334 struct netdev_hw_addr *ha;
7335 u8 *haddr;
7336 int mc_count = 0;
7337 bool update = false;
7338 int off = 0;
7339
7340 netdev_for_each_mc_addr(ha, dev) {
7341 if (mc_count >= BNXT_MAX_MC_ADDRS) {
7342 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7343 vnic->mc_list_count = 0;
7344 return false;
7345 }
7346 haddr = ha->addr;
7347 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
7348 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
7349 update = true;
7350 }
7351 off += ETH_ALEN;
7352 mc_count++;
7353 }
7354 if (mc_count)
7355 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
7356
7357 if (mc_count != vnic->mc_list_count) {
7358 vnic->mc_list_count = mc_count;
7359 update = true;
7360 }
7361 return update;
7362 }
7363
7364 static bool bnxt_uc_list_updated(struct bnxt *bp)
7365 {
7366 struct net_device *dev = bp->dev;
7367 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7368 struct netdev_hw_addr *ha;
7369 int off = 0;
7370
7371 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
7372 return true;
7373
7374 netdev_for_each_uc_addr(ha, dev) {
7375 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
7376 return true;
7377
7378 off += ETH_ALEN;
7379 }
7380 return false;
7381 }
7382
7383 static void bnxt_set_rx_mode(struct net_device *dev)
7384 {
7385 struct bnxt *bp = netdev_priv(dev);
7386 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7387 u32 mask = vnic->rx_mask;
7388 bool mc_update = false;
7389 bool uc_update;
7390
7391 if (!netif_running(dev))
7392 return;
7393
7394 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
7395 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
7396 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
7397 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
7398
7399 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7400 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7401
7402 uc_update = bnxt_uc_list_updated(bp);
7403
7404 if (dev->flags & IFF_BROADCAST)
7405 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7406 if (dev->flags & IFF_ALLMULTI) {
7407 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7408 vnic->mc_list_count = 0;
7409 } else {
7410 mc_update = bnxt_mc_list_updated(bp, &mask);
7411 }
7412
7413 if (mask != vnic->rx_mask || uc_update || mc_update) {
7414 vnic->rx_mask = mask;
7415
7416 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
7417 bnxt_queue_sp_work(bp);
7418 }
7419 }
7420
7421 static int bnxt_cfg_rx_mode(struct bnxt *bp)
7422 {
7423 struct net_device *dev = bp->dev;
7424 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7425 struct netdev_hw_addr *ha;
7426 int i, off = 0, rc;
7427 bool uc_update;
7428
7429 netif_addr_lock_bh(dev);
7430 uc_update = bnxt_uc_list_updated(bp);
7431 netif_addr_unlock_bh(dev);
7432
7433 if (!uc_update)
7434 goto skip_uc;
7435
7436 mutex_lock(&bp->hwrm_cmd_lock);
7437 for (i = 1; i < vnic->uc_filter_count; i++) {
7438 struct hwrm_cfa_l2_filter_free_input req = {0};
7439
7440 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
7441 -1);
7442
7443 req.l2_filter_id = vnic->fw_l2_filter_id[i];
7444
7445 rc = _hwrm_send_message(bp, &req, sizeof(req),
7446 HWRM_CMD_TIMEOUT);
7447 }
7448 mutex_unlock(&bp->hwrm_cmd_lock);
7449
7450 vnic->uc_filter_count = 1;
7451
7452 netif_addr_lock_bh(dev);
7453 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
7454 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7455 } else {
7456 netdev_for_each_uc_addr(ha, dev) {
7457 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
7458 off += ETH_ALEN;
7459 vnic->uc_filter_count++;
7460 }
7461 }
7462 netif_addr_unlock_bh(dev);
7463
7464 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
7465 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
7466 if (rc) {
7467 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
7468 rc);
7469 vnic->uc_filter_count = i;
7470 return rc;
7471 }
7472 }
7473
7474 skip_uc:
7475 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
7476 if (rc && vnic->mc_list_count) {
7477 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
7478 rc);
7479 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7480 vnic->mc_list_count = 0;
7481 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
7482 }
7483 if (rc)
7484 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
7485 rc);
7486
7487 return rc;
7488 }
7489
7490 static bool bnxt_can_reserve_rings(struct bnxt *bp)
7491 {
7492 #ifdef CONFIG_BNXT_SRIOV
7493 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
7494 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7495
7496 /* No minimum rings were provisioned by the PF. Don't
7497 * reserve rings by default when device is down.
7498 */
7499 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
7500 return true;
7501
7502 if (!netif_running(bp->dev))
7503 return false;
7504 }
7505 #endif
7506 return true;
7507 }
7508
7509 /* If the chip and firmware supports RFS */
7510 static bool bnxt_rfs_supported(struct bnxt *bp)
7511 {
7512 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
7513 return true;
7514 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7515 return true;
7516 return false;
7517 }
7518
7519 /* If runtime conditions support RFS */
7520 static bool bnxt_rfs_capable(struct bnxt *bp)
7521 {
7522 #ifdef CONFIG_RFS_ACCEL
7523 int vnics, max_vnics, max_rss_ctxs;
7524
7525 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
7526 return false;
7527
7528 vnics = 1 + bp->rx_nr_rings;
7529 max_vnics = bnxt_get_max_func_vnics(bp);
7530 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
7531
7532 /* RSS contexts not a limiting factor */
7533 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7534 max_rss_ctxs = max_vnics;
7535 if (vnics > max_vnics || vnics > max_rss_ctxs) {
7536 if (bp->rx_nr_rings > 1)
7537 netdev_warn(bp->dev,
7538 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
7539 min(max_rss_ctxs - 1, max_vnics - 1));
7540 return false;
7541 }
7542
7543 if (!BNXT_NEW_RM(bp))
7544 return true;
7545
7546 if (vnics == bp->hw_resc.resv_vnics)
7547 return true;
7548
7549 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics);
7550 if (vnics <= bp->hw_resc.resv_vnics)
7551 return true;
7552
7553 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
7554 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1);
7555 return false;
7556 #else
7557 return false;
7558 #endif
7559 }
7560
7561 static netdev_features_t bnxt_fix_features(struct net_device *dev,
7562 netdev_features_t features)
7563 {
7564 struct bnxt *bp = netdev_priv(dev);
7565 netdev_features_t vlan_features;
7566
7567 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
7568 features &= ~NETIF_F_NTUPLE;
7569
7570 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7571 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
7572
7573 if (!(features & NETIF_F_GRO))
7574 features &= ~NETIF_F_GRO_HW;
7575
7576 if (features & NETIF_F_GRO_HW)
7577 features &= ~NETIF_F_LRO;
7578
7579 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
7580 * turned on or off together.
7581 */
7582 vlan_features = features & (NETIF_F_HW_VLAN_CTAG_RX |
7583 NETIF_F_HW_VLAN_STAG_RX);
7584 if (vlan_features != (NETIF_F_HW_VLAN_CTAG_RX |
7585 NETIF_F_HW_VLAN_STAG_RX)) {
7586 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
7587 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7588 NETIF_F_HW_VLAN_STAG_RX);
7589 else if (vlan_features)
7590 features |= NETIF_F_HW_VLAN_CTAG_RX |
7591 NETIF_F_HW_VLAN_STAG_RX;
7592 }
7593 #ifdef CONFIG_BNXT_SRIOV
7594 if (BNXT_VF(bp)) {
7595 if (bp->vf.vlan) {
7596 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7597 NETIF_F_HW_VLAN_STAG_RX);
7598 }
7599 }
7600 #endif
7601 return features;
7602 }
7603
7604 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
7605 {
7606 struct bnxt *bp = netdev_priv(dev);
7607 u32 flags = bp->flags;
7608 u32 changes;
7609 int rc = 0;
7610 bool re_init = false;
7611 bool update_tpa = false;
7612
7613 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
7614 if (features & NETIF_F_GRO_HW)
7615 flags |= BNXT_FLAG_GRO;
7616 else if (features & NETIF_F_LRO)
7617 flags |= BNXT_FLAG_LRO;
7618
7619 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7620 flags &= ~BNXT_FLAG_TPA;
7621
7622 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7623 flags |= BNXT_FLAG_STRIP_VLAN;
7624
7625 if (features & NETIF_F_NTUPLE)
7626 flags |= BNXT_FLAG_RFS;
7627
7628 changes = flags ^ bp->flags;
7629 if (changes & BNXT_FLAG_TPA) {
7630 update_tpa = true;
7631 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
7632 (flags & BNXT_FLAG_TPA) == 0)
7633 re_init = true;
7634 }
7635
7636 if (changes & ~BNXT_FLAG_TPA)
7637 re_init = true;
7638
7639 if (flags != bp->flags) {
7640 u32 old_flags = bp->flags;
7641
7642 bp->flags = flags;
7643
7644 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7645 if (update_tpa)
7646 bnxt_set_ring_params(bp);
7647 return rc;
7648 }
7649
7650 if (re_init) {
7651 bnxt_close_nic(bp, false, false);
7652 if (update_tpa)
7653 bnxt_set_ring_params(bp);
7654
7655 return bnxt_open_nic(bp, false, false);
7656 }
7657 if (update_tpa) {
7658 rc = bnxt_set_tpa(bp,
7659 (flags & BNXT_FLAG_TPA) ?
7660 true : false);
7661 if (rc)
7662 bp->flags = old_flags;
7663 }
7664 }
7665 return rc;
7666 }
7667
7668 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
7669 {
7670 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
7671 int i = bnapi->index;
7672
7673 if (!txr)
7674 return;
7675
7676 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
7677 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
7678 txr->tx_cons);
7679 }
7680
7681 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
7682 {
7683 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
7684 int i = bnapi->index;
7685
7686 if (!rxr)
7687 return;
7688
7689 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
7690 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
7691 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
7692 rxr->rx_sw_agg_prod);
7693 }
7694
7695 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
7696 {
7697 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7698 int i = bnapi->index;
7699
7700 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
7701 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
7702 }
7703
7704 static void bnxt_dbg_dump_states(struct bnxt *bp)
7705 {
7706 int i;
7707 struct bnxt_napi *bnapi;
7708
7709 for (i = 0; i < bp->cp_nr_rings; i++) {
7710 bnapi = bp->bnapi[i];
7711 if (netif_msg_drv(bp)) {
7712 bnxt_dump_tx_sw_state(bnapi);
7713 bnxt_dump_rx_sw_state(bnapi);
7714 bnxt_dump_cp_sw_state(bnapi);
7715 }
7716 }
7717 }
7718
7719 static void bnxt_reset_task(struct bnxt *bp, bool silent)
7720 {
7721 if (!silent)
7722 bnxt_dbg_dump_states(bp);
7723 if (netif_running(bp->dev)) {
7724 int rc;
7725
7726 if (!silent)
7727 bnxt_ulp_stop(bp);
7728 bnxt_close_nic(bp, false, false);
7729 rc = bnxt_open_nic(bp, false, false);
7730 if (!silent && !rc)
7731 bnxt_ulp_start(bp);
7732 }
7733 }
7734
7735 static void bnxt_tx_timeout(struct net_device *dev)
7736 {
7737 struct bnxt *bp = netdev_priv(dev);
7738
7739 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
7740 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
7741 bnxt_queue_sp_work(bp);
7742 }
7743
7744 static void bnxt_timer(struct timer_list *t)
7745 {
7746 struct bnxt *bp = from_timer(bp, t, timer);
7747 struct net_device *dev = bp->dev;
7748
7749 if (!netif_running(dev))
7750 return;
7751
7752 if (atomic_read(&bp->intr_sem) != 0)
7753 goto bnxt_restart_timer;
7754
7755 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
7756 bp->stats_coal_ticks) {
7757 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
7758 bnxt_queue_sp_work(bp);
7759 }
7760
7761 if (bnxt_tc_flower_enabled(bp)) {
7762 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
7763 bnxt_queue_sp_work(bp);
7764 }
7765
7766 if (bp->link_info.phy_retry) {
7767 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
7768 bp->link_info.phy_retry = 0;
7769 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
7770 } else {
7771 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
7772 bnxt_queue_sp_work(bp);
7773 }
7774 }
7775 bnxt_restart_timer:
7776 mod_timer(&bp->timer, jiffies + bp->current_interval);
7777 }
7778
7779 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
7780 {
7781 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
7782 * set. If the device is being closed, bnxt_close() may be holding
7783 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
7784 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
7785 */
7786 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7787 rtnl_lock();
7788 }
7789
7790 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
7791 {
7792 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7793 rtnl_unlock();
7794 }
7795
7796 /* Only called from bnxt_sp_task() */
7797 static void bnxt_reset(struct bnxt *bp, bool silent)
7798 {
7799 bnxt_rtnl_lock_sp(bp);
7800 if (test_bit(BNXT_STATE_OPEN, &bp->state))
7801 bnxt_reset_task(bp, silent);
7802 bnxt_rtnl_unlock_sp(bp);
7803 }
7804
7805 static void bnxt_cfg_ntp_filters(struct bnxt *);
7806
7807 static void bnxt_sp_task(struct work_struct *work)
7808 {
7809 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
7810
7811 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7812 smp_mb__after_atomic();
7813 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7814 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7815 return;
7816 }
7817
7818 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
7819 bnxt_cfg_rx_mode(bp);
7820
7821 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
7822 bnxt_cfg_ntp_filters(bp);
7823 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7824 bnxt_hwrm_exec_fwd_req(bp);
7825 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7826 bnxt_hwrm_tunnel_dst_port_alloc(
7827 bp, bp->vxlan_port,
7828 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7829 }
7830 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7831 bnxt_hwrm_tunnel_dst_port_free(
7832 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7833 }
7834 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7835 bnxt_hwrm_tunnel_dst_port_alloc(
7836 bp, bp->nge_port,
7837 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7838 }
7839 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7840 bnxt_hwrm_tunnel_dst_port_free(
7841 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7842 }
7843 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
7844 bnxt_hwrm_port_qstats(bp);
7845 bnxt_hwrm_port_qstats_ext(bp);
7846 }
7847
7848 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
7849 int rc;
7850
7851 mutex_lock(&bp->link_lock);
7852 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7853 &bp->sp_event))
7854 bnxt_hwrm_phy_qcaps(bp);
7855
7856 rc = bnxt_update_link(bp, true);
7857 mutex_unlock(&bp->link_lock);
7858 if (rc)
7859 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7860 rc);
7861 }
7862 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
7863 int rc;
7864
7865 mutex_lock(&bp->link_lock);
7866 rc = bnxt_update_phy_setting(bp);
7867 mutex_unlock(&bp->link_lock);
7868 if (rc) {
7869 netdev_warn(bp->dev, "update phy settings retry failed\n");
7870 } else {
7871 bp->link_info.phy_retry = false;
7872 netdev_info(bp->dev, "update phy settings retry succeeded\n");
7873 }
7874 }
7875 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
7876 mutex_lock(&bp->link_lock);
7877 bnxt_get_port_module_status(bp);
7878 mutex_unlock(&bp->link_lock);
7879 }
7880
7881 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
7882 bnxt_tc_flow_stats_work(bp);
7883
7884 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
7885 * must be the last functions to be called before exiting.
7886 */
7887 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7888 bnxt_reset(bp, false);
7889
7890 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7891 bnxt_reset(bp, true);
7892
7893 smp_mb__before_atomic();
7894 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7895 }
7896
7897 /* Under rtnl_lock */
7898 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7899 int tx_xdp)
7900 {
7901 int max_rx, max_tx, tx_sets = 1;
7902 int tx_rings_needed;
7903 int rx_rings = rx;
7904 int cp, vnics, rc;
7905
7906 if (tcs)
7907 tx_sets = tcs;
7908
7909 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7910 if (rc)
7911 return rc;
7912
7913 if (max_rx < rx)
7914 return -ENOMEM;
7915
7916 tx_rings_needed = tx * tx_sets + tx_xdp;
7917 if (max_tx < tx_rings_needed)
7918 return -ENOMEM;
7919
7920 vnics = 1;
7921 if (bp->flags & BNXT_FLAG_RFS)
7922 vnics += rx_rings;
7923
7924 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7925 rx_rings <<= 1;
7926 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
7927 if (BNXT_NEW_RM(bp))
7928 cp += bnxt_get_ulp_msix_num(bp);
7929 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
7930 vnics);
7931 }
7932
7933 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7934 {
7935 if (bp->bar2) {
7936 pci_iounmap(pdev, bp->bar2);
7937 bp->bar2 = NULL;
7938 }
7939
7940 if (bp->bar1) {
7941 pci_iounmap(pdev, bp->bar1);
7942 bp->bar1 = NULL;
7943 }
7944
7945 if (bp->bar0) {
7946 pci_iounmap(pdev, bp->bar0);
7947 bp->bar0 = NULL;
7948 }
7949 }
7950
7951 static void bnxt_cleanup_pci(struct bnxt *bp)
7952 {
7953 bnxt_unmap_bars(bp, bp->pdev);
7954 pci_release_regions(bp->pdev);
7955 pci_disable_device(bp->pdev);
7956 }
7957
7958 static void bnxt_init_dflt_coal(struct bnxt *bp)
7959 {
7960 struct bnxt_coal *coal;
7961
7962 /* Tick values in micro seconds.
7963 * 1 coal_buf x bufs_per_record = 1 completion record.
7964 */
7965 coal = &bp->rx_coal;
7966 coal->coal_ticks = 14;
7967 coal->coal_bufs = 30;
7968 coal->coal_ticks_irq = 1;
7969 coal->coal_bufs_irq = 2;
7970 coal->idle_thresh = 50;
7971 coal->bufs_per_record = 2;
7972 coal->budget = 64; /* NAPI budget */
7973
7974 coal = &bp->tx_coal;
7975 coal->coal_ticks = 28;
7976 coal->coal_bufs = 30;
7977 coal->coal_ticks_irq = 2;
7978 coal->coal_bufs_irq = 2;
7979 coal->bufs_per_record = 1;
7980
7981 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
7982 }
7983
7984 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
7985 {
7986 int rc;
7987 struct bnxt *bp = netdev_priv(dev);
7988
7989 SET_NETDEV_DEV(dev, &pdev->dev);
7990
7991 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7992 rc = pci_enable_device(pdev);
7993 if (rc) {
7994 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7995 goto init_err;
7996 }
7997
7998 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7999 dev_err(&pdev->dev,
8000 "Cannot find PCI device base address, aborting\n");
8001 rc = -ENODEV;
8002 goto init_err_disable;
8003 }
8004
8005 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
8006 if (rc) {
8007 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
8008 goto init_err_disable;
8009 }
8010
8011 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
8012 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
8013 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
8014 goto init_err_disable;
8015 }
8016
8017 pci_set_master(pdev);
8018
8019 bp->dev = dev;
8020 bp->pdev = pdev;
8021
8022 bp->bar0 = pci_ioremap_bar(pdev, 0);
8023 if (!bp->bar0) {
8024 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
8025 rc = -ENOMEM;
8026 goto init_err_release;
8027 }
8028
8029 bp->bar1 = pci_ioremap_bar(pdev, 2);
8030 if (!bp->bar1) {
8031 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
8032 rc = -ENOMEM;
8033 goto init_err_release;
8034 }
8035
8036 bp->bar2 = pci_ioremap_bar(pdev, 4);
8037 if (!bp->bar2) {
8038 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
8039 rc = -ENOMEM;
8040 goto init_err_release;
8041 }
8042
8043 pci_enable_pcie_error_reporting(pdev);
8044
8045 INIT_WORK(&bp->sp_task, bnxt_sp_task);
8046
8047 spin_lock_init(&bp->ntp_fltr_lock);
8048
8049 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
8050 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
8051
8052 bnxt_init_dflt_coal(bp);
8053
8054 timer_setup(&bp->timer, bnxt_timer, 0);
8055 bp->current_interval = BNXT_TIMER_INTERVAL;
8056
8057 clear_bit(BNXT_STATE_OPEN, &bp->state);
8058 return 0;
8059
8060 init_err_release:
8061 bnxt_unmap_bars(bp, pdev);
8062 pci_release_regions(pdev);
8063
8064 init_err_disable:
8065 pci_disable_device(pdev);
8066
8067 init_err:
8068 return rc;
8069 }
8070
8071 /* rtnl_lock held */
8072 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
8073 {
8074 struct sockaddr *addr = p;
8075 struct bnxt *bp = netdev_priv(dev);
8076 int rc = 0;
8077
8078 if (!is_valid_ether_addr(addr->sa_data))
8079 return -EADDRNOTAVAIL;
8080
8081 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
8082 return 0;
8083
8084 rc = bnxt_approve_mac(bp, addr->sa_data, true);
8085 if (rc)
8086 return rc;
8087
8088 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8089 if (netif_running(dev)) {
8090 bnxt_close_nic(bp, false, false);
8091 rc = bnxt_open_nic(bp, false, false);
8092 }
8093
8094 return rc;
8095 }
8096
8097 /* rtnl_lock held */
8098 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
8099 {
8100 struct bnxt *bp = netdev_priv(dev);
8101
8102 if (netif_running(dev))
8103 bnxt_close_nic(bp, true, false);
8104
8105 dev->mtu = new_mtu;
8106 bnxt_set_ring_params(bp);
8107
8108 if (netif_running(dev))
8109 return bnxt_open_nic(bp, true, false);
8110
8111 return 0;
8112 }
8113
8114 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
8115 {
8116 struct bnxt *bp = netdev_priv(dev);
8117 bool sh = false;
8118 int rc;
8119
8120 if (tc > bp->max_tc) {
8121 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
8122 tc, bp->max_tc);
8123 return -EINVAL;
8124 }
8125
8126 if (netdev_get_num_tc(dev) == tc)
8127 return 0;
8128
8129 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
8130 sh = true;
8131
8132 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
8133 sh, tc, bp->tx_nr_rings_xdp);
8134 if (rc)
8135 return rc;
8136
8137 /* Needs to close the device and do hw resource re-allocations */
8138 if (netif_running(bp->dev))
8139 bnxt_close_nic(bp, true, false);
8140
8141 if (tc) {
8142 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
8143 netdev_set_num_tc(dev, tc);
8144 } else {
8145 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8146 netdev_reset_tc(dev);
8147 }
8148 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
8149 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
8150 bp->tx_nr_rings + bp->rx_nr_rings;
8151 bp->num_stat_ctxs = bp->cp_nr_rings;
8152
8153 if (netif_running(bp->dev))
8154 return bnxt_open_nic(bp, true, false);
8155
8156 return 0;
8157 }
8158
8159 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
8160 void *cb_priv)
8161 {
8162 struct bnxt *bp = cb_priv;
8163
8164 if (!bnxt_tc_flower_enabled(bp) ||
8165 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
8166 return -EOPNOTSUPP;
8167
8168 switch (type) {
8169 case TC_SETUP_CLSFLOWER:
8170 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
8171 default:
8172 return -EOPNOTSUPP;
8173 }
8174 }
8175
8176 static int bnxt_setup_tc_block(struct net_device *dev,
8177 struct tc_block_offload *f)
8178 {
8179 struct bnxt *bp = netdev_priv(dev);
8180
8181 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
8182 return -EOPNOTSUPP;
8183
8184 switch (f->command) {
8185 case TC_BLOCK_BIND:
8186 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
8187 bp, bp, f->extack);
8188 case TC_BLOCK_UNBIND:
8189 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
8190 return 0;
8191 default:
8192 return -EOPNOTSUPP;
8193 }
8194 }
8195
8196 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
8197 void *type_data)
8198 {
8199 switch (type) {
8200 case TC_SETUP_BLOCK:
8201 return bnxt_setup_tc_block(dev, type_data);
8202 case TC_SETUP_QDISC_MQPRIO: {
8203 struct tc_mqprio_qopt *mqprio = type_data;
8204
8205 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
8206
8207 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
8208 }
8209 default:
8210 return -EOPNOTSUPP;
8211 }
8212 }
8213
8214 #ifdef CONFIG_RFS_ACCEL
8215 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
8216 struct bnxt_ntuple_filter *f2)
8217 {
8218 struct flow_keys *keys1 = &f1->fkeys;
8219 struct flow_keys *keys2 = &f2->fkeys;
8220
8221 if (keys1->basic.n_proto != keys2->basic.n_proto ||
8222 keys1->basic.ip_proto != keys2->basic.ip_proto)
8223 return false;
8224
8225 if (keys1->basic.n_proto == htons(ETH_P_IP)) {
8226 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
8227 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst)
8228 return false;
8229 } else {
8230 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src,
8231 sizeof(keys1->addrs.v6addrs.src)) ||
8232 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst,
8233 sizeof(keys1->addrs.v6addrs.dst)))
8234 return false;
8235 }
8236
8237 if (keys1->ports.ports == keys2->ports.ports &&
8238 keys1->control.flags == keys2->control.flags &&
8239 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
8240 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
8241 return true;
8242
8243 return false;
8244 }
8245
8246 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
8247 u16 rxq_index, u32 flow_id)
8248 {
8249 struct bnxt *bp = netdev_priv(dev);
8250 struct bnxt_ntuple_filter *fltr, *new_fltr;
8251 struct flow_keys *fkeys;
8252 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
8253 int rc = 0, idx, bit_id, l2_idx = 0;
8254 struct hlist_head *head;
8255
8256 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
8257 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8258 int off = 0, j;
8259
8260 netif_addr_lock_bh(dev);
8261 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
8262 if (ether_addr_equal(eth->h_dest,
8263 vnic->uc_list + off)) {
8264 l2_idx = j + 1;
8265 break;
8266 }
8267 }
8268 netif_addr_unlock_bh(dev);
8269 if (!l2_idx)
8270 return -EINVAL;
8271 }
8272 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
8273 if (!new_fltr)
8274 return -ENOMEM;
8275
8276 fkeys = &new_fltr->fkeys;
8277 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
8278 rc = -EPROTONOSUPPORT;
8279 goto err_free;
8280 }
8281
8282 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
8283 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
8284 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
8285 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
8286 rc = -EPROTONOSUPPORT;
8287 goto err_free;
8288 }
8289 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
8290 bp->hwrm_spec_code < 0x10601) {
8291 rc = -EPROTONOSUPPORT;
8292 goto err_free;
8293 }
8294 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
8295 bp->hwrm_spec_code < 0x10601) {
8296 rc = -EPROTONOSUPPORT;
8297 goto err_free;
8298 }
8299
8300 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
8301 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
8302
8303 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
8304 head = &bp->ntp_fltr_hash_tbl[idx];
8305 rcu_read_lock();
8306 hlist_for_each_entry_rcu(fltr, head, hash) {
8307 if (bnxt_fltr_match(fltr, new_fltr)) {
8308 rcu_read_unlock();
8309 rc = 0;
8310 goto err_free;
8311 }
8312 }
8313 rcu_read_unlock();
8314
8315 spin_lock_bh(&bp->ntp_fltr_lock);
8316 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
8317 BNXT_NTP_FLTR_MAX_FLTR, 0);
8318 if (bit_id < 0) {
8319 spin_unlock_bh(&bp->ntp_fltr_lock);
8320 rc = -ENOMEM;
8321 goto err_free;
8322 }
8323
8324 new_fltr->sw_id = (u16)bit_id;
8325 new_fltr->flow_id = flow_id;
8326 new_fltr->l2_fltr_idx = l2_idx;
8327 new_fltr->rxq = rxq_index;
8328 hlist_add_head_rcu(&new_fltr->hash, head);
8329 bp->ntp_fltr_count++;
8330 spin_unlock_bh(&bp->ntp_fltr_lock);
8331
8332 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
8333 bnxt_queue_sp_work(bp);
8334
8335 return new_fltr->sw_id;
8336
8337 err_free:
8338 kfree(new_fltr);
8339 return rc;
8340 }
8341
8342 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8343 {
8344 int i;
8345
8346 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
8347 struct hlist_head *head;
8348 struct hlist_node *tmp;
8349 struct bnxt_ntuple_filter *fltr;
8350 int rc;
8351
8352 head = &bp->ntp_fltr_hash_tbl[i];
8353 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
8354 bool del = false;
8355
8356 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
8357 if (rps_may_expire_flow(bp->dev, fltr->rxq,
8358 fltr->flow_id,
8359 fltr->sw_id)) {
8360 bnxt_hwrm_cfa_ntuple_filter_free(bp,
8361 fltr);
8362 del = true;
8363 }
8364 } else {
8365 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
8366 fltr);
8367 if (rc)
8368 del = true;
8369 else
8370 set_bit(BNXT_FLTR_VALID, &fltr->state);
8371 }
8372
8373 if (del) {
8374 spin_lock_bh(&bp->ntp_fltr_lock);
8375 hlist_del_rcu(&fltr->hash);
8376 bp->ntp_fltr_count--;
8377 spin_unlock_bh(&bp->ntp_fltr_lock);
8378 synchronize_rcu();
8379 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
8380 kfree(fltr);
8381 }
8382 }
8383 }
8384 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
8385 netdev_info(bp->dev, "Receive PF driver unload event!");
8386 }
8387
8388 #else
8389
8390 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8391 {
8392 }
8393
8394 #endif /* CONFIG_RFS_ACCEL */
8395
8396 static void bnxt_udp_tunnel_add(struct net_device *dev,
8397 struct udp_tunnel_info *ti)
8398 {
8399 struct bnxt *bp = netdev_priv(dev);
8400
8401 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8402 return;
8403
8404 if (!netif_running(dev))
8405 return;
8406
8407 switch (ti->type) {
8408 case UDP_TUNNEL_TYPE_VXLAN:
8409 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
8410 return;
8411
8412 bp->vxlan_port_cnt++;
8413 if (bp->vxlan_port_cnt == 1) {
8414 bp->vxlan_port = ti->port;
8415 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
8416 bnxt_queue_sp_work(bp);
8417 }
8418 break;
8419 case UDP_TUNNEL_TYPE_GENEVE:
8420 if (bp->nge_port_cnt && bp->nge_port != ti->port)
8421 return;
8422
8423 bp->nge_port_cnt++;
8424 if (bp->nge_port_cnt == 1) {
8425 bp->nge_port = ti->port;
8426 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
8427 }
8428 break;
8429 default:
8430 return;
8431 }
8432
8433 bnxt_queue_sp_work(bp);
8434 }
8435
8436 static void bnxt_udp_tunnel_del(struct net_device *dev,
8437 struct udp_tunnel_info *ti)
8438 {
8439 struct bnxt *bp = netdev_priv(dev);
8440
8441 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8442 return;
8443
8444 if (!netif_running(dev))
8445 return;
8446
8447 switch (ti->type) {
8448 case UDP_TUNNEL_TYPE_VXLAN:
8449 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
8450 return;
8451 bp->vxlan_port_cnt--;
8452
8453 if (bp->vxlan_port_cnt != 0)
8454 return;
8455
8456 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
8457 break;
8458 case UDP_TUNNEL_TYPE_GENEVE:
8459 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
8460 return;
8461 bp->nge_port_cnt--;
8462
8463 if (bp->nge_port_cnt != 0)
8464 return;
8465
8466 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
8467 break;
8468 default:
8469 return;
8470 }
8471
8472 bnxt_queue_sp_work(bp);
8473 }
8474
8475 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8476 struct net_device *dev, u32 filter_mask,
8477 int nlflags)
8478 {
8479 struct bnxt *bp = netdev_priv(dev);
8480
8481 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
8482 nlflags, filter_mask, NULL);
8483 }
8484
8485 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
8486 u16 flags)
8487 {
8488 struct bnxt *bp = netdev_priv(dev);
8489 struct nlattr *attr, *br_spec;
8490 int rem, rc = 0;
8491
8492 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
8493 return -EOPNOTSUPP;
8494
8495 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8496 if (!br_spec)
8497 return -EINVAL;
8498
8499 nla_for_each_nested(attr, br_spec, rem) {
8500 u16 mode;
8501
8502 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8503 continue;
8504
8505 if (nla_len(attr) < sizeof(mode))
8506 return -EINVAL;
8507
8508 mode = nla_get_u16(attr);
8509 if (mode == bp->br_mode)
8510 break;
8511
8512 rc = bnxt_hwrm_set_br_mode(bp, mode);
8513 if (!rc)
8514 bp->br_mode = mode;
8515 break;
8516 }
8517 return rc;
8518 }
8519
8520 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
8521 size_t len)
8522 {
8523 struct bnxt *bp = netdev_priv(dev);
8524 int rc;
8525
8526 /* The PF and it's VF-reps only support the switchdev framework */
8527 if (!BNXT_PF(bp))
8528 return -EOPNOTSUPP;
8529
8530 rc = snprintf(buf, len, "p%d", bp->pf.port_id);
8531
8532 if (rc >= len)
8533 return -EOPNOTSUPP;
8534 return 0;
8535 }
8536
8537 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
8538 {
8539 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
8540 return -EOPNOTSUPP;
8541
8542 /* The PF and it's VF-reps only support the switchdev framework */
8543 if (!BNXT_PF(bp))
8544 return -EOPNOTSUPP;
8545
8546 switch (attr->id) {
8547 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
8548 attr->u.ppid.id_len = sizeof(bp->switch_id);
8549 memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len);
8550 break;
8551 default:
8552 return -EOPNOTSUPP;
8553 }
8554 return 0;
8555 }
8556
8557 static int bnxt_swdev_port_attr_get(struct net_device *dev,
8558 struct switchdev_attr *attr)
8559 {
8560 return bnxt_port_attr_get(netdev_priv(dev), attr);
8561 }
8562
8563 static const struct switchdev_ops bnxt_switchdev_ops = {
8564 .switchdev_port_attr_get = bnxt_swdev_port_attr_get
8565 };
8566
8567 static const struct net_device_ops bnxt_netdev_ops = {
8568 .ndo_open = bnxt_open,
8569 .ndo_start_xmit = bnxt_start_xmit,
8570 .ndo_stop = bnxt_close,
8571 .ndo_get_stats64 = bnxt_get_stats64,
8572 .ndo_set_rx_mode = bnxt_set_rx_mode,
8573 .ndo_do_ioctl = bnxt_ioctl,
8574 .ndo_validate_addr = eth_validate_addr,
8575 .ndo_set_mac_address = bnxt_change_mac_addr,
8576 .ndo_change_mtu = bnxt_change_mtu,
8577 .ndo_fix_features = bnxt_fix_features,
8578 .ndo_set_features = bnxt_set_features,
8579 .ndo_tx_timeout = bnxt_tx_timeout,
8580 #ifdef CONFIG_BNXT_SRIOV
8581 .ndo_get_vf_config = bnxt_get_vf_config,
8582 .ndo_set_vf_mac = bnxt_set_vf_mac,
8583 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
8584 .ndo_set_vf_rate = bnxt_set_vf_bw,
8585 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
8586 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
8587 .ndo_set_vf_trust = bnxt_set_vf_trust,
8588 #endif
8589 .ndo_setup_tc = bnxt_setup_tc,
8590 #ifdef CONFIG_RFS_ACCEL
8591 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
8592 #endif
8593 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
8594 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
8595 .ndo_bpf = bnxt_xdp,
8596 .ndo_bridge_getlink = bnxt_bridge_getlink,
8597 .ndo_bridge_setlink = bnxt_bridge_setlink,
8598 .ndo_get_phys_port_name = bnxt_get_phys_port_name
8599 };
8600
8601 static void bnxt_remove_one(struct pci_dev *pdev)
8602 {
8603 struct net_device *dev = pci_get_drvdata(pdev);
8604 struct bnxt *bp = netdev_priv(dev);
8605
8606 if (BNXT_PF(bp)) {
8607 bnxt_sriov_disable(bp);
8608 bnxt_dl_unregister(bp);
8609 }
8610
8611 pci_disable_pcie_error_reporting(pdev);
8612 unregister_netdev(dev);
8613 bnxt_shutdown_tc(bp);
8614 bnxt_cancel_sp_work(bp);
8615 bp->sp_event = 0;
8616
8617 bnxt_clear_int_mode(bp);
8618 bnxt_hwrm_func_drv_unrgtr(bp);
8619 bnxt_free_hwrm_resources(bp);
8620 bnxt_free_hwrm_short_cmd_req(bp);
8621 bnxt_ethtool_free(bp);
8622 bnxt_dcb_free(bp);
8623 kfree(bp->edev);
8624 bp->edev = NULL;
8625 bnxt_cleanup_pci(bp);
8626 free_netdev(dev);
8627 }
8628
8629 static int bnxt_probe_phy(struct bnxt *bp)
8630 {
8631 int rc = 0;
8632 struct bnxt_link_info *link_info = &bp->link_info;
8633
8634 rc = bnxt_hwrm_phy_qcaps(bp);
8635 if (rc) {
8636 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
8637 rc);
8638 return rc;
8639 }
8640 mutex_init(&bp->link_lock);
8641
8642 rc = bnxt_update_link(bp, false);
8643 if (rc) {
8644 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
8645 rc);
8646 return rc;
8647 }
8648
8649 /* Older firmware does not have supported_auto_speeds, so assume
8650 * that all supported speeds can be autonegotiated.
8651 */
8652 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
8653 link_info->support_auto_speeds = link_info->support_speeds;
8654
8655 /*initialize the ethool setting copy with NVM settings */
8656 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
8657 link_info->autoneg = BNXT_AUTONEG_SPEED;
8658 if (bp->hwrm_spec_code >= 0x10201) {
8659 if (link_info->auto_pause_setting &
8660 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
8661 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8662 } else {
8663 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8664 }
8665 link_info->advertising = link_info->auto_link_speeds;
8666 } else {
8667 link_info->req_link_speed = link_info->force_link_speed;
8668 link_info->req_duplex = link_info->duplex_setting;
8669 }
8670 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
8671 link_info->req_flow_ctrl =
8672 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
8673 else
8674 link_info->req_flow_ctrl = link_info->force_pause_setting;
8675 return rc;
8676 }
8677
8678 static int bnxt_get_max_irq(struct pci_dev *pdev)
8679 {
8680 u16 ctrl;
8681
8682 if (!pdev->msix_cap)
8683 return 1;
8684
8685 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
8686 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
8687 }
8688
8689 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8690 int *max_cp)
8691 {
8692 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8693 int max_ring_grps = 0;
8694
8695 *max_tx = hw_resc->max_tx_rings;
8696 *max_rx = hw_resc->max_rx_rings;
8697 *max_cp = min_t(int, bnxt_get_max_func_cp_rings_for_en(bp),
8698 hw_resc->max_irqs - bnxt_get_ulp_msix_num(bp));
8699 *max_cp = min_t(int, *max_cp, hw_resc->max_stat_ctxs);
8700 max_ring_grps = hw_resc->max_hw_ring_grps;
8701 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
8702 *max_cp -= 1;
8703 *max_rx -= 2;
8704 }
8705 if (bp->flags & BNXT_FLAG_AGG_RINGS)
8706 *max_rx >>= 1;
8707 *max_rx = min_t(int, *max_rx, max_ring_grps);
8708 }
8709
8710 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
8711 {
8712 int rx, tx, cp;
8713
8714 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
8715 *max_rx = rx;
8716 *max_tx = tx;
8717 if (!rx || !tx || !cp)
8718 return -ENOMEM;
8719
8720 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
8721 }
8722
8723 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8724 bool shared)
8725 {
8726 int rc;
8727
8728 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8729 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
8730 /* Not enough rings, try disabling agg rings. */
8731 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
8732 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8733 if (rc) {
8734 /* set BNXT_FLAG_AGG_RINGS back for consistency */
8735 bp->flags |= BNXT_FLAG_AGG_RINGS;
8736 return rc;
8737 }
8738 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
8739 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8740 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8741 bnxt_set_ring_params(bp);
8742 }
8743
8744 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
8745 int max_cp, max_stat, max_irq;
8746
8747 /* Reserve minimum resources for RoCE */
8748 max_cp = bnxt_get_max_func_cp_rings(bp);
8749 max_stat = bnxt_get_max_func_stat_ctxs(bp);
8750 max_irq = bnxt_get_max_func_irqs(bp);
8751 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
8752 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
8753 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
8754 return 0;
8755
8756 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
8757 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
8758 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
8759 max_cp = min_t(int, max_cp, max_irq);
8760 max_cp = min_t(int, max_cp, max_stat);
8761 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
8762 if (rc)
8763 rc = 0;
8764 }
8765 return rc;
8766 }
8767
8768 /* In initial default shared ring setting, each shared ring must have a
8769 * RX/TX ring pair.
8770 */
8771 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
8772 {
8773 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
8774 bp->rx_nr_rings = bp->cp_nr_rings;
8775 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
8776 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8777 }
8778
8779 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
8780 {
8781 int dflt_rings, max_rx_rings, max_tx_rings, rc;
8782
8783 if (!bnxt_can_reserve_rings(bp))
8784 return 0;
8785
8786 if (sh)
8787 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8788 dflt_rings = netif_get_num_default_rss_queues();
8789 /* Reduce default rings on multi-port cards so that total default
8790 * rings do not exceed CPU count.
8791 */
8792 if (bp->port_count > 1) {
8793 int max_rings =
8794 max_t(int, num_online_cpus() / bp->port_count, 1);
8795
8796 dflt_rings = min_t(int, dflt_rings, max_rings);
8797 }
8798 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
8799 if (rc)
8800 return rc;
8801 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
8802 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
8803 if (sh)
8804 bnxt_trim_dflt_sh_rings(bp);
8805 else
8806 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
8807 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8808
8809 rc = __bnxt_reserve_rings(bp);
8810 if (rc)
8811 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
8812 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8813 if (sh)
8814 bnxt_trim_dflt_sh_rings(bp);
8815
8816 /* Rings may have been trimmed, re-reserve the trimmed rings. */
8817 if (bnxt_need_reserve_rings(bp)) {
8818 rc = __bnxt_reserve_rings(bp);
8819 if (rc)
8820 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
8821 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8822 }
8823 bp->num_stat_ctxs = bp->cp_nr_rings;
8824 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8825 bp->rx_nr_rings++;
8826 bp->cp_nr_rings++;
8827 }
8828 if (rc) {
8829 bp->tx_nr_rings = 0;
8830 bp->rx_nr_rings = 0;
8831 }
8832 return rc;
8833 }
8834
8835 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
8836 {
8837 int rc;
8838
8839 if (bp->tx_nr_rings)
8840 return 0;
8841
8842 bnxt_ulp_irq_stop(bp);
8843 bnxt_clear_int_mode(bp);
8844 rc = bnxt_set_dflt_rings(bp, true);
8845 if (rc) {
8846 netdev_err(bp->dev, "Not enough rings available.\n");
8847 goto init_dflt_ring_err;
8848 }
8849 rc = bnxt_init_int_mode(bp);
8850 if (rc)
8851 goto init_dflt_ring_err;
8852
8853 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8854 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
8855 bp->flags |= BNXT_FLAG_RFS;
8856 bp->dev->features |= NETIF_F_NTUPLE;
8857 }
8858 init_dflt_ring_err:
8859 bnxt_ulp_irq_restart(bp, rc);
8860 return rc;
8861 }
8862
8863 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
8864 {
8865 int rc;
8866
8867 ASSERT_RTNL();
8868 bnxt_hwrm_func_qcaps(bp);
8869
8870 if (netif_running(bp->dev))
8871 __bnxt_close_nic(bp, true, false);
8872
8873 bnxt_ulp_irq_stop(bp);
8874 bnxt_clear_int_mode(bp);
8875 rc = bnxt_init_int_mode(bp);
8876 bnxt_ulp_irq_restart(bp, rc);
8877
8878 if (netif_running(bp->dev)) {
8879 if (rc)
8880 dev_close(bp->dev);
8881 else
8882 rc = bnxt_open_nic(bp, true, false);
8883 }
8884
8885 return rc;
8886 }
8887
8888 static int bnxt_init_mac_addr(struct bnxt *bp)
8889 {
8890 int rc = 0;
8891
8892 if (BNXT_PF(bp)) {
8893 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
8894 } else {
8895 #ifdef CONFIG_BNXT_SRIOV
8896 struct bnxt_vf_info *vf = &bp->vf;
8897 bool strict_approval = true;
8898
8899 if (is_valid_ether_addr(vf->mac_addr)) {
8900 /* overwrite netdev dev_addr with admin VF MAC */
8901 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
8902 /* Older PF driver or firmware may not approve this
8903 * correctly.
8904 */
8905 strict_approval = false;
8906 } else {
8907 eth_hw_addr_random(bp->dev);
8908 }
8909 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
8910 #endif
8911 }
8912 return rc;
8913 }
8914
8915 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8916 {
8917 static int version_printed;
8918 struct net_device *dev;
8919 struct bnxt *bp;
8920 int rc, max_irqs;
8921
8922 if (pci_is_bridge(pdev))
8923 return -ENODEV;
8924
8925 if (version_printed++ == 0)
8926 pr_info("%s", version);
8927
8928 max_irqs = bnxt_get_max_irq(pdev);
8929 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
8930 if (!dev)
8931 return -ENOMEM;
8932
8933 bp = netdev_priv(dev);
8934
8935 if (bnxt_vf_pciid(ent->driver_data))
8936 bp->flags |= BNXT_FLAG_VF;
8937
8938 if (pdev->msix_cap)
8939 bp->flags |= BNXT_FLAG_MSIX_CAP;
8940
8941 rc = bnxt_init_board(pdev, dev);
8942 if (rc < 0)
8943 goto init_err_free;
8944
8945 dev->netdev_ops = &bnxt_netdev_ops;
8946 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8947 dev->ethtool_ops = &bnxt_ethtool_ops;
8948 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
8949 pci_set_drvdata(pdev, dev);
8950
8951 rc = bnxt_alloc_hwrm_resources(bp);
8952 if (rc)
8953 goto init_err_pci_clean;
8954
8955 mutex_init(&bp->hwrm_cmd_lock);
8956 rc = bnxt_hwrm_ver_get(bp);
8957 if (rc)
8958 goto init_err_pci_clean;
8959
8960 if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) {
8961 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8962 if (rc)
8963 goto init_err_pci_clean;
8964 }
8965
8966 rc = bnxt_hwrm_func_reset(bp);
8967 if (rc)
8968 goto init_err_pci_clean;
8969
8970 bnxt_hwrm_fw_set_time(bp);
8971
8972 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8973 NETIF_F_TSO | NETIF_F_TSO6 |
8974 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8975 NETIF_F_GSO_IPXIP4 |
8976 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8977 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
8978 NETIF_F_RXCSUM | NETIF_F_GRO;
8979
8980 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8981 dev->hw_features |= NETIF_F_LRO;
8982
8983 dev->hw_enc_features =
8984 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8985 NETIF_F_TSO | NETIF_F_TSO6 |
8986 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8987 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8988 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
8989 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
8990 NETIF_F_GSO_GRE_CSUM;
8991 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
8992 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
8993 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
8994 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8995 dev->hw_features |= NETIF_F_GRO_HW;
8996 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
8997 if (dev->features & NETIF_F_GRO_HW)
8998 dev->features &= ~NETIF_F_LRO;
8999 dev->priv_flags |= IFF_UNICAST_FLT;
9000
9001 #ifdef CONFIG_BNXT_SRIOV
9002 init_waitqueue_head(&bp->sriov_cfg_wait);
9003 mutex_init(&bp->sriov_lock);
9004 #endif
9005 bp->gro_func = bnxt_gro_func_5730x;
9006 if (BNXT_CHIP_P4_PLUS(bp))
9007 bp->gro_func = bnxt_gro_func_5731x;
9008 else
9009 bp->flags |= BNXT_FLAG_DOUBLE_DB;
9010
9011 rc = bnxt_hwrm_func_drv_rgtr(bp);
9012 if (rc)
9013 goto init_err_pci_clean;
9014
9015 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
9016 if (rc)
9017 goto init_err_pci_clean;
9018
9019 bp->ulp_probe = bnxt_ulp_probe;
9020
9021 /* Get the MAX capabilities for this function */
9022 rc = bnxt_hwrm_func_qcaps(bp);
9023 if (rc) {
9024 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
9025 rc);
9026 rc = -1;
9027 goto init_err_pci_clean;
9028 }
9029 rc = bnxt_init_mac_addr(bp);
9030 if (rc) {
9031 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
9032 rc = -EADDRNOTAVAIL;
9033 goto init_err_pci_clean;
9034 }
9035 rc = bnxt_hwrm_queue_qportcfg(bp);
9036 if (rc) {
9037 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
9038 rc);
9039 rc = -1;
9040 goto init_err_pci_clean;
9041 }
9042
9043 bnxt_hwrm_func_qcfg(bp);
9044 bnxt_hwrm_port_led_qcaps(bp);
9045 bnxt_ethtool_init(bp);
9046 bnxt_dcb_init(bp);
9047
9048 /* MTU range: 60 - FW defined max */
9049 dev->min_mtu = ETH_ZLEN;
9050 dev->max_mtu = bp->max_mtu;
9051
9052 rc = bnxt_probe_phy(bp);
9053 if (rc)
9054 goto init_err_pci_clean;
9055
9056 bnxt_set_rx_skb_mode(bp, false);
9057 bnxt_set_tpa_flags(bp);
9058 bnxt_set_ring_params(bp);
9059 bnxt_set_max_func_irqs(bp, max_irqs);
9060 rc = bnxt_set_dflt_rings(bp, true);
9061 if (rc) {
9062 netdev_err(bp->dev, "Not enough rings available.\n");
9063 rc = -ENOMEM;
9064 goto init_err_pci_clean;
9065 }
9066
9067 /* Default RSS hash cfg. */
9068 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
9069 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
9070 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
9071 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
9072 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
9073 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
9074 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
9075 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
9076 }
9077
9078 bnxt_hwrm_vnic_qcaps(bp);
9079 if (bnxt_rfs_supported(bp)) {
9080 dev->hw_features |= NETIF_F_NTUPLE;
9081 if (bnxt_rfs_capable(bp)) {
9082 bp->flags |= BNXT_FLAG_RFS;
9083 dev->features |= NETIF_F_NTUPLE;
9084 }
9085 }
9086
9087 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
9088 bp->flags |= BNXT_FLAG_STRIP_VLAN;
9089
9090 rc = bnxt_init_int_mode(bp);
9091 if (rc)
9092 goto init_err_pci_clean;
9093
9094 /* No TC has been set yet and rings may have been trimmed due to
9095 * limited MSIX, so we re-initialize the TX rings per TC.
9096 */
9097 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9098
9099 bnxt_get_wol_settings(bp);
9100 if (bp->flags & BNXT_FLAG_WOL_CAP)
9101 device_set_wakeup_enable(&pdev->dev, bp->wol);
9102 else
9103 device_set_wakeup_capable(&pdev->dev, false);
9104
9105 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
9106
9107 if (BNXT_PF(bp)) {
9108 if (!bnxt_pf_wq) {
9109 bnxt_pf_wq =
9110 create_singlethread_workqueue("bnxt_pf_wq");
9111 if (!bnxt_pf_wq) {
9112 dev_err(&pdev->dev, "Unable to create workqueue.\n");
9113 goto init_err_pci_clean;
9114 }
9115 }
9116 bnxt_init_tc(bp);
9117 }
9118
9119 rc = register_netdev(dev);
9120 if (rc)
9121 goto init_err_cleanup_tc;
9122
9123 if (BNXT_PF(bp))
9124 bnxt_dl_register(bp);
9125
9126 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
9127 board_info[ent->driver_data].name,
9128 (long)pci_resource_start(pdev, 0), dev->dev_addr);
9129 pcie_print_link_status(pdev);
9130
9131 return 0;
9132
9133 init_err_cleanup_tc:
9134 bnxt_shutdown_tc(bp);
9135 bnxt_clear_int_mode(bp);
9136
9137 init_err_pci_clean:
9138 bnxt_free_hwrm_short_cmd_req(bp);
9139 bnxt_free_hwrm_resources(bp);
9140 bnxt_cleanup_pci(bp);
9141
9142 init_err_free:
9143 free_netdev(dev);
9144 return rc;
9145 }
9146
9147 static void bnxt_shutdown(struct pci_dev *pdev)
9148 {
9149 struct net_device *dev = pci_get_drvdata(pdev);
9150 struct bnxt *bp;
9151
9152 if (!dev)
9153 return;
9154
9155 rtnl_lock();
9156 bp = netdev_priv(dev);
9157 if (!bp)
9158 goto shutdown_exit;
9159
9160 if (netif_running(dev))
9161 dev_close(dev);
9162
9163 bnxt_ulp_shutdown(bp);
9164
9165 if (system_state == SYSTEM_POWER_OFF) {
9166 bnxt_clear_int_mode(bp);
9167 pci_wake_from_d3(pdev, bp->wol);
9168 pci_set_power_state(pdev, PCI_D3hot);
9169 }
9170
9171 shutdown_exit:
9172 rtnl_unlock();
9173 }
9174
9175 #ifdef CONFIG_PM_SLEEP
9176 static int bnxt_suspend(struct device *device)
9177 {
9178 struct pci_dev *pdev = to_pci_dev(device);
9179 struct net_device *dev = pci_get_drvdata(pdev);
9180 struct bnxt *bp = netdev_priv(dev);
9181 int rc = 0;
9182
9183 rtnl_lock();
9184 if (netif_running(dev)) {
9185 netif_device_detach(dev);
9186 rc = bnxt_close(dev);
9187 }
9188 bnxt_hwrm_func_drv_unrgtr(bp);
9189 rtnl_unlock();
9190 return rc;
9191 }
9192
9193 static int bnxt_resume(struct device *device)
9194 {
9195 struct pci_dev *pdev = to_pci_dev(device);
9196 struct net_device *dev = pci_get_drvdata(pdev);
9197 struct bnxt *bp = netdev_priv(dev);
9198 int rc = 0;
9199
9200 rtnl_lock();
9201 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
9202 rc = -ENODEV;
9203 goto resume_exit;
9204 }
9205 rc = bnxt_hwrm_func_reset(bp);
9206 if (rc) {
9207 rc = -EBUSY;
9208 goto resume_exit;
9209 }
9210 bnxt_get_wol_settings(bp);
9211 if (netif_running(dev)) {
9212 rc = bnxt_open(dev);
9213 if (!rc)
9214 netif_device_attach(dev);
9215 }
9216
9217 resume_exit:
9218 rtnl_unlock();
9219 return rc;
9220 }
9221
9222 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
9223 #define BNXT_PM_OPS (&bnxt_pm_ops)
9224
9225 #else
9226
9227 #define BNXT_PM_OPS NULL
9228
9229 #endif /* CONFIG_PM_SLEEP */
9230
9231 /**
9232 * bnxt_io_error_detected - called when PCI error is detected
9233 * @pdev: Pointer to PCI device
9234 * @state: The current pci connection state
9235 *
9236 * This function is called after a PCI bus error affecting
9237 * this device has been detected.
9238 */
9239 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
9240 pci_channel_state_t state)
9241 {
9242 struct net_device *netdev = pci_get_drvdata(pdev);
9243 struct bnxt *bp = netdev_priv(netdev);
9244
9245 netdev_info(netdev, "PCI I/O error detected\n");
9246
9247 rtnl_lock();
9248 netif_device_detach(netdev);
9249
9250 bnxt_ulp_stop(bp);
9251
9252 if (state == pci_channel_io_perm_failure) {
9253 rtnl_unlock();
9254 return PCI_ERS_RESULT_DISCONNECT;
9255 }
9256
9257 if (netif_running(netdev))
9258 bnxt_close(netdev);
9259
9260 pci_disable_device(pdev);
9261 rtnl_unlock();
9262
9263 /* Request a slot slot reset. */
9264 return PCI_ERS_RESULT_NEED_RESET;
9265 }
9266
9267 /**
9268 * bnxt_io_slot_reset - called after the pci bus has been reset.
9269 * @pdev: Pointer to PCI device
9270 *
9271 * Restart the card from scratch, as if from a cold-boot.
9272 * At this point, the card has exprienced a hard reset,
9273 * followed by fixups by BIOS, and has its config space
9274 * set up identically to what it was at cold boot.
9275 */
9276 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
9277 {
9278 struct net_device *netdev = pci_get_drvdata(pdev);
9279 struct bnxt *bp = netdev_priv(netdev);
9280 int err = 0;
9281 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
9282
9283 netdev_info(bp->dev, "PCI Slot Reset\n");
9284
9285 rtnl_lock();
9286
9287 if (pci_enable_device(pdev)) {
9288 dev_err(&pdev->dev,
9289 "Cannot re-enable PCI device after reset.\n");
9290 } else {
9291 pci_set_master(pdev);
9292
9293 err = bnxt_hwrm_func_reset(bp);
9294 if (!err && netif_running(netdev))
9295 err = bnxt_open(netdev);
9296
9297 if (!err) {
9298 result = PCI_ERS_RESULT_RECOVERED;
9299 bnxt_ulp_start(bp);
9300 }
9301 }
9302
9303 if (result != PCI_ERS_RESULT_RECOVERED) {
9304 if (netif_running(netdev))
9305 dev_close(netdev);
9306 pci_disable_device(pdev);
9307 }
9308
9309 rtnl_unlock();
9310
9311 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9312 if (err) {
9313 dev_err(&pdev->dev,
9314 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9315 err); /* non-fatal, continue */
9316 }
9317
9318 return result;
9319 }
9320
9321 /**
9322 * bnxt_io_resume - called when traffic can start flowing again.
9323 * @pdev: Pointer to PCI device
9324 *
9325 * This callback is called when the error recovery driver tells
9326 * us that its OK to resume normal operation.
9327 */
9328 static void bnxt_io_resume(struct pci_dev *pdev)
9329 {
9330 struct net_device *netdev = pci_get_drvdata(pdev);
9331
9332 rtnl_lock();
9333
9334 netif_device_attach(netdev);
9335
9336 rtnl_unlock();
9337 }
9338
9339 static const struct pci_error_handlers bnxt_err_handler = {
9340 .error_detected = bnxt_io_error_detected,
9341 .slot_reset = bnxt_io_slot_reset,
9342 .resume = bnxt_io_resume
9343 };
9344
9345 static struct pci_driver bnxt_pci_driver = {
9346 .name = DRV_MODULE_NAME,
9347 .id_table = bnxt_pci_tbl,
9348 .probe = bnxt_init_one,
9349 .remove = bnxt_remove_one,
9350 .shutdown = bnxt_shutdown,
9351 .driver.pm = BNXT_PM_OPS,
9352 .err_handler = &bnxt_err_handler,
9353 #if defined(CONFIG_BNXT_SRIOV)
9354 .sriov_configure = bnxt_sriov_configure,
9355 #endif
9356 };
9357
9358 static int __init bnxt_init(void)
9359 {
9360 bnxt_debug_init();
9361 return pci_register_driver(&bnxt_pci_driver);
9362 }
9363
9364 static void __exit bnxt_exit(void)
9365 {
9366 pci_unregister_driver(&bnxt_pci_driver);
9367 if (bnxt_pf_wq)
9368 destroy_workqueue(bnxt_pf_wq);
9369 bnxt_debug_exit();
9370 }
9371
9372 module_init(bnxt_init);
9373 module_exit(bnxt_exit);
Linux with added FPC-III support