drivers/net/ethernet/broadcom/genet/bcmgenet.h

   1 /*
   2  * Copyright (c) 2014-2017 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef __BCMGENET_H__
  10 #define __BCMGENET_H__
  11
  12 #include <linux/skbuff.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/clk.h>
  16 #include <linux/mii.h>
  17 #include <linux/if_vlan.h>
  18 #include <linux/phy.h>
  19 #include <linux/net_dim.h>
  20
  21 /* total number of Buffer Descriptors, same for Rx/Tx */
  22 #define TOTAL_DESC                              256
  23
  24 /* which ring is descriptor based */
  25 #define DESC_INDEX                              16
  26
  27 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
  28  * 1536 is multiple of 256 bytes
  29  */
  30 #define ENET_BRCM_TAG_LEN       6
  31 #define ENET_PAD                8
  32 #define ENET_MAX_MTU_SIZE       (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
  33                                  ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
  34 #define DMA_MAX_BURST_LENGTH    0x10
  35
  36 /* misc. configuration */
  37 #define CLEAR_ALL_HFB                   0xFF
  38 #define DMA_FC_THRESH_HI                (TOTAL_DESC >> 4)
  39 #define DMA_FC_THRESH_LO                5
  40
  41 /* 64B receive/transmit status block */
  42 struct status_64 {
  43         u32     length_status;          /* length and peripheral status */
  44         u32     ext_status;             /* Extended status*/
  45         u32     rx_csum;                /* partial rx checksum */
  46         u32     unused1[9];             /* unused */
  47         u32     tx_csum_info;           /* Tx checksum info. */
  48         u32     unused2[3];             /* unused */
  49 };
  50
  51 /* Rx status bits */
  52 #define STATUS_RX_EXT_MASK              0x1FFFFF
  53 #define STATUS_RX_CSUM_MASK             0xFFFF
  54 #define STATUS_RX_CSUM_OK               0x10000
  55 #define STATUS_RX_CSUM_FR               0x20000
  56 #define STATUS_RX_PROTO_TCP             0
  57 #define STATUS_RX_PROTO_UDP             1
  58 #define STATUS_RX_PROTO_ICMP            2
  59 #define STATUS_RX_PROTO_OTHER           3
  60 #define STATUS_RX_PROTO_MASK            3
  61 #define STATUS_RX_PROTO_SHIFT           18
  62 #define STATUS_FILTER_INDEX_MASK        0xFFFF
  63 /* Tx status bits */
  64 #define STATUS_TX_CSUM_START_MASK       0X7FFF
  65 #define STATUS_TX_CSUM_START_SHIFT      16
  66 #define STATUS_TX_CSUM_PROTO_UDP        0x8000
  67 #define STATUS_TX_CSUM_OFFSET_MASK      0x7FFF
  68 #define STATUS_TX_CSUM_LV               0x80000000
  69
  70 /* DMA Descriptor */
  71 #define DMA_DESC_LENGTH_STATUS  0x00    /* in bytes of data in buffer */
  72 #define DMA_DESC_ADDRESS_LO     0x04    /* lower bits of PA */
  73 #define DMA_DESC_ADDRESS_HI     0x08    /* upper 32 bits of PA, GENETv4+ */
  74
  75 /* Rx/Tx common counter group */
  76 struct bcmgenet_pkt_counters {
  77         u32     cnt_64;         /* RO Received/Transmited 64 bytes packet */
  78         u32     cnt_127;        /* RO Rx/Tx 127 bytes packet */
  79         u32     cnt_255;        /* RO Rx/Tx 65-255 bytes packet */
  80         u32     cnt_511;        /* RO Rx/Tx 256-511 bytes packet */
  81         u32     cnt_1023;       /* RO Rx/Tx 512-1023 bytes packet */
  82         u32     cnt_1518;       /* RO Rx/Tx 1024-1518 bytes packet */
  83         u32     cnt_mgv;        /* RO Rx/Tx 1519-1522 good VLAN packet */
  84         u32     cnt_2047;       /* RO Rx/Tx 1522-2047 bytes packet*/
  85         u32     cnt_4095;       /* RO Rx/Tx 2048-4095 bytes packet*/
  86         u32     cnt_9216;       /* RO Rx/Tx 4096-9216 bytes packet*/
  87 };
  88
  89 /* RSV, Receive Status Vector */
  90 struct bcmgenet_rx_counters {
  91         struct  bcmgenet_pkt_counters pkt_cnt;
  92         u32     pkt;            /* RO (0x428) Received pkt count*/
  93         u32     bytes;          /* RO Received byte count */
  94         u32     mca;            /* RO # of Received multicast pkt */
  95         u32     bca;            /* RO # of Receive broadcast pkt */
  96         u32     fcs;            /* RO # of Received FCS error  */
  97         u32     cf;             /* RO # of Received control frame pkt*/
  98         u32     pf;             /* RO # of Received pause frame pkt */
  99         u32     uo;             /* RO # of unknown op code pkt */
 100         u32     aln;            /* RO # of alignment error count */
 101         u32     flr;            /* RO # of frame length out of range count */
 102         u32     cde;            /* RO # of code error pkt */
 103         u32     fcr;            /* RO # of carrier sense error pkt */
 104         u32     ovr;            /* RO # of oversize pkt*/
 105         u32     jbr;            /* RO # of jabber count */
 106         u32     mtue;           /* RO # of MTU error pkt*/
 107         u32     pok;            /* RO # of Received good pkt */
 108         u32     uc;             /* RO # of unicast pkt */
 109         u32     ppp;            /* RO # of PPP pkt */
 110         u32     rcrc;           /* RO (0x470),# of CRC match pkt */
 111 };
 112
 113 /* TSV, Transmit Status Vector */
 114 struct bcmgenet_tx_counters {
 115         struct bcmgenet_pkt_counters pkt_cnt;
 116         u32     pkts;           /* RO (0x4a8) Transmited pkt */
 117         u32     mca;            /* RO # of xmited multicast pkt */
 118         u32     bca;            /* RO # of xmited broadcast pkt */
 119         u32     pf;             /* RO # of xmited pause frame count */
 120         u32     cf;             /* RO # of xmited control frame count */
 121         u32     fcs;            /* RO # of xmited FCS error count */
 122         u32     ovr;            /* RO # of xmited oversize pkt */
 123         u32     drf;            /* RO # of xmited deferral pkt */
 124         u32     edf;            /* RO # of xmited Excessive deferral pkt*/
 125         u32     scl;            /* RO # of xmited single collision pkt */
 126         u32     mcl;            /* RO # of xmited multiple collision pkt*/
 127         u32     lcl;            /* RO # of xmited late collision pkt */
 128         u32     ecl;            /* RO # of xmited excessive collision pkt*/
 129         u32     frg;            /* RO # of xmited fragments pkt*/
 130         u32     ncl;            /* RO # of xmited total collision count */
 131         u32     jbr;            /* RO # of xmited jabber count*/
 132         u32     bytes;          /* RO # of xmited byte count */
 133         u32     pok;            /* RO # of xmited good pkt */
 134         u32     uc;             /* RO (0x0x4f0)# of xmited unitcast pkt */
 135 };
 136
 137 struct bcmgenet_mib_counters {
 138         struct bcmgenet_rx_counters rx;
 139         struct bcmgenet_tx_counters tx;
 140         u32     rx_runt_cnt;
 141         u32     rx_runt_fcs;
 142         u32     rx_runt_fcs_align;
 143         u32     rx_runt_bytes;
 144         u32     rbuf_ovflow_cnt;
 145         u32     rbuf_err_cnt;
 146         u32     mdf_err_cnt;
 147         u32     alloc_rx_buff_failed;
 148         u32     rx_dma_failed;
 149         u32     tx_dma_failed;
 150 };
 151
 152 #define UMAC_HD_BKP_CTRL                0x004
 153 #define  HD_FC_EN                       (1 << 0)
 154 #define  HD_FC_BKOFF_OK                 (1 << 1)
 155 #define  IPG_CONFIG_RX_SHIFT            2
 156 #define  IPG_CONFIG_RX_MASK             0x1F
 157
 158 #define UMAC_CMD                        0x008
 159 #define  CMD_TX_EN                      (1 << 0)
 160 #define  CMD_RX_EN                      (1 << 1)
 161 #define  UMAC_SPEED_10                  0
 162 #define  UMAC_SPEED_100                 1
 163 #define  UMAC_SPEED_1000                2
 164 #define  UMAC_SPEED_2500                3
 165 #define  CMD_SPEED_SHIFT                2
 166 #define  CMD_SPEED_MASK                 3
 167 #define  CMD_PROMISC                    (1 << 4)
 168 #define  CMD_PAD_EN                     (1 << 5)
 169 #define  CMD_CRC_FWD                    (1 << 6)
 170 #define  CMD_PAUSE_FWD                  (1 << 7)
 171 #define  CMD_RX_PAUSE_IGNORE            (1 << 8)
 172 #define  CMD_TX_ADDR_INS                (1 << 9)
 173 #define  CMD_HD_EN                      (1 << 10)
 174 #define  CMD_SW_RESET                   (1 << 13)
 175 #define  CMD_LCL_LOOP_EN                (1 << 15)
 176 #define  CMD_AUTO_CONFIG                (1 << 22)
 177 #define  CMD_CNTL_FRM_EN                (1 << 23)
 178 #define  CMD_NO_LEN_CHK                 (1 << 24)
 179 #define  CMD_RMT_LOOP_EN                (1 << 25)
 180 #define  CMD_PRBL_EN                    (1 << 27)
 181 #define  CMD_TX_PAUSE_IGNORE            (1 << 28)
 182 #define  CMD_TX_RX_EN                   (1 << 29)
 183 #define  CMD_RUNT_FILTER_DIS            (1 << 30)
 184
 185 #define UMAC_MAC0                       0x00C
 186 #define UMAC_MAC1                       0x010
 187 #define UMAC_MAX_FRAME_LEN              0x014
 188
 189 #define UMAC_MODE                       0x44
 190 #define  MODE_LINK_STATUS               (1 << 5)
 191
 192 #define UMAC_EEE_CTRL                   0x064
 193 #define  EN_LPI_RX_PAUSE                (1 << 0)
 194 #define  EN_LPI_TX_PFC                  (1 << 1)
 195 #define  EN_LPI_TX_PAUSE                (1 << 2)
 196 #define  EEE_EN                         (1 << 3)
 197 #define  RX_FIFO_CHECK                  (1 << 4)
 198 #define  EEE_TX_CLK_DIS                 (1 << 5)
 199 #define  DIS_EEE_10M                    (1 << 6)
 200 #define  LP_IDLE_PREDICTION_MODE        (1 << 7)
 201
 202 #define UMAC_EEE_LPI_TIMER              0x068
 203 #define UMAC_EEE_WAKE_TIMER             0x06C
 204 #define UMAC_EEE_REF_COUNT              0x070
 205 #define  EEE_REFERENCE_COUNT_MASK       0xffff
 206
 207 #define UMAC_TX_FLUSH                   0x334
 208
 209 #define UMAC_MIB_START                  0x400
 210
 211 #define UMAC_MDIO_CMD                   0x614
 212 #define  MDIO_START_BUSY                (1 << 29)
 213 #define  MDIO_READ_FAIL                 (1 << 28)
 214 #define  MDIO_RD                        (2 << 26)
 215 #define  MDIO_WR                        (1 << 26)
 216 #define  MDIO_PMD_SHIFT                 21
 217 #define  MDIO_PMD_MASK                  0x1F
 218 #define  MDIO_REG_SHIFT                 16
 219 #define  MDIO_REG_MASK                  0x1F
 220
 221 #define UMAC_RBUF_OVFL_CNT_V1           0x61C
 222 #define RBUF_OVFL_CNT_V2                0x80
 223 #define RBUF_OVFL_CNT_V3PLUS            0x94
 224
 225 #define UMAC_MPD_CTRL                   0x620
 226 #define  MPD_EN                         (1 << 0)
 227 #define  MPD_PW_EN                      (1 << 27)
 228 #define  MPD_MSEQ_LEN_SHIFT             16
 229 #define  MPD_MSEQ_LEN_MASK              0xFF
 230
 231 #define UMAC_MPD_PW_MS                  0x624
 232 #define UMAC_MPD_PW_LS                  0x628
 233 #define UMAC_RBUF_ERR_CNT_V1            0x634
 234 #define RBUF_ERR_CNT_V2                 0x84
 235 #define RBUF_ERR_CNT_V3PLUS             0x98
 236 #define UMAC_MDF_ERR_CNT                0x638
 237 #define UMAC_MDF_CTRL                   0x650
 238 #define UMAC_MDF_ADDR                   0x654
 239 #define UMAC_MIB_CTRL                   0x580
 240 #define  MIB_RESET_RX                   (1 << 0)
 241 #define  MIB_RESET_RUNT                 (1 << 1)
 242 #define  MIB_RESET_TX                   (1 << 2)
 243
 244 #define RBUF_CTRL                       0x00
 245 #define  RBUF_64B_EN                    (1 << 0)
 246 #define  RBUF_ALIGN_2B                  (1 << 1)
 247 #define  RBUF_BAD_DIS                   (1 << 2)
 248
 249 #define RBUF_STATUS                     0x0C
 250 #define  RBUF_STATUS_WOL                (1 << 0)
 251 #define  RBUF_STATUS_MPD_INTR_ACTIVE    (1 << 1)
 252 #define  RBUF_STATUS_ACPI_INTR_ACTIVE   (1 << 2)
 253
 254 #define RBUF_CHK_CTRL                   0x14
 255 #define  RBUF_RXCHK_EN                  (1 << 0)
 256 #define  RBUF_SKIP_FCS                  (1 << 4)
 257
 258 #define RBUF_ENERGY_CTRL                0x9c
 259 #define  RBUF_EEE_EN                    (1 << 0)
 260 #define  RBUF_PM_EN                     (1 << 1)
 261
 262 #define RBUF_TBUF_SIZE_CTRL             0xb4
 263
 264 #define RBUF_HFB_CTRL_V1                0x38
 265 #define  RBUF_HFB_FILTER_EN_SHIFT       16
 266 #define  RBUF_HFB_FILTER_EN_MASK        0xffff0000
 267 #define  RBUF_HFB_EN                    (1 << 0)
 268 #define  RBUF_HFB_256B                  (1 << 1)
 269 #define  RBUF_ACPI_EN                   (1 << 2)
 270
 271 #define RBUF_HFB_LEN_V1                 0x3C
 272 #define  RBUF_FLTR_LEN_MASK             0xFF
 273 #define  RBUF_FLTR_LEN_SHIFT            8
 274
 275 #define TBUF_CTRL                       0x00
 276 #define TBUF_BP_MC                      0x0C
 277 #define TBUF_ENERGY_CTRL                0x14
 278 #define  TBUF_EEE_EN                    (1 << 0)
 279 #define  TBUF_PM_EN                     (1 << 1)
 280
 281 #define TBUF_CTRL_V1                    0x80
 282 #define TBUF_BP_MC_V1                   0xA0
 283
 284 #define HFB_CTRL                        0x00
 285 #define HFB_FLT_ENABLE_V3PLUS           0x04
 286 #define HFB_FLT_LEN_V2                  0x04
 287 #define HFB_FLT_LEN_V3PLUS              0x1C
 288
 289 /* uniMac intrl2 registers */
 290 #define INTRL2_CPU_STAT                 0x00
 291 #define INTRL2_CPU_SET                  0x04
 292 #define INTRL2_CPU_CLEAR                0x08
 293 #define INTRL2_CPU_MASK_STATUS          0x0C
 294 #define INTRL2_CPU_MASK_SET             0x10
 295 #define INTRL2_CPU_MASK_CLEAR           0x14
 296
 297 /* INTRL2 instance 0 definitions */
 298 #define UMAC_IRQ_SCB                    (1 << 0)
 299 #define UMAC_IRQ_EPHY                   (1 << 1)
 300 #define UMAC_IRQ_PHY_DET_R              (1 << 2)
 301 #define UMAC_IRQ_PHY_DET_F              (1 << 3)
 302 #define UMAC_IRQ_LINK_UP                (1 << 4)
 303 #define UMAC_IRQ_LINK_DOWN              (1 << 5)
 304 #define UMAC_IRQ_LINK_EVENT             (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN)
 305 #define UMAC_IRQ_UMAC                   (1 << 6)
 306 #define UMAC_IRQ_UMAC_TSV               (1 << 7)
 307 #define UMAC_IRQ_TBUF_UNDERRUN          (1 << 8)
 308 #define UMAC_IRQ_RBUF_OVERFLOW          (1 << 9)
 309 #define UMAC_IRQ_HFB_SM                 (1 << 10)
 310 #define UMAC_IRQ_HFB_MM                 (1 << 11)
 311 #define UMAC_IRQ_MPD_R                  (1 << 12)
 312 #define UMAC_IRQ_RXDMA_MBDONE           (1 << 13)
 313 #define UMAC_IRQ_RXDMA_PDONE            (1 << 14)
 314 #define UMAC_IRQ_RXDMA_BDONE            (1 << 15)
 315 #define UMAC_IRQ_RXDMA_DONE             UMAC_IRQ_RXDMA_MBDONE
 316 #define UMAC_IRQ_TXDMA_MBDONE           (1 << 16)
 317 #define UMAC_IRQ_TXDMA_PDONE            (1 << 17)
 318 #define UMAC_IRQ_TXDMA_BDONE            (1 << 18)
 319 #define UMAC_IRQ_TXDMA_DONE             UMAC_IRQ_TXDMA_MBDONE
 320
 321 /* Only valid for GENETv3+ */
 322 #define UMAC_IRQ_MDIO_DONE              (1 << 23)
 323 #define UMAC_IRQ_MDIO_ERROR             (1 << 24)
 324
 325 /* INTRL2 instance 1 definitions */
 326 #define UMAC_IRQ1_TX_INTR_MASK          0xFFFF
 327 #define UMAC_IRQ1_RX_INTR_MASK          0xFFFF
 328 #define UMAC_IRQ1_RX_INTR_SHIFT         16
 329
 330 /* Register block offsets */
 331 #define GENET_SYS_OFF                   0x0000
 332 #define GENET_GR_BRIDGE_OFF             0x0040
 333 #define GENET_EXT_OFF                   0x0080
 334 #define GENET_INTRL2_0_OFF              0x0200
 335 #define GENET_INTRL2_1_OFF              0x0240
 336 #define GENET_RBUF_OFF                  0x0300
 337 #define GENET_UMAC_OFF                  0x0800
 338
 339 /* SYS block offsets and register definitions */
 340 #define SYS_REV_CTRL                    0x00
 341 #define SYS_PORT_CTRL                   0x04
 342 #define  PORT_MODE_INT_EPHY             0
 343 #define  PORT_MODE_INT_GPHY             1
 344 #define  PORT_MODE_EXT_EPHY             2
 345 #define  PORT_MODE_EXT_GPHY             3
 346 #define  PORT_MODE_EXT_RVMII_25         (4 | BIT(4))
 347 #define  PORT_MODE_EXT_RVMII_50         4
 348 #define  LED_ACT_SOURCE_MAC             (1 << 9)
 349
 350 #define SYS_RBUF_FLUSH_CTRL             0x08
 351 #define SYS_TBUF_FLUSH_CTRL             0x0C
 352 #define RBUF_FLUSH_CTRL_V1              0x04
 353
 354 /* Ext block register offsets and definitions */
 355 #define EXT_EXT_PWR_MGMT                0x00
 356 #define  EXT_PWR_DOWN_BIAS              (1 << 0)
 357 #define  EXT_PWR_DOWN_DLL               (1 << 1)
 358 #define  EXT_PWR_DOWN_PHY               (1 << 2)
 359 #define  EXT_PWR_DN_EN_LD               (1 << 3)
 360 #define  EXT_ENERGY_DET                 (1 << 4)
 361 #define  EXT_IDDQ_FROM_PHY              (1 << 5)
 362 #define  EXT_IDDQ_GLBL_PWR              (1 << 7)
 363 #define  EXT_PHY_RESET                  (1 << 8)
 364 #define  EXT_ENERGY_DET_MASK            (1 << 12)
 365 #define  EXT_PWR_DOWN_PHY_TX            (1 << 16)
 366 #define  EXT_PWR_DOWN_PHY_RX            (1 << 17)
 367 #define  EXT_PWR_DOWN_PHY_SD            (1 << 18)
 368 #define  EXT_PWR_DOWN_PHY_RD            (1 << 19)
 369 #define  EXT_PWR_DOWN_PHY_EN            (1 << 20)
 370
 371 #define EXT_RGMII_OOB_CTRL              0x0C
 372 #define  RGMII_MODE_EN_V123             (1 << 0)
 373 #define  RGMII_LINK                     (1 << 4)
 374 #define  OOB_DISABLE                    (1 << 5)
 375 #define  RGMII_MODE_EN                  (1 << 6)
 376 #define  ID_MODE_DIS                    (1 << 16)
 377
 378 #define EXT_GPHY_CTRL                   0x1C
 379 #define  EXT_CFG_IDDQ_BIAS              (1 << 0)
 380 #define  EXT_CFG_PWR_DOWN               (1 << 1)
 381 #define  EXT_CK25_DIS                   (1 << 4)
 382 #define  EXT_GPHY_RESET                 (1 << 5)
 383
 384 /* DMA rings size */
 385 #define DMA_RING_SIZE                   (0x40)
 386 #define DMA_RINGS_SIZE                  (DMA_RING_SIZE * (DESC_INDEX + 1))
 387
 388 /* DMA registers common definitions */
 389 #define DMA_RW_POINTER_MASK             0x1FF
 390 #define DMA_P_INDEX_DISCARD_CNT_MASK    0xFFFF
 391 #define DMA_P_INDEX_DISCARD_CNT_SHIFT   16
 392 #define DMA_BUFFER_DONE_CNT_MASK        0xFFFF
 393 #define DMA_BUFFER_DONE_CNT_SHIFT       16
 394 #define DMA_P_INDEX_MASK                0xFFFF
 395 #define DMA_C_INDEX_MASK                0xFFFF
 396
 397 /* DMA ring size register */
 398 #define DMA_RING_SIZE_MASK              0xFFFF
 399 #define DMA_RING_SIZE_SHIFT             16
 400 #define DMA_RING_BUFFER_SIZE_MASK       0xFFFF
 401
 402 /* DMA interrupt threshold register */
 403 #define DMA_INTR_THRESHOLD_MASK         0x01FF
 404
 405 /* DMA XON/XOFF register */
 406 #define DMA_XON_THREHOLD_MASK           0xFFFF
 407 #define DMA_XOFF_THRESHOLD_MASK         0xFFFF
 408 #define DMA_XOFF_THRESHOLD_SHIFT        16
 409
 410 /* DMA flow period register */
 411 #define DMA_FLOW_PERIOD_MASK            0xFFFF
 412 #define DMA_MAX_PKT_SIZE_MASK           0xFFFF
 413 #define DMA_MAX_PKT_SIZE_SHIFT          16
 414
 415
 416 /* DMA control register */
 417 #define DMA_EN                          (1 << 0)
 418 #define DMA_RING_BUF_EN_SHIFT           0x01
 419 #define DMA_RING_BUF_EN_MASK            0xFFFF
 420 #define DMA_TSB_SWAP_EN                 (1 << 20)
 421
 422 /* DMA status register */
 423 #define DMA_DISABLED                    (1 << 0)
 424 #define DMA_DESC_RAM_INIT_BUSY          (1 << 1)
 425
 426 /* DMA SCB burst size register */
 427 #define DMA_SCB_BURST_SIZE_MASK         0x1F
 428
 429 /* DMA activity vector register */
 430 #define DMA_ACTIVITY_VECTOR_MASK        0x1FFFF
 431
 432 /* DMA backpressure mask register */
 433 #define DMA_BACKPRESSURE_MASK           0x1FFFF
 434 #define DMA_PFC_ENABLE                  (1 << 31)
 435
 436 /* DMA backpressure status register */
 437 #define DMA_BACKPRESSURE_STATUS_MASK    0x1FFFF
 438
 439 /* DMA override register */
 440 #define DMA_LITTLE_ENDIAN_MODE          (1 << 0)
 441 #define DMA_REGISTER_MODE               (1 << 1)
 442
 443 /* DMA timeout register */
 444 #define DMA_TIMEOUT_MASK                0xFFFF
 445 #define DMA_TIMEOUT_VAL                 5000    /* micro seconds */
 446
 447 /* TDMA rate limiting control register */
 448 #define DMA_RATE_LIMIT_EN_MASK          0xFFFF
 449
 450 /* TDMA arbitration control register */
 451 #define DMA_ARBITER_MODE_MASK           0x03
 452 #define DMA_RING_BUF_PRIORITY_MASK      0x1F
 453 #define DMA_RING_BUF_PRIORITY_SHIFT     5
 454 #define DMA_PRIO_REG_INDEX(q)           ((q) / 6)
 455 #define DMA_PRIO_REG_SHIFT(q)           (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT)
 456 #define DMA_RATE_ADJ_MASK               0xFF
 457
 458 /* Tx/Rx Dma Descriptor common bits*/
 459 #define DMA_BUFLENGTH_MASK              0x0fff
 460 #define DMA_BUFLENGTH_SHIFT             16
 461 #define DMA_OWN                         0x8000
 462 #define DMA_EOP                         0x4000
 463 #define DMA_SOP                         0x2000
 464 #define DMA_WRAP                        0x1000
 465 /* Tx specific Dma descriptor bits */
 466 #define DMA_TX_UNDERRUN                 0x0200
 467 #define DMA_TX_APPEND_CRC               0x0040
 468 #define DMA_TX_OW_CRC                   0x0020
 469 #define DMA_TX_DO_CSUM                  0x0010
 470 #define DMA_TX_QTAG_SHIFT               7
 471
 472 /* Rx Specific Dma descriptor bits */
 473 #define DMA_RX_CHK_V3PLUS               0x8000
 474 #define DMA_RX_CHK_V12                  0x1000
 475 #define DMA_RX_BRDCAST                  0x0040
 476 #define DMA_RX_MULT                     0x0020
 477 #define DMA_RX_LG                       0x0010
 478 #define DMA_RX_NO                       0x0008
 479 #define DMA_RX_RXER                     0x0004
 480 #define DMA_RX_CRC_ERROR                0x0002
 481 #define DMA_RX_OV                       0x0001
 482 #define DMA_RX_FI_MASK                  0x001F
 483 #define DMA_RX_FI_SHIFT                 0x0007
 484 #define DMA_DESC_ALLOC_MASK             0x00FF
 485
 486 #define DMA_ARBITER_RR                  0x00
 487 #define DMA_ARBITER_WRR                 0x01
 488 #define DMA_ARBITER_SP                  0x02
 489
 490 struct enet_cb {
 491         struct sk_buff      *skb;
 492         void __iomem *bd_addr;
 493         DEFINE_DMA_UNMAP_ADDR(dma_addr);
 494         DEFINE_DMA_UNMAP_LEN(dma_len);
 495 };
 496
 497 /* power management mode */
 498 enum bcmgenet_power_mode {
 499         GENET_POWER_CABLE_SENSE = 0,
 500         GENET_POWER_PASSIVE,
 501         GENET_POWER_WOL_MAGIC,
 502 };
 503
 504 struct bcmgenet_priv;
 505
 506 /* We support both runtime GENET detection and compile-time
 507  * to optimize code-paths for a given hardware
 508  */
 509 enum bcmgenet_version {
 510         GENET_V1 = 1,
 511         GENET_V2,
 512         GENET_V3,
 513         GENET_V4,
 514         GENET_V5
 515 };
 516
 517 #define GENET_IS_V1(p)  ((p)->version == GENET_V1)
 518 #define GENET_IS_V2(p)  ((p)->version == GENET_V2)
 519 #define GENET_IS_V3(p)  ((p)->version == GENET_V3)
 520 #define GENET_IS_V4(p)  ((p)->version == GENET_V4)
 521 #define GENET_IS_V5(p)  ((p)->version == GENET_V5)
 522
 523 /* Hardware flags */
 524 #define GENET_HAS_40BITS        (1 << 0)
 525 #define GENET_HAS_EXT           (1 << 1)
 526 #define GENET_HAS_MDIO_INTR     (1 << 2)
 527 #define GENET_HAS_MOCA_LINK_DET (1 << 3)
 528
 529 /* BCMGENET hardware parameters, keep this structure nicely aligned
 530  * since it is going to be used in hot paths
 531  */
 532 struct bcmgenet_hw_params {
 533         u8              tx_queues;
 534         u8              tx_bds_per_q;
 535         u8              rx_queues;
 536         u8              rx_bds_per_q;
 537         u8              bp_in_en_shift;
 538         u32             bp_in_mask;
 539         u8              hfb_filter_cnt;
 540         u8              hfb_filter_size;
 541         u8              qtag_mask;
 542         u16             tbuf_offset;
 543         u32             hfb_offset;
 544         u32             hfb_reg_offset;
 545         u32             rdma_offset;
 546         u32             tdma_offset;
 547         u32             words_per_bd;
 548         u32             flags;
 549 };
 550
 551 struct bcmgenet_skb_cb {
 552         struct enet_cb *first_cb;       /* First control block of SKB */
 553         struct enet_cb *last_cb;        /* Last control block of SKB */
 554         unsigned int bytes_sent;        /* bytes on the wire (no TSB) */
 555 };
 556
 557 #define GENET_CB(skb)   ((struct bcmgenet_skb_cb *)((skb)->cb))
 558
 559 struct bcmgenet_tx_ring {
 560         spinlock_t      lock;           /* ring lock */
 561         struct napi_struct napi;        /* NAPI per tx queue */
 562         unsigned long   packets;
 563         unsigned long   bytes;
 564         unsigned int    index;          /* ring index */
 565         unsigned int    queue;          /* queue index */
 566         struct enet_cb  *cbs;           /* tx ring buffer control block*/
 567         unsigned int    size;           /* size of each tx ring */
 568         unsigned int    clean_ptr;      /* Tx ring clean pointer */
 569         unsigned int    c_index;        /* last consumer index of each ring*/
 570         unsigned int    free_bds;       /* # of free bds for each ring */
 571         unsigned int    write_ptr;      /* Tx ring write pointer SW copy */
 572         unsigned int    prod_index;     /* Tx ring producer index SW copy */
 573         unsigned int    cb_ptr;         /* Tx ring initial CB ptr */
 574         unsigned int    end_ptr;        /* Tx ring end CB ptr */
 575         void (*int_enable)(struct bcmgenet_tx_ring *);
 576         void (*int_disable)(struct bcmgenet_tx_ring *);
 577         struct bcmgenet_priv *priv;
 578 };
 579
 580 struct bcmgenet_net_dim {
 581         u16             use_dim;
 582         u16             event_ctr;
 583         unsigned long   packets;
 584         unsigned long   bytes;
 585         struct net_dim  dim;
 586 };
 587
 588 struct bcmgenet_rx_ring {
 589         struct napi_struct napi;        /* Rx NAPI struct */
 590         unsigned long   bytes;
 591         unsigned long   packets;
 592         unsigned long   errors;
 593         unsigned long   dropped;
 594         unsigned int    index;          /* Rx ring index */
 595         struct enet_cb  *cbs;           /* Rx ring buffer control block */
 596         unsigned int    size;           /* Rx ring size */
 597         unsigned int    c_index;        /* Rx last consumer index */
 598         unsigned int    read_ptr;       /* Rx ring read pointer */
 599         unsigned int    cb_ptr;         /* Rx ring initial CB ptr */
 600         unsigned int    end_ptr;        /* Rx ring end CB ptr */
 601         unsigned int    old_discards;
 602         struct bcmgenet_net_dim dim;
 603         u32             rx_max_coalesced_frames;
 604         u32             rx_coalesce_usecs;
 605         void (*int_enable)(struct bcmgenet_rx_ring *);
 606         void (*int_disable)(struct bcmgenet_rx_ring *);
 607         struct bcmgenet_priv *priv;
 608 };
 609
 610 /* device context */
 611 struct bcmgenet_priv {
 612         void __iomem *base;
 613         enum bcmgenet_version version;
 614         struct net_device *dev;
 615
 616         /* transmit variables */
 617         void __iomem *tx_bds;
 618         struct enet_cb *tx_cbs;
 619         unsigned int num_tx_bds;
 620
 621         struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1];
 622
 623         /* receive variables */
 624         void __iomem *rx_bds;
 625         struct enet_cb *rx_cbs;
 626         unsigned int num_rx_bds;
 627         unsigned int rx_buf_len;
 628
 629         struct bcmgenet_rx_ring rx_rings[DESC_INDEX + 1];
 630
 631         /* other misc variables */
 632         struct bcmgenet_hw_params *hw_params;
 633
 634         /* MDIO bus variables */
 635         wait_queue_head_t wq;
 636         bool internal_phy;
 637         struct device_node *phy_dn;
 638         struct device_node *mdio_dn;
 639         struct mii_bus *mii_bus;
 640         u16 gphy_rev;
 641         struct clk *clk_eee;
 642         bool clk_eee_enabled;
 643
 644         /* PHY device variables */
 645         int old_link;
 646         int old_speed;
 647         int old_duplex;
 648         int old_pause;
 649         phy_interface_t phy_interface;
 650         int phy_addr;
 651         int ext_phy;
 652
 653         /* Interrupt variables */
 654         struct work_struct bcmgenet_irq_work;
 655         int irq0;
 656         int irq1;
 657         int wol_irq;
 658         bool wol_irq_disabled;
 659
 660         /* shared status */
 661         spinlock_t lock;
 662         unsigned int irq0_stat;
 663
 664         /* HW descriptors/checksum variables */
 665         bool desc_64b_en;
 666         bool desc_rxchk_en;
 667         bool crc_fwd_en;
 668
 669         unsigned int dma_rx_chk_bit;
 670
 671         u32 msg_enable;
 672
 673         struct clk *clk;
 674         struct platform_device *pdev;
 675         struct platform_device *mii_pdev;
 676
 677         /* WOL */
 678         struct clk *clk_wol;
 679         u32 wolopts;
 680
 681         struct bcmgenet_mib_counters mib;
 682
 683         struct ethtool_eee eee;
 684 };
 685
 686 #define GENET_IO_MACRO(name, offset)                                    \
 687 static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv,   \
 688                                         u32 off)                        \
 689 {                                                                       \
 690         /* MIPS chips strapped for BE will automagically configure the  \
 691          * peripheral registers for CPU-native byte order.              \
 692          */                                                             \
 693         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
 694                 return __raw_readl(priv->base + offset + off);          \
 695         else                                                            \
 696                 return readl_relaxed(priv->base + offset + off);        \
 697 }                                                                       \
 698 static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \
 699                                         u32 val, u32 off)               \
 700 {                                                                       \
 701         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
 702                 __raw_writel(val, priv->base + offset + off);           \
 703         else                                                            \
 704                 writel_relaxed(val, priv->base + offset + off);         \
 705 }
 706
 707 GENET_IO_MACRO(ext, GENET_EXT_OFF);
 708 GENET_IO_MACRO(umac, GENET_UMAC_OFF);
 709 GENET_IO_MACRO(sys, GENET_SYS_OFF);
 710
 711 /* interrupt l2 registers accessors */
 712 GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF);
 713 GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF);
 714
 715 /* HFB register accessors  */
 716 GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset);
 717
 718 /* GENET v2+ HFB control and filter len helpers */
 719 GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset);
 720
 721 /* RBUF register accessors */
 722 GENET_IO_MACRO(rbuf, GENET_RBUF_OFF);
 723
 724 /* MDIO routines */
 725 int bcmgenet_mii_init(struct net_device *dev);
 726 int bcmgenet_mii_config(struct net_device *dev, bool init);
 727 int bcmgenet_mii_probe(struct net_device *dev);
 728 void bcmgenet_mii_exit(struct net_device *dev);
 729 void bcmgenet_phy_power_set(struct net_device *dev, bool enable);
 730 void bcmgenet_mii_setup(struct net_device *dev);
 731
 732 /* Wake-on-LAN routines */
 733 void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
 734 int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
 735 int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
 736                                 enum bcmgenet_power_mode mode);
 737 void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
 738                                enum bcmgenet_power_mode mode);
 739
 740 #endif /* __BCMGENET_H__ */