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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / cadence / macb_main.c
blobacae87f548a169c382c4b1296718a974aaba95c3
1 /*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/crc32.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/circ_buf.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/gpio.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/interrupt.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_data/macb.h>
29 #include <linux/platform_device.h>
30 #include <linux/phy.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/ip.h>
37 #include <linux/udp.h>
38 #include <linux/tcp.h>
39 #include "macb.h"
40
41 #define MACB_RX_BUFFER_SIZE 128
42 #define RX_BUFFER_MULTIPLE 64 /* bytes */
43
44 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
45 #define MIN_RX_RING_SIZE 64
46 #define MAX_RX_RING_SIZE 8192
47 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
48 * (bp)->rx_ring_size)
49
50 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
51 #define MIN_TX_RING_SIZE 64
52 #define MAX_TX_RING_SIZE 4096
53 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
54 * (bp)->tx_ring_size)
55
56 /* level of occupied TX descriptors under which we wake up TX process */
57 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
58
59 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
60 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
61 | MACB_BIT(ISR_RLE) \
62 | MACB_BIT(TXERR))
63 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
64 | MACB_BIT(TXUBR))
65
66 /* Max length of transmit frame must be a multiple of 8 bytes */
67 #define MACB_TX_LEN_ALIGN 8
68 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
69 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
70 * false amba_error in TX path from the DMA assuming there is not enough
71 * space in the SRAM (16KB) even when there is.
72 */
73 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
74
75 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
76 #define MACB_NETIF_LSO NETIF_F_TSO
77
78 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
79 #define MACB_WOL_ENABLED (0x1 << 1)
80
81 /* Graceful stop timeouts in us. We should allow up to
82 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
83 */
84 #define MACB_HALT_TIMEOUT 1230
85
86 /* DMA buffer descriptor might be different size
87 * depends on hardware configuration:
88 *
89 * 1. dma address width 32 bits:
90 * word 1: 32 bit address of Data Buffer
91 * word 2: control
92 *
93 * 2. dma address width 64 bits:
94 * word 1: 32 bit address of Data Buffer
95 * word 2: control
96 * word 3: upper 32 bit address of Data Buffer
97 * word 4: unused
98 *
99 * 3. dma address width 32 bits with hardware timestamping:
100 * word 1: 32 bit address of Data Buffer
101 * word 2: control
102 * word 3: timestamp word 1
103 * word 4: timestamp word 2
104 *
105 * 4. dma address width 64 bits with hardware timestamping:
106 * word 1: 32 bit address of Data Buffer
107 * word 2: control
108 * word 3: upper 32 bit address of Data Buffer
109 * word 4: unused
110 * word 5: timestamp word 1
111 * word 6: timestamp word 2
112 */
113 static unsigned int macb_dma_desc_get_size(struct macb *bp)
114 {
115 #ifdef MACB_EXT_DESC
116 unsigned int desc_size;
117
118 switch (bp->hw_dma_cap) {
119 case HW_DMA_CAP_64B:
120 desc_size = sizeof(struct macb_dma_desc)
121 + sizeof(struct macb_dma_desc_64);
122 break;
123 case HW_DMA_CAP_PTP:
124 desc_size = sizeof(struct macb_dma_desc)
125 + sizeof(struct macb_dma_desc_ptp);
126 break;
127 case HW_DMA_CAP_64B_PTP:
128 desc_size = sizeof(struct macb_dma_desc)
129 + sizeof(struct macb_dma_desc_64)
130 + sizeof(struct macb_dma_desc_ptp);
131 break;
132 default:
133 desc_size = sizeof(struct macb_dma_desc);
134 }
135 return desc_size;
136 #endif
137 return sizeof(struct macb_dma_desc);
138 }
139
140 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
141 {
142 #ifdef MACB_EXT_DESC
143 switch (bp->hw_dma_cap) {
144 case HW_DMA_CAP_64B:
145 case HW_DMA_CAP_PTP:
146 desc_idx <<= 1;
147 break;
148 case HW_DMA_CAP_64B_PTP:
149 desc_idx *= 3;
150 break;
151 default:
152 break;
153 }
154 #endif
155 return desc_idx;
156 }
157
158 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
159 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
160 {
161 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
162 return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc));
163 return NULL;
164 }
165 #endif
166
167 /* Ring buffer accessors */
168 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
169 {
170 return index & (bp->tx_ring_size - 1);
171 }
172
173 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
174 unsigned int index)
175 {
176 index = macb_tx_ring_wrap(queue->bp, index);
177 index = macb_adj_dma_desc_idx(queue->bp, index);
178 return &queue->tx_ring[index];
179 }
180
181 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
182 unsigned int index)
183 {
184 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
185 }
186
187 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
188 {
189 dma_addr_t offset;
190
191 offset = macb_tx_ring_wrap(queue->bp, index) *
192 macb_dma_desc_get_size(queue->bp);
193
194 return queue->tx_ring_dma + offset;
195 }
196
197 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
198 {
199 return index & (bp->rx_ring_size - 1);
200 }
201
202 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
203 {
204 index = macb_rx_ring_wrap(queue->bp, index);
205 index = macb_adj_dma_desc_idx(queue->bp, index);
206 return &queue->rx_ring[index];
207 }
208
209 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
210 {
211 return queue->rx_buffers + queue->bp->rx_buffer_size *
212 macb_rx_ring_wrap(queue->bp, index);
213 }
214
215 /* I/O accessors */
216 static u32 hw_readl_native(struct macb *bp, int offset)
217 {
218 return __raw_readl(bp->regs + offset);
219 }
220
221 static void hw_writel_native(struct macb *bp, int offset, u32 value)
222 {
223 __raw_writel(value, bp->regs + offset);
224 }
225
226 static u32 hw_readl(struct macb *bp, int offset)
227 {
228 return readl_relaxed(bp->regs + offset);
229 }
230
231 static void hw_writel(struct macb *bp, int offset, u32 value)
232 {
233 writel_relaxed(value, bp->regs + offset);
234 }
235
236 /* Find the CPU endianness by using the loopback bit of NCR register. When the
237 * CPU is in big endian we need to program swapped mode for management
238 * descriptor access.
239 */
240 static bool hw_is_native_io(void __iomem *addr)
241 {
242 u32 value = MACB_BIT(LLB);
243
244 __raw_writel(value, addr + MACB_NCR);
245 value = __raw_readl(addr + MACB_NCR);
246
247 /* Write 0 back to disable everything */
248 __raw_writel(0, addr + MACB_NCR);
249
250 return value == MACB_BIT(LLB);
251 }
252
253 static bool hw_is_gem(void __iomem *addr, bool native_io)
254 {
255 u32 id;
256
257 if (native_io)
258 id = __raw_readl(addr + MACB_MID);
259 else
260 id = readl_relaxed(addr + MACB_MID);
261
262 return MACB_BFEXT(IDNUM, id) >= 0x2;
263 }
264
265 static void macb_set_hwaddr(struct macb *bp)
266 {
267 u32 bottom;
268 u16 top;
269
270 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
271 macb_or_gem_writel(bp, SA1B, bottom);
272 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
273 macb_or_gem_writel(bp, SA1T, top);
274
275 /* Clear unused address register sets */
276 macb_or_gem_writel(bp, SA2B, 0);
277 macb_or_gem_writel(bp, SA2T, 0);
278 macb_or_gem_writel(bp, SA3B, 0);
279 macb_or_gem_writel(bp, SA3T, 0);
280 macb_or_gem_writel(bp, SA4B, 0);
281 macb_or_gem_writel(bp, SA4T, 0);
282 }
283
284 static void macb_get_hwaddr(struct macb *bp)
285 {
286 struct macb_platform_data *pdata;
287 u32 bottom;
288 u16 top;
289 u8 addr[6];
290 int i;
291
292 pdata = dev_get_platdata(&bp->pdev->dev);
293
294 /* Check all 4 address register for valid address */
295 for (i = 0; i < 4; i++) {
296 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
297 top = macb_or_gem_readl(bp, SA1T + i * 8);
298
299 if (pdata && pdata->rev_eth_addr) {
300 addr[5] = bottom & 0xff;
301 addr[4] = (bottom >> 8) & 0xff;
302 addr[3] = (bottom >> 16) & 0xff;
303 addr[2] = (bottom >> 24) & 0xff;
304 addr[1] = top & 0xff;
305 addr[0] = (top & 0xff00) >> 8;
306 } else {
307 addr[0] = bottom & 0xff;
308 addr[1] = (bottom >> 8) & 0xff;
309 addr[2] = (bottom >> 16) & 0xff;
310 addr[3] = (bottom >> 24) & 0xff;
311 addr[4] = top & 0xff;
312 addr[5] = (top >> 8) & 0xff;
313 }
314
315 if (is_valid_ether_addr(addr)) {
316 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
317 return;
318 }
319 }
320
321 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
322 eth_hw_addr_random(bp->dev);
323 }
324
325 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
326 {
327 struct macb *bp = bus->priv;
328 int value;
329
330 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
331 | MACB_BF(RW, MACB_MAN_READ)
332 | MACB_BF(PHYA, mii_id)
333 | MACB_BF(REGA, regnum)
334 | MACB_BF(CODE, MACB_MAN_CODE)));
335
336 /* wait for end of transfer */
337 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
338 cpu_relax();
339
340 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
341
342 return value;
343 }
344
345 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
346 u16 value)
347 {
348 struct macb *bp = bus->priv;
349
350 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
351 | MACB_BF(RW, MACB_MAN_WRITE)
352 | MACB_BF(PHYA, mii_id)
353 | MACB_BF(REGA, regnum)
354 | MACB_BF(CODE, MACB_MAN_CODE)
355 | MACB_BF(DATA, value)));
356
357 /* wait for end of transfer */
358 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
359 cpu_relax();
360
361 return 0;
362 }
363
364 /**
365 * macb_set_tx_clk() - Set a clock to a new frequency
366 * @clk Pointer to the clock to change
367 * @rate New frequency in Hz
368 * @dev Pointer to the struct net_device
369 */
370 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
371 {
372 long ferr, rate, rate_rounded;
373
374 if (!clk)
375 return;
376
377 switch (speed) {
378 case SPEED_10:
379 rate = 2500000;
380 break;
381 case SPEED_100:
382 rate = 25000000;
383 break;
384 case SPEED_1000:
385 rate = 125000000;
386 break;
387 default:
388 return;
389 }
390
391 rate_rounded = clk_round_rate(clk, rate);
392 if (rate_rounded < 0)
393 return;
394
395 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
396 * is not satisfied.
397 */
398 ferr = abs(rate_rounded - rate);
399 ferr = DIV_ROUND_UP(ferr, rate / 100000);
400 if (ferr > 5)
401 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
402 rate);
403
404 if (clk_set_rate(clk, rate_rounded))
405 netdev_err(dev, "adjusting tx_clk failed.\n");
406 }
407
408 static void macb_handle_link_change(struct net_device *dev)
409 {
410 struct macb *bp = netdev_priv(dev);
411 struct phy_device *phydev = dev->phydev;
412 unsigned long flags;
413 int status_change = 0;
414
415 spin_lock_irqsave(&bp->lock, flags);
416
417 if (phydev->link) {
418 if ((bp->speed != phydev->speed) ||
419 (bp->duplex != phydev->duplex)) {
420 u32 reg;
421
422 reg = macb_readl(bp, NCFGR);
423 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
424 if (macb_is_gem(bp))
425 reg &= ~GEM_BIT(GBE);
426
427 if (phydev->duplex)
428 reg |= MACB_BIT(FD);
429 if (phydev->speed == SPEED_100)
430 reg |= MACB_BIT(SPD);
431 if (phydev->speed == SPEED_1000 &&
432 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
433 reg |= GEM_BIT(GBE);
434
435 macb_or_gem_writel(bp, NCFGR, reg);
436
437 bp->speed = phydev->speed;
438 bp->duplex = phydev->duplex;
439 status_change = 1;
440 }
441 }
442
443 if (phydev->link != bp->link) {
444 if (!phydev->link) {
445 bp->speed = 0;
446 bp->duplex = -1;
447 }
448 bp->link = phydev->link;
449
450 status_change = 1;
451 }
452
453 spin_unlock_irqrestore(&bp->lock, flags);
454
455 if (status_change) {
456 if (phydev->link) {
457 /* Update the TX clock rate if and only if the link is
458 * up and there has been a link change.
459 */
460 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
461
462 netif_carrier_on(dev);
463 netdev_info(dev, "link up (%d/%s)\n",
464 phydev->speed,
465 phydev->duplex == DUPLEX_FULL ?
466 "Full" : "Half");
467 } else {
468 netif_carrier_off(dev);
469 netdev_info(dev, "link down\n");
470 }
471 }
472 }
473
474 /* based on au1000_eth. c*/
475 static int macb_mii_probe(struct net_device *dev)
476 {
477 struct macb *bp = netdev_priv(dev);
478 struct macb_platform_data *pdata;
479 struct phy_device *phydev;
480 struct device_node *np;
481 int phy_irq, ret, i;
482
483 pdata = dev_get_platdata(&bp->pdev->dev);
484 np = bp->pdev->dev.of_node;
485 ret = 0;
486
487 if (np) {
488 if (of_phy_is_fixed_link(np)) {
489 bp->phy_node = of_node_get(np);
490 } else {
491 bp->phy_node = of_parse_phandle(np, "phy-handle", 0);
492 /* fallback to standard phy registration if no
493 * phy-handle was found nor any phy found during
494 * dt phy registration
495 */
496 if (!bp->phy_node && !phy_find_first(bp->mii_bus)) {
497 for (i = 0; i < PHY_MAX_ADDR; i++) {
498 struct phy_device *phydev;
499
500 phydev = mdiobus_scan(bp->mii_bus, i);
501 if (IS_ERR(phydev) &&
502 PTR_ERR(phydev) != -ENODEV) {
503 ret = PTR_ERR(phydev);
504 break;
505 }
506 }
507
508 if (ret)
509 return -ENODEV;
510 }
511 }
512 }
513
514 if (bp->phy_node) {
515 phydev = of_phy_connect(dev, bp->phy_node,
516 &macb_handle_link_change, 0,
517 bp->phy_interface);
518 if (!phydev)
519 return -ENODEV;
520 } else {
521 phydev = phy_find_first(bp->mii_bus);
522 if (!phydev) {
523 netdev_err(dev, "no PHY found\n");
524 return -ENXIO;
525 }
526
527 if (pdata) {
528 if (gpio_is_valid(pdata->phy_irq_pin)) {
529 ret = devm_gpio_request(&bp->pdev->dev,
530 pdata->phy_irq_pin, "phy int");
531 if (!ret) {
532 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
533 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
534 }
535 } else {
536 phydev->irq = PHY_POLL;
537 }
538 }
539
540 /* attach the mac to the phy */
541 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
542 bp->phy_interface);
543 if (ret) {
544 netdev_err(dev, "Could not attach to PHY\n");
545 return ret;
546 }
547 }
548
549 /* mask with MAC supported features */
550 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
551 phydev->supported &= PHY_GBIT_FEATURES;
552 else
553 phydev->supported &= PHY_BASIC_FEATURES;
554
555 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
556 phydev->supported &= ~SUPPORTED_1000baseT_Half;
557
558 phydev->advertising = phydev->supported;
559
560 bp->link = 0;
561 bp->speed = 0;
562 bp->duplex = -1;
563
564 return 0;
565 }
566
567 static int macb_mii_init(struct macb *bp)
568 {
569 struct macb_platform_data *pdata;
570 struct device_node *np;
571 int err = -ENXIO;
572
573 /* Enable management port */
574 macb_writel(bp, NCR, MACB_BIT(MPE));
575
576 bp->mii_bus = mdiobus_alloc();
577 if (!bp->mii_bus) {
578 err = -ENOMEM;
579 goto err_out;
580 }
581
582 bp->mii_bus->name = "MACB_mii_bus";
583 bp->mii_bus->read = &macb_mdio_read;
584 bp->mii_bus->write = &macb_mdio_write;
585 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
586 bp->pdev->name, bp->pdev->id);
587 bp->mii_bus->priv = bp;
588 bp->mii_bus->parent = &bp->pdev->dev;
589 pdata = dev_get_platdata(&bp->pdev->dev);
590
591 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
592
593 np = bp->pdev->dev.of_node;
594 if (np && of_phy_is_fixed_link(np)) {
595 if (of_phy_register_fixed_link(np) < 0) {
596 dev_err(&bp->pdev->dev,
597 "broken fixed-link specification %pOF\n", np);
598 goto err_out_free_mdiobus;
599 }
600
601 err = mdiobus_register(bp->mii_bus);
602 } else {
603 if (pdata)
604 bp->mii_bus->phy_mask = pdata->phy_mask;
605
606 err = of_mdiobus_register(bp->mii_bus, np);
607 }
608
609 if (err)
610 goto err_out_free_fixed_link;
611
612 err = macb_mii_probe(bp->dev);
613 if (err)
614 goto err_out_unregister_bus;
615
616 return 0;
617
618 err_out_unregister_bus:
619 mdiobus_unregister(bp->mii_bus);
620 err_out_free_fixed_link:
621 if (np && of_phy_is_fixed_link(np))
622 of_phy_deregister_fixed_link(np);
623 err_out_free_mdiobus:
624 of_node_put(bp->phy_node);
625 mdiobus_free(bp->mii_bus);
626 err_out:
627 return err;
628 }
629
630 static void macb_update_stats(struct macb *bp)
631 {
632 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
633 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
634 int offset = MACB_PFR;
635
636 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
637
638 for (; p < end; p++, offset += 4)
639 *p += bp->macb_reg_readl(bp, offset);
640 }
641
642 static int macb_halt_tx(struct macb *bp)
643 {
644 unsigned long halt_time, timeout;
645 u32 status;
646
647 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
648
649 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
650 do {
651 halt_time = jiffies;
652 status = macb_readl(bp, TSR);
653 if (!(status & MACB_BIT(TGO)))
654 return 0;
655
656 udelay(250);
657 } while (time_before(halt_time, timeout));
658
659 return -ETIMEDOUT;
660 }
661
662 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
663 {
664 if (tx_skb->mapping) {
665 if (tx_skb->mapped_as_page)
666 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
667 tx_skb->size, DMA_TO_DEVICE);
668 else
669 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
670 tx_skb->size, DMA_TO_DEVICE);
671 tx_skb->mapping = 0;
672 }
673
674 if (tx_skb->skb) {
675 dev_kfree_skb_any(tx_skb->skb);
676 tx_skb->skb = NULL;
677 }
678 }
679
680 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
681 {
682 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
683 struct macb_dma_desc_64 *desc_64;
684
685 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
686 desc_64 = macb_64b_desc(bp, desc);
687 desc_64->addrh = upper_32_bits(addr);
688 /* The low bits of RX address contain the RX_USED bit, clearing
689 * of which allows packet RX. Make sure the high bits are also
690 * visible to HW at that point.
691 */
692 dma_wmb();
693 }
694 #endif
695 desc->addr = lower_32_bits(addr);
696 }
697
698 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
699 {
700 dma_addr_t addr = 0;
701 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
702 struct macb_dma_desc_64 *desc_64;
703
704 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
705 desc_64 = macb_64b_desc(bp, desc);
706 addr = ((u64)(desc_64->addrh) << 32);
707 }
708 #endif
709 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
710 return addr;
711 }
712
713 static void macb_tx_error_task(struct work_struct *work)
714 {
715 struct macb_queue *queue = container_of(work, struct macb_queue,
716 tx_error_task);
717 struct macb *bp = queue->bp;
718 struct macb_tx_skb *tx_skb;
719 struct macb_dma_desc *desc;
720 struct sk_buff *skb;
721 unsigned int tail;
722 unsigned long flags;
723
724 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
725 (unsigned int)(queue - bp->queues),
726 queue->tx_tail, queue->tx_head);
727
728 /* Prevent the queue IRQ handlers from running: each of them may call
729 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
730 * As explained below, we have to halt the transmission before updating
731 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
732 * network engine about the macb/gem being halted.
733 */
734 spin_lock_irqsave(&bp->lock, flags);
735
736 /* Make sure nobody is trying to queue up new packets */
737 netif_tx_stop_all_queues(bp->dev);
738
739 /* Stop transmission now
740 * (in case we have just queued new packets)
741 * macb/gem must be halted to write TBQP register
742 */
743 if (macb_halt_tx(bp))
744 /* Just complain for now, reinitializing TX path can be good */
745 netdev_err(bp->dev, "BUG: halt tx timed out\n");
746
747 /* Treat frames in TX queue including the ones that caused the error.
748 * Free transmit buffers in upper layer.
749 */
750 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
751 u32 ctrl;
752
753 desc = macb_tx_desc(queue, tail);
754 ctrl = desc->ctrl;
755 tx_skb = macb_tx_skb(queue, tail);
756 skb = tx_skb->skb;
757
758 if (ctrl & MACB_BIT(TX_USED)) {
759 /* skb is set for the last buffer of the frame */
760 while (!skb) {
761 macb_tx_unmap(bp, tx_skb);
762 tail++;
763 tx_skb = macb_tx_skb(queue, tail);
764 skb = tx_skb->skb;
765 }
766
767 /* ctrl still refers to the first buffer descriptor
768 * since it's the only one written back by the hardware
769 */
770 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
771 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
772 macb_tx_ring_wrap(bp, tail),
773 skb->data);
774 bp->dev->stats.tx_packets++;
775 queue->stats.tx_packets++;
776 bp->dev->stats.tx_bytes += skb->len;
777 queue->stats.tx_bytes += skb->len;
778 }
779 } else {
780 /* "Buffers exhausted mid-frame" errors may only happen
781 * if the driver is buggy, so complain loudly about
782 * those. Statistics are updated by hardware.
783 */
784 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
785 netdev_err(bp->dev,
786 "BUG: TX buffers exhausted mid-frame\n");
787
788 desc->ctrl = ctrl | MACB_BIT(TX_USED);
789 }
790
791 macb_tx_unmap(bp, tx_skb);
792 }
793
794 /* Set end of TX queue */
795 desc = macb_tx_desc(queue, 0);
796 macb_set_addr(bp, desc, 0);
797 desc->ctrl = MACB_BIT(TX_USED);
798
799 /* Make descriptor updates visible to hardware */
800 wmb();
801
802 /* Reinitialize the TX desc queue */
803 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
804 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
805 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
806 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
807 #endif
808 /* Make TX ring reflect state of hardware */
809 queue->tx_head = 0;
810 queue->tx_tail = 0;
811
812 /* Housework before enabling TX IRQ */
813 macb_writel(bp, TSR, macb_readl(bp, TSR));
814 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
815
816 /* Now we are ready to start transmission again */
817 netif_tx_start_all_queues(bp->dev);
818 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
819
820 spin_unlock_irqrestore(&bp->lock, flags);
821 }
822
823 static void macb_tx_interrupt(struct macb_queue *queue)
824 {
825 unsigned int tail;
826 unsigned int head;
827 u32 status;
828 struct macb *bp = queue->bp;
829 u16 queue_index = queue - bp->queues;
830
831 status = macb_readl(bp, TSR);
832 macb_writel(bp, TSR, status);
833
834 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
835 queue_writel(queue, ISR, MACB_BIT(TCOMP));
836
837 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
838 (unsigned long)status);
839
840 head = queue->tx_head;
841 for (tail = queue->tx_tail; tail != head; tail++) {
842 struct macb_tx_skb *tx_skb;
843 struct sk_buff *skb;
844 struct macb_dma_desc *desc;
845 u32 ctrl;
846
847 desc = macb_tx_desc(queue, tail);
848
849 /* Make hw descriptor updates visible to CPU */
850 rmb();
851
852 ctrl = desc->ctrl;
853
854 /* TX_USED bit is only set by hardware on the very first buffer
855 * descriptor of the transmitted frame.
856 */
857 if (!(ctrl & MACB_BIT(TX_USED)))
858 break;
859
860 /* Process all buffers of the current transmitted frame */
861 for (;; tail++) {
862 tx_skb = macb_tx_skb(queue, tail);
863 skb = tx_skb->skb;
864
865 /* First, update TX stats if needed */
866 if (skb) {
867 if (unlikely(skb_shinfo(skb)->tx_flags &
868 SKBTX_HW_TSTAMP) &&
869 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
870 /* skb now belongs to timestamp buffer
871 * and will be removed later
872 */
873 tx_skb->skb = NULL;
874 }
875 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
876 macb_tx_ring_wrap(bp, tail),
877 skb->data);
878 bp->dev->stats.tx_packets++;
879 queue->stats.tx_packets++;
880 bp->dev->stats.tx_bytes += skb->len;
881 queue->stats.tx_bytes += skb->len;
882 }
883
884 /* Now we can safely release resources */
885 macb_tx_unmap(bp, tx_skb);
886
887 /* skb is set only for the last buffer of the frame.
888 * WARNING: at this point skb has been freed by
889 * macb_tx_unmap().
890 */
891 if (skb)
892 break;
893 }
894 }
895
896 queue->tx_tail = tail;
897 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
898 CIRC_CNT(queue->tx_head, queue->tx_tail,
899 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
900 netif_wake_subqueue(bp->dev, queue_index);
901 }
902
903 static void gem_rx_refill(struct macb_queue *queue)
904 {
905 unsigned int entry;
906 struct sk_buff *skb;
907 dma_addr_t paddr;
908 struct macb *bp = queue->bp;
909 struct macb_dma_desc *desc;
910
911 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
912 bp->rx_ring_size) > 0) {
913 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
914
915 /* Make hw descriptor updates visible to CPU */
916 rmb();
917
918 queue->rx_prepared_head++;
919 desc = macb_rx_desc(queue, entry);
920
921 if (!queue->rx_skbuff[entry]) {
922 /* allocate sk_buff for this free entry in ring */
923 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
924 if (unlikely(!skb)) {
925 netdev_err(bp->dev,
926 "Unable to allocate sk_buff\n");
927 break;
928 }
929
930 /* now fill corresponding descriptor entry */
931 paddr = dma_map_single(&bp->pdev->dev, skb->data,
932 bp->rx_buffer_size,
933 DMA_FROM_DEVICE);
934 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
935 dev_kfree_skb(skb);
936 break;
937 }
938
939 queue->rx_skbuff[entry] = skb;
940
941 if (entry == bp->rx_ring_size - 1)
942 paddr |= MACB_BIT(RX_WRAP);
943 desc->ctrl = 0;
944 /* Setting addr clears RX_USED and allows reception,
945 * make sure ctrl is cleared first to avoid a race.
946 */
947 dma_wmb();
948 macb_set_addr(bp, desc, paddr);
949
950 /* properly align Ethernet header */
951 skb_reserve(skb, NET_IP_ALIGN);
952 } else {
953 desc->ctrl = 0;
954 dma_wmb();
955 desc->addr &= ~MACB_BIT(RX_USED);
956 }
957 }
958
959 /* Make descriptor updates visible to hardware */
960 wmb();
961
962 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
963 queue, queue->rx_prepared_head, queue->rx_tail);
964 }
965
966 /* Mark DMA descriptors from begin up to and not including end as unused */
967 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
968 unsigned int end)
969 {
970 unsigned int frag;
971
972 for (frag = begin; frag != end; frag++) {
973 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
974
975 desc->addr &= ~MACB_BIT(RX_USED);
976 }
977
978 /* Make descriptor updates visible to hardware */
979 wmb();
980
981 /* When this happens, the hardware stats registers for
982 * whatever caused this is updated, so we don't have to record
983 * anything.
984 */
985 }
986
987 static int gem_rx(struct macb_queue *queue, int budget)
988 {
989 struct macb *bp = queue->bp;
990 unsigned int len;
991 unsigned int entry;
992 struct sk_buff *skb;
993 struct macb_dma_desc *desc;
994 int count = 0;
995
996 while (count < budget) {
997 u32 ctrl;
998 dma_addr_t addr;
999 bool rxused;
1000
1001 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1002 desc = macb_rx_desc(queue, entry);
1003
1004 /* Make hw descriptor updates visible to CPU */
1005 rmb();
1006
1007 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1008 addr = macb_get_addr(bp, desc);
1009
1010 if (!rxused)
1011 break;
1012
1013 /* Ensure ctrl is at least as up-to-date as rxused */
1014 dma_rmb();
1015
1016 ctrl = desc->ctrl;
1017
1018 queue->rx_tail++;
1019 count++;
1020
1021 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1022 netdev_err(bp->dev,
1023 "not whole frame pointed by descriptor\n");
1024 bp->dev->stats.rx_dropped++;
1025 queue->stats.rx_dropped++;
1026 break;
1027 }
1028 skb = queue->rx_skbuff[entry];
1029 if (unlikely(!skb)) {
1030 netdev_err(bp->dev,
1031 "inconsistent Rx descriptor chain\n");
1032 bp->dev->stats.rx_dropped++;
1033 queue->stats.rx_dropped++;
1034 break;
1035 }
1036 /* now everything is ready for receiving packet */
1037 queue->rx_skbuff[entry] = NULL;
1038 len = ctrl & bp->rx_frm_len_mask;
1039
1040 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1041
1042 skb_put(skb, len);
1043 dma_unmap_single(&bp->pdev->dev, addr,
1044 bp->rx_buffer_size, DMA_FROM_DEVICE);
1045
1046 skb->protocol = eth_type_trans(skb, bp->dev);
1047 skb_checksum_none_assert(skb);
1048 if (bp->dev->features & NETIF_F_RXCSUM &&
1049 !(bp->dev->flags & IFF_PROMISC) &&
1050 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1051 skb->ip_summed = CHECKSUM_UNNECESSARY;
1052
1053 bp->dev->stats.rx_packets++;
1054 queue->stats.rx_packets++;
1055 bp->dev->stats.rx_bytes += skb->len;
1056 queue->stats.rx_bytes += skb->len;
1057
1058 gem_ptp_do_rxstamp(bp, skb, desc);
1059
1060 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1061 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1062 skb->len, skb->csum);
1063 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1064 skb_mac_header(skb), 16, true);
1065 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1066 skb->data, 32, true);
1067 #endif
1068
1069 netif_receive_skb(skb);
1070 }
1071
1072 gem_rx_refill(queue);
1073
1074 return count;
1075 }
1076
1077 static int macb_rx_frame(struct macb_queue *queue, unsigned int first_frag,
1078 unsigned int last_frag)
1079 {
1080 unsigned int len;
1081 unsigned int frag;
1082 unsigned int offset;
1083 struct sk_buff *skb;
1084 struct macb_dma_desc *desc;
1085 struct macb *bp = queue->bp;
1086
1087 desc = macb_rx_desc(queue, last_frag);
1088 len = desc->ctrl & bp->rx_frm_len_mask;
1089
1090 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1091 macb_rx_ring_wrap(bp, first_frag),
1092 macb_rx_ring_wrap(bp, last_frag), len);
1093
1094 /* The ethernet header starts NET_IP_ALIGN bytes into the
1095 * first buffer. Since the header is 14 bytes, this makes the
1096 * payload word-aligned.
1097 *
1098 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1099 * the two padding bytes into the skb so that we avoid hitting
1100 * the slowpath in memcpy(), and pull them off afterwards.
1101 */
1102 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1103 if (!skb) {
1104 bp->dev->stats.rx_dropped++;
1105 for (frag = first_frag; ; frag++) {
1106 desc = macb_rx_desc(queue, frag);
1107 desc->addr &= ~MACB_BIT(RX_USED);
1108 if (frag == last_frag)
1109 break;
1110 }
1111
1112 /* Make descriptor updates visible to hardware */
1113 wmb();
1114
1115 return 1;
1116 }
1117
1118 offset = 0;
1119 len += NET_IP_ALIGN;
1120 skb_checksum_none_assert(skb);
1121 skb_put(skb, len);
1122
1123 for (frag = first_frag; ; frag++) {
1124 unsigned int frag_len = bp->rx_buffer_size;
1125
1126 if (offset + frag_len > len) {
1127 if (unlikely(frag != last_frag)) {
1128 dev_kfree_skb_any(skb);
1129 return -1;
1130 }
1131 frag_len = len - offset;
1132 }
1133 skb_copy_to_linear_data_offset(skb, offset,
1134 macb_rx_buffer(queue, frag),
1135 frag_len);
1136 offset += bp->rx_buffer_size;
1137 desc = macb_rx_desc(queue, frag);
1138 desc->addr &= ~MACB_BIT(RX_USED);
1139
1140 if (frag == last_frag)
1141 break;
1142 }
1143
1144 /* Make descriptor updates visible to hardware */
1145 wmb();
1146
1147 __skb_pull(skb, NET_IP_ALIGN);
1148 skb->protocol = eth_type_trans(skb, bp->dev);
1149
1150 bp->dev->stats.rx_packets++;
1151 bp->dev->stats.rx_bytes += skb->len;
1152 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1153 skb->len, skb->csum);
1154 netif_receive_skb(skb);
1155
1156 return 0;
1157 }
1158
1159 static inline void macb_init_rx_ring(struct macb_queue *queue)
1160 {
1161 struct macb *bp = queue->bp;
1162 dma_addr_t addr;
1163 struct macb_dma_desc *desc = NULL;
1164 int i;
1165
1166 addr = queue->rx_buffers_dma;
1167 for (i = 0; i < bp->rx_ring_size; i++) {
1168 desc = macb_rx_desc(queue, i);
1169 macb_set_addr(bp, desc, addr);
1170 desc->ctrl = 0;
1171 addr += bp->rx_buffer_size;
1172 }
1173 desc->addr |= MACB_BIT(RX_WRAP);
1174 queue->rx_tail = 0;
1175 }
1176
1177 static int macb_rx(struct macb_queue *queue, int budget)
1178 {
1179 struct macb *bp = queue->bp;
1180 bool reset_rx_queue = false;
1181 int received = 0;
1182 unsigned int tail;
1183 int first_frag = -1;
1184
1185 for (tail = queue->rx_tail; budget > 0; tail++) {
1186 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1187 u32 ctrl;
1188
1189 /* Make hw descriptor updates visible to CPU */
1190 rmb();
1191
1192 if (!(desc->addr & MACB_BIT(RX_USED)))
1193 break;
1194
1195 /* Ensure ctrl is at least as up-to-date as addr */
1196 dma_rmb();
1197
1198 ctrl = desc->ctrl;
1199
1200 if (ctrl & MACB_BIT(RX_SOF)) {
1201 if (first_frag != -1)
1202 discard_partial_frame(queue, first_frag, tail);
1203 first_frag = tail;
1204 }
1205
1206 if (ctrl & MACB_BIT(RX_EOF)) {
1207 int dropped;
1208
1209 if (unlikely(first_frag == -1)) {
1210 reset_rx_queue = true;
1211 continue;
1212 }
1213
1214 dropped = macb_rx_frame(queue, first_frag, tail);
1215 first_frag = -1;
1216 if (unlikely(dropped < 0)) {
1217 reset_rx_queue = true;
1218 continue;
1219 }
1220 if (!dropped) {
1221 received++;
1222 budget--;
1223 }
1224 }
1225 }
1226
1227 if (unlikely(reset_rx_queue)) {
1228 unsigned long flags;
1229 u32 ctrl;
1230
1231 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1232
1233 spin_lock_irqsave(&bp->lock, flags);
1234
1235 ctrl = macb_readl(bp, NCR);
1236 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1237
1238 macb_init_rx_ring(queue);
1239 queue_writel(queue, RBQP, queue->rx_ring_dma);
1240
1241 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1242
1243 spin_unlock_irqrestore(&bp->lock, flags);
1244 return received;
1245 }
1246
1247 if (first_frag != -1)
1248 queue->rx_tail = first_frag;
1249 else
1250 queue->rx_tail = tail;
1251
1252 return received;
1253 }
1254
1255 static int macb_poll(struct napi_struct *napi, int budget)
1256 {
1257 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1258 struct macb *bp = queue->bp;
1259 int work_done;
1260 u32 status;
1261
1262 status = macb_readl(bp, RSR);
1263 macb_writel(bp, RSR, status);
1264
1265 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1266 (unsigned long)status, budget);
1267
1268 work_done = bp->macbgem_ops.mog_rx(queue, budget);
1269 if (work_done < budget) {
1270 napi_complete_done(napi, work_done);
1271
1272 /* Packets received while interrupts were disabled */
1273 status = macb_readl(bp, RSR);
1274 if (status) {
1275 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1276 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1277 napi_reschedule(napi);
1278 } else {
1279 queue_writel(queue, IER, bp->rx_intr_mask);
1280 }
1281 }
1282
1283 /* TODO: Handle errors */
1284
1285 return work_done;
1286 }
1287
1288 static void macb_hresp_error_task(unsigned long data)
1289 {
1290 struct macb *bp = (struct macb *)data;
1291 struct net_device *dev = bp->dev;
1292 struct macb_queue *queue = bp->queues;
1293 unsigned int q;
1294 u32 ctrl;
1295
1296 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1297 queue_writel(queue, IDR, bp->rx_intr_mask |
1298 MACB_TX_INT_FLAGS |
1299 MACB_BIT(HRESP));
1300 }
1301 ctrl = macb_readl(bp, NCR);
1302 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1303 macb_writel(bp, NCR, ctrl);
1304
1305 netif_tx_stop_all_queues(dev);
1306 netif_carrier_off(dev);
1307
1308 bp->macbgem_ops.mog_init_rings(bp);
1309
1310 /* Initialize TX and RX buffers */
1311 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1312 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
1313 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1314 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1315 queue_writel(queue, RBQPH,
1316 upper_32_bits(queue->rx_ring_dma));
1317 #endif
1318 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1319 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1320 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1321 queue_writel(queue, TBQPH,
1322 upper_32_bits(queue->tx_ring_dma));
1323 #endif
1324
1325 /* Enable interrupts */
1326 queue_writel(queue, IER,
1327 bp->rx_intr_mask |
1328 MACB_TX_INT_FLAGS |
1329 MACB_BIT(HRESP));
1330 }
1331
1332 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1333 macb_writel(bp, NCR, ctrl);
1334
1335 netif_carrier_on(dev);
1336 netif_tx_start_all_queues(dev);
1337 }
1338
1339 static void macb_tx_restart(struct macb_queue *queue)
1340 {
1341 unsigned int head = queue->tx_head;
1342 unsigned int tail = queue->tx_tail;
1343 struct macb *bp = queue->bp;
1344
1345 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1346 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1347
1348 if (head == tail)
1349 return;
1350
1351 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1352 }
1353
1354 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1355 {
1356 struct macb_queue *queue = dev_id;
1357 struct macb *bp = queue->bp;
1358 struct net_device *dev = bp->dev;
1359 u32 status, ctrl;
1360
1361 status = queue_readl(queue, ISR);
1362
1363 if (unlikely(!status))
1364 return IRQ_NONE;
1365
1366 spin_lock(&bp->lock);
1367
1368 while (status) {
1369 /* close possible race with dev_close */
1370 if (unlikely(!netif_running(dev))) {
1371 queue_writel(queue, IDR, -1);
1372 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1373 queue_writel(queue, ISR, -1);
1374 break;
1375 }
1376
1377 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1378 (unsigned int)(queue - bp->queues),
1379 (unsigned long)status);
1380
1381 if (status & bp->rx_intr_mask) {
1382 /* There's no point taking any more interrupts
1383 * until we have processed the buffers. The
1384 * scheduling call may fail if the poll routine
1385 * is already scheduled, so disable interrupts
1386 * now.
1387 */
1388 queue_writel(queue, IDR, bp->rx_intr_mask);
1389 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1390 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1391
1392 if (napi_schedule_prep(&queue->napi)) {
1393 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1394 __napi_schedule(&queue->napi);
1395 }
1396 }
1397
1398 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1399 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1400 schedule_work(&queue->tx_error_task);
1401
1402 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1403 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1404
1405 break;
1406 }
1407
1408 if (status & MACB_BIT(TCOMP))
1409 macb_tx_interrupt(queue);
1410
1411 if (status & MACB_BIT(TXUBR))
1412 macb_tx_restart(queue);
1413
1414 /* Link change detection isn't possible with RMII, so we'll
1415 * add that if/when we get our hands on a full-blown MII PHY.
1416 */
1417
1418 /* There is a hardware issue under heavy load where DMA can
1419 * stop, this causes endless "used buffer descriptor read"
1420 * interrupts but it can be cleared by re-enabling RX. See
1421 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1422 * section 16.7.4 for details. RXUBR is only enabled for
1423 * these two versions.
1424 */
1425 if (status & MACB_BIT(RXUBR)) {
1426 ctrl = macb_readl(bp, NCR);
1427 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1428 wmb();
1429 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1430
1431 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1432 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1433 }
1434
1435 if (status & MACB_BIT(ISR_ROVR)) {
1436 /* We missed at least one packet */
1437 if (macb_is_gem(bp))
1438 bp->hw_stats.gem.rx_overruns++;
1439 else
1440 bp->hw_stats.macb.rx_overruns++;
1441
1442 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1443 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1444 }
1445
1446 if (status & MACB_BIT(HRESP)) {
1447 tasklet_schedule(&bp->hresp_err_tasklet);
1448 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1449
1450 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1451 queue_writel(queue, ISR, MACB_BIT(HRESP));
1452 }
1453 status = queue_readl(queue, ISR);
1454 }
1455
1456 spin_unlock(&bp->lock);
1457
1458 return IRQ_HANDLED;
1459 }
1460
1461 #ifdef CONFIG_NET_POLL_CONTROLLER
1462 /* Polling receive - used by netconsole and other diagnostic tools
1463 * to allow network i/o with interrupts disabled.
1464 */
1465 static void macb_poll_controller(struct net_device *dev)
1466 {
1467 struct macb *bp = netdev_priv(dev);
1468 struct macb_queue *queue;
1469 unsigned long flags;
1470 unsigned int q;
1471
1472 local_irq_save(flags);
1473 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1474 macb_interrupt(dev->irq, queue);
1475 local_irq_restore(flags);
1476 }
1477 #endif
1478
1479 static unsigned int macb_tx_map(struct macb *bp,
1480 struct macb_queue *queue,
1481 struct sk_buff *skb,
1482 unsigned int hdrlen)
1483 {
1484 dma_addr_t mapping;
1485 unsigned int len, entry, i, tx_head = queue->tx_head;
1486 struct macb_tx_skb *tx_skb = NULL;
1487 struct macb_dma_desc *desc;
1488 unsigned int offset, size, count = 0;
1489 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1490 unsigned int eof = 1, mss_mfs = 0;
1491 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1492
1493 /* LSO */
1494 if (skb_shinfo(skb)->gso_size != 0) {
1495 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1496 /* UDP - UFO */
1497 lso_ctrl = MACB_LSO_UFO_ENABLE;
1498 else
1499 /* TCP - TSO */
1500 lso_ctrl = MACB_LSO_TSO_ENABLE;
1501 }
1502
1503 /* First, map non-paged data */
1504 len = skb_headlen(skb);
1505
1506 /* first buffer length */
1507 size = hdrlen;
1508
1509 offset = 0;
1510 while (len) {
1511 entry = macb_tx_ring_wrap(bp, tx_head);
1512 tx_skb = &queue->tx_skb[entry];
1513
1514 mapping = dma_map_single(&bp->pdev->dev,
1515 skb->data + offset,
1516 size, DMA_TO_DEVICE);
1517 if (dma_mapping_error(&bp->pdev->dev, mapping))
1518 goto dma_error;
1519
1520 /* Save info to properly release resources */
1521 tx_skb->skb = NULL;
1522 tx_skb->mapping = mapping;
1523 tx_skb->size = size;
1524 tx_skb->mapped_as_page = false;
1525
1526 len -= size;
1527 offset += size;
1528 count++;
1529 tx_head++;
1530
1531 size = min(len, bp->max_tx_length);
1532 }
1533
1534 /* Then, map paged data from fragments */
1535 for (f = 0; f < nr_frags; f++) {
1536 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1537
1538 len = skb_frag_size(frag);
1539 offset = 0;
1540 while (len) {
1541 size = min(len, bp->max_tx_length);
1542 entry = macb_tx_ring_wrap(bp, tx_head);
1543 tx_skb = &queue->tx_skb[entry];
1544
1545 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1546 offset, size, DMA_TO_DEVICE);
1547 if (dma_mapping_error(&bp->pdev->dev, mapping))
1548 goto dma_error;
1549
1550 /* Save info to properly release resources */
1551 tx_skb->skb = NULL;
1552 tx_skb->mapping = mapping;
1553 tx_skb->size = size;
1554 tx_skb->mapped_as_page = true;
1555
1556 len -= size;
1557 offset += size;
1558 count++;
1559 tx_head++;
1560 }
1561 }
1562
1563 /* Should never happen */
1564 if (unlikely(!tx_skb)) {
1565 netdev_err(bp->dev, "BUG! empty skb!\n");
1566 return 0;
1567 }
1568
1569 /* This is the last buffer of the frame: save socket buffer */
1570 tx_skb->skb = skb;
1571
1572 /* Update TX ring: update buffer descriptors in reverse order
1573 * to avoid race condition
1574 */
1575
1576 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1577 * to set the end of TX queue
1578 */
1579 i = tx_head;
1580 entry = macb_tx_ring_wrap(bp, i);
1581 ctrl = MACB_BIT(TX_USED);
1582 desc = macb_tx_desc(queue, entry);
1583 desc->ctrl = ctrl;
1584
1585 if (lso_ctrl) {
1586 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1587 /* include header and FCS in value given to h/w */
1588 mss_mfs = skb_shinfo(skb)->gso_size +
1589 skb_transport_offset(skb) +
1590 ETH_FCS_LEN;
1591 else /* TSO */ {
1592 mss_mfs = skb_shinfo(skb)->gso_size;
1593 /* TCP Sequence Number Source Select
1594 * can be set only for TSO
1595 */
1596 seq_ctrl = 0;
1597 }
1598 }
1599
1600 do {
1601 i--;
1602 entry = macb_tx_ring_wrap(bp, i);
1603 tx_skb = &queue->tx_skb[entry];
1604 desc = macb_tx_desc(queue, entry);
1605
1606 ctrl = (u32)tx_skb->size;
1607 if (eof) {
1608 ctrl |= MACB_BIT(TX_LAST);
1609 eof = 0;
1610 }
1611 if (unlikely(entry == (bp->tx_ring_size - 1)))
1612 ctrl |= MACB_BIT(TX_WRAP);
1613
1614 /* First descriptor is header descriptor */
1615 if (i == queue->tx_head) {
1616 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1617 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1618 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1619 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1620 ctrl |= MACB_BIT(TX_NOCRC);
1621 } else
1622 /* Only set MSS/MFS on payload descriptors
1623 * (second or later descriptor)
1624 */
1625 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1626
1627 /* Set TX buffer descriptor */
1628 macb_set_addr(bp, desc, tx_skb->mapping);
1629 /* desc->addr must be visible to hardware before clearing
1630 * 'TX_USED' bit in desc->ctrl.
1631 */
1632 wmb();
1633 desc->ctrl = ctrl;
1634 } while (i != queue->tx_head);
1635
1636 queue->tx_head = tx_head;
1637
1638 return count;
1639
1640 dma_error:
1641 netdev_err(bp->dev, "TX DMA map failed\n");
1642
1643 for (i = queue->tx_head; i != tx_head; i++) {
1644 tx_skb = macb_tx_skb(queue, i);
1645
1646 macb_tx_unmap(bp, tx_skb);
1647 }
1648
1649 return 0;
1650 }
1651
1652 static netdev_features_t macb_features_check(struct sk_buff *skb,
1653 struct net_device *dev,
1654 netdev_features_t features)
1655 {
1656 unsigned int nr_frags, f;
1657 unsigned int hdrlen;
1658
1659 /* Validate LSO compatibility */
1660
1661 /* there is only one buffer or protocol is not UDP */
1662 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
1663 return features;
1664
1665 /* length of header */
1666 hdrlen = skb_transport_offset(skb);
1667
1668 /* For UFO only:
1669 * When software supplies two or more payload buffers all payload buffers
1670 * apart from the last must be a multiple of 8 bytes in size.
1671 */
1672 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1673 return features & ~MACB_NETIF_LSO;
1674
1675 nr_frags = skb_shinfo(skb)->nr_frags;
1676 /* No need to check last fragment */
1677 nr_frags--;
1678 for (f = 0; f < nr_frags; f++) {
1679 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1680
1681 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1682 return features & ~MACB_NETIF_LSO;
1683 }
1684 return features;
1685 }
1686
1687 static inline int macb_clear_csum(struct sk_buff *skb)
1688 {
1689 /* no change for packets without checksum offloading */
1690 if (skb->ip_summed != CHECKSUM_PARTIAL)
1691 return 0;
1692
1693 /* make sure we can modify the header */
1694 if (unlikely(skb_cow_head(skb, 0)))
1695 return -1;
1696
1697 /* initialize checksum field
1698 * This is required - at least for Zynq, which otherwise calculates
1699 * wrong UDP header checksums for UDP packets with UDP data len <=2
1700 */
1701 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1702 return 0;
1703 }
1704
1705 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1706 {
1707 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb);
1708 int padlen = ETH_ZLEN - (*skb)->len;
1709 int headroom = skb_headroom(*skb);
1710 int tailroom = skb_tailroom(*skb);
1711 struct sk_buff *nskb;
1712 u32 fcs;
1713
1714 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1715 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1716 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1717 return 0;
1718
1719 if (padlen <= 0) {
1720 /* FCS could be appeded to tailroom. */
1721 if (tailroom >= ETH_FCS_LEN)
1722 goto add_fcs;
1723 /* FCS could be appeded by moving data to headroom. */
1724 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1725 padlen = 0;
1726 /* No room for FCS, need to reallocate skb. */
1727 else
1728 padlen = ETH_FCS_LEN;
1729 } else {
1730 /* Add room for FCS. */
1731 padlen += ETH_FCS_LEN;
1732 }
1733
1734 if (!cloned && headroom + tailroom >= padlen) {
1735 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1736 skb_set_tail_pointer(*skb, (*skb)->len);
1737 } else {
1738 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1739 if (!nskb)
1740 return -ENOMEM;
1741
1742 dev_kfree_skb_any(*skb);
1743 *skb = nskb;
1744 }
1745
1746 if (padlen) {
1747 if (padlen >= ETH_FCS_LEN)
1748 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1749 else
1750 skb_trim(*skb, ETH_FCS_LEN - padlen);
1751 }
1752
1753 add_fcs:
1754 /* set FCS to packet */
1755 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1756 fcs = ~fcs;
1757
1758 skb_put_u8(*skb, fcs & 0xff);
1759 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1760 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1761 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1762
1763 return 0;
1764 }
1765
1766 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1767 {
1768 u16 queue_index = skb_get_queue_mapping(skb);
1769 struct macb *bp = netdev_priv(dev);
1770 struct macb_queue *queue = &bp->queues[queue_index];
1771 unsigned long flags;
1772 unsigned int desc_cnt, nr_frags, frag_size, f;
1773 unsigned int hdrlen;
1774 bool is_lso, is_udp = 0;
1775 netdev_tx_t ret = NETDEV_TX_OK;
1776
1777 if (macb_clear_csum(skb)) {
1778 dev_kfree_skb_any(skb);
1779 return ret;
1780 }
1781
1782 if (macb_pad_and_fcs(&skb, dev)) {
1783 dev_kfree_skb_any(skb);
1784 return ret;
1785 }
1786
1787 is_lso = (skb_shinfo(skb)->gso_size != 0);
1788
1789 if (is_lso) {
1790 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1791
1792 /* length of headers */
1793 if (is_udp)
1794 /* only queue eth + ip headers separately for UDP */
1795 hdrlen = skb_transport_offset(skb);
1796 else
1797 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1798 if (skb_headlen(skb) < hdrlen) {
1799 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1800 /* if this is required, would need to copy to single buffer */
1801 return NETDEV_TX_BUSY;
1802 }
1803 } else
1804 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1805
1806 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1807 netdev_vdbg(bp->dev,
1808 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1809 queue_index, skb->len, skb->head, skb->data,
1810 skb_tail_pointer(skb), skb_end_pointer(skb));
1811 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1812 skb->data, 16, true);
1813 #endif
1814
1815 /* Count how many TX buffer descriptors are needed to send this
1816 * socket buffer: skb fragments of jumbo frames may need to be
1817 * split into many buffer descriptors.
1818 */
1819 if (is_lso && (skb_headlen(skb) > hdrlen))
1820 /* extra header descriptor if also payload in first buffer */
1821 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1822 else
1823 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1824 nr_frags = skb_shinfo(skb)->nr_frags;
1825 for (f = 0; f < nr_frags; f++) {
1826 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1827 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1828 }
1829
1830 spin_lock_irqsave(&bp->lock, flags);
1831
1832 /* This is a hard error, log it. */
1833 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1834 bp->tx_ring_size) < desc_cnt) {
1835 netif_stop_subqueue(dev, queue_index);
1836 spin_unlock_irqrestore(&bp->lock, flags);
1837 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1838 queue->tx_head, queue->tx_tail);
1839 return NETDEV_TX_BUSY;
1840 }
1841
1842 /* Map socket buffer for DMA transfer */
1843 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1844 dev_kfree_skb_any(skb);
1845 goto unlock;
1846 }
1847
1848 /* Make newly initialized descriptor visible to hardware */
1849 wmb();
1850 skb_tx_timestamp(skb);
1851
1852 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1853
1854 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1855 netif_stop_subqueue(dev, queue_index);
1856
1857 unlock:
1858 spin_unlock_irqrestore(&bp->lock, flags);
1859
1860 return ret;
1861 }
1862
1863 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1864 {
1865 if (!macb_is_gem(bp)) {
1866 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1867 } else {
1868 bp->rx_buffer_size = size;
1869
1870 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1871 netdev_dbg(bp->dev,
1872 "RX buffer must be multiple of %d bytes, expanding\n",
1873 RX_BUFFER_MULTIPLE);
1874 bp->rx_buffer_size =
1875 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1876 }
1877 }
1878
1879 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
1880 bp->dev->mtu, bp->rx_buffer_size);
1881 }
1882
1883 static void gem_free_rx_buffers(struct macb *bp)
1884 {
1885 struct sk_buff *skb;
1886 struct macb_dma_desc *desc;
1887 struct macb_queue *queue;
1888 dma_addr_t addr;
1889 unsigned int q;
1890 int i;
1891
1892 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1893 if (!queue->rx_skbuff)
1894 continue;
1895
1896 for (i = 0; i < bp->rx_ring_size; i++) {
1897 skb = queue->rx_skbuff[i];
1898
1899 if (!skb)
1900 continue;
1901
1902 desc = macb_rx_desc(queue, i);
1903 addr = macb_get_addr(bp, desc);
1904
1905 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1906 DMA_FROM_DEVICE);
1907 dev_kfree_skb_any(skb);
1908 skb = NULL;
1909 }
1910
1911 kfree(queue->rx_skbuff);
1912 queue->rx_skbuff = NULL;
1913 }
1914 }
1915
1916 static void macb_free_rx_buffers(struct macb *bp)
1917 {
1918 struct macb_queue *queue = &bp->queues[0];
1919
1920 if (queue->rx_buffers) {
1921 dma_free_coherent(&bp->pdev->dev,
1922 bp->rx_ring_size * bp->rx_buffer_size,
1923 queue->rx_buffers, queue->rx_buffers_dma);
1924 queue->rx_buffers = NULL;
1925 }
1926 }
1927
1928 static void macb_free_consistent(struct macb *bp)
1929 {
1930 struct macb_queue *queue;
1931 unsigned int q;
1932 int size;
1933
1934 bp->macbgem_ops.mog_free_rx_buffers(bp);
1935
1936 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1937 kfree(queue->tx_skb);
1938 queue->tx_skb = NULL;
1939 if (queue->tx_ring) {
1940 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
1941 dma_free_coherent(&bp->pdev->dev, size,
1942 queue->tx_ring, queue->tx_ring_dma);
1943 queue->tx_ring = NULL;
1944 }
1945 if (queue->rx_ring) {
1946 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
1947 dma_free_coherent(&bp->pdev->dev, size,
1948 queue->rx_ring, queue->rx_ring_dma);
1949 queue->rx_ring = NULL;
1950 }
1951 }
1952 }
1953
1954 static int gem_alloc_rx_buffers(struct macb *bp)
1955 {
1956 struct macb_queue *queue;
1957 unsigned int q;
1958 int size;
1959
1960 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1961 size = bp->rx_ring_size * sizeof(struct sk_buff *);
1962 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
1963 if (!queue->rx_skbuff)
1964 return -ENOMEM;
1965 else
1966 netdev_dbg(bp->dev,
1967 "Allocated %d RX struct sk_buff entries at %p\n",
1968 bp->rx_ring_size, queue->rx_skbuff);
1969 }
1970 return 0;
1971 }
1972
1973 static int macb_alloc_rx_buffers(struct macb *bp)
1974 {
1975 struct macb_queue *queue = &bp->queues[0];
1976 int size;
1977
1978 size = bp->rx_ring_size * bp->rx_buffer_size;
1979 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1980 &queue->rx_buffers_dma, GFP_KERNEL);
1981 if (!queue->rx_buffers)
1982 return -ENOMEM;
1983
1984 netdev_dbg(bp->dev,
1985 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1986 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
1987 return 0;
1988 }
1989
1990 static int macb_alloc_consistent(struct macb *bp)
1991 {
1992 struct macb_queue *queue;
1993 unsigned int q;
1994 int size;
1995
1996 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1997 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
1998 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1999 &queue->tx_ring_dma,
2000 GFP_KERNEL);
2001 if (!queue->tx_ring)
2002 goto out_err;
2003 netdev_dbg(bp->dev,
2004 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2005 q, size, (unsigned long)queue->tx_ring_dma,
2006 queue->tx_ring);
2007
2008 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2009 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2010 if (!queue->tx_skb)
2011 goto out_err;
2012
2013 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2014 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2015 &queue->rx_ring_dma, GFP_KERNEL);
2016 if (!queue->rx_ring)
2017 goto out_err;
2018 netdev_dbg(bp->dev,
2019 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2020 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2021 }
2022 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2023 goto out_err;
2024
2025 return 0;
2026
2027 out_err:
2028 macb_free_consistent(bp);
2029 return -ENOMEM;
2030 }
2031
2032 static void gem_init_rings(struct macb *bp)
2033 {
2034 struct macb_queue *queue;
2035 struct macb_dma_desc *desc = NULL;
2036 unsigned int q;
2037 int i;
2038
2039 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2040 for (i = 0; i < bp->tx_ring_size; i++) {
2041 desc = macb_tx_desc(queue, i);
2042 macb_set_addr(bp, desc, 0);
2043 desc->ctrl = MACB_BIT(TX_USED);
2044 }
2045 desc->ctrl |= MACB_BIT(TX_WRAP);
2046 queue->tx_head = 0;
2047 queue->tx_tail = 0;
2048
2049 queue->rx_tail = 0;
2050 queue->rx_prepared_head = 0;
2051
2052 gem_rx_refill(queue);
2053 }
2054
2055 }
2056
2057 static void macb_init_rings(struct macb *bp)
2058 {
2059 int i;
2060 struct macb_dma_desc *desc = NULL;
2061
2062 macb_init_rx_ring(&bp->queues[0]);
2063
2064 for (i = 0; i < bp->tx_ring_size; i++) {
2065 desc = macb_tx_desc(&bp->queues[0], i);
2066 macb_set_addr(bp, desc, 0);
2067 desc->ctrl = MACB_BIT(TX_USED);
2068 }
2069 bp->queues[0].tx_head = 0;
2070 bp->queues[0].tx_tail = 0;
2071 desc->ctrl |= MACB_BIT(TX_WRAP);
2072 }
2073
2074 static void macb_reset_hw(struct macb *bp)
2075 {
2076 struct macb_queue *queue;
2077 unsigned int q;
2078 u32 ctrl = macb_readl(bp, NCR);
2079
2080 /* Disable RX and TX (XXX: Should we halt the transmission
2081 * more gracefully?)
2082 */
2083 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2084
2085 /* Clear the stats registers (XXX: Update stats first?) */
2086 ctrl |= MACB_BIT(CLRSTAT);
2087
2088 macb_writel(bp, NCR, ctrl);
2089
2090 /* Clear all status flags */
2091 macb_writel(bp, TSR, -1);
2092 macb_writel(bp, RSR, -1);
2093
2094 /* Disable all interrupts */
2095 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2096 queue_writel(queue, IDR, -1);
2097 queue_readl(queue, ISR);
2098 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2099 queue_writel(queue, ISR, -1);
2100 }
2101 }
2102
2103 static u32 gem_mdc_clk_div(struct macb *bp)
2104 {
2105 u32 config;
2106 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2107
2108 if (pclk_hz <= 20000000)
2109 config = GEM_BF(CLK, GEM_CLK_DIV8);
2110 else if (pclk_hz <= 40000000)
2111 config = GEM_BF(CLK, GEM_CLK_DIV16);
2112 else if (pclk_hz <= 80000000)
2113 config = GEM_BF(CLK, GEM_CLK_DIV32);
2114 else if (pclk_hz <= 120000000)
2115 config = GEM_BF(CLK, GEM_CLK_DIV48);
2116 else if (pclk_hz <= 160000000)
2117 config = GEM_BF(CLK, GEM_CLK_DIV64);
2118 else
2119 config = GEM_BF(CLK, GEM_CLK_DIV96);
2120
2121 return config;
2122 }
2123
2124 static u32 macb_mdc_clk_div(struct macb *bp)
2125 {
2126 u32 config;
2127 unsigned long pclk_hz;
2128
2129 if (macb_is_gem(bp))
2130 return gem_mdc_clk_div(bp);
2131
2132 pclk_hz = clk_get_rate(bp->pclk);
2133 if (pclk_hz <= 20000000)
2134 config = MACB_BF(CLK, MACB_CLK_DIV8);
2135 else if (pclk_hz <= 40000000)
2136 config = MACB_BF(CLK, MACB_CLK_DIV16);
2137 else if (pclk_hz <= 80000000)
2138 config = MACB_BF(CLK, MACB_CLK_DIV32);
2139 else
2140 config = MACB_BF(CLK, MACB_CLK_DIV64);
2141
2142 return config;
2143 }
2144
2145 /* Get the DMA bus width field of the network configuration register that we
2146 * should program. We find the width from decoding the design configuration
2147 * register to find the maximum supported data bus width.
2148 */
2149 static u32 macb_dbw(struct macb *bp)
2150 {
2151 if (!macb_is_gem(bp))
2152 return 0;
2153
2154 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2155 case 4:
2156 return GEM_BF(DBW, GEM_DBW128);
2157 case 2:
2158 return GEM_BF(DBW, GEM_DBW64);
2159 case 1:
2160 default:
2161 return GEM_BF(DBW, GEM_DBW32);
2162 }
2163 }
2164
2165 /* Configure the receive DMA engine
2166 * - use the correct receive buffer size
2167 * - set best burst length for DMA operations
2168 * (if not supported by FIFO, it will fallback to default)
2169 * - set both rx/tx packet buffers to full memory size
2170 * These are configurable parameters for GEM.
2171 */
2172 static void macb_configure_dma(struct macb *bp)
2173 {
2174 struct macb_queue *queue;
2175 u32 buffer_size;
2176 unsigned int q;
2177 u32 dmacfg;
2178
2179 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2180 if (macb_is_gem(bp)) {
2181 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2182 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2183 if (q)
2184 queue_writel(queue, RBQS, buffer_size);
2185 else
2186 dmacfg |= GEM_BF(RXBS, buffer_size);
2187 }
2188 if (bp->dma_burst_length)
2189 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2190 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2191 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2192
2193 if (bp->native_io)
2194 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2195 else
2196 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2197
2198 if (bp->dev->features & NETIF_F_HW_CSUM)
2199 dmacfg |= GEM_BIT(TXCOEN);
2200 else
2201 dmacfg &= ~GEM_BIT(TXCOEN);
2202
2203 dmacfg &= ~GEM_BIT(ADDR64);
2204 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2205 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2206 dmacfg |= GEM_BIT(ADDR64);
2207 #endif
2208 #ifdef CONFIG_MACB_USE_HWSTAMP
2209 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2210 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2211 #endif
2212 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2213 dmacfg);
2214 gem_writel(bp, DMACFG, dmacfg);
2215 }
2216 }
2217
2218 static void macb_init_hw(struct macb *bp)
2219 {
2220 struct macb_queue *queue;
2221 unsigned int q;
2222
2223 u32 config;
2224
2225 macb_reset_hw(bp);
2226 macb_set_hwaddr(bp);
2227
2228 config = macb_mdc_clk_div(bp);
2229 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2230 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2231 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2232 config |= MACB_BIT(PAE); /* PAuse Enable */
2233 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2234 if (bp->caps & MACB_CAPS_JUMBO)
2235 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2236 else
2237 config |= MACB_BIT(BIG); /* Receive oversized frames */
2238 if (bp->dev->flags & IFF_PROMISC)
2239 config |= MACB_BIT(CAF); /* Copy All Frames */
2240 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2241 config |= GEM_BIT(RXCOEN);
2242 if (!(bp->dev->flags & IFF_BROADCAST))
2243 config |= MACB_BIT(NBC); /* No BroadCast */
2244 config |= macb_dbw(bp);
2245 macb_writel(bp, NCFGR, config);
2246 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2247 gem_writel(bp, JML, bp->jumbo_max_len);
2248 bp->speed = SPEED_10;
2249 bp->duplex = DUPLEX_HALF;
2250 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2251 if (bp->caps & MACB_CAPS_JUMBO)
2252 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2253
2254 macb_configure_dma(bp);
2255
2256 /* Initialize TX and RX buffers */
2257 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2258 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
2259 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2260 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2261 queue_writel(queue, RBQPH, upper_32_bits(queue->rx_ring_dma));
2262 #endif
2263 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
2264 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2265 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2266 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
2267 #endif
2268
2269 /* Enable interrupts */
2270 queue_writel(queue, IER,
2271 bp->rx_intr_mask |
2272 MACB_TX_INT_FLAGS |
2273 MACB_BIT(HRESP));
2274 }
2275
2276 /* Enable TX and RX */
2277 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
2278 }
2279
2280 /* The hash address register is 64 bits long and takes up two
2281 * locations in the memory map. The least significant bits are stored
2282 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2283 *
2284 * The unicast hash enable and the multicast hash enable bits in the
2285 * network configuration register enable the reception of hash matched
2286 * frames. The destination address is reduced to a 6 bit index into
2287 * the 64 bit hash register using the following hash function. The
2288 * hash function is an exclusive or of every sixth bit of the
2289 * destination address.
2290 *
2291 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2292 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2293 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2294 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2295 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2296 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2297 *
2298 * da[0] represents the least significant bit of the first byte
2299 * received, that is, the multicast/unicast indicator, and da[47]
2300 * represents the most significant bit of the last byte received. If
2301 * the hash index, hi[n], points to a bit that is set in the hash
2302 * register then the frame will be matched according to whether the
2303 * frame is multicast or unicast. A multicast match will be signalled
2304 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2305 * index points to a bit set in the hash register. A unicast match
2306 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2307 * and the hash index points to a bit set in the hash register. To
2308 * receive all multicast frames, the hash register should be set with
2309 * all ones and the multicast hash enable bit should be set in the
2310 * network configuration register.
2311 */
2312
2313 static inline int hash_bit_value(int bitnr, __u8 *addr)
2314 {
2315 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2316 return 1;
2317 return 0;
2318 }
2319
2320 /* Return the hash index value for the specified address. */
2321 static int hash_get_index(__u8 *addr)
2322 {
2323 int i, j, bitval;
2324 int hash_index = 0;
2325
2326 for (j = 0; j < 6; j++) {
2327 for (i = 0, bitval = 0; i < 8; i++)
2328 bitval ^= hash_bit_value(i * 6 + j, addr);
2329
2330 hash_index |= (bitval << j);
2331 }
2332
2333 return hash_index;
2334 }
2335
2336 /* Add multicast addresses to the internal multicast-hash table. */
2337 static void macb_sethashtable(struct net_device *dev)
2338 {
2339 struct netdev_hw_addr *ha;
2340 unsigned long mc_filter[2];
2341 unsigned int bitnr;
2342 struct macb *bp = netdev_priv(dev);
2343
2344 mc_filter[0] = 0;
2345 mc_filter[1] = 0;
2346
2347 netdev_for_each_mc_addr(ha, dev) {
2348 bitnr = hash_get_index(ha->addr);
2349 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2350 }
2351
2352 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2353 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2354 }
2355
2356 /* Enable/Disable promiscuous and multicast modes. */
2357 static void macb_set_rx_mode(struct net_device *dev)
2358 {
2359 unsigned long cfg;
2360 struct macb *bp = netdev_priv(dev);
2361
2362 cfg = macb_readl(bp, NCFGR);
2363
2364 if (dev->flags & IFF_PROMISC) {
2365 /* Enable promiscuous mode */
2366 cfg |= MACB_BIT(CAF);
2367
2368 /* Disable RX checksum offload */
2369 if (macb_is_gem(bp))
2370 cfg &= ~GEM_BIT(RXCOEN);
2371 } else {
2372 /* Disable promiscuous mode */
2373 cfg &= ~MACB_BIT(CAF);
2374
2375 /* Enable RX checksum offload only if requested */
2376 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2377 cfg |= GEM_BIT(RXCOEN);
2378 }
2379
2380 if (dev->flags & IFF_ALLMULTI) {
2381 /* Enable all multicast mode */
2382 macb_or_gem_writel(bp, HRB, -1);
2383 macb_or_gem_writel(bp, HRT, -1);
2384 cfg |= MACB_BIT(NCFGR_MTI);
2385 } else if (!netdev_mc_empty(dev)) {
2386 /* Enable specific multicasts */
2387 macb_sethashtable(dev);
2388 cfg |= MACB_BIT(NCFGR_MTI);
2389 } else if (dev->flags & (~IFF_ALLMULTI)) {
2390 /* Disable all multicast mode */
2391 macb_or_gem_writel(bp, HRB, 0);
2392 macb_or_gem_writel(bp, HRT, 0);
2393 cfg &= ~MACB_BIT(NCFGR_MTI);
2394 }
2395
2396 macb_writel(bp, NCFGR, cfg);
2397 }
2398
2399 static int macb_open(struct net_device *dev)
2400 {
2401 struct macb *bp = netdev_priv(dev);
2402 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2403 struct macb_queue *queue;
2404 unsigned int q;
2405 int err;
2406
2407 netdev_dbg(bp->dev, "open\n");
2408
2409 /* carrier starts down */
2410 netif_carrier_off(dev);
2411
2412 /* if the phy is not yet register, retry later*/
2413 if (!dev->phydev)
2414 return -EAGAIN;
2415
2416 /* RX buffers initialization */
2417 macb_init_rx_buffer_size(bp, bufsz);
2418
2419 err = macb_alloc_consistent(bp);
2420 if (err) {
2421 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2422 err);
2423 return err;
2424 }
2425
2426 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2427 napi_enable(&queue->napi);
2428
2429 bp->macbgem_ops.mog_init_rings(bp);
2430 macb_init_hw(bp);
2431
2432 /* schedule a link state check */
2433 phy_start(dev->phydev);
2434
2435 netif_tx_start_all_queues(dev);
2436
2437 if (bp->ptp_info)
2438 bp->ptp_info->ptp_init(dev);
2439
2440 return 0;
2441 }
2442
2443 static int macb_close(struct net_device *dev)
2444 {
2445 struct macb *bp = netdev_priv(dev);
2446 struct macb_queue *queue;
2447 unsigned long flags;
2448 unsigned int q;
2449
2450 netif_tx_stop_all_queues(dev);
2451
2452 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2453 napi_disable(&queue->napi);
2454
2455 if (dev->phydev)
2456 phy_stop(dev->phydev);
2457
2458 spin_lock_irqsave(&bp->lock, flags);
2459 macb_reset_hw(bp);
2460 netif_carrier_off(dev);
2461 spin_unlock_irqrestore(&bp->lock, flags);
2462
2463 macb_free_consistent(bp);
2464
2465 if (bp->ptp_info)
2466 bp->ptp_info->ptp_remove(dev);
2467
2468 return 0;
2469 }
2470
2471 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2472 {
2473 if (netif_running(dev))
2474 return -EBUSY;
2475
2476 dev->mtu = new_mtu;
2477
2478 return 0;
2479 }
2480
2481 static void gem_update_stats(struct macb *bp)
2482 {
2483 struct macb_queue *queue;
2484 unsigned int i, q, idx;
2485 unsigned long *stat;
2486
2487 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2488
2489 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2490 u32 offset = gem_statistics[i].offset;
2491 u64 val = bp->macb_reg_readl(bp, offset);
2492
2493 bp->ethtool_stats[i] += val;
2494 *p += val;
2495
2496 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2497 /* Add GEM_OCTTXH, GEM_OCTRXH */
2498 val = bp->macb_reg_readl(bp, offset + 4);
2499 bp->ethtool_stats[i] += ((u64)val) << 32;
2500 *(++p) += val;
2501 }
2502 }
2503
2504 idx = GEM_STATS_LEN;
2505 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2506 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2507 bp->ethtool_stats[idx++] = *stat;
2508 }
2509
2510 static struct net_device_stats *gem_get_stats(struct macb *bp)
2511 {
2512 struct gem_stats *hwstat = &bp->hw_stats.gem;
2513 struct net_device_stats *nstat = &bp->dev->stats;
2514
2515 gem_update_stats(bp);
2516
2517 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2518 hwstat->rx_alignment_errors +
2519 hwstat->rx_resource_errors +
2520 hwstat->rx_overruns +
2521 hwstat->rx_oversize_frames +
2522 hwstat->rx_jabbers +
2523 hwstat->rx_undersized_frames +
2524 hwstat->rx_length_field_frame_errors);
2525 nstat->tx_errors = (hwstat->tx_late_collisions +
2526 hwstat->tx_excessive_collisions +
2527 hwstat->tx_underrun +
2528 hwstat->tx_carrier_sense_errors);
2529 nstat->multicast = hwstat->rx_multicast_frames;
2530 nstat->collisions = (hwstat->tx_single_collision_frames +
2531 hwstat->tx_multiple_collision_frames +
2532 hwstat->tx_excessive_collisions);
2533 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2534 hwstat->rx_jabbers +
2535 hwstat->rx_undersized_frames +
2536 hwstat->rx_length_field_frame_errors);
2537 nstat->rx_over_errors = hwstat->rx_resource_errors;
2538 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2539 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2540 nstat->rx_fifo_errors = hwstat->rx_overruns;
2541 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2542 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2543 nstat->tx_fifo_errors = hwstat->tx_underrun;
2544
2545 return nstat;
2546 }
2547
2548 static void gem_get_ethtool_stats(struct net_device *dev,
2549 struct ethtool_stats *stats, u64 *data)
2550 {
2551 struct macb *bp;
2552
2553 bp = netdev_priv(dev);
2554 gem_update_stats(bp);
2555 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2556 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2557 }
2558
2559 static int gem_get_sset_count(struct net_device *dev, int sset)
2560 {
2561 struct macb *bp = netdev_priv(dev);
2562
2563 switch (sset) {
2564 case ETH_SS_STATS:
2565 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2566 default:
2567 return -EOPNOTSUPP;
2568 }
2569 }
2570
2571 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2572 {
2573 char stat_string[ETH_GSTRING_LEN];
2574 struct macb *bp = netdev_priv(dev);
2575 struct macb_queue *queue;
2576 unsigned int i;
2577 unsigned int q;
2578
2579 switch (sset) {
2580 case ETH_SS_STATS:
2581 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2582 memcpy(p, gem_statistics[i].stat_string,
2583 ETH_GSTRING_LEN);
2584
2585 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2586 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2587 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2588 q, queue_statistics[i].stat_string);
2589 memcpy(p, stat_string, ETH_GSTRING_LEN);
2590 }
2591 }
2592 break;
2593 }
2594 }
2595
2596 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2597 {
2598 struct macb *bp = netdev_priv(dev);
2599 struct net_device_stats *nstat = &bp->dev->stats;
2600 struct macb_stats *hwstat = &bp->hw_stats.macb;
2601
2602 if (macb_is_gem(bp))
2603 return gem_get_stats(bp);
2604
2605 /* read stats from hardware */
2606 macb_update_stats(bp);
2607
2608 /* Convert HW stats into netdevice stats */
2609 nstat->rx_errors = (hwstat->rx_fcs_errors +
2610 hwstat->rx_align_errors +
2611 hwstat->rx_resource_errors +
2612 hwstat->rx_overruns +
2613 hwstat->rx_oversize_pkts +
2614 hwstat->rx_jabbers +
2615 hwstat->rx_undersize_pkts +
2616 hwstat->rx_length_mismatch);
2617 nstat->tx_errors = (hwstat->tx_late_cols +
2618 hwstat->tx_excessive_cols +
2619 hwstat->tx_underruns +
2620 hwstat->tx_carrier_errors +
2621 hwstat->sqe_test_errors);
2622 nstat->collisions = (hwstat->tx_single_cols +
2623 hwstat->tx_multiple_cols +
2624 hwstat->tx_excessive_cols);
2625 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2626 hwstat->rx_jabbers +
2627 hwstat->rx_undersize_pkts +
2628 hwstat->rx_length_mismatch);
2629 nstat->rx_over_errors = hwstat->rx_resource_errors +
2630 hwstat->rx_overruns;
2631 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2632 nstat->rx_frame_errors = hwstat->rx_align_errors;
2633 nstat->rx_fifo_errors = hwstat->rx_overruns;
2634 /* XXX: What does "missed" mean? */
2635 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2636 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2637 nstat->tx_fifo_errors = hwstat->tx_underruns;
2638 /* Don't know about heartbeat or window errors... */
2639
2640 return nstat;
2641 }
2642
2643 static int macb_get_regs_len(struct net_device *netdev)
2644 {
2645 return MACB_GREGS_NBR * sizeof(u32);
2646 }
2647
2648 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2649 void *p)
2650 {
2651 struct macb *bp = netdev_priv(dev);
2652 unsigned int tail, head;
2653 u32 *regs_buff = p;
2654
2655 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2656 | MACB_GREGS_VERSION;
2657
2658 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2659 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2660
2661 regs_buff[0] = macb_readl(bp, NCR);
2662 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2663 regs_buff[2] = macb_readl(bp, NSR);
2664 regs_buff[3] = macb_readl(bp, TSR);
2665 regs_buff[4] = macb_readl(bp, RBQP);
2666 regs_buff[5] = macb_readl(bp, TBQP);
2667 regs_buff[6] = macb_readl(bp, RSR);
2668 regs_buff[7] = macb_readl(bp, IMR);
2669
2670 regs_buff[8] = tail;
2671 regs_buff[9] = head;
2672 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2673 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2674
2675 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2676 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2677 if (macb_is_gem(bp))
2678 regs_buff[13] = gem_readl(bp, DMACFG);
2679 }
2680
2681 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2682 {
2683 struct macb *bp = netdev_priv(netdev);
2684
2685 wol->supported = 0;
2686 wol->wolopts = 0;
2687
2688 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2689 wol->supported = WAKE_MAGIC;
2690
2691 if (bp->wol & MACB_WOL_ENABLED)
2692 wol->wolopts |= WAKE_MAGIC;
2693 }
2694 }
2695
2696 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2697 {
2698 struct macb *bp = netdev_priv(netdev);
2699
2700 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2701 (wol->wolopts & ~WAKE_MAGIC))
2702 return -EOPNOTSUPP;
2703
2704 if (wol->wolopts & WAKE_MAGIC)
2705 bp->wol |= MACB_WOL_ENABLED;
2706 else
2707 bp->wol &= ~MACB_WOL_ENABLED;
2708
2709 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2710
2711 return 0;
2712 }
2713
2714 static void macb_get_ringparam(struct net_device *netdev,
2715 struct ethtool_ringparam *ring)
2716 {
2717 struct macb *bp = netdev_priv(netdev);
2718
2719 ring->rx_max_pending = MAX_RX_RING_SIZE;
2720 ring->tx_max_pending = MAX_TX_RING_SIZE;
2721
2722 ring->rx_pending = bp->rx_ring_size;
2723 ring->tx_pending = bp->tx_ring_size;
2724 }
2725
2726 static int macb_set_ringparam(struct net_device *netdev,
2727 struct ethtool_ringparam *ring)
2728 {
2729 struct macb *bp = netdev_priv(netdev);
2730 u32 new_rx_size, new_tx_size;
2731 unsigned int reset = 0;
2732
2733 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2734 return -EINVAL;
2735
2736 new_rx_size = clamp_t(u32, ring->rx_pending,
2737 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2738 new_rx_size = roundup_pow_of_two(new_rx_size);
2739
2740 new_tx_size = clamp_t(u32, ring->tx_pending,
2741 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2742 new_tx_size = roundup_pow_of_two(new_tx_size);
2743
2744 if ((new_tx_size == bp->tx_ring_size) &&
2745 (new_rx_size == bp->rx_ring_size)) {
2746 /* nothing to do */
2747 return 0;
2748 }
2749
2750 if (netif_running(bp->dev)) {
2751 reset = 1;
2752 macb_close(bp->dev);
2753 }
2754
2755 bp->rx_ring_size = new_rx_size;
2756 bp->tx_ring_size = new_tx_size;
2757
2758 if (reset)
2759 macb_open(bp->dev);
2760
2761 return 0;
2762 }
2763
2764 #ifdef CONFIG_MACB_USE_HWSTAMP
2765 static unsigned int gem_get_tsu_rate(struct macb *bp)
2766 {
2767 struct clk *tsu_clk;
2768 unsigned int tsu_rate;
2769
2770 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2771 if (!IS_ERR(tsu_clk))
2772 tsu_rate = clk_get_rate(tsu_clk);
2773 /* try pclk instead */
2774 else if (!IS_ERR(bp->pclk)) {
2775 tsu_clk = bp->pclk;
2776 tsu_rate = clk_get_rate(tsu_clk);
2777 } else
2778 return -ENOTSUPP;
2779 return tsu_rate;
2780 }
2781
2782 static s32 gem_get_ptp_max_adj(void)
2783 {
2784 return 64000000;
2785 }
2786
2787 static int gem_get_ts_info(struct net_device *dev,
2788 struct ethtool_ts_info *info)
2789 {
2790 struct macb *bp = netdev_priv(dev);
2791
2792 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2793 ethtool_op_get_ts_info(dev, info);
2794 return 0;
2795 }
2796
2797 info->so_timestamping =
2798 SOF_TIMESTAMPING_TX_SOFTWARE |
2799 SOF_TIMESTAMPING_RX_SOFTWARE |
2800 SOF_TIMESTAMPING_SOFTWARE |
2801 SOF_TIMESTAMPING_TX_HARDWARE |
2802 SOF_TIMESTAMPING_RX_HARDWARE |
2803 SOF_TIMESTAMPING_RAW_HARDWARE;
2804 info->tx_types =
2805 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2806 (1 << HWTSTAMP_TX_OFF) |
2807 (1 << HWTSTAMP_TX_ON);
2808 info->rx_filters =
2809 (1 << HWTSTAMP_FILTER_NONE) |
2810 (1 << HWTSTAMP_FILTER_ALL);
2811
2812 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2813
2814 return 0;
2815 }
2816
2817 static struct macb_ptp_info gem_ptp_info = {
2818 .ptp_init = gem_ptp_init,
2819 .ptp_remove = gem_ptp_remove,
2820 .get_ptp_max_adj = gem_get_ptp_max_adj,
2821 .get_tsu_rate = gem_get_tsu_rate,
2822 .get_ts_info = gem_get_ts_info,
2823 .get_hwtst = gem_get_hwtst,
2824 .set_hwtst = gem_set_hwtst,
2825 };
2826 #endif
2827
2828 static int macb_get_ts_info(struct net_device *netdev,
2829 struct ethtool_ts_info *info)
2830 {
2831 struct macb *bp = netdev_priv(netdev);
2832
2833 if (bp->ptp_info)
2834 return bp->ptp_info->get_ts_info(netdev, info);
2835
2836 return ethtool_op_get_ts_info(netdev, info);
2837 }
2838
2839 static void gem_enable_flow_filters(struct macb *bp, bool enable)
2840 {
2841 struct ethtool_rx_fs_item *item;
2842 u32 t2_scr;
2843 int num_t2_scr;
2844
2845 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
2846
2847 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2848 struct ethtool_rx_flow_spec *fs = &item->fs;
2849 struct ethtool_tcpip4_spec *tp4sp_m;
2850
2851 if (fs->location >= num_t2_scr)
2852 continue;
2853
2854 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
2855
2856 /* enable/disable screener regs for the flow entry */
2857 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
2858
2859 /* only enable fields with no masking */
2860 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2861
2862 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
2863 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
2864 else
2865 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
2866
2867 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
2868 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
2869 else
2870 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
2871
2872 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
2873 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
2874 else
2875 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
2876
2877 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
2878 }
2879 }
2880
2881 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
2882 {
2883 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
2884 uint16_t index = fs->location;
2885 u32 w0, w1, t2_scr;
2886 bool cmp_a = false;
2887 bool cmp_b = false;
2888 bool cmp_c = false;
2889
2890 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
2891 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2892
2893 /* ignore field if any masking set */
2894 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
2895 /* 1st compare reg - IP source address */
2896 w0 = 0;
2897 w1 = 0;
2898 w0 = tp4sp_v->ip4src;
2899 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2900 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2901 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
2902 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
2903 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
2904 cmp_a = true;
2905 }
2906
2907 /* ignore field if any masking set */
2908 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
2909 /* 2nd compare reg - IP destination address */
2910 w0 = 0;
2911 w1 = 0;
2912 w0 = tp4sp_v->ip4dst;
2913 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2914 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2915 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
2916 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
2917 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
2918 cmp_b = true;
2919 }
2920
2921 /* ignore both port fields if masking set in both */
2922 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
2923 /* 3rd compare reg - source port, destination port */
2924 w0 = 0;
2925 w1 = 0;
2926 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
2927 if (tp4sp_m->psrc == tp4sp_m->pdst) {
2928 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
2929 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2930 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2931 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2932 } else {
2933 /* only one port definition */
2934 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
2935 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
2936 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
2937 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
2938 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2939 } else { /* dst port */
2940 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2941 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
2942 }
2943 }
2944 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
2945 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
2946 cmp_c = true;
2947 }
2948
2949 t2_scr = 0;
2950 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
2951 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
2952 if (cmp_a)
2953 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
2954 if (cmp_b)
2955 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
2956 if (cmp_c)
2957 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
2958 gem_writel_n(bp, SCRT2, index, t2_scr);
2959 }
2960
2961 static int gem_add_flow_filter(struct net_device *netdev,
2962 struct ethtool_rxnfc *cmd)
2963 {
2964 struct macb *bp = netdev_priv(netdev);
2965 struct ethtool_rx_flow_spec *fs = &cmd->fs;
2966 struct ethtool_rx_fs_item *item, *newfs;
2967 unsigned long flags;
2968 int ret = -EINVAL;
2969 bool added = false;
2970
2971 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
2972 if (newfs == NULL)
2973 return -ENOMEM;
2974 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
2975
2976 netdev_dbg(netdev,
2977 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
2978 fs->flow_type, (int)fs->ring_cookie, fs->location,
2979 htonl(fs->h_u.tcp_ip4_spec.ip4src),
2980 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
2981 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
2982
2983 spin_lock_irqsave(&bp->rx_fs_lock, flags);
2984
2985 /* find correct place to add in list */
2986 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2987 if (item->fs.location > newfs->fs.location) {
2988 list_add_tail(&newfs->list, &item->list);
2989 added = true;
2990 break;
2991 } else if (item->fs.location == fs->location) {
2992 netdev_err(netdev, "Rule not added: location %d not free!\n",
2993 fs->location);
2994 ret = -EBUSY;
2995 goto err;
2996 }
2997 }
2998 if (!added)
2999 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3000
3001 gem_prog_cmp_regs(bp, fs);
3002 bp->rx_fs_list.count++;
3003 /* enable filtering if NTUPLE on */
3004 if (netdev->features & NETIF_F_NTUPLE)
3005 gem_enable_flow_filters(bp, 1);
3006
3007 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3008 return 0;
3009
3010 err:
3011 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3012 kfree(newfs);
3013 return ret;
3014 }
3015
3016 static int gem_del_flow_filter(struct net_device *netdev,
3017 struct ethtool_rxnfc *cmd)
3018 {
3019 struct macb *bp = netdev_priv(netdev);
3020 struct ethtool_rx_fs_item *item;
3021 struct ethtool_rx_flow_spec *fs;
3022 unsigned long flags;
3023
3024 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3025
3026 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3027 if (item->fs.location == cmd->fs.location) {
3028 /* disable screener regs for the flow entry */
3029 fs = &(item->fs);
3030 netdev_dbg(netdev,
3031 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3032 fs->flow_type, (int)fs->ring_cookie, fs->location,
3033 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3034 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3035 htons(fs->h_u.tcp_ip4_spec.psrc),
3036 htons(fs->h_u.tcp_ip4_spec.pdst));
3037
3038 gem_writel_n(bp, SCRT2, fs->location, 0);
3039
3040 list_del(&item->list);
3041 bp->rx_fs_list.count--;
3042 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3043 kfree(item);
3044 return 0;
3045 }
3046 }
3047
3048 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3049 return -EINVAL;
3050 }
3051
3052 static int gem_get_flow_entry(struct net_device *netdev,
3053 struct ethtool_rxnfc *cmd)
3054 {
3055 struct macb *bp = netdev_priv(netdev);
3056 struct ethtool_rx_fs_item *item;
3057
3058 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3059 if (item->fs.location == cmd->fs.location) {
3060 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3061 return 0;
3062 }
3063 }
3064 return -EINVAL;
3065 }
3066
3067 static int gem_get_all_flow_entries(struct net_device *netdev,
3068 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3069 {
3070 struct macb *bp = netdev_priv(netdev);
3071 struct ethtool_rx_fs_item *item;
3072 uint32_t cnt = 0;
3073
3074 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3075 if (cnt == cmd->rule_cnt)
3076 return -EMSGSIZE;
3077 rule_locs[cnt] = item->fs.location;
3078 cnt++;
3079 }
3080 cmd->data = bp->max_tuples;
3081 cmd->rule_cnt = cnt;
3082
3083 return 0;
3084 }
3085
3086 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3087 u32 *rule_locs)
3088 {
3089 struct macb *bp = netdev_priv(netdev);
3090 int ret = 0;
3091
3092 switch (cmd->cmd) {
3093 case ETHTOOL_GRXRINGS:
3094 cmd->data = bp->num_queues;
3095 break;
3096 case ETHTOOL_GRXCLSRLCNT:
3097 cmd->rule_cnt = bp->rx_fs_list.count;
3098 break;
3099 case ETHTOOL_GRXCLSRULE:
3100 ret = gem_get_flow_entry(netdev, cmd);
3101 break;
3102 case ETHTOOL_GRXCLSRLALL:
3103 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3104 break;
3105 default:
3106 netdev_err(netdev,
3107 "Command parameter %d is not supported\n", cmd->cmd);
3108 ret = -EOPNOTSUPP;
3109 }
3110
3111 return ret;
3112 }
3113
3114 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3115 {
3116 struct macb *bp = netdev_priv(netdev);
3117 int ret;
3118
3119 switch (cmd->cmd) {
3120 case ETHTOOL_SRXCLSRLINS:
3121 if ((cmd->fs.location >= bp->max_tuples)
3122 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3123 ret = -EINVAL;
3124 break;
3125 }
3126 ret = gem_add_flow_filter(netdev, cmd);
3127 break;
3128 case ETHTOOL_SRXCLSRLDEL:
3129 ret = gem_del_flow_filter(netdev, cmd);
3130 break;
3131 default:
3132 netdev_err(netdev,
3133 "Command parameter %d is not supported\n", cmd->cmd);
3134 ret = -EOPNOTSUPP;
3135 }
3136
3137 return ret;
3138 }
3139
3140 static const struct ethtool_ops macb_ethtool_ops = {
3141 .get_regs_len = macb_get_regs_len,
3142 .get_regs = macb_get_regs,
3143 .get_link = ethtool_op_get_link,
3144 .get_ts_info = ethtool_op_get_ts_info,
3145 .get_wol = macb_get_wol,
3146 .set_wol = macb_set_wol,
3147 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3148 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3149 .get_ringparam = macb_get_ringparam,
3150 .set_ringparam = macb_set_ringparam,
3151 };
3152
3153 static const struct ethtool_ops gem_ethtool_ops = {
3154 .get_regs_len = macb_get_regs_len,
3155 .get_regs = macb_get_regs,
3156 .get_link = ethtool_op_get_link,
3157 .get_ts_info = macb_get_ts_info,
3158 .get_ethtool_stats = gem_get_ethtool_stats,
3159 .get_strings = gem_get_ethtool_strings,
3160 .get_sset_count = gem_get_sset_count,
3161 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3162 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3163 .get_ringparam = macb_get_ringparam,
3164 .set_ringparam = macb_set_ringparam,
3165 .get_rxnfc = gem_get_rxnfc,
3166 .set_rxnfc = gem_set_rxnfc,
3167 };
3168
3169 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3170 {
3171 struct phy_device *phydev = dev->phydev;
3172 struct macb *bp = netdev_priv(dev);
3173
3174 if (!netif_running(dev))
3175 return -EINVAL;
3176
3177 if (!phydev)
3178 return -ENODEV;
3179
3180 if (!bp->ptp_info)
3181 return phy_mii_ioctl(phydev, rq, cmd);
3182
3183 switch (cmd) {
3184 case SIOCSHWTSTAMP:
3185 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3186 case SIOCGHWTSTAMP:
3187 return bp->ptp_info->get_hwtst(dev, rq);
3188 default:
3189 return phy_mii_ioctl(phydev, rq, cmd);
3190 }
3191 }
3192
3193 static int macb_set_features(struct net_device *netdev,
3194 netdev_features_t features)
3195 {
3196 struct macb *bp = netdev_priv(netdev);
3197 netdev_features_t changed = features ^ netdev->features;
3198
3199 /* TX checksum offload */
3200 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
3201 u32 dmacfg;
3202
3203 dmacfg = gem_readl(bp, DMACFG);
3204 if (features & NETIF_F_HW_CSUM)
3205 dmacfg |= GEM_BIT(TXCOEN);
3206 else
3207 dmacfg &= ~GEM_BIT(TXCOEN);
3208 gem_writel(bp, DMACFG, dmacfg);
3209 }
3210
3211 /* RX checksum offload */
3212 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
3213 u32 netcfg;
3214
3215 netcfg = gem_readl(bp, NCFGR);
3216 if (features & NETIF_F_RXCSUM &&
3217 !(netdev->flags & IFF_PROMISC))
3218 netcfg |= GEM_BIT(RXCOEN);
3219 else
3220 netcfg &= ~GEM_BIT(RXCOEN);
3221 gem_writel(bp, NCFGR, netcfg);
3222 }
3223
3224 /* RX Flow Filters */
3225 if ((changed & NETIF_F_NTUPLE) && macb_is_gem(bp)) {
3226 bool turn_on = features & NETIF_F_NTUPLE;
3227
3228 gem_enable_flow_filters(bp, turn_on);
3229 }
3230 return 0;
3231 }
3232
3233 static const struct net_device_ops macb_netdev_ops = {
3234 .ndo_open = macb_open,
3235 .ndo_stop = macb_close,
3236 .ndo_start_xmit = macb_start_xmit,
3237 .ndo_set_rx_mode = macb_set_rx_mode,
3238 .ndo_get_stats = macb_get_stats,
3239 .ndo_do_ioctl = macb_ioctl,
3240 .ndo_validate_addr = eth_validate_addr,
3241 .ndo_change_mtu = macb_change_mtu,
3242 .ndo_set_mac_address = eth_mac_addr,
3243 #ifdef CONFIG_NET_POLL_CONTROLLER
3244 .ndo_poll_controller = macb_poll_controller,
3245 #endif
3246 .ndo_set_features = macb_set_features,
3247 .ndo_features_check = macb_features_check,
3248 };
3249
3250 /* Configure peripheral capabilities according to device tree
3251 * and integration options used
3252 */
3253 static void macb_configure_caps(struct macb *bp,
3254 const struct macb_config *dt_conf)
3255 {
3256 u32 dcfg;
3257
3258 if (dt_conf)
3259 bp->caps = dt_conf->caps;
3260
3261 if (hw_is_gem(bp->regs, bp->native_io)) {
3262 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3263
3264 dcfg = gem_readl(bp, DCFG1);
3265 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3266 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3267 dcfg = gem_readl(bp, DCFG2);
3268 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3269 bp->caps |= MACB_CAPS_FIFO_MODE;
3270 #ifdef CONFIG_MACB_USE_HWSTAMP
3271 if (gem_has_ptp(bp)) {
3272 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3273 pr_err("GEM doesn't support hardware ptp.\n");
3274 else {
3275 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3276 bp->ptp_info = &gem_ptp_info;
3277 }
3278 }
3279 #endif
3280 }
3281
3282 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3283 }
3284
3285 static void macb_probe_queues(void __iomem *mem,
3286 bool native_io,
3287 unsigned int *queue_mask,
3288 unsigned int *num_queues)
3289 {
3290 unsigned int hw_q;
3291
3292 *queue_mask = 0x1;
3293 *num_queues = 1;
3294
3295 /* is it macb or gem ?
3296 *
3297 * We need to read directly from the hardware here because
3298 * we are early in the probe process and don't have the
3299 * MACB_CAPS_MACB_IS_GEM flag positioned
3300 */
3301 if (!hw_is_gem(mem, native_io))
3302 return;
3303
3304 /* bit 0 is never set but queue 0 always exists */
3305 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
3306
3307 *queue_mask |= 0x1;
3308
3309 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
3310 if (*queue_mask & (1 << hw_q))
3311 (*num_queues)++;
3312 }
3313
3314 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3315 struct clk **hclk, struct clk **tx_clk,
3316 struct clk **rx_clk)
3317 {
3318 struct macb_platform_data *pdata;
3319 int err;
3320
3321 pdata = dev_get_platdata(&pdev->dev);
3322 if (pdata) {
3323 *pclk = pdata->pclk;
3324 *hclk = pdata->hclk;
3325 } else {
3326 *pclk = devm_clk_get(&pdev->dev, "pclk");
3327 *hclk = devm_clk_get(&pdev->dev, "hclk");
3328 }
3329
3330 if (IS_ERR_OR_NULL(*pclk)) {
3331 err = PTR_ERR(*pclk);
3332 if (!err)
3333 err = -ENODEV;
3334
3335 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
3336 return err;
3337 }
3338
3339 if (IS_ERR_OR_NULL(*hclk)) {
3340 err = PTR_ERR(*hclk);
3341 if (!err)
3342 err = -ENODEV;
3343
3344 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
3345 return err;
3346 }
3347
3348 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
3349 if (IS_ERR(*tx_clk))
3350 *tx_clk = NULL;
3351
3352 *rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
3353 if (IS_ERR(*rx_clk))
3354 *rx_clk = NULL;
3355
3356 err = clk_prepare_enable(*pclk);
3357 if (err) {
3358 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3359 return err;
3360 }
3361
3362 err = clk_prepare_enable(*hclk);
3363 if (err) {
3364 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3365 goto err_disable_pclk;
3366 }
3367
3368 err = clk_prepare_enable(*tx_clk);
3369 if (err) {
3370 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3371 goto err_disable_hclk;
3372 }
3373
3374 err = clk_prepare_enable(*rx_clk);
3375 if (err) {
3376 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3377 goto err_disable_txclk;
3378 }
3379
3380 return 0;
3381
3382 err_disable_txclk:
3383 clk_disable_unprepare(*tx_clk);
3384
3385 err_disable_hclk:
3386 clk_disable_unprepare(*hclk);
3387
3388 err_disable_pclk:
3389 clk_disable_unprepare(*pclk);
3390
3391 return err;
3392 }
3393
3394 static int macb_init(struct platform_device *pdev)
3395 {
3396 struct net_device *dev = platform_get_drvdata(pdev);
3397 unsigned int hw_q, q;
3398 struct macb *bp = netdev_priv(dev);
3399 struct macb_queue *queue;
3400 int err;
3401 u32 val, reg;
3402
3403 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3404 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3405
3406 /* set the queue register mapping once for all: queue0 has a special
3407 * register mapping but we don't want to test the queue index then
3408 * compute the corresponding register offset at run time.
3409 */
3410 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3411 if (!(bp->queue_mask & (1 << hw_q)))
3412 continue;
3413
3414 queue = &bp->queues[q];
3415 queue->bp = bp;
3416 netif_napi_add(dev, &queue->napi, macb_poll, 64);
3417 if (hw_q) {
3418 queue->ISR = GEM_ISR(hw_q - 1);
3419 queue->IER = GEM_IER(hw_q - 1);
3420 queue->IDR = GEM_IDR(hw_q - 1);
3421 queue->IMR = GEM_IMR(hw_q - 1);
3422 queue->TBQP = GEM_TBQP(hw_q - 1);
3423 queue->RBQP = GEM_RBQP(hw_q - 1);
3424 queue->RBQS = GEM_RBQS(hw_q - 1);
3425 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3426 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3427 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3428 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3429 }
3430 #endif
3431 } else {
3432 /* queue0 uses legacy registers */
3433 queue->ISR = MACB_ISR;
3434 queue->IER = MACB_IER;
3435 queue->IDR = MACB_IDR;
3436 queue->IMR = MACB_IMR;
3437 queue->TBQP = MACB_TBQP;
3438 queue->RBQP = MACB_RBQP;
3439 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3440 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3441 queue->TBQPH = MACB_TBQPH;
3442 queue->RBQPH = MACB_RBQPH;
3443 }
3444 #endif
3445 }
3446
3447 /* get irq: here we use the linux queue index, not the hardware
3448 * queue index. the queue irq definitions in the device tree
3449 * must remove the optional gaps that could exist in the
3450 * hardware queue mask.
3451 */
3452 queue->irq = platform_get_irq(pdev, q);
3453 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3454 IRQF_SHARED, dev->name, queue);
3455 if (err) {
3456 dev_err(&pdev->dev,
3457 "Unable to request IRQ %d (error %d)\n",
3458 queue->irq, err);
3459 return err;
3460 }
3461
3462 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3463 q++;
3464 }
3465
3466 dev->netdev_ops = &macb_netdev_ops;
3467
3468 /* setup appropriated routines according to adapter type */
3469 if (macb_is_gem(bp)) {
3470 bp->max_tx_length = GEM_MAX_TX_LEN;
3471 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3472 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3473 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3474 bp->macbgem_ops.mog_rx = gem_rx;
3475 dev->ethtool_ops = &gem_ethtool_ops;
3476 } else {
3477 bp->max_tx_length = MACB_MAX_TX_LEN;
3478 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3479 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3480 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3481 bp->macbgem_ops.mog_rx = macb_rx;
3482 dev->ethtool_ops = &macb_ethtool_ops;
3483 }
3484
3485 /* Set features */
3486 dev->hw_features = NETIF_F_SG;
3487
3488 /* Check LSO capability */
3489 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3490 dev->hw_features |= MACB_NETIF_LSO;
3491
3492 /* Checksum offload is only available on gem with packet buffer */
3493 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3494 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3495 if (bp->caps & MACB_CAPS_SG_DISABLED)
3496 dev->hw_features &= ~NETIF_F_SG;
3497 dev->features = dev->hw_features;
3498
3499 /* Check RX Flow Filters support.
3500 * Max Rx flows set by availability of screeners & compare regs:
3501 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3502 */
3503 reg = gem_readl(bp, DCFG8);
3504 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3505 GEM_BFEXT(T2SCR, reg));
3506 if (bp->max_tuples > 0) {
3507 /* also needs one ethtype match to check IPv4 */
3508 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3509 /* program this reg now */
3510 reg = 0;
3511 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3512 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3513 /* Filtering is supported in hw but don't enable it in kernel now */
3514 dev->hw_features |= NETIF_F_NTUPLE;
3515 /* init Rx flow definitions */
3516 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3517 bp->rx_fs_list.count = 0;
3518 spin_lock_init(&bp->rx_fs_lock);
3519 } else
3520 bp->max_tuples = 0;
3521 }
3522
3523 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3524 val = 0;
3525 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
3526 val = GEM_BIT(RGMII);
3527 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3528 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3529 val = MACB_BIT(RMII);
3530 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3531 val = MACB_BIT(MII);
3532
3533 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3534 val |= MACB_BIT(CLKEN);
3535
3536 macb_or_gem_writel(bp, USRIO, val);
3537 }
3538
3539 /* Set MII management clock divider */
3540 val = macb_mdc_clk_div(bp);
3541 val |= macb_dbw(bp);
3542 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3543 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3544 macb_writel(bp, NCFGR, val);
3545
3546 return 0;
3547 }
3548
3549 #if defined(CONFIG_OF)
3550 /* 1518 rounded up */
3551 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3552 /* max number of receive buffers */
3553 #define AT91ETHER_MAX_RX_DESCR 9
3554
3555 /* Initialize and start the Receiver and Transmit subsystems */
3556 static int at91ether_start(struct net_device *dev)
3557 {
3558 struct macb *lp = netdev_priv(dev);
3559 struct macb_queue *q = &lp->queues[0];
3560 struct macb_dma_desc *desc;
3561 dma_addr_t addr;
3562 u32 ctl;
3563 int i;
3564
3565 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3566 (AT91ETHER_MAX_RX_DESCR *
3567 macb_dma_desc_get_size(lp)),
3568 &q->rx_ring_dma, GFP_KERNEL);
3569 if (!q->rx_ring)
3570 return -ENOMEM;
3571
3572 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3573 AT91ETHER_MAX_RX_DESCR *
3574 AT91ETHER_MAX_RBUFF_SZ,
3575 &q->rx_buffers_dma, GFP_KERNEL);
3576 if (!q->rx_buffers) {
3577 dma_free_coherent(&lp->pdev->dev,
3578 AT91ETHER_MAX_RX_DESCR *
3579 macb_dma_desc_get_size(lp),
3580 q->rx_ring, q->rx_ring_dma);
3581 q->rx_ring = NULL;
3582 return -ENOMEM;
3583 }
3584
3585 addr = q->rx_buffers_dma;
3586 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3587 desc = macb_rx_desc(q, i);
3588 macb_set_addr(lp, desc, addr);
3589 desc->ctrl = 0;
3590 addr += AT91ETHER_MAX_RBUFF_SZ;
3591 }
3592
3593 /* Set the Wrap bit on the last descriptor */
3594 desc->addr |= MACB_BIT(RX_WRAP);
3595
3596 /* Reset buffer index */
3597 q->rx_tail = 0;
3598
3599 /* Program address of descriptor list in Rx Buffer Queue register */
3600 macb_writel(lp, RBQP, q->rx_ring_dma);
3601
3602 /* Enable Receive and Transmit */
3603 ctl = macb_readl(lp, NCR);
3604 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3605
3606 return 0;
3607 }
3608
3609 /* Open the ethernet interface */
3610 static int at91ether_open(struct net_device *dev)
3611 {
3612 struct macb *lp = netdev_priv(dev);
3613 u32 ctl;
3614 int ret;
3615
3616 /* Clear internal statistics */
3617 ctl = macb_readl(lp, NCR);
3618 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3619
3620 macb_set_hwaddr(lp);
3621
3622 ret = at91ether_start(dev);
3623 if (ret)
3624 return ret;
3625
3626 /* Enable MAC interrupts */
3627 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3628 MACB_BIT(RXUBR) |
3629 MACB_BIT(ISR_TUND) |
3630 MACB_BIT(ISR_RLE) |
3631 MACB_BIT(TCOMP) |
3632 MACB_BIT(ISR_ROVR) |
3633 MACB_BIT(HRESP));
3634
3635 /* schedule a link state check */
3636 phy_start(dev->phydev);
3637
3638 netif_start_queue(dev);
3639
3640 return 0;
3641 }
3642
3643 /* Close the interface */
3644 static int at91ether_close(struct net_device *dev)
3645 {
3646 struct macb *lp = netdev_priv(dev);
3647 struct macb_queue *q = &lp->queues[0];
3648 u32 ctl;
3649
3650 /* Disable Receiver and Transmitter */
3651 ctl = macb_readl(lp, NCR);
3652 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3653
3654 /* Disable MAC interrupts */
3655 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3656 MACB_BIT(RXUBR) |
3657 MACB_BIT(ISR_TUND) |
3658 MACB_BIT(ISR_RLE) |
3659 MACB_BIT(TCOMP) |
3660 MACB_BIT(ISR_ROVR) |
3661 MACB_BIT(HRESP));
3662
3663 netif_stop_queue(dev);
3664
3665 dma_free_coherent(&lp->pdev->dev,
3666 AT91ETHER_MAX_RX_DESCR *
3667 macb_dma_desc_get_size(lp),
3668 q->rx_ring, q->rx_ring_dma);
3669 q->rx_ring = NULL;
3670
3671 dma_free_coherent(&lp->pdev->dev,
3672 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3673 q->rx_buffers, q->rx_buffers_dma);
3674 q->rx_buffers = NULL;
3675
3676 return 0;
3677 }
3678
3679 /* Transmit packet */
3680 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
3681 struct net_device *dev)
3682 {
3683 struct macb *lp = netdev_priv(dev);
3684
3685 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3686 netif_stop_queue(dev);
3687
3688 /* Store packet information (to free when Tx completed) */
3689 lp->skb = skb;
3690 lp->skb_length = skb->len;
3691 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
3692 DMA_TO_DEVICE);
3693 if (dma_mapping_error(NULL, lp->skb_physaddr)) {
3694 dev_kfree_skb_any(skb);
3695 dev->stats.tx_dropped++;
3696 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3697 return NETDEV_TX_OK;
3698 }
3699
3700 /* Set address of the data in the Transmit Address register */
3701 macb_writel(lp, TAR, lp->skb_physaddr);
3702 /* Set length of the packet in the Transmit Control register */
3703 macb_writel(lp, TCR, skb->len);
3704
3705 } else {
3706 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3707 return NETDEV_TX_BUSY;
3708 }
3709
3710 return NETDEV_TX_OK;
3711 }
3712
3713 /* Extract received frame from buffer descriptors and sent to upper layers.
3714 * (Called from interrupt context)
3715 */
3716 static void at91ether_rx(struct net_device *dev)
3717 {
3718 struct macb *lp = netdev_priv(dev);
3719 struct macb_queue *q = &lp->queues[0];
3720 struct macb_dma_desc *desc;
3721 unsigned char *p_recv;
3722 struct sk_buff *skb;
3723 unsigned int pktlen;
3724
3725 desc = macb_rx_desc(q, q->rx_tail);
3726 while (desc->addr & MACB_BIT(RX_USED)) {
3727 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3728 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3729 skb = netdev_alloc_skb(dev, pktlen + 2);
3730 if (skb) {
3731 skb_reserve(skb, 2);
3732 skb_put_data(skb, p_recv, pktlen);
3733
3734 skb->protocol = eth_type_trans(skb, dev);
3735 dev->stats.rx_packets++;
3736 dev->stats.rx_bytes += pktlen;
3737 netif_rx(skb);
3738 } else {
3739 dev->stats.rx_dropped++;
3740 }
3741
3742 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3743 dev->stats.multicast++;
3744
3745 /* reset ownership bit */
3746 desc->addr &= ~MACB_BIT(RX_USED);
3747
3748 /* wrap after last buffer */
3749 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3750 q->rx_tail = 0;
3751 else
3752 q->rx_tail++;
3753
3754 desc = macb_rx_desc(q, q->rx_tail);
3755 }
3756 }
3757
3758 /* MAC interrupt handler */
3759 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3760 {
3761 struct net_device *dev = dev_id;
3762 struct macb *lp = netdev_priv(dev);
3763 u32 intstatus, ctl;
3764
3765 /* MAC Interrupt Status register indicates what interrupts are pending.
3766 * It is automatically cleared once read.
3767 */
3768 intstatus = macb_readl(lp, ISR);
3769
3770 /* Receive complete */
3771 if (intstatus & MACB_BIT(RCOMP))
3772 at91ether_rx(dev);
3773
3774 /* Transmit complete */
3775 if (intstatus & MACB_BIT(TCOMP)) {
3776 /* The TCOM bit is set even if the transmission failed */
3777 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3778 dev->stats.tx_errors++;
3779
3780 if (lp->skb) {
3781 dev_kfree_skb_irq(lp->skb);
3782 lp->skb = NULL;
3783 dma_unmap_single(NULL, lp->skb_physaddr,
3784 lp->skb_length, DMA_TO_DEVICE);
3785 dev->stats.tx_packets++;
3786 dev->stats.tx_bytes += lp->skb_length;
3787 }
3788 netif_wake_queue(dev);
3789 }
3790
3791 /* Work-around for EMAC Errata section 41.3.1 */
3792 if (intstatus & MACB_BIT(RXUBR)) {
3793 ctl = macb_readl(lp, NCR);
3794 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3795 wmb();
3796 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3797 }
3798
3799 if (intstatus & MACB_BIT(ISR_ROVR))
3800 netdev_err(dev, "ROVR error\n");
3801
3802 return IRQ_HANDLED;
3803 }
3804
3805 #ifdef CONFIG_NET_POLL_CONTROLLER
3806 static void at91ether_poll_controller(struct net_device *dev)
3807 {
3808 unsigned long flags;
3809
3810 local_irq_save(flags);
3811 at91ether_interrupt(dev->irq, dev);
3812 local_irq_restore(flags);
3813 }
3814 #endif
3815
3816 static const struct net_device_ops at91ether_netdev_ops = {
3817 .ndo_open = at91ether_open,
3818 .ndo_stop = at91ether_close,
3819 .ndo_start_xmit = at91ether_start_xmit,
3820 .ndo_get_stats = macb_get_stats,
3821 .ndo_set_rx_mode = macb_set_rx_mode,
3822 .ndo_set_mac_address = eth_mac_addr,
3823 .ndo_do_ioctl = macb_ioctl,
3824 .ndo_validate_addr = eth_validate_addr,
3825 #ifdef CONFIG_NET_POLL_CONTROLLER
3826 .ndo_poll_controller = at91ether_poll_controller,
3827 #endif
3828 };
3829
3830 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
3831 struct clk **hclk, struct clk **tx_clk,
3832 struct clk **rx_clk)
3833 {
3834 int err;
3835
3836 *hclk = NULL;
3837 *tx_clk = NULL;
3838 *rx_clk = NULL;
3839
3840 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
3841 if (IS_ERR(*pclk))
3842 return PTR_ERR(*pclk);
3843
3844 err = clk_prepare_enable(*pclk);
3845 if (err) {
3846 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3847 return err;
3848 }
3849
3850 return 0;
3851 }
3852
3853 static int at91ether_init(struct platform_device *pdev)
3854 {
3855 struct net_device *dev = platform_get_drvdata(pdev);
3856 struct macb *bp = netdev_priv(dev);
3857 int err;
3858 u32 reg;
3859
3860 bp->queues[0].bp = bp;
3861
3862 dev->netdev_ops = &at91ether_netdev_ops;
3863 dev->ethtool_ops = &macb_ethtool_ops;
3864
3865 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
3866 0, dev->name, dev);
3867 if (err)
3868 return err;
3869
3870 macb_writel(bp, NCR, 0);
3871
3872 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
3873 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
3874 reg |= MACB_BIT(RM9200_RMII);
3875
3876 macb_writel(bp, NCFGR, reg);
3877
3878 return 0;
3879 }
3880
3881 static const struct macb_config at91sam9260_config = {
3882 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3883 .clk_init = macb_clk_init,
3884 .init = macb_init,
3885 };
3886
3887 static const struct macb_config sama5d3macb_config = {
3888 .caps = MACB_CAPS_SG_DISABLED
3889 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3890 .clk_init = macb_clk_init,
3891 .init = macb_init,
3892 };
3893
3894 static const struct macb_config pc302gem_config = {
3895 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
3896 .dma_burst_length = 16,
3897 .clk_init = macb_clk_init,
3898 .init = macb_init,
3899 };
3900
3901 static const struct macb_config sama5d2_config = {
3902 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3903 .dma_burst_length = 16,
3904 .clk_init = macb_clk_init,
3905 .init = macb_init,
3906 };
3907
3908 static const struct macb_config sama5d3_config = {
3909 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
3910 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
3911 .dma_burst_length = 16,
3912 .clk_init = macb_clk_init,
3913 .init = macb_init,
3914 .jumbo_max_len = 10240,
3915 };
3916
3917 static const struct macb_config sama5d4_config = {
3918 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3919 .dma_burst_length = 4,
3920 .clk_init = macb_clk_init,
3921 .init = macb_init,
3922 };
3923
3924 static const struct macb_config emac_config = {
3925 .caps = MACB_CAPS_NEEDS_RSTONUBR,
3926 .clk_init = at91ether_clk_init,
3927 .init = at91ether_init,
3928 };
3929
3930 static const struct macb_config np4_config = {
3931 .caps = MACB_CAPS_USRIO_DISABLED,
3932 .clk_init = macb_clk_init,
3933 .init = macb_init,
3934 };
3935
3936 static const struct macb_config zynqmp_config = {
3937 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3938 MACB_CAPS_JUMBO |
3939 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
3940 .dma_burst_length = 16,
3941 .clk_init = macb_clk_init,
3942 .init = macb_init,
3943 .jumbo_max_len = 10240,
3944 };
3945
3946 static const struct macb_config zynq_config = {
3947 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
3948 MACB_CAPS_NEEDS_RSTONUBR,
3949 .dma_burst_length = 16,
3950 .clk_init = macb_clk_init,
3951 .init = macb_init,
3952 };
3953
3954 static const struct of_device_id macb_dt_ids[] = {
3955 { .compatible = "cdns,at32ap7000-macb" },
3956 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
3957 { .compatible = "cdns,macb" },
3958 { .compatible = "cdns,np4-macb", .data = &np4_config },
3959 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
3960 { .compatible = "cdns,gem", .data = &pc302gem_config },
3961 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
3962 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
3963 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
3964 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
3965 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
3966 { .compatible = "cdns,emac", .data = &emac_config },
3967 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
3968 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
3969 { /* sentinel */ }
3970 };
3971 MODULE_DEVICE_TABLE(of, macb_dt_ids);
3972 #endif /* CONFIG_OF */
3973
3974 static const struct macb_config default_gem_config = {
3975 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3976 MACB_CAPS_JUMBO |
3977 MACB_CAPS_GEM_HAS_PTP,
3978 .dma_burst_length = 16,
3979 .clk_init = macb_clk_init,
3980 .init = macb_init,
3981 .jumbo_max_len = 10240,
3982 };
3983
3984 static int macb_probe(struct platform_device *pdev)
3985 {
3986 const struct macb_config *macb_config = &default_gem_config;
3987 int (*clk_init)(struct platform_device *, struct clk **,
3988 struct clk **, struct clk **, struct clk **)
3989 = macb_config->clk_init;
3990 int (*init)(struct platform_device *) = macb_config->init;
3991 struct device_node *np = pdev->dev.of_node;
3992 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
3993 unsigned int queue_mask, num_queues;
3994 struct macb_platform_data *pdata;
3995 bool native_io;
3996 struct phy_device *phydev;
3997 struct net_device *dev;
3998 struct resource *regs;
3999 void __iomem *mem;
4000 const char *mac;
4001 struct macb *bp;
4002 int err, val;
4003
4004 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4005 mem = devm_ioremap_resource(&pdev->dev, regs);
4006 if (IS_ERR(mem))
4007 return PTR_ERR(mem);
4008
4009 if (np) {
4010 const struct of_device_id *match;
4011
4012 match = of_match_node(macb_dt_ids, np);
4013 if (match && match->data) {
4014 macb_config = match->data;
4015 clk_init = macb_config->clk_init;
4016 init = macb_config->init;
4017 }
4018 }
4019
4020 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
4021 if (err)
4022 return err;
4023
4024 native_io = hw_is_native_io(mem);
4025
4026 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4027 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4028 if (!dev) {
4029 err = -ENOMEM;
4030 goto err_disable_clocks;
4031 }
4032
4033 dev->base_addr = regs->start;
4034
4035 SET_NETDEV_DEV(dev, &pdev->dev);
4036
4037 bp = netdev_priv(dev);
4038 bp->pdev = pdev;
4039 bp->dev = dev;
4040 bp->regs = mem;
4041 bp->native_io = native_io;
4042 if (native_io) {
4043 bp->macb_reg_readl = hw_readl_native;
4044 bp->macb_reg_writel = hw_writel_native;
4045 } else {
4046 bp->macb_reg_readl = hw_readl;
4047 bp->macb_reg_writel = hw_writel;
4048 }
4049 bp->num_queues = num_queues;
4050 bp->queue_mask = queue_mask;
4051 if (macb_config)
4052 bp->dma_burst_length = macb_config->dma_burst_length;
4053 bp->pclk = pclk;
4054 bp->hclk = hclk;
4055 bp->tx_clk = tx_clk;
4056 bp->rx_clk = rx_clk;
4057 if (macb_config)
4058 bp->jumbo_max_len = macb_config->jumbo_max_len;
4059
4060 bp->wol = 0;
4061 if (of_get_property(np, "magic-packet", NULL))
4062 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4063 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4064
4065 spin_lock_init(&bp->lock);
4066
4067 /* setup capabilities */
4068 macb_configure_caps(bp, macb_config);
4069
4070 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4071 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4072 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4073 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4074 }
4075 #endif
4076 platform_set_drvdata(pdev, dev);
4077
4078 dev->irq = platform_get_irq(pdev, 0);
4079 if (dev->irq < 0) {
4080 err = dev->irq;
4081 goto err_out_free_netdev;
4082 }
4083
4084 /* MTU range: 68 - 1500 or 10240 */
4085 dev->min_mtu = GEM_MTU_MIN_SIZE;
4086 if (bp->caps & MACB_CAPS_JUMBO)
4087 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4088 else
4089 dev->max_mtu = ETH_DATA_LEN;
4090
4091 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4092 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4093 if (val)
4094 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4095 macb_dma_desc_get_size(bp);
4096
4097 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4098 if (val)
4099 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4100 macb_dma_desc_get_size(bp);
4101 }
4102
4103 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4104 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4105 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4106
4107 mac = of_get_mac_address(np);
4108 if (mac) {
4109 ether_addr_copy(bp->dev->dev_addr, mac);
4110 } else {
4111 err = of_get_nvmem_mac_address(np, bp->dev->dev_addr);
4112 if (err) {
4113 if (err == -EPROBE_DEFER)
4114 goto err_out_free_netdev;
4115 macb_get_hwaddr(bp);
4116 }
4117 }
4118
4119 err = of_get_phy_mode(np);
4120 if (err < 0) {
4121 pdata = dev_get_platdata(&pdev->dev);
4122 if (pdata && pdata->is_rmii)
4123 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
4124 else
4125 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4126 } else {
4127 bp->phy_interface = err;
4128 }
4129
4130 /* IP specific init */
4131 err = init(pdev);
4132 if (err)
4133 goto err_out_free_netdev;
4134
4135 err = macb_mii_init(bp);
4136 if (err)
4137 goto err_out_free_netdev;
4138
4139 phydev = dev->phydev;
4140
4141 netif_carrier_off(dev);
4142
4143 err = register_netdev(dev);
4144 if (err) {
4145 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4146 goto err_out_unregister_mdio;
4147 }
4148
4149 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
4150 (unsigned long)bp);
4151
4152 phy_attached_info(phydev);
4153
4154 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4155 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4156 dev->base_addr, dev->irq, dev->dev_addr);
4157
4158 return 0;
4159
4160 err_out_unregister_mdio:
4161 phy_disconnect(dev->phydev);
4162 mdiobus_unregister(bp->mii_bus);
4163 of_node_put(bp->phy_node);
4164 if (np && of_phy_is_fixed_link(np))
4165 of_phy_deregister_fixed_link(np);
4166 mdiobus_free(bp->mii_bus);
4167
4168 err_out_free_netdev:
4169 free_netdev(dev);
4170
4171 err_disable_clocks:
4172 clk_disable_unprepare(tx_clk);
4173 clk_disable_unprepare(hclk);
4174 clk_disable_unprepare(pclk);
4175 clk_disable_unprepare(rx_clk);
4176
4177 return err;
4178 }
4179
4180 static int macb_remove(struct platform_device *pdev)
4181 {
4182 struct net_device *dev;
4183 struct macb *bp;
4184 struct device_node *np = pdev->dev.of_node;
4185
4186 dev = platform_get_drvdata(pdev);
4187
4188 if (dev) {
4189 bp = netdev_priv(dev);
4190 if (dev->phydev)
4191 phy_disconnect(dev->phydev);
4192 mdiobus_unregister(bp->mii_bus);
4193 if (np && of_phy_is_fixed_link(np))
4194 of_phy_deregister_fixed_link(np);
4195 dev->phydev = NULL;
4196 mdiobus_free(bp->mii_bus);
4197
4198 unregister_netdev(dev);
4199 tasklet_kill(&bp->hresp_err_tasklet);
4200 clk_disable_unprepare(bp->tx_clk);
4201 clk_disable_unprepare(bp->hclk);
4202 clk_disable_unprepare(bp->pclk);
4203 clk_disable_unprepare(bp->rx_clk);
4204 of_node_put(bp->phy_node);
4205 free_netdev(dev);
4206 }
4207
4208 return 0;
4209 }
4210
4211 static int __maybe_unused macb_suspend(struct device *dev)
4212 {
4213 struct platform_device *pdev = to_platform_device(dev);
4214 struct net_device *netdev = platform_get_drvdata(pdev);
4215 struct macb *bp = netdev_priv(netdev);
4216
4217 netif_carrier_off(netdev);
4218 netif_device_detach(netdev);
4219
4220 if (bp->wol & MACB_WOL_ENABLED) {
4221 macb_writel(bp, IER, MACB_BIT(WOL));
4222 macb_writel(bp, WOL, MACB_BIT(MAG));
4223 enable_irq_wake(bp->queues[0].irq);
4224 } else {
4225 clk_disable_unprepare(bp->tx_clk);
4226 clk_disable_unprepare(bp->hclk);
4227 clk_disable_unprepare(bp->pclk);
4228 clk_disable_unprepare(bp->rx_clk);
4229 }
4230
4231 return 0;
4232 }
4233
4234 static int __maybe_unused macb_resume(struct device *dev)
4235 {
4236 struct platform_device *pdev = to_platform_device(dev);
4237 struct net_device *netdev = platform_get_drvdata(pdev);
4238 struct macb *bp = netdev_priv(netdev);
4239
4240 if (bp->wol & MACB_WOL_ENABLED) {
4241 macb_writel(bp, IDR, MACB_BIT(WOL));
4242 macb_writel(bp, WOL, 0);
4243 disable_irq_wake(bp->queues[0].irq);
4244 } else {
4245 clk_prepare_enable(bp->pclk);
4246 clk_prepare_enable(bp->hclk);
4247 clk_prepare_enable(bp->tx_clk);
4248 clk_prepare_enable(bp->rx_clk);
4249 }
4250
4251 netif_device_attach(netdev);
4252
4253 return 0;
4254 }
4255
4256 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
4257
4258 static struct platform_driver macb_driver = {
4259 .probe = macb_probe,
4260 .remove = macb_remove,
4261 .driver = {
4262 .name = "macb",
4263 .of_match_table = of_match_ptr(macb_dt_ids),
4264 .pm = &macb_pm_ops,
4265 },
4266 };
4267
4268 module_platform_driver(macb_driver);
4269
4270 MODULE_LICENSE("GPL");
4271 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4272 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4273 MODULE_ALIAS("platform:macb");
Linux with added FPC-III support