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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / hisilicon / hip04_eth.c
blob718afa4be2a061b2de70c6a2b40fb4e9a09404fb
1
2 /* Copyright (c) 2014 Linaro Ltd.
3 * Copyright (c) 2014 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11 #include <linux/module.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/interrupt.h>
15 #include <linux/ktime.h>
16 #include <linux/of_address.h>
17 #include <linux/phy.h>
18 #include <linux/of_mdio.h>
19 #include <linux/of_net.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/regmap.h>
22
23 #define PPE_CFG_RX_ADDR 0x100
24 #define PPE_CFG_POOL_GRP 0x300
25 #define PPE_CFG_RX_BUF_SIZE 0x400
26 #define PPE_CFG_RX_FIFO_SIZE 0x500
27 #define PPE_CURR_BUF_CNT 0xa200
28
29 #define GE_DUPLEX_TYPE 0x08
30 #define GE_MAX_FRM_SIZE_REG 0x3c
31 #define GE_PORT_MODE 0x40
32 #define GE_PORT_EN 0x44
33 #define GE_SHORT_RUNTS_THR_REG 0x50
34 #define GE_TX_LOCAL_PAGE_REG 0x5c
35 #define GE_TRANSMIT_CONTROL_REG 0x60
36 #define GE_CF_CRC_STRIP_REG 0x1b0
37 #define GE_MODE_CHANGE_REG 0x1b4
38 #define GE_RECV_CONTROL_REG 0x1e0
39 #define GE_STATION_MAC_ADDRESS 0x210
40 #define PPE_CFG_CPU_ADD_ADDR 0x580
41 #define PPE_CFG_MAX_FRAME_LEN_REG 0x408
42 #define PPE_CFG_BUS_CTRL_REG 0x424
43 #define PPE_CFG_RX_CTRL_REG 0x428
44 #define PPE_CFG_RX_PKT_MODE_REG 0x438
45 #define PPE_CFG_QOS_VMID_GEN 0x500
46 #define PPE_CFG_RX_PKT_INT 0x538
47 #define PPE_INTEN 0x600
48 #define PPE_INTSTS 0x608
49 #define PPE_RINT 0x604
50 #define PPE_CFG_STS_MODE 0x700
51 #define PPE_HIS_RX_PKT_CNT 0x804
52
53 /* REG_INTERRUPT */
54 #define RCV_INT BIT(10)
55 #define RCV_NOBUF BIT(8)
56 #define RCV_DROP BIT(7)
57 #define TX_DROP BIT(6)
58 #define DEF_INT_ERR (RCV_NOBUF | RCV_DROP | TX_DROP)
59 #define DEF_INT_MASK (RCV_INT | DEF_INT_ERR)
60
61 /* TX descriptor config */
62 #define TX_FREE_MEM BIT(0)
63 #define TX_READ_ALLOC_L3 BIT(1)
64 #define TX_FINISH_CACHE_INV BIT(2)
65 #define TX_CLEAR_WB BIT(4)
66 #define TX_L3_CHECKSUM BIT(5)
67 #define TX_LOOP_BACK BIT(11)
68
69 /* RX error */
70 #define RX_PKT_DROP BIT(0)
71 #define RX_L2_ERR BIT(1)
72 #define RX_PKT_ERR (RX_PKT_DROP | RX_L2_ERR)
73
74 #define SGMII_SPEED_1000 0x08
75 #define SGMII_SPEED_100 0x07
76 #define SGMII_SPEED_10 0x06
77 #define MII_SPEED_100 0x01
78 #define MII_SPEED_10 0x00
79
80 #define GE_DUPLEX_FULL BIT(0)
81 #define GE_DUPLEX_HALF 0x00
82 #define GE_MODE_CHANGE_EN BIT(0)
83
84 #define GE_TX_AUTO_NEG BIT(5)
85 #define GE_TX_ADD_CRC BIT(6)
86 #define GE_TX_SHORT_PAD_THROUGH BIT(7)
87
88 #define GE_RX_STRIP_CRC BIT(0)
89 #define GE_RX_STRIP_PAD BIT(3)
90 #define GE_RX_PAD_EN BIT(4)
91
92 #define GE_AUTO_NEG_CTL BIT(0)
93
94 #define GE_RX_INT_THRESHOLD BIT(6)
95 #define GE_RX_TIMEOUT 0x04
96
97 #define GE_RX_PORT_EN BIT(1)
98 #define GE_TX_PORT_EN BIT(2)
99
100 #define PPE_CFG_STS_RX_PKT_CNT_RC BIT(12)
101
102 #define PPE_CFG_RX_PKT_ALIGN BIT(18)
103 #define PPE_CFG_QOS_VMID_MODE BIT(14)
104 #define PPE_CFG_QOS_VMID_GRP_SHIFT 8
105
106 #define PPE_CFG_RX_FIFO_FSFU BIT(11)
107 #define PPE_CFG_RX_DEPTH_SHIFT 16
108 #define PPE_CFG_RX_START_SHIFT 0
109 #define PPE_CFG_RX_CTRL_ALIGN_SHIFT 11
110
111 #define PPE_CFG_BUS_LOCAL_REL BIT(14)
112 #define PPE_CFG_BUS_BIG_ENDIEN BIT(0)
113
114 #define RX_DESC_NUM 128
115 #define TX_DESC_NUM 256
116 #define TX_NEXT(N) (((N) + 1) & (TX_DESC_NUM-1))
117 #define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM-1))
118
119 #define GMAC_PPE_RX_PKT_MAX_LEN 379
120 #define GMAC_MAX_PKT_LEN 1516
121 #define GMAC_MIN_PKT_LEN 31
122 #define RX_BUF_SIZE 1600
123 #define RESET_TIMEOUT 1000
124 #define TX_TIMEOUT (6 * HZ)
125
126 #define DRV_NAME "hip04-ether"
127 #define DRV_VERSION "v1.0"
128
129 #define HIP04_MAX_TX_COALESCE_USECS 200
130 #define HIP04_MIN_TX_COALESCE_USECS 100
131 #define HIP04_MAX_TX_COALESCE_FRAMES 200
132 #define HIP04_MIN_TX_COALESCE_FRAMES 100
133
134 struct tx_desc {
135 u32 send_addr;
136 u32 send_size;
137 u32 next_addr;
138 u32 cfg;
139 u32 wb_addr;
140 } __aligned(64);
141
142 struct rx_desc {
143 u16 reserved_16;
144 u16 pkt_len;
145 u32 reserve1[3];
146 u32 pkt_err;
147 u32 reserve2[4];
148 };
149
150 struct hip04_priv {
151 void __iomem *base;
152 int phy_mode;
153 int chan;
154 unsigned int port;
155 unsigned int speed;
156 unsigned int duplex;
157 unsigned int reg_inten;
158
159 struct napi_struct napi;
160 struct device *dev;
161 struct net_device *ndev;
162
163 struct tx_desc *tx_desc;
164 dma_addr_t tx_desc_dma;
165 struct sk_buff *tx_skb[TX_DESC_NUM];
166 dma_addr_t tx_phys[TX_DESC_NUM];
167 unsigned int tx_head;
168
169 int tx_coalesce_frames;
170 int tx_coalesce_usecs;
171 struct hrtimer tx_coalesce_timer;
172
173 unsigned char *rx_buf[RX_DESC_NUM];
174 dma_addr_t rx_phys[RX_DESC_NUM];
175 unsigned int rx_head;
176 unsigned int rx_buf_size;
177 unsigned int rx_cnt_remaining;
178
179 struct device_node *phy_node;
180 struct phy_device *phy;
181 struct regmap *map;
182 struct work_struct tx_timeout_task;
183
184 /* written only by tx cleanup */
185 unsigned int tx_tail ____cacheline_aligned_in_smp;
186 };
187
188 static inline unsigned int tx_count(unsigned int head, unsigned int tail)
189 {
190 return (head - tail) % TX_DESC_NUM;
191 }
192
193 static void hip04_config_port(struct net_device *ndev, u32 speed, u32 duplex)
194 {
195 struct hip04_priv *priv = netdev_priv(ndev);
196 u32 val;
197
198 priv->speed = speed;
199 priv->duplex = duplex;
200
201 switch (priv->phy_mode) {
202 case PHY_INTERFACE_MODE_SGMII:
203 if (speed == SPEED_1000)
204 val = SGMII_SPEED_1000;
205 else if (speed == SPEED_100)
206 val = SGMII_SPEED_100;
207 else
208 val = SGMII_SPEED_10;
209 break;
210 case PHY_INTERFACE_MODE_MII:
211 if (speed == SPEED_100)
212 val = MII_SPEED_100;
213 else
214 val = MII_SPEED_10;
215 break;
216 default:
217 netdev_warn(ndev, "not supported mode\n");
218 val = MII_SPEED_10;
219 break;
220 }
221 writel_relaxed(val, priv->base + GE_PORT_MODE);
222
223 val = duplex ? GE_DUPLEX_FULL : GE_DUPLEX_HALF;
224 writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
225
226 val = GE_MODE_CHANGE_EN;
227 writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);
228 }
229
230 static void hip04_reset_ppe(struct hip04_priv *priv)
231 {
232 u32 val, tmp, timeout = 0;
233
234 do {
235 regmap_read(priv->map, priv->port * 4 + PPE_CURR_BUF_CNT, &val);
236 regmap_read(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, &tmp);
237 if (timeout++ > RESET_TIMEOUT)
238 break;
239 } while (val & 0xfff);
240 }
241
242 static void hip04_config_fifo(struct hip04_priv *priv)
243 {
244 u32 val;
245
246 val = readl_relaxed(priv->base + PPE_CFG_STS_MODE);
247 val |= PPE_CFG_STS_RX_PKT_CNT_RC;
248 writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);
249
250 val = BIT(priv->port);
251 regmap_write(priv->map, priv->port * 4 + PPE_CFG_POOL_GRP, val);
252
253 val = priv->port << PPE_CFG_QOS_VMID_GRP_SHIFT;
254 val |= PPE_CFG_QOS_VMID_MODE;
255 writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);
256
257 val = RX_BUF_SIZE;
258 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_BUF_SIZE, val);
259
260 val = RX_DESC_NUM << PPE_CFG_RX_DEPTH_SHIFT;
261 val |= PPE_CFG_RX_FIFO_FSFU;
262 val |= priv->chan << PPE_CFG_RX_START_SHIFT;
263 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_FIFO_SIZE, val);
264
265 val = NET_IP_ALIGN << PPE_CFG_RX_CTRL_ALIGN_SHIFT;
266 writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);
267
268 val = PPE_CFG_RX_PKT_ALIGN;
269 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
270
271 val = PPE_CFG_BUS_LOCAL_REL | PPE_CFG_BUS_BIG_ENDIEN;
272 writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
273
274 val = GMAC_PPE_RX_PKT_MAX_LEN;
275 writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
276
277 val = GMAC_MAX_PKT_LEN;
278 writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
279
280 val = GMAC_MIN_PKT_LEN;
281 writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
282
283 val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);
284 val |= GE_TX_AUTO_NEG | GE_TX_ADD_CRC | GE_TX_SHORT_PAD_THROUGH;
285 writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
286
287 val = GE_RX_STRIP_CRC;
288 writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
289
290 val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);
291 val |= GE_RX_STRIP_PAD | GE_RX_PAD_EN;
292 writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
293
294 val = GE_AUTO_NEG_CTL;
295 writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
296 }
297
298 static void hip04_mac_enable(struct net_device *ndev)
299 {
300 struct hip04_priv *priv = netdev_priv(ndev);
301 u32 val;
302
303 /* enable tx & rx */
304 val = readl_relaxed(priv->base + GE_PORT_EN);
305 val |= GE_RX_PORT_EN | GE_TX_PORT_EN;
306 writel_relaxed(val, priv->base + GE_PORT_EN);
307
308 /* clear rx int */
309 val = RCV_INT;
310 writel_relaxed(val, priv->base + PPE_RINT);
311
312 /* config recv int */
313 val = GE_RX_INT_THRESHOLD | GE_RX_TIMEOUT;
314 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);
315
316 /* enable interrupt */
317 priv->reg_inten = DEF_INT_MASK;
318 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
319 }
320
321 static void hip04_mac_disable(struct net_device *ndev)
322 {
323 struct hip04_priv *priv = netdev_priv(ndev);
324 u32 val;
325
326 /* disable int */
327 priv->reg_inten &= ~(DEF_INT_MASK);
328 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
329
330 /* disable tx & rx */
331 val = readl_relaxed(priv->base + GE_PORT_EN);
332 val &= ~(GE_RX_PORT_EN | GE_TX_PORT_EN);
333 writel_relaxed(val, priv->base + GE_PORT_EN);
334 }
335
336 static void hip04_set_xmit_desc(struct hip04_priv *priv, dma_addr_t phys)
337 {
338 writel(phys, priv->base + PPE_CFG_CPU_ADD_ADDR);
339 }
340
341 static void hip04_set_recv_desc(struct hip04_priv *priv, dma_addr_t phys)
342 {
343 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, phys);
344 }
345
346 static u32 hip04_recv_cnt(struct hip04_priv *priv)
347 {
348 return readl(priv->base + PPE_HIS_RX_PKT_CNT);
349 }
350
351 static void hip04_update_mac_address(struct net_device *ndev)
352 {
353 struct hip04_priv *priv = netdev_priv(ndev);
354
355 writel_relaxed(((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])),
356 priv->base + GE_STATION_MAC_ADDRESS);
357 writel_relaxed(((ndev->dev_addr[2] << 24) | (ndev->dev_addr[3] << 16) |
358 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5])),
359 priv->base + GE_STATION_MAC_ADDRESS + 4);
360 }
361
362 static int hip04_set_mac_address(struct net_device *ndev, void *addr)
363 {
364 eth_mac_addr(ndev, addr);
365 hip04_update_mac_address(ndev);
366 return 0;
367 }
368
369 static int hip04_tx_reclaim(struct net_device *ndev, bool force)
370 {
371 struct hip04_priv *priv = netdev_priv(ndev);
372 unsigned tx_tail = priv->tx_tail;
373 struct tx_desc *desc;
374 unsigned int bytes_compl = 0, pkts_compl = 0;
375 unsigned int count;
376
377 smp_rmb();
378 count = tx_count(READ_ONCE(priv->tx_head), tx_tail);
379 if (count == 0)
380 goto out;
381
382 while (count) {
383 desc = &priv->tx_desc[tx_tail];
384 if (desc->send_addr != 0) {
385 if (force)
386 desc->send_addr = 0;
387 else
388 break;
389 }
390
391 if (priv->tx_phys[tx_tail]) {
392 dma_unmap_single(priv->dev, priv->tx_phys[tx_tail],
393 priv->tx_skb[tx_tail]->len,
394 DMA_TO_DEVICE);
395 priv->tx_phys[tx_tail] = 0;
396 }
397 pkts_compl++;
398 bytes_compl += priv->tx_skb[tx_tail]->len;
399 dev_kfree_skb(priv->tx_skb[tx_tail]);
400 priv->tx_skb[tx_tail] = NULL;
401 tx_tail = TX_NEXT(tx_tail);
402 count--;
403 }
404
405 priv->tx_tail = tx_tail;
406 smp_wmb(); /* Ensure tx_tail visible to xmit */
407
408 out:
409 if (pkts_compl || bytes_compl)
410 netdev_completed_queue(ndev, pkts_compl, bytes_compl);
411
412 if (unlikely(netif_queue_stopped(ndev)) && (count < (TX_DESC_NUM - 1)))
413 netif_wake_queue(ndev);
414
415 return count;
416 }
417
418 static void hip04_start_tx_timer(struct hip04_priv *priv)
419 {
420 unsigned long ns = priv->tx_coalesce_usecs * NSEC_PER_USEC / 2;
421
422 /* allow timer to fire after half the time at the earliest */
423 hrtimer_start_range_ns(&priv->tx_coalesce_timer, ns_to_ktime(ns),
424 ns, HRTIMER_MODE_REL);
425 }
426
427 static netdev_tx_t
428 hip04_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
429 {
430 struct hip04_priv *priv = netdev_priv(ndev);
431 struct net_device_stats *stats = &ndev->stats;
432 unsigned int tx_head = priv->tx_head, count;
433 struct tx_desc *desc = &priv->tx_desc[tx_head];
434 dma_addr_t phys;
435
436 smp_rmb();
437 count = tx_count(tx_head, READ_ONCE(priv->tx_tail));
438 if (count == (TX_DESC_NUM - 1)) {
439 netif_stop_queue(ndev);
440 return NETDEV_TX_BUSY;
441 }
442
443 phys = dma_map_single(priv->dev, skb->data, skb->len, DMA_TO_DEVICE);
444 if (dma_mapping_error(priv->dev, phys)) {
445 dev_kfree_skb(skb);
446 return NETDEV_TX_OK;
447 }
448
449 priv->tx_skb[tx_head] = skb;
450 priv->tx_phys[tx_head] = phys;
451 desc->send_addr = cpu_to_be32(phys);
452 desc->send_size = cpu_to_be32(skb->len);
453 desc->cfg = cpu_to_be32(TX_CLEAR_WB | TX_FINISH_CACHE_INV);
454 phys = priv->tx_desc_dma + tx_head * sizeof(struct tx_desc);
455 desc->wb_addr = cpu_to_be32(phys);
456 skb_tx_timestamp(skb);
457
458 hip04_set_xmit_desc(priv, phys);
459 count++;
460 netdev_sent_queue(ndev, skb->len);
461 priv->tx_head = TX_NEXT(tx_head);
462
463 stats->tx_bytes += skb->len;
464 stats->tx_packets++;
465
466 /* Ensure tx_head update visible to tx reclaim */
467 smp_wmb();
468
469 /* queue is getting full, better start cleaning up now */
470 if (count >= priv->tx_coalesce_frames) {
471 if (napi_schedule_prep(&priv->napi)) {
472 /* disable rx interrupt and timer */
473 priv->reg_inten &= ~(RCV_INT);
474 writel_relaxed(DEF_INT_MASK & ~RCV_INT,
475 priv->base + PPE_INTEN);
476 hrtimer_cancel(&priv->tx_coalesce_timer);
477 __napi_schedule(&priv->napi);
478 }
479 } else if (!hrtimer_is_queued(&priv->tx_coalesce_timer)) {
480 /* cleanup not pending yet, start a new timer */
481 hip04_start_tx_timer(priv);
482 }
483
484 return NETDEV_TX_OK;
485 }
486
487 static int hip04_rx_poll(struct napi_struct *napi, int budget)
488 {
489 struct hip04_priv *priv = container_of(napi, struct hip04_priv, napi);
490 struct net_device *ndev = priv->ndev;
491 struct net_device_stats *stats = &ndev->stats;
492 struct rx_desc *desc;
493 struct sk_buff *skb;
494 unsigned char *buf;
495 bool last = false;
496 dma_addr_t phys;
497 int rx = 0;
498 int tx_remaining;
499 u16 len;
500 u32 err;
501
502 /* clean up tx descriptors */
503 tx_remaining = hip04_tx_reclaim(ndev, false);
504 priv->rx_cnt_remaining += hip04_recv_cnt(priv);
505 while (priv->rx_cnt_remaining && !last) {
506 buf = priv->rx_buf[priv->rx_head];
507 skb = build_skb(buf, priv->rx_buf_size);
508 if (unlikely(!skb)) {
509 net_dbg_ratelimited("build_skb failed\n");
510 goto refill;
511 }
512
513 dma_unmap_single(priv->dev, priv->rx_phys[priv->rx_head],
514 RX_BUF_SIZE, DMA_FROM_DEVICE);
515 priv->rx_phys[priv->rx_head] = 0;
516
517 desc = (struct rx_desc *)skb->data;
518 len = be16_to_cpu(desc->pkt_len);
519 err = be32_to_cpu(desc->pkt_err);
520
521 if (0 == len) {
522 dev_kfree_skb_any(skb);
523 last = true;
524 } else if ((err & RX_PKT_ERR) || (len >= GMAC_MAX_PKT_LEN)) {
525 dev_kfree_skb_any(skb);
526 stats->rx_dropped++;
527 stats->rx_errors++;
528 } else {
529 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
530 skb_put(skb, len);
531 skb->protocol = eth_type_trans(skb, ndev);
532 napi_gro_receive(&priv->napi, skb);
533 stats->rx_packets++;
534 stats->rx_bytes += len;
535 rx++;
536 }
537
538 refill:
539 buf = netdev_alloc_frag(priv->rx_buf_size);
540 if (!buf)
541 goto done;
542 phys = dma_map_single(priv->dev, buf,
543 RX_BUF_SIZE, DMA_FROM_DEVICE);
544 if (dma_mapping_error(priv->dev, phys))
545 goto done;
546 priv->rx_buf[priv->rx_head] = buf;
547 priv->rx_phys[priv->rx_head] = phys;
548 hip04_set_recv_desc(priv, phys);
549
550 priv->rx_head = RX_NEXT(priv->rx_head);
551 if (rx >= budget) {
552 --priv->rx_cnt_remaining;
553 goto done;
554 }
555
556 if (--priv->rx_cnt_remaining == 0)
557 priv->rx_cnt_remaining += hip04_recv_cnt(priv);
558 }
559
560 if (!(priv->reg_inten & RCV_INT)) {
561 /* enable rx interrupt */
562 priv->reg_inten |= RCV_INT;
563 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
564 }
565 napi_complete_done(napi, rx);
566 done:
567 /* start a new timer if necessary */
568 if (rx < budget && tx_remaining)
569 hip04_start_tx_timer(priv);
570
571 return rx;
572 }
573
574 static irqreturn_t hip04_mac_interrupt(int irq, void *dev_id)
575 {
576 struct net_device *ndev = (struct net_device *)dev_id;
577 struct hip04_priv *priv = netdev_priv(ndev);
578 struct net_device_stats *stats = &ndev->stats;
579 u32 ists = readl_relaxed(priv->base + PPE_INTSTS);
580
581 if (!ists)
582 return IRQ_NONE;
583
584 writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);
585
586 if (unlikely(ists & DEF_INT_ERR)) {
587 if (ists & (RCV_NOBUF | RCV_DROP)) {
588 stats->rx_errors++;
589 stats->rx_dropped++;
590 netdev_err(ndev, "rx drop\n");
591 }
592 if (ists & TX_DROP) {
593 stats->tx_dropped++;
594 netdev_err(ndev, "tx drop\n");
595 }
596 }
597
598 if (ists & RCV_INT && napi_schedule_prep(&priv->napi)) {
599 /* disable rx interrupt */
600 priv->reg_inten &= ~(RCV_INT);
601 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
602 hrtimer_cancel(&priv->tx_coalesce_timer);
603 __napi_schedule(&priv->napi);
604 }
605
606 return IRQ_HANDLED;
607 }
608
609 static enum hrtimer_restart tx_done(struct hrtimer *hrtimer)
610 {
611 struct hip04_priv *priv;
612
613 priv = container_of(hrtimer, struct hip04_priv, tx_coalesce_timer);
614
615 if (napi_schedule_prep(&priv->napi)) {
616 /* disable rx interrupt */
617 priv->reg_inten &= ~(RCV_INT);
618 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
619 __napi_schedule(&priv->napi);
620 }
621
622 return HRTIMER_NORESTART;
623 }
624
625 static void hip04_adjust_link(struct net_device *ndev)
626 {
627 struct hip04_priv *priv = netdev_priv(ndev);
628 struct phy_device *phy = priv->phy;
629
630 if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) {
631 hip04_config_port(ndev, phy->speed, phy->duplex);
632 phy_print_status(phy);
633 }
634 }
635
636 static int hip04_mac_open(struct net_device *ndev)
637 {
638 struct hip04_priv *priv = netdev_priv(ndev);
639 int i;
640
641 priv->rx_head = 0;
642 priv->rx_cnt_remaining = 0;
643 priv->tx_head = 0;
644 priv->tx_tail = 0;
645 hip04_reset_ppe(priv);
646
647 for (i = 0; i < RX_DESC_NUM; i++) {
648 dma_addr_t phys;
649
650 phys = dma_map_single(priv->dev, priv->rx_buf[i],
651 RX_BUF_SIZE, DMA_FROM_DEVICE);
652 if (dma_mapping_error(priv->dev, phys))
653 return -EIO;
654
655 priv->rx_phys[i] = phys;
656 hip04_set_recv_desc(priv, phys);
657 }
658
659 if (priv->phy)
660 phy_start(priv->phy);
661
662 netdev_reset_queue(ndev);
663 netif_start_queue(ndev);
664 hip04_mac_enable(ndev);
665 napi_enable(&priv->napi);
666
667 return 0;
668 }
669
670 static int hip04_mac_stop(struct net_device *ndev)
671 {
672 struct hip04_priv *priv = netdev_priv(ndev);
673 int i;
674
675 napi_disable(&priv->napi);
676 netif_stop_queue(ndev);
677 hip04_mac_disable(ndev);
678 hip04_tx_reclaim(ndev, true);
679 hip04_reset_ppe(priv);
680
681 if (priv->phy)
682 phy_stop(priv->phy);
683
684 for (i = 0; i < RX_DESC_NUM; i++) {
685 if (priv->rx_phys[i]) {
686 dma_unmap_single(priv->dev, priv->rx_phys[i],
687 RX_BUF_SIZE, DMA_FROM_DEVICE);
688 priv->rx_phys[i] = 0;
689 }
690 }
691
692 return 0;
693 }
694
695 static void hip04_timeout(struct net_device *ndev)
696 {
697 struct hip04_priv *priv = netdev_priv(ndev);
698
699 schedule_work(&priv->tx_timeout_task);
700 }
701
702 static void hip04_tx_timeout_task(struct work_struct *work)
703 {
704 struct hip04_priv *priv;
705
706 priv = container_of(work, struct hip04_priv, tx_timeout_task);
707 hip04_mac_stop(priv->ndev);
708 hip04_mac_open(priv->ndev);
709 }
710
711 static int hip04_get_coalesce(struct net_device *netdev,
712 struct ethtool_coalesce *ec)
713 {
714 struct hip04_priv *priv = netdev_priv(netdev);
715
716 ec->tx_coalesce_usecs = priv->tx_coalesce_usecs;
717 ec->tx_max_coalesced_frames = priv->tx_coalesce_frames;
718
719 return 0;
720 }
721
722 static int hip04_set_coalesce(struct net_device *netdev,
723 struct ethtool_coalesce *ec)
724 {
725 struct hip04_priv *priv = netdev_priv(netdev);
726
727 /* Check not supported parameters */
728 if ((ec->rx_max_coalesced_frames) || (ec->rx_coalesce_usecs_irq) ||
729 (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) ||
730 (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) ||
731 (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) ||
732 (ec->rx_max_coalesced_frames_low) || (ec->tx_coalesce_usecs_high) ||
733 (ec->tx_max_coalesced_frames_low) || (ec->pkt_rate_high) ||
734 (ec->tx_coalesce_usecs_low) || (ec->rx_coalesce_usecs_high) ||
735 (ec->rx_max_coalesced_frames_high) || (ec->rx_coalesce_usecs) ||
736 (ec->tx_max_coalesced_frames_irq) ||
737 (ec->stats_block_coalesce_usecs) ||
738 (ec->tx_max_coalesced_frames_high) || (ec->rate_sample_interval))
739 return -EOPNOTSUPP;
740
741 if ((ec->tx_coalesce_usecs > HIP04_MAX_TX_COALESCE_USECS ||
742 ec->tx_coalesce_usecs < HIP04_MIN_TX_COALESCE_USECS) ||
743 (ec->tx_max_coalesced_frames > HIP04_MAX_TX_COALESCE_FRAMES ||
744 ec->tx_max_coalesced_frames < HIP04_MIN_TX_COALESCE_FRAMES))
745 return -EINVAL;
746
747 priv->tx_coalesce_usecs = ec->tx_coalesce_usecs;
748 priv->tx_coalesce_frames = ec->tx_max_coalesced_frames;
749
750 return 0;
751 }
752
753 static void hip04_get_drvinfo(struct net_device *netdev,
754 struct ethtool_drvinfo *drvinfo)
755 {
756 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
757 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
758 }
759
760 static const struct ethtool_ops hip04_ethtool_ops = {
761 .get_coalesce = hip04_get_coalesce,
762 .set_coalesce = hip04_set_coalesce,
763 .get_drvinfo = hip04_get_drvinfo,
764 };
765
766 static const struct net_device_ops hip04_netdev_ops = {
767 .ndo_open = hip04_mac_open,
768 .ndo_stop = hip04_mac_stop,
769 .ndo_start_xmit = hip04_mac_start_xmit,
770 .ndo_set_mac_address = hip04_set_mac_address,
771 .ndo_tx_timeout = hip04_timeout,
772 .ndo_validate_addr = eth_validate_addr,
773 };
774
775 static int hip04_alloc_ring(struct net_device *ndev, struct device *d)
776 {
777 struct hip04_priv *priv = netdev_priv(ndev);
778 int i;
779
780 priv->tx_desc = dma_alloc_coherent(d,
781 TX_DESC_NUM * sizeof(struct tx_desc),
782 &priv->tx_desc_dma, GFP_KERNEL);
783 if (!priv->tx_desc)
784 return -ENOMEM;
785
786 priv->rx_buf_size = RX_BUF_SIZE +
787 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
788 for (i = 0; i < RX_DESC_NUM; i++) {
789 priv->rx_buf[i] = netdev_alloc_frag(priv->rx_buf_size);
790 if (!priv->rx_buf[i])
791 return -ENOMEM;
792 }
793
794 return 0;
795 }
796
797 static void hip04_free_ring(struct net_device *ndev, struct device *d)
798 {
799 struct hip04_priv *priv = netdev_priv(ndev);
800 int i;
801
802 for (i = 0; i < RX_DESC_NUM; i++)
803 if (priv->rx_buf[i])
804 skb_free_frag(priv->rx_buf[i]);
805
806 for (i = 0; i < TX_DESC_NUM; i++)
807 if (priv->tx_skb[i])
808 dev_kfree_skb_any(priv->tx_skb[i]);
809
810 dma_free_coherent(d, TX_DESC_NUM * sizeof(struct tx_desc),
811 priv->tx_desc, priv->tx_desc_dma);
812 }
813
814 static int hip04_mac_probe(struct platform_device *pdev)
815 {
816 struct device *d = &pdev->dev;
817 struct device_node *node = d->of_node;
818 struct of_phandle_args arg;
819 struct net_device *ndev;
820 struct hip04_priv *priv;
821 struct resource *res;
822 int irq;
823 int ret;
824
825 ndev = alloc_etherdev(sizeof(struct hip04_priv));
826 if (!ndev)
827 return -ENOMEM;
828
829 priv = netdev_priv(ndev);
830 priv->dev = d;
831 priv->ndev = ndev;
832 platform_set_drvdata(pdev, ndev);
833 SET_NETDEV_DEV(ndev, &pdev->dev);
834
835 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
836 priv->base = devm_ioremap_resource(d, res);
837 if (IS_ERR(priv->base)) {
838 ret = PTR_ERR(priv->base);
839 goto init_fail;
840 }
841
842 ret = of_parse_phandle_with_fixed_args(node, "port-handle", 2, 0, &arg);
843 if (ret < 0) {
844 dev_warn(d, "no port-handle\n");
845 goto init_fail;
846 }
847
848 priv->port = arg.args[0];
849 priv->chan = arg.args[1] * RX_DESC_NUM;
850
851 hrtimer_init(&priv->tx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
852
853 /* BQL will try to keep the TX queue as short as possible, but it can't
854 * be faster than tx_coalesce_usecs, so we need a fast timeout here,
855 * but also long enough to gather up enough frames to ensure we don't
856 * get more interrupts than necessary.
857 * 200us is enough for 16 frames of 1500 bytes at gigabit ethernet rate
858 */
859 priv->tx_coalesce_frames = TX_DESC_NUM * 3 / 4;
860 priv->tx_coalesce_usecs = 200;
861 priv->tx_coalesce_timer.function = tx_done;
862
863 priv->map = syscon_node_to_regmap(arg.np);
864 if (IS_ERR(priv->map)) {
865 dev_warn(d, "no syscon hisilicon,hip04-ppe\n");
866 ret = PTR_ERR(priv->map);
867 goto init_fail;
868 }
869
870 priv->phy_mode = of_get_phy_mode(node);
871 if (priv->phy_mode < 0) {
872 dev_warn(d, "not find phy-mode\n");
873 ret = -EINVAL;
874 goto init_fail;
875 }
876
877 irq = platform_get_irq(pdev, 0);
878 if (irq <= 0) {
879 ret = -EINVAL;
880 goto init_fail;
881 }
882
883 ret = devm_request_irq(d, irq, hip04_mac_interrupt,
884 0, pdev->name, ndev);
885 if (ret) {
886 netdev_err(ndev, "devm_request_irq failed\n");
887 goto init_fail;
888 }
889
890 priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
891 if (priv->phy_node) {
892 priv->phy = of_phy_connect(ndev, priv->phy_node,
893 &hip04_adjust_link,
894 0, priv->phy_mode);
895 if (!priv->phy) {
896 ret = -EPROBE_DEFER;
897 goto init_fail;
898 }
899 }
900
901 INIT_WORK(&priv->tx_timeout_task, hip04_tx_timeout_task);
902
903 ndev->netdev_ops = &hip04_netdev_ops;
904 ndev->ethtool_ops = &hip04_ethtool_ops;
905 ndev->watchdog_timeo = TX_TIMEOUT;
906 ndev->priv_flags |= IFF_UNICAST_FLT;
907 ndev->irq = irq;
908 netif_napi_add(ndev, &priv->napi, hip04_rx_poll, NAPI_POLL_WEIGHT);
909
910 hip04_reset_ppe(priv);
911 if (priv->phy_mode == PHY_INTERFACE_MODE_MII)
912 hip04_config_port(ndev, SPEED_100, DUPLEX_FULL);
913
914 hip04_config_fifo(priv);
915 eth_random_addr(ndev->dev_addr);
916 hip04_update_mac_address(ndev);
917
918 ret = hip04_alloc_ring(ndev, d);
919 if (ret) {
920 netdev_err(ndev, "alloc ring fail\n");
921 goto alloc_fail;
922 }
923
924 ret = register_netdev(ndev);
925 if (ret)
926 goto alloc_fail;
927
928 return 0;
929
930 alloc_fail:
931 hip04_free_ring(ndev, d);
932 init_fail:
933 of_node_put(priv->phy_node);
934 free_netdev(ndev);
935 return ret;
936 }
937
938 static int hip04_remove(struct platform_device *pdev)
939 {
940 struct net_device *ndev = platform_get_drvdata(pdev);
941 struct hip04_priv *priv = netdev_priv(ndev);
942 struct device *d = &pdev->dev;
943
944 if (priv->phy)
945 phy_disconnect(priv->phy);
946
947 hip04_free_ring(ndev, d);
948 unregister_netdev(ndev);
949 of_node_put(priv->phy_node);
950 cancel_work_sync(&priv->tx_timeout_task);
951 free_netdev(ndev);
952
953 return 0;
954 }
955
956 static const struct of_device_id hip04_mac_match[] = {
957 { .compatible = "hisilicon,hip04-mac" },
958 { }
959 };
960
961 MODULE_DEVICE_TABLE(of, hip04_mac_match);
962
963 static struct platform_driver hip04_mac_driver = {
964 .probe = hip04_mac_probe,
965 .remove = hip04_remove,
966 .driver = {
967 .name = DRV_NAME,
968 .of_match_table = hip04_mac_match,
969 },
970 };
971 module_platform_driver(hip04_mac_driver);
972
973 MODULE_DESCRIPTION("HISILICON P04 Ethernet driver");
974 MODULE_LICENSE("GPL");
Linux with added FPC-III support