drivers/net/ethernet/hisilicon/hns_mdio.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/errno.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/mfd/syscon.h>
  16 #include <linux/module.h>
  17 #include <linux/mutex.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of.h>
  21 #include <linux/of_mdio.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26
  27 #define MDIO_DRV_NAME "Hi-HNS_MDIO"
  28 #define MDIO_BUS_NAME "Hisilicon MII Bus"
  29
  30 #define MDIO_TIMEOUT                    1000000
  31
  32 struct hns_mdio_sc_reg {
  33         u16 mdio_clk_en;
  34         u16 mdio_clk_dis;
  35         u16 mdio_reset_req;
  36         u16 mdio_reset_dreq;
  37         u16 mdio_clk_st;
  38         u16 mdio_reset_st;
  39 };
  40
  41 struct hns_mdio_device {
  42         void *vbase;            /* mdio reg base address */
  43         struct regmap *subctrl_vbase;
  44         struct hns_mdio_sc_reg sc_reg;
  45 };
  46
  47 /* mdio reg */
  48 #define MDIO_COMMAND_REG                0x0
  49 #define MDIO_ADDR_REG                   0x4
  50 #define MDIO_WDATA_REG                  0x8
  51 #define MDIO_RDATA_REG                  0xc
  52 #define MDIO_STA_REG                    0x10
  53
  54 /* cfg phy bit map */
  55 #define MDIO_CMD_DEVAD_M        0x1f
  56 #define MDIO_CMD_DEVAD_S        0
  57 #define MDIO_CMD_PRTAD_M        0x1f
  58 #define MDIO_CMD_PRTAD_S        5
  59 #define MDIO_CMD_OP_S           10
  60 #define MDIO_CMD_ST_S           12
  61 #define MDIO_CMD_START_B        14
  62
  63 #define MDIO_ADDR_DATA_M        0xffff
  64 #define MDIO_ADDR_DATA_S        0
  65
  66 #define MDIO_WDATA_DATA_M       0xffff
  67 #define MDIO_WDATA_DATA_S       0
  68
  69 #define MDIO_RDATA_DATA_M       0xffff
  70 #define MDIO_RDATA_DATA_S       0
  71
  72 #define MDIO_STATE_STA_B        0
  73
  74 enum mdio_st_clause {
  75         MDIO_ST_CLAUSE_45 = 0,
  76         MDIO_ST_CLAUSE_22
  77 };
  78
  79 enum mdio_c22_op_seq {
  80         MDIO_C22_WRITE = 1,
  81         MDIO_C22_READ = 2
  82 };
  83
  84 enum mdio_c45_op_seq {
  85         MDIO_C45_WRITE_ADDR = 0,
  86         MDIO_C45_WRITE_DATA,
  87         MDIO_C45_READ_INCREMENT,
  88         MDIO_C45_READ
  89 };
  90
  91 /* peri subctrl reg */
  92 #define MDIO_SC_CLK_EN          0x338
  93 #define MDIO_SC_CLK_DIS         0x33C
  94 #define MDIO_SC_RESET_REQ       0xA38
  95 #define MDIO_SC_RESET_DREQ      0xA3C
  96 #define MDIO_SC_CLK_ST          0x531C
  97 #define MDIO_SC_RESET_ST        0x5A1C
  98
  99 static void mdio_write_reg(void *base, u32 reg, u32 value)
 100 {
 101         u8 __iomem *reg_addr = (u8 __iomem *)base;
 102
 103         writel_relaxed(value, reg_addr + reg);
 104 }
 105
 106 #define MDIO_WRITE_REG(a, reg, value) \
 107         mdio_write_reg((a)->vbase, (reg), (value))
 108
 109 static u32 mdio_read_reg(void *base, u32 reg)
 110 {
 111         u8 __iomem *reg_addr = (u8 __iomem *)base;
 112
 113         return readl_relaxed(reg_addr + reg);
 114 }
 115
 116 #define mdio_set_field(origin, mask, shift, val) \
 117         do { \
 118                 (origin) &= (~((mask) << (shift))); \
 119                 (origin) |= (((val) & (mask)) << (shift)); \
 120         } while (0)
 121
 122 #define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))
 123
 124 static void mdio_set_reg_field(void *base, u32 reg, u32 mask, u32 shift,
 125                                u32 val)
 126 {
 127         u32 origin = mdio_read_reg(base, reg);
 128
 129         mdio_set_field(origin, mask, shift, val);
 130         mdio_write_reg(base, reg, origin);
 131 }
 132
 133 #define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
 134         mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))
 135
 136 static u32 mdio_get_reg_field(void *base, u32 reg, u32 mask, u32 shift)
 137 {
 138         u32 origin;
 139
 140         origin = mdio_read_reg(base, reg);
 141         return mdio_get_field(origin, mask, shift);
 142 }
 143
 144 #define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
 145                 mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))
 146
 147 #define MDIO_GET_REG_BIT(dev, reg, bit) \
 148                 mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))
 149
 150 #define MDIO_CHECK_SET_ST       1
 151 #define MDIO_CHECK_CLR_ST       0
 152
 153 static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
 154                                  u32 cfg_reg, u32 set_val,
 155                                  u32 st_reg, u32 st_msk, u8 check_st)
 156 {
 157         u32 time_cnt;
 158         u32 reg_value;
 159         int ret;
 160
 161         regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);
 162
 163         for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
 164                 ret = regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);
 165                 if (ret)
 166                         return ret;
 167
 168                 reg_value &= st_msk;
 169                 if ((!!check_st) == (!!reg_value))
 170                         break;
 171         }
 172
 173         if ((!!check_st) != (!!reg_value))
 174                 return -EBUSY;
 175
 176         return 0;
 177 }
 178
 179 static int hns_mdio_wait_ready(struct mii_bus *bus)
 180 {
 181         struct hns_mdio_device *mdio_dev = bus->priv;
 182         u32 cmd_reg_value;
 183         int i;
 184
 185         /* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
 186         /* after that can do read or write*/
 187         for (i = 0; i < MDIO_TIMEOUT; i++) {
 188                 cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
 189                                                  MDIO_COMMAND_REG,
 190                                                  MDIO_CMD_START_B);
 191                 if (!cmd_reg_value)
 192                         break;
 193         }
 194         if ((i == MDIO_TIMEOUT) && cmd_reg_value)
 195                 return -ETIMEDOUT;
 196
 197         return 0;
 198 }
 199
 200 static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
 201                                u8 is_c45, u8 op, u8 phy_id, u16 cmd)
 202 {
 203         u32 cmd_reg_value;
 204         u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;
 205
 206         cmd_reg_value = st << MDIO_CMD_ST_S;
 207         cmd_reg_value |= op << MDIO_CMD_OP_S;
 208         cmd_reg_value |=
 209                 (phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
 210         cmd_reg_value |= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
 211         cmd_reg_value |= 1 << MDIO_CMD_START_B;
 212
 213         MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
 214 }
 215
 216 /**
 217  * hns_mdio_write - access phy register
 218  * @bus: mdio bus
 219  * @phy_id: phy id
 220  * @regnum: register num
 221  * @value: register value
 222  *
 223  * Return 0 on success, negative on failure
 224  */
 225 static int hns_mdio_write(struct mii_bus *bus,
 226                           int phy_id, int regnum, u16 data)
 227 {
 228         int ret;
 229         struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
 230         u8 devad = ((regnum >> 16) & 0x1f);
 231         u8 is_c45 = !!(regnum & MII_ADDR_C45);
 232         u16 reg = (u16)(regnum & 0xffff);
 233         u8 op;
 234         u16 cmd_reg_cfg;
 235
 236         dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
 237                 bus->id, mdio_dev->vbase);
 238         dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
 239                 phy_id, is_c45, devad, reg, data);
 240
 241         /* wait for ready */
 242         ret = hns_mdio_wait_ready(bus);
 243         if (ret) {
 244                 dev_err(&bus->dev, "MDIO bus is busy\n");
 245                 return ret;
 246         }
 247
 248         if (!is_c45) {
 249                 cmd_reg_cfg = reg;
 250                 op = MDIO_C22_WRITE;
 251         } else {
 252                 /* config the cmd-reg to write addr*/
 253                 MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
 254                                    MDIO_ADDR_DATA_S, reg);
 255
 256                 hns_mdio_cmd_write(mdio_dev, is_c45,
 257                                    MDIO_C45_WRITE_ADDR, phy_id, devad);
 258
 259                 /* check for read or write opt is finished */
 260                 ret = hns_mdio_wait_ready(bus);
 261                 if (ret) {
 262                         dev_err(&bus->dev, "MDIO bus is busy\n");
 263                         return ret;
 264                 }
 265
 266                 /* config the data needed writing */
 267                 cmd_reg_cfg = devad;
 268                 op = MDIO_C45_WRITE_DATA;
 269         }
 270
 271         MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
 272                            MDIO_WDATA_DATA_S, data);
 273
 274         hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);
 275
 276         return 0;
 277 }
 278
 279 /**
 280  * hns_mdio_read - access phy register
 281  * @bus: mdio bus
 282  * @phy_id: phy id
 283  * @regnum: register num
 284  * @value: register value
 285  *
 286  * Return phy register value
 287  */
 288 static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
 289 {
 290         int ret;
 291         u16 reg_val = 0;
 292         u8 devad = ((regnum >> 16) & 0x1f);
 293         u8 is_c45 = !!(regnum & MII_ADDR_C45);
 294         u16 reg = (u16)(regnum & 0xffff);
 295         struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
 296
 297         dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
 298                 bus->id, mdio_dev->vbase);
 299         dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
 300                 phy_id, is_c45, devad, reg);
 301
 302         /* Step 1: wait for ready */
 303         ret = hns_mdio_wait_ready(bus);
 304         if (ret) {
 305                 dev_err(&bus->dev, "MDIO bus is busy\n");
 306                 return ret;
 307         }
 308
 309         if (!is_c45) {
 310                 hns_mdio_cmd_write(mdio_dev, is_c45,
 311                                    MDIO_C22_READ, phy_id, reg);
 312         } else {
 313                 MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
 314                                    MDIO_ADDR_DATA_S, reg);
 315
 316                 /* Step 2; config the cmd-reg to write addr*/
 317                 hns_mdio_cmd_write(mdio_dev, is_c45,
 318                                    MDIO_C45_WRITE_ADDR, phy_id, devad);
 319
 320                 /* Step 3: check for read or write opt is finished */
 321                 ret = hns_mdio_wait_ready(bus);
 322                 if (ret) {
 323                         dev_err(&bus->dev, "MDIO bus is busy\n");
 324                         return ret;
 325                 }
 326
 327                 hns_mdio_cmd_write(mdio_dev, is_c45,
 328                                    MDIO_C45_READ, phy_id, devad);
 329         }
 330
 331         /* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
 332         /* check for read or write opt is finished */
 333         ret = hns_mdio_wait_ready(bus);
 334         if (ret) {
 335                 dev_err(&bus->dev, "MDIO bus is busy\n");
 336                 return ret;
 337         }
 338
 339         reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
 340         if (reg_val) {
 341                 dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
 342                 return -EBUSY;
 343         }
 344
 345         /* Step 6; get out data*/
 346         reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
 347                                           MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);
 348
 349         return reg_val;
 350 }
 351
 352 /**
 353  * hns_mdio_reset - reset mdio bus
 354  * @bus: mdio bus
 355  *
 356  * Return 0 on success, negative on failure
 357  */
 358 static int hns_mdio_reset(struct mii_bus *bus)
 359 {
 360         struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
 361         const struct hns_mdio_sc_reg *sc_reg;
 362         int ret;
 363
 364         if (dev_of_node(bus->parent)) {
 365                 if (!mdio_dev->subctrl_vbase) {
 366                         dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
 367                         return -ENODEV;
 368                 }
 369
 370                 sc_reg = &mdio_dev->sc_reg;
 371                 /* 1. reset req, and read reset st check */
 372                 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_req,
 373                                             0x1, sc_reg->mdio_reset_st, 0x1,
 374                                             MDIO_CHECK_SET_ST);
 375                 if (ret) {
 376                         dev_err(&bus->dev, "MDIO reset fail\n");
 377                         return ret;
 378                 }
 379
 380                 /* 2. dis clk, and read clk st check */
 381                 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_dis,
 382                                             0x1, sc_reg->mdio_clk_st, 0x1,
 383                                             MDIO_CHECK_CLR_ST);
 384                 if (ret) {
 385                         dev_err(&bus->dev, "MDIO dis clk fail\n");
 386                         return ret;
 387                 }
 388
 389                 /* 3. reset dreq, and read reset st check */
 390                 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_dreq,
 391                                             0x1, sc_reg->mdio_reset_st, 0x1,
 392                                             MDIO_CHECK_CLR_ST);
 393                 if (ret) {
 394                         dev_err(&bus->dev, "MDIO dis clk fail\n");
 395                         return ret;
 396                 }
 397
 398                 /* 4. en clk, and read clk st check */
 399                 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_en,
 400                                             0x1, sc_reg->mdio_clk_st, 0x1,
 401                                             MDIO_CHECK_SET_ST);
 402                 if (ret)
 403                         dev_err(&bus->dev, "MDIO en clk fail\n");
 404         } else if (is_acpi_node(bus->parent->fwnode)) {
 405                 acpi_status s;
 406
 407                 s = acpi_evaluate_object(ACPI_HANDLE(bus->parent),
 408                                          "_RST", NULL, NULL);
 409                 if (ACPI_FAILURE(s)) {
 410                         dev_err(&bus->dev, "Reset failed, return:%#x\n", s);
 411                         ret = -EBUSY;
 412                 } else {
 413                         ret = 0;
 414                 }
 415         } else {
 416                 dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n");
 417                 ret = -ENXIO;
 418         }
 419         return ret;
 420 }
 421
 422 /**
 423  * hns_mdio_probe - probe mdio device
 424  * @pdev: mdio platform device
 425  *
 426  * Return 0 on success, negative on failure
 427  */
 428 static int hns_mdio_probe(struct platform_device *pdev)
 429 {
 430         struct hns_mdio_device *mdio_dev;
 431         struct mii_bus *new_bus;
 432         struct resource *res;
 433         int ret = -ENODEV;
 434
 435         if (!pdev) {
 436                 dev_err(NULL, "pdev is NULL!\r\n");
 437                 return -ENODEV;
 438         }
 439
 440         mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
 441         if (!mdio_dev)
 442                 return -ENOMEM;
 443
 444         new_bus = devm_mdiobus_alloc(&pdev->dev);
 445         if (!new_bus) {
 446                 dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
 447                 return -ENOMEM;
 448         }
 449
 450         new_bus->name = MDIO_BUS_NAME;
 451         new_bus->read = hns_mdio_read;
 452         new_bus->write = hns_mdio_write;
 453         new_bus->reset = hns_mdio_reset;
 454         new_bus->priv = mdio_dev;
 455         new_bus->parent = &pdev->dev;
 456
 457         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 458         mdio_dev->vbase = devm_ioremap_resource(&pdev->dev, res);
 459         if (IS_ERR(mdio_dev->vbase)) {
 460                 ret = PTR_ERR(mdio_dev->vbase);
 461                 return ret;
 462         }
 463
 464         platform_set_drvdata(pdev, new_bus);
 465         snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii",
 466                  dev_name(&pdev->dev));
 467         if (dev_of_node(&pdev->dev)) {
 468                 struct of_phandle_args reg_args;
 469
 470                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
 471                                                        "subctrl-vbase",
 472                                                        4,
 473                                                        0,
 474                                                        &reg_args);
 475                 if (!ret) {
 476                         mdio_dev->subctrl_vbase =
 477                                 syscon_node_to_regmap(reg_args.np);
 478                         if (IS_ERR(mdio_dev->subctrl_vbase)) {
 479                                 dev_warn(&pdev->dev, "syscon_node_to_regmap error\n");
 480                                 mdio_dev->subctrl_vbase = NULL;
 481                         } else {
 482                                 if (reg_args.args_count == 4) {
 483                                         mdio_dev->sc_reg.mdio_clk_en =
 484                                                 (u16)reg_args.args[0];
 485                                         mdio_dev->sc_reg.mdio_clk_dis =
 486                                                 (u16)reg_args.args[0] + 4;
 487                                         mdio_dev->sc_reg.mdio_reset_req =
 488                                                 (u16)reg_args.args[1];
 489                                         mdio_dev->sc_reg.mdio_reset_dreq =
 490                                                 (u16)reg_args.args[1] + 4;
 491                                         mdio_dev->sc_reg.mdio_clk_st =
 492                                                 (u16)reg_args.args[2];
 493                                         mdio_dev->sc_reg.mdio_reset_st =
 494                                                 (u16)reg_args.args[3];
 495                                 } else {
 496                                         /* for compatible */
 497                                         mdio_dev->sc_reg.mdio_clk_en =
 498                                                 MDIO_SC_CLK_EN;
 499                                         mdio_dev->sc_reg.mdio_clk_dis =
 500                                                 MDIO_SC_CLK_DIS;
 501                                         mdio_dev->sc_reg.mdio_reset_req =
 502                                                 MDIO_SC_RESET_REQ;
 503                                         mdio_dev->sc_reg.mdio_reset_dreq =
 504                                                 MDIO_SC_RESET_DREQ;
 505                                         mdio_dev->sc_reg.mdio_clk_st =
 506                                                 MDIO_SC_CLK_ST;
 507                                         mdio_dev->sc_reg.mdio_reset_st =
 508                                                 MDIO_SC_RESET_ST;
 509                                 }
 510                         }
 511                 } else {
 512                         dev_warn(&pdev->dev, "find syscon ret = %#x\n", ret);
 513                         mdio_dev->subctrl_vbase = NULL;
 514                 }
 515
 516                 ret = of_mdiobus_register(new_bus, pdev->dev.of_node);
 517         } else if (is_acpi_node(pdev->dev.fwnode)) {
 518                 /* Clear all the IRQ properties */
 519                 memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR);
 520
 521                 /* Mask out all PHYs from auto probing. */
 522                 new_bus->phy_mask = ~0;
 523
 524                 /* Register the MDIO bus */
 525                 ret = mdiobus_register(new_bus);
 526         } else {
 527                 dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n");
 528                 ret = -ENXIO;
 529         }
 530
 531         if (ret) {
 532                 dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
 533                 platform_set_drvdata(pdev, NULL);
 534                 return ret;
 535         }
 536
 537         return 0;
 538 }
 539
 540 /**
 541  * hns_mdio_remove - remove mdio device
 542  * @pdev: mdio platform device
 543  *
 544  * Return 0 on success, negative on failure
 545  */
 546 static int hns_mdio_remove(struct platform_device *pdev)
 547 {
 548         struct mii_bus *bus;
 549
 550         bus = platform_get_drvdata(pdev);
 551
 552         mdiobus_unregister(bus);
 553         platform_set_drvdata(pdev, NULL);
 554         return 0;
 555 }
 556
 557 static const struct of_device_id hns_mdio_match[] = {
 558         {.compatible = "hisilicon,mdio"},
 559         {.compatible = "hisilicon,hns-mdio"},
 560         {}
 561 };
 562 MODULE_DEVICE_TABLE(of, hns_mdio_match);
 563
 564 static const struct acpi_device_id hns_mdio_acpi_match[] = {
 565         { "HISI0141", 0 },
 566         { },
 567 };
 568 MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match);
 569
 570 static struct platform_driver hns_mdio_driver = {
 571         .probe = hns_mdio_probe,
 572         .remove = hns_mdio_remove,
 573         .driver = {
 574                    .name = MDIO_DRV_NAME,
 575                    .of_match_table = hns_mdio_match,
 576                    .acpi_match_table = ACPI_PTR(hns_mdio_acpi_match),
 577                    },
 578 };
 579
 580 module_platform_driver(hns_mdio_driver);
 581
 582 MODULE_LICENSE("GPL");
 583 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
 584 MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
 585 MODULE_ALIAS("platform:" MDIO_DRV_NAME);