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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
blobeb0ae6ab01e265403eef21c2eed6d79c4ea99253
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4 #include "i40e_type.h"
5 #include "i40e_adminq.h"
6 #include "i40e_prototype.h"
7 #include <linux/avf/virtchnl.h>
8
9 /**
10 * i40e_set_mac_type - Sets MAC type
11 * @hw: pointer to the HW structure
12 *
13 * This function sets the mac type of the adapter based on the
14 * vendor ID and device ID stored in the hw structure.
15 **/
16 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
17 {
18 i40e_status status = 0;
19
20 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
21 switch (hw->device_id) {
22 case I40E_DEV_ID_SFP_XL710:
23 case I40E_DEV_ID_QEMU:
24 case I40E_DEV_ID_KX_B:
25 case I40E_DEV_ID_KX_C:
26 case I40E_DEV_ID_QSFP_A:
27 case I40E_DEV_ID_QSFP_B:
28 case I40E_DEV_ID_QSFP_C:
29 case I40E_DEV_ID_10G_BASE_T:
30 case I40E_DEV_ID_10G_BASE_T4:
31 case I40E_DEV_ID_20G_KR2:
32 case I40E_DEV_ID_20G_KR2_A:
33 case I40E_DEV_ID_25G_B:
34 case I40E_DEV_ID_25G_SFP28:
35 hw->mac.type = I40E_MAC_XL710;
36 break;
37 case I40E_DEV_ID_KX_X722:
38 case I40E_DEV_ID_QSFP_X722:
39 case I40E_DEV_ID_SFP_X722:
40 case I40E_DEV_ID_1G_BASE_T_X722:
41 case I40E_DEV_ID_10G_BASE_T_X722:
42 case I40E_DEV_ID_SFP_I_X722:
43 hw->mac.type = I40E_MAC_X722;
44 break;
45 default:
46 hw->mac.type = I40E_MAC_GENERIC;
47 break;
48 }
49 } else {
50 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
51 }
52
53 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
54 hw->mac.type, status);
55 return status;
56 }
57
58 /**
59 * i40e_aq_str - convert AQ err code to a string
60 * @hw: pointer to the HW structure
61 * @aq_err: the AQ error code to convert
62 **/
63 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
64 {
65 switch (aq_err) {
66 case I40E_AQ_RC_OK:
67 return "OK";
68 case I40E_AQ_RC_EPERM:
69 return "I40E_AQ_RC_EPERM";
70 case I40E_AQ_RC_ENOENT:
71 return "I40E_AQ_RC_ENOENT";
72 case I40E_AQ_RC_ESRCH:
73 return "I40E_AQ_RC_ESRCH";
74 case I40E_AQ_RC_EINTR:
75 return "I40E_AQ_RC_EINTR";
76 case I40E_AQ_RC_EIO:
77 return "I40E_AQ_RC_EIO";
78 case I40E_AQ_RC_ENXIO:
79 return "I40E_AQ_RC_ENXIO";
80 case I40E_AQ_RC_E2BIG:
81 return "I40E_AQ_RC_E2BIG";
82 case I40E_AQ_RC_EAGAIN:
83 return "I40E_AQ_RC_EAGAIN";
84 case I40E_AQ_RC_ENOMEM:
85 return "I40E_AQ_RC_ENOMEM";
86 case I40E_AQ_RC_EACCES:
87 return "I40E_AQ_RC_EACCES";
88 case I40E_AQ_RC_EFAULT:
89 return "I40E_AQ_RC_EFAULT";
90 case I40E_AQ_RC_EBUSY:
91 return "I40E_AQ_RC_EBUSY";
92 case I40E_AQ_RC_EEXIST:
93 return "I40E_AQ_RC_EEXIST";
94 case I40E_AQ_RC_EINVAL:
95 return "I40E_AQ_RC_EINVAL";
96 case I40E_AQ_RC_ENOTTY:
97 return "I40E_AQ_RC_ENOTTY";
98 case I40E_AQ_RC_ENOSPC:
99 return "I40E_AQ_RC_ENOSPC";
100 case I40E_AQ_RC_ENOSYS:
101 return "I40E_AQ_RC_ENOSYS";
102 case I40E_AQ_RC_ERANGE:
103 return "I40E_AQ_RC_ERANGE";
104 case I40E_AQ_RC_EFLUSHED:
105 return "I40E_AQ_RC_EFLUSHED";
106 case I40E_AQ_RC_BAD_ADDR:
107 return "I40E_AQ_RC_BAD_ADDR";
108 case I40E_AQ_RC_EMODE:
109 return "I40E_AQ_RC_EMODE";
110 case I40E_AQ_RC_EFBIG:
111 return "I40E_AQ_RC_EFBIG";
112 }
113
114 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
115 return hw->err_str;
116 }
117
118 /**
119 * i40e_stat_str - convert status err code to a string
120 * @hw: pointer to the HW structure
121 * @stat_err: the status error code to convert
122 **/
123 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
124 {
125 switch (stat_err) {
126 case 0:
127 return "OK";
128 case I40E_ERR_NVM:
129 return "I40E_ERR_NVM";
130 case I40E_ERR_NVM_CHECKSUM:
131 return "I40E_ERR_NVM_CHECKSUM";
132 case I40E_ERR_PHY:
133 return "I40E_ERR_PHY";
134 case I40E_ERR_CONFIG:
135 return "I40E_ERR_CONFIG";
136 case I40E_ERR_PARAM:
137 return "I40E_ERR_PARAM";
138 case I40E_ERR_MAC_TYPE:
139 return "I40E_ERR_MAC_TYPE";
140 case I40E_ERR_UNKNOWN_PHY:
141 return "I40E_ERR_UNKNOWN_PHY";
142 case I40E_ERR_LINK_SETUP:
143 return "I40E_ERR_LINK_SETUP";
144 case I40E_ERR_ADAPTER_STOPPED:
145 return "I40E_ERR_ADAPTER_STOPPED";
146 case I40E_ERR_INVALID_MAC_ADDR:
147 return "I40E_ERR_INVALID_MAC_ADDR";
148 case I40E_ERR_DEVICE_NOT_SUPPORTED:
149 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
150 case I40E_ERR_MASTER_REQUESTS_PENDING:
151 return "I40E_ERR_MASTER_REQUESTS_PENDING";
152 case I40E_ERR_INVALID_LINK_SETTINGS:
153 return "I40E_ERR_INVALID_LINK_SETTINGS";
154 case I40E_ERR_AUTONEG_NOT_COMPLETE:
155 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
156 case I40E_ERR_RESET_FAILED:
157 return "I40E_ERR_RESET_FAILED";
158 case I40E_ERR_SWFW_SYNC:
159 return "I40E_ERR_SWFW_SYNC";
160 case I40E_ERR_NO_AVAILABLE_VSI:
161 return "I40E_ERR_NO_AVAILABLE_VSI";
162 case I40E_ERR_NO_MEMORY:
163 return "I40E_ERR_NO_MEMORY";
164 case I40E_ERR_BAD_PTR:
165 return "I40E_ERR_BAD_PTR";
166 case I40E_ERR_RING_FULL:
167 return "I40E_ERR_RING_FULL";
168 case I40E_ERR_INVALID_PD_ID:
169 return "I40E_ERR_INVALID_PD_ID";
170 case I40E_ERR_INVALID_QP_ID:
171 return "I40E_ERR_INVALID_QP_ID";
172 case I40E_ERR_INVALID_CQ_ID:
173 return "I40E_ERR_INVALID_CQ_ID";
174 case I40E_ERR_INVALID_CEQ_ID:
175 return "I40E_ERR_INVALID_CEQ_ID";
176 case I40E_ERR_INVALID_AEQ_ID:
177 return "I40E_ERR_INVALID_AEQ_ID";
178 case I40E_ERR_INVALID_SIZE:
179 return "I40E_ERR_INVALID_SIZE";
180 case I40E_ERR_INVALID_ARP_INDEX:
181 return "I40E_ERR_INVALID_ARP_INDEX";
182 case I40E_ERR_INVALID_FPM_FUNC_ID:
183 return "I40E_ERR_INVALID_FPM_FUNC_ID";
184 case I40E_ERR_QP_INVALID_MSG_SIZE:
185 return "I40E_ERR_QP_INVALID_MSG_SIZE";
186 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
187 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
188 case I40E_ERR_INVALID_FRAG_COUNT:
189 return "I40E_ERR_INVALID_FRAG_COUNT";
190 case I40E_ERR_QUEUE_EMPTY:
191 return "I40E_ERR_QUEUE_EMPTY";
192 case I40E_ERR_INVALID_ALIGNMENT:
193 return "I40E_ERR_INVALID_ALIGNMENT";
194 case I40E_ERR_FLUSHED_QUEUE:
195 return "I40E_ERR_FLUSHED_QUEUE";
196 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
197 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
198 case I40E_ERR_INVALID_IMM_DATA_SIZE:
199 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
200 case I40E_ERR_TIMEOUT:
201 return "I40E_ERR_TIMEOUT";
202 case I40E_ERR_OPCODE_MISMATCH:
203 return "I40E_ERR_OPCODE_MISMATCH";
204 case I40E_ERR_CQP_COMPL_ERROR:
205 return "I40E_ERR_CQP_COMPL_ERROR";
206 case I40E_ERR_INVALID_VF_ID:
207 return "I40E_ERR_INVALID_VF_ID";
208 case I40E_ERR_INVALID_HMCFN_ID:
209 return "I40E_ERR_INVALID_HMCFN_ID";
210 case I40E_ERR_BACKING_PAGE_ERROR:
211 return "I40E_ERR_BACKING_PAGE_ERROR";
212 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
213 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
214 case I40E_ERR_INVALID_PBLE_INDEX:
215 return "I40E_ERR_INVALID_PBLE_INDEX";
216 case I40E_ERR_INVALID_SD_INDEX:
217 return "I40E_ERR_INVALID_SD_INDEX";
218 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
219 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
220 case I40E_ERR_INVALID_SD_TYPE:
221 return "I40E_ERR_INVALID_SD_TYPE";
222 case I40E_ERR_MEMCPY_FAILED:
223 return "I40E_ERR_MEMCPY_FAILED";
224 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
225 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
226 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
227 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
228 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
229 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
230 case I40E_ERR_SRQ_ENABLED:
231 return "I40E_ERR_SRQ_ENABLED";
232 case I40E_ERR_ADMIN_QUEUE_ERROR:
233 return "I40E_ERR_ADMIN_QUEUE_ERROR";
234 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
235 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
236 case I40E_ERR_BUF_TOO_SHORT:
237 return "I40E_ERR_BUF_TOO_SHORT";
238 case I40E_ERR_ADMIN_QUEUE_FULL:
239 return "I40E_ERR_ADMIN_QUEUE_FULL";
240 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
241 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
242 case I40E_ERR_BAD_IWARP_CQE:
243 return "I40E_ERR_BAD_IWARP_CQE";
244 case I40E_ERR_NVM_BLANK_MODE:
245 return "I40E_ERR_NVM_BLANK_MODE";
246 case I40E_ERR_NOT_IMPLEMENTED:
247 return "I40E_ERR_NOT_IMPLEMENTED";
248 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
249 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
250 case I40E_ERR_DIAG_TEST_FAILED:
251 return "I40E_ERR_DIAG_TEST_FAILED";
252 case I40E_ERR_NOT_READY:
253 return "I40E_ERR_NOT_READY";
254 case I40E_NOT_SUPPORTED:
255 return "I40E_NOT_SUPPORTED";
256 case I40E_ERR_FIRMWARE_API_VERSION:
257 return "I40E_ERR_FIRMWARE_API_VERSION";
258 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
259 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
260 }
261
262 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
263 return hw->err_str;
264 }
265
266 /**
267 * i40e_debug_aq
268 * @hw: debug mask related to admin queue
269 * @mask: debug mask
270 * @desc: pointer to admin queue descriptor
271 * @buffer: pointer to command buffer
272 * @buf_len: max length of buffer
273 *
274 * Dumps debug log about adminq command with descriptor contents.
275 **/
276 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
277 void *buffer, u16 buf_len)
278 {
279 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
280 u16 len;
281 u8 *buf = (u8 *)buffer;
282
283 if ((!(mask & hw->debug_mask)) || (desc == NULL))
284 return;
285
286 len = le16_to_cpu(aq_desc->datalen);
287
288 i40e_debug(hw, mask,
289 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
290 le16_to_cpu(aq_desc->opcode),
291 le16_to_cpu(aq_desc->flags),
292 le16_to_cpu(aq_desc->datalen),
293 le16_to_cpu(aq_desc->retval));
294 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
295 le32_to_cpu(aq_desc->cookie_high),
296 le32_to_cpu(aq_desc->cookie_low));
297 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
298 le32_to_cpu(aq_desc->params.internal.param0),
299 le32_to_cpu(aq_desc->params.internal.param1));
300 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
301 le32_to_cpu(aq_desc->params.external.addr_high),
302 le32_to_cpu(aq_desc->params.external.addr_low));
303
304 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
305 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
306 if (buf_len < len)
307 len = buf_len;
308 /* write the full 16-byte chunks */
309 if (hw->debug_mask & mask) {
310 char prefix[27];
311
312 snprintf(prefix, sizeof(prefix),
313 "i40e %02x:%02x.%x: \t0x",
314 hw->bus.bus_id,
315 hw->bus.device,
316 hw->bus.func);
317
318 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
319 16, 1, buf, len, false);
320 }
321 }
322 }
323
324 /**
325 * i40e_check_asq_alive
326 * @hw: pointer to the hw struct
327 *
328 * Returns true if Queue is enabled else false.
329 **/
330 bool i40e_check_asq_alive(struct i40e_hw *hw)
331 {
332 if (hw->aq.asq.len)
333 return !!(rd32(hw, hw->aq.asq.len) &
334 I40E_PF_ATQLEN_ATQENABLE_MASK);
335 else
336 return false;
337 }
338
339 /**
340 * i40e_aq_queue_shutdown
341 * @hw: pointer to the hw struct
342 * @unloading: is the driver unloading itself
343 *
344 * Tell the Firmware that we're shutting down the AdminQ and whether
345 * or not the driver is unloading as well.
346 **/
347 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
348 bool unloading)
349 {
350 struct i40e_aq_desc desc;
351 struct i40e_aqc_queue_shutdown *cmd =
352 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
353 i40e_status status;
354
355 i40e_fill_default_direct_cmd_desc(&desc,
356 i40e_aqc_opc_queue_shutdown);
357
358 if (unloading)
359 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
360 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
361
362 return status;
363 }
364
365 /**
366 * i40e_aq_get_set_rss_lut
367 * @hw: pointer to the hardware structure
368 * @vsi_id: vsi fw index
369 * @pf_lut: for PF table set true, for VSI table set false
370 * @lut: pointer to the lut buffer provided by the caller
371 * @lut_size: size of the lut buffer
372 * @set: set true to set the table, false to get the table
373 *
374 * Internal function to get or set RSS look up table
375 **/
376 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
377 u16 vsi_id, bool pf_lut,
378 u8 *lut, u16 lut_size,
379 bool set)
380 {
381 i40e_status status;
382 struct i40e_aq_desc desc;
383 struct i40e_aqc_get_set_rss_lut *cmd_resp =
384 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
385
386 if (set)
387 i40e_fill_default_direct_cmd_desc(&desc,
388 i40e_aqc_opc_set_rss_lut);
389 else
390 i40e_fill_default_direct_cmd_desc(&desc,
391 i40e_aqc_opc_get_rss_lut);
392
393 /* Indirect command */
394 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
395 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
396
397 cmd_resp->vsi_id =
398 cpu_to_le16((u16)((vsi_id <<
399 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
400 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
401 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
402
403 if (pf_lut)
404 cmd_resp->flags |= cpu_to_le16((u16)
405 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
406 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
407 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
408 else
409 cmd_resp->flags |= cpu_to_le16((u16)
410 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
411 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
412 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
413
414 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
415
416 return status;
417 }
418
419 /**
420 * i40e_aq_get_rss_lut
421 * @hw: pointer to the hardware structure
422 * @vsi_id: vsi fw index
423 * @pf_lut: for PF table set true, for VSI table set false
424 * @lut: pointer to the lut buffer provided by the caller
425 * @lut_size: size of the lut buffer
426 *
427 * get the RSS lookup table, PF or VSI type
428 **/
429 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
430 bool pf_lut, u8 *lut, u16 lut_size)
431 {
432 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
433 false);
434 }
435
436 /**
437 * i40e_aq_set_rss_lut
438 * @hw: pointer to the hardware structure
439 * @vsi_id: vsi fw index
440 * @pf_lut: for PF table set true, for VSI table set false
441 * @lut: pointer to the lut buffer provided by the caller
442 * @lut_size: size of the lut buffer
443 *
444 * set the RSS lookup table, PF or VSI type
445 **/
446 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
447 bool pf_lut, u8 *lut, u16 lut_size)
448 {
449 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
450 }
451
452 /**
453 * i40e_aq_get_set_rss_key
454 * @hw: pointer to the hw struct
455 * @vsi_id: vsi fw index
456 * @key: pointer to key info struct
457 * @set: set true to set the key, false to get the key
458 *
459 * get the RSS key per VSI
460 **/
461 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
462 u16 vsi_id,
463 struct i40e_aqc_get_set_rss_key_data *key,
464 bool set)
465 {
466 i40e_status status;
467 struct i40e_aq_desc desc;
468 struct i40e_aqc_get_set_rss_key *cmd_resp =
469 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
470 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
471
472 if (set)
473 i40e_fill_default_direct_cmd_desc(&desc,
474 i40e_aqc_opc_set_rss_key);
475 else
476 i40e_fill_default_direct_cmd_desc(&desc,
477 i40e_aqc_opc_get_rss_key);
478
479 /* Indirect command */
480 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
481 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
482
483 cmd_resp->vsi_id =
484 cpu_to_le16((u16)((vsi_id <<
485 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
486 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
487 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
488
489 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
490
491 return status;
492 }
493
494 /**
495 * i40e_aq_get_rss_key
496 * @hw: pointer to the hw struct
497 * @vsi_id: vsi fw index
498 * @key: pointer to key info struct
499 *
500 **/
501 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
502 u16 vsi_id,
503 struct i40e_aqc_get_set_rss_key_data *key)
504 {
505 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
506 }
507
508 /**
509 * i40e_aq_set_rss_key
510 * @hw: pointer to the hw struct
511 * @vsi_id: vsi fw index
512 * @key: pointer to key info struct
513 *
514 * set the RSS key per VSI
515 **/
516 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
517 u16 vsi_id,
518 struct i40e_aqc_get_set_rss_key_data *key)
519 {
520 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
521 }
522
523 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
524 * hardware to a bit-field that can be used by SW to more easily determine the
525 * packet type.
526 *
527 * Macros are used to shorten the table lines and make this table human
528 * readable.
529 *
530 * We store the PTYPE in the top byte of the bit field - this is just so that
531 * we can check that the table doesn't have a row missing, as the index into
532 * the table should be the PTYPE.
533 *
534 * Typical work flow:
535 *
536 * IF NOT i40e_ptype_lookup[ptype].known
537 * THEN
538 * Packet is unknown
539 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
540 * Use the rest of the fields to look at the tunnels, inner protocols, etc
541 * ELSE
542 * Use the enum i40e_rx_l2_ptype to decode the packet type
543 * ENDIF
544 */
545
546 /* macro to make the table lines short */
547 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
548 { PTYPE, \
549 1, \
550 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
551 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
552 I40E_RX_PTYPE_##OUTER_FRAG, \
553 I40E_RX_PTYPE_TUNNEL_##T, \
554 I40E_RX_PTYPE_TUNNEL_END_##TE, \
555 I40E_RX_PTYPE_##TEF, \
556 I40E_RX_PTYPE_INNER_PROT_##I, \
557 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
558
559 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
560 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
561
562 /* shorter macros makes the table fit but are terse */
563 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
564 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
565 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
566
567 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
568 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
569 /* L2 Packet types */
570 I40E_PTT_UNUSED_ENTRY(0),
571 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
572 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
573 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
574 I40E_PTT_UNUSED_ENTRY(4),
575 I40E_PTT_UNUSED_ENTRY(5),
576 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
577 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
578 I40E_PTT_UNUSED_ENTRY(8),
579 I40E_PTT_UNUSED_ENTRY(9),
580 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
581 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
582 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
583 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
584 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
585 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
586 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
587 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
588 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
589 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
590 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
591 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
592
593 /* Non Tunneled IPv4 */
594 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
597 I40E_PTT_UNUSED_ENTRY(25),
598 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
599 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
600 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
601
602 /* IPv4 --> IPv4 */
603 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
604 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
605 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
606 I40E_PTT_UNUSED_ENTRY(32),
607 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
608 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
609 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
610
611 /* IPv4 --> IPv6 */
612 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
613 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
614 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
615 I40E_PTT_UNUSED_ENTRY(39),
616 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
617 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
618 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
619
620 /* IPv4 --> GRE/NAT */
621 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
622
623 /* IPv4 --> GRE/NAT --> IPv4 */
624 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
625 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
626 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
627 I40E_PTT_UNUSED_ENTRY(47),
628 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
629 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
630 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
631
632 /* IPv4 --> GRE/NAT --> IPv6 */
633 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
634 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
635 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
636 I40E_PTT_UNUSED_ENTRY(54),
637 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
638 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
639 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
640
641 /* IPv4 --> GRE/NAT --> MAC */
642 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
643
644 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
645 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
646 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
647 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
648 I40E_PTT_UNUSED_ENTRY(62),
649 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
650 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
651 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
652
653 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
654 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
655 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
656 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
657 I40E_PTT_UNUSED_ENTRY(69),
658 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
659 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
660 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
661
662 /* IPv4 --> GRE/NAT --> MAC/VLAN */
663 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
664
665 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
666 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
667 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
668 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
669 I40E_PTT_UNUSED_ENTRY(77),
670 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
671 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
672 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
673
674 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
675 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
676 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
677 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
678 I40E_PTT_UNUSED_ENTRY(84),
679 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
680 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
681 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
682
683 /* Non Tunneled IPv6 */
684 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
685 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
686 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
687 I40E_PTT_UNUSED_ENTRY(91),
688 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
689 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
690 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
691
692 /* IPv6 --> IPv4 */
693 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
694 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
695 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
696 I40E_PTT_UNUSED_ENTRY(98),
697 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
698 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
699 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
700
701 /* IPv6 --> IPv6 */
702 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
703 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
704 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
705 I40E_PTT_UNUSED_ENTRY(105),
706 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
707 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
708 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
709
710 /* IPv6 --> GRE/NAT */
711 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
712
713 /* IPv6 --> GRE/NAT -> IPv4 */
714 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
715 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
716 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
717 I40E_PTT_UNUSED_ENTRY(113),
718 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
719 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
720 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
721
722 /* IPv6 --> GRE/NAT -> IPv6 */
723 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
724 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
725 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
726 I40E_PTT_UNUSED_ENTRY(120),
727 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
728 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
729 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
730
731 /* IPv6 --> GRE/NAT -> MAC */
732 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
733
734 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
735 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
736 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
737 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
738 I40E_PTT_UNUSED_ENTRY(128),
739 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
740 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
741 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
742
743 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
744 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
745 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
746 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
747 I40E_PTT_UNUSED_ENTRY(135),
748 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
749 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
750 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
751
752 /* IPv6 --> GRE/NAT -> MAC/VLAN */
753 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
754
755 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
756 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
757 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
758 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
759 I40E_PTT_UNUSED_ENTRY(143),
760 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
761 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
762 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
763
764 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
765 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
766 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
767 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
768 I40E_PTT_UNUSED_ENTRY(150),
769 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
770 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
771 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
772
773 /* unused entries */
774 I40E_PTT_UNUSED_ENTRY(154),
775 I40E_PTT_UNUSED_ENTRY(155),
776 I40E_PTT_UNUSED_ENTRY(156),
777 I40E_PTT_UNUSED_ENTRY(157),
778 I40E_PTT_UNUSED_ENTRY(158),
779 I40E_PTT_UNUSED_ENTRY(159),
780
781 I40E_PTT_UNUSED_ENTRY(160),
782 I40E_PTT_UNUSED_ENTRY(161),
783 I40E_PTT_UNUSED_ENTRY(162),
784 I40E_PTT_UNUSED_ENTRY(163),
785 I40E_PTT_UNUSED_ENTRY(164),
786 I40E_PTT_UNUSED_ENTRY(165),
787 I40E_PTT_UNUSED_ENTRY(166),
788 I40E_PTT_UNUSED_ENTRY(167),
789 I40E_PTT_UNUSED_ENTRY(168),
790 I40E_PTT_UNUSED_ENTRY(169),
791
792 I40E_PTT_UNUSED_ENTRY(170),
793 I40E_PTT_UNUSED_ENTRY(171),
794 I40E_PTT_UNUSED_ENTRY(172),
795 I40E_PTT_UNUSED_ENTRY(173),
796 I40E_PTT_UNUSED_ENTRY(174),
797 I40E_PTT_UNUSED_ENTRY(175),
798 I40E_PTT_UNUSED_ENTRY(176),
799 I40E_PTT_UNUSED_ENTRY(177),
800 I40E_PTT_UNUSED_ENTRY(178),
801 I40E_PTT_UNUSED_ENTRY(179),
802
803 I40E_PTT_UNUSED_ENTRY(180),
804 I40E_PTT_UNUSED_ENTRY(181),
805 I40E_PTT_UNUSED_ENTRY(182),
806 I40E_PTT_UNUSED_ENTRY(183),
807 I40E_PTT_UNUSED_ENTRY(184),
808 I40E_PTT_UNUSED_ENTRY(185),
809 I40E_PTT_UNUSED_ENTRY(186),
810 I40E_PTT_UNUSED_ENTRY(187),
811 I40E_PTT_UNUSED_ENTRY(188),
812 I40E_PTT_UNUSED_ENTRY(189),
813
814 I40E_PTT_UNUSED_ENTRY(190),
815 I40E_PTT_UNUSED_ENTRY(191),
816 I40E_PTT_UNUSED_ENTRY(192),
817 I40E_PTT_UNUSED_ENTRY(193),
818 I40E_PTT_UNUSED_ENTRY(194),
819 I40E_PTT_UNUSED_ENTRY(195),
820 I40E_PTT_UNUSED_ENTRY(196),
821 I40E_PTT_UNUSED_ENTRY(197),
822 I40E_PTT_UNUSED_ENTRY(198),
823 I40E_PTT_UNUSED_ENTRY(199),
824
825 I40E_PTT_UNUSED_ENTRY(200),
826 I40E_PTT_UNUSED_ENTRY(201),
827 I40E_PTT_UNUSED_ENTRY(202),
828 I40E_PTT_UNUSED_ENTRY(203),
829 I40E_PTT_UNUSED_ENTRY(204),
830 I40E_PTT_UNUSED_ENTRY(205),
831 I40E_PTT_UNUSED_ENTRY(206),
832 I40E_PTT_UNUSED_ENTRY(207),
833 I40E_PTT_UNUSED_ENTRY(208),
834 I40E_PTT_UNUSED_ENTRY(209),
835
836 I40E_PTT_UNUSED_ENTRY(210),
837 I40E_PTT_UNUSED_ENTRY(211),
838 I40E_PTT_UNUSED_ENTRY(212),
839 I40E_PTT_UNUSED_ENTRY(213),
840 I40E_PTT_UNUSED_ENTRY(214),
841 I40E_PTT_UNUSED_ENTRY(215),
842 I40E_PTT_UNUSED_ENTRY(216),
843 I40E_PTT_UNUSED_ENTRY(217),
844 I40E_PTT_UNUSED_ENTRY(218),
845 I40E_PTT_UNUSED_ENTRY(219),
846
847 I40E_PTT_UNUSED_ENTRY(220),
848 I40E_PTT_UNUSED_ENTRY(221),
849 I40E_PTT_UNUSED_ENTRY(222),
850 I40E_PTT_UNUSED_ENTRY(223),
851 I40E_PTT_UNUSED_ENTRY(224),
852 I40E_PTT_UNUSED_ENTRY(225),
853 I40E_PTT_UNUSED_ENTRY(226),
854 I40E_PTT_UNUSED_ENTRY(227),
855 I40E_PTT_UNUSED_ENTRY(228),
856 I40E_PTT_UNUSED_ENTRY(229),
857
858 I40E_PTT_UNUSED_ENTRY(230),
859 I40E_PTT_UNUSED_ENTRY(231),
860 I40E_PTT_UNUSED_ENTRY(232),
861 I40E_PTT_UNUSED_ENTRY(233),
862 I40E_PTT_UNUSED_ENTRY(234),
863 I40E_PTT_UNUSED_ENTRY(235),
864 I40E_PTT_UNUSED_ENTRY(236),
865 I40E_PTT_UNUSED_ENTRY(237),
866 I40E_PTT_UNUSED_ENTRY(238),
867 I40E_PTT_UNUSED_ENTRY(239),
868
869 I40E_PTT_UNUSED_ENTRY(240),
870 I40E_PTT_UNUSED_ENTRY(241),
871 I40E_PTT_UNUSED_ENTRY(242),
872 I40E_PTT_UNUSED_ENTRY(243),
873 I40E_PTT_UNUSED_ENTRY(244),
874 I40E_PTT_UNUSED_ENTRY(245),
875 I40E_PTT_UNUSED_ENTRY(246),
876 I40E_PTT_UNUSED_ENTRY(247),
877 I40E_PTT_UNUSED_ENTRY(248),
878 I40E_PTT_UNUSED_ENTRY(249),
879
880 I40E_PTT_UNUSED_ENTRY(250),
881 I40E_PTT_UNUSED_ENTRY(251),
882 I40E_PTT_UNUSED_ENTRY(252),
883 I40E_PTT_UNUSED_ENTRY(253),
884 I40E_PTT_UNUSED_ENTRY(254),
885 I40E_PTT_UNUSED_ENTRY(255)
886 };
887
888 /**
889 * i40e_init_shared_code - Initialize the shared code
890 * @hw: pointer to hardware structure
891 *
892 * This assigns the MAC type and PHY code and inits the NVM.
893 * Does not touch the hardware. This function must be called prior to any
894 * other function in the shared code. The i40e_hw structure should be
895 * memset to 0 prior to calling this function. The following fields in
896 * hw structure should be filled in prior to calling this function:
897 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
898 * subsystem_vendor_id, and revision_id
899 **/
900 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
901 {
902 i40e_status status = 0;
903 u32 port, ari, func_rid;
904
905 i40e_set_mac_type(hw);
906
907 switch (hw->mac.type) {
908 case I40E_MAC_XL710:
909 case I40E_MAC_X722:
910 break;
911 default:
912 return I40E_ERR_DEVICE_NOT_SUPPORTED;
913 }
914
915 hw->phy.get_link_info = true;
916
917 /* Determine port number and PF number*/
918 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
919 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
920 hw->port = (u8)port;
921 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
922 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
923 func_rid = rd32(hw, I40E_PF_FUNC_RID);
924 if (ari)
925 hw->pf_id = (u8)(func_rid & 0xff);
926 else
927 hw->pf_id = (u8)(func_rid & 0x7);
928
929 if (hw->mac.type == I40E_MAC_X722)
930 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
931 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
932
933 status = i40e_init_nvm(hw);
934 return status;
935 }
936
937 /**
938 * i40e_aq_mac_address_read - Retrieve the MAC addresses
939 * @hw: pointer to the hw struct
940 * @flags: a return indicator of what addresses were added to the addr store
941 * @addrs: the requestor's mac addr store
942 * @cmd_details: pointer to command details structure or NULL
943 **/
944 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
945 u16 *flags,
946 struct i40e_aqc_mac_address_read_data *addrs,
947 struct i40e_asq_cmd_details *cmd_details)
948 {
949 struct i40e_aq_desc desc;
950 struct i40e_aqc_mac_address_read *cmd_data =
951 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
952 i40e_status status;
953
954 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
955 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
956
957 status = i40e_asq_send_command(hw, &desc, addrs,
958 sizeof(*addrs), cmd_details);
959 *flags = le16_to_cpu(cmd_data->command_flags);
960
961 return status;
962 }
963
964 /**
965 * i40e_aq_mac_address_write - Change the MAC addresses
966 * @hw: pointer to the hw struct
967 * @flags: indicates which MAC to be written
968 * @mac_addr: address to write
969 * @cmd_details: pointer to command details structure or NULL
970 **/
971 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
972 u16 flags, u8 *mac_addr,
973 struct i40e_asq_cmd_details *cmd_details)
974 {
975 struct i40e_aq_desc desc;
976 struct i40e_aqc_mac_address_write *cmd_data =
977 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
978 i40e_status status;
979
980 i40e_fill_default_direct_cmd_desc(&desc,
981 i40e_aqc_opc_mac_address_write);
982 cmd_data->command_flags = cpu_to_le16(flags);
983 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
984 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
985 ((u32)mac_addr[3] << 16) |
986 ((u32)mac_addr[4] << 8) |
987 mac_addr[5]);
988
989 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
990
991 return status;
992 }
993
994 /**
995 * i40e_get_mac_addr - get MAC address
996 * @hw: pointer to the HW structure
997 * @mac_addr: pointer to MAC address
998 *
999 * Reads the adapter's MAC address from register
1000 **/
1001 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1002 {
1003 struct i40e_aqc_mac_address_read_data addrs;
1004 i40e_status status;
1005 u16 flags = 0;
1006
1007 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1008
1009 if (flags & I40E_AQC_LAN_ADDR_VALID)
1010 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1011
1012 return status;
1013 }
1014
1015 /**
1016 * i40e_get_port_mac_addr - get Port MAC address
1017 * @hw: pointer to the HW structure
1018 * @mac_addr: pointer to Port MAC address
1019 *
1020 * Reads the adapter's Port MAC address
1021 **/
1022 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1023 {
1024 struct i40e_aqc_mac_address_read_data addrs;
1025 i40e_status status;
1026 u16 flags = 0;
1027
1028 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1029 if (status)
1030 return status;
1031
1032 if (flags & I40E_AQC_PORT_ADDR_VALID)
1033 ether_addr_copy(mac_addr, addrs.port_mac);
1034 else
1035 status = I40E_ERR_INVALID_MAC_ADDR;
1036
1037 return status;
1038 }
1039
1040 /**
1041 * i40e_pre_tx_queue_cfg - pre tx queue configure
1042 * @hw: pointer to the HW structure
1043 * @queue: target PF queue index
1044 * @enable: state change request
1045 *
1046 * Handles hw requirement to indicate intention to enable
1047 * or disable target queue.
1048 **/
1049 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1050 {
1051 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1052 u32 reg_block = 0;
1053 u32 reg_val;
1054
1055 if (abs_queue_idx >= 128) {
1056 reg_block = abs_queue_idx / 128;
1057 abs_queue_idx %= 128;
1058 }
1059
1060 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1061 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1062 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1063
1064 if (enable)
1065 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1066 else
1067 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1068
1069 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1070 }
1071
1072 /**
1073 * i40e_read_pba_string - Reads part number string from EEPROM
1074 * @hw: pointer to hardware structure
1075 * @pba_num: stores the part number string from the EEPROM
1076 * @pba_num_size: part number string buffer length
1077 *
1078 * Reads the part number string from the EEPROM.
1079 **/
1080 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1081 u32 pba_num_size)
1082 {
1083 i40e_status status = 0;
1084 u16 pba_word = 0;
1085 u16 pba_size = 0;
1086 u16 pba_ptr = 0;
1087 u16 i = 0;
1088
1089 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1090 if (status || (pba_word != 0xFAFA)) {
1091 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1092 return status;
1093 }
1094
1095 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1096 if (status) {
1097 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1098 return status;
1099 }
1100
1101 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1102 if (status) {
1103 hw_dbg(hw, "Failed to read PBA Block size.\n");
1104 return status;
1105 }
1106
1107 /* Subtract one to get PBA word count (PBA Size word is included in
1108 * total size)
1109 */
1110 pba_size--;
1111 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1112 hw_dbg(hw, "Buffer to small for PBA data.\n");
1113 return I40E_ERR_PARAM;
1114 }
1115
1116 for (i = 0; i < pba_size; i++) {
1117 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1118 if (status) {
1119 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1120 return status;
1121 }
1122
1123 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1124 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1125 }
1126 pba_num[(pba_size * 2)] = '\0';
1127
1128 return status;
1129 }
1130
1131 /**
1132 * i40e_get_media_type - Gets media type
1133 * @hw: pointer to the hardware structure
1134 **/
1135 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1136 {
1137 enum i40e_media_type media;
1138
1139 switch (hw->phy.link_info.phy_type) {
1140 case I40E_PHY_TYPE_10GBASE_SR:
1141 case I40E_PHY_TYPE_10GBASE_LR:
1142 case I40E_PHY_TYPE_1000BASE_SX:
1143 case I40E_PHY_TYPE_1000BASE_LX:
1144 case I40E_PHY_TYPE_40GBASE_SR4:
1145 case I40E_PHY_TYPE_40GBASE_LR4:
1146 case I40E_PHY_TYPE_25GBASE_LR:
1147 case I40E_PHY_TYPE_25GBASE_SR:
1148 media = I40E_MEDIA_TYPE_FIBER;
1149 break;
1150 case I40E_PHY_TYPE_100BASE_TX:
1151 case I40E_PHY_TYPE_1000BASE_T:
1152 case I40E_PHY_TYPE_10GBASE_T:
1153 media = I40E_MEDIA_TYPE_BASET;
1154 break;
1155 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1156 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1157 case I40E_PHY_TYPE_10GBASE_CR1:
1158 case I40E_PHY_TYPE_40GBASE_CR4:
1159 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1160 case I40E_PHY_TYPE_40GBASE_AOC:
1161 case I40E_PHY_TYPE_10GBASE_AOC:
1162 case I40E_PHY_TYPE_25GBASE_CR:
1163 case I40E_PHY_TYPE_25GBASE_AOC:
1164 case I40E_PHY_TYPE_25GBASE_ACC:
1165 media = I40E_MEDIA_TYPE_DA;
1166 break;
1167 case I40E_PHY_TYPE_1000BASE_KX:
1168 case I40E_PHY_TYPE_10GBASE_KX4:
1169 case I40E_PHY_TYPE_10GBASE_KR:
1170 case I40E_PHY_TYPE_40GBASE_KR4:
1171 case I40E_PHY_TYPE_20GBASE_KR2:
1172 case I40E_PHY_TYPE_25GBASE_KR:
1173 media = I40E_MEDIA_TYPE_BACKPLANE;
1174 break;
1175 case I40E_PHY_TYPE_SGMII:
1176 case I40E_PHY_TYPE_XAUI:
1177 case I40E_PHY_TYPE_XFI:
1178 case I40E_PHY_TYPE_XLAUI:
1179 case I40E_PHY_TYPE_XLPPI:
1180 default:
1181 media = I40E_MEDIA_TYPE_UNKNOWN;
1182 break;
1183 }
1184
1185 return media;
1186 }
1187
1188 /**
1189 * i40e_poll_globr - Poll for Global Reset completion
1190 * @hw: pointer to the hardware structure
1191 * @retry_limit: how many times to retry before failure
1192 **/
1193 static i40e_status i40e_poll_globr(struct i40e_hw *hw,
1194 u32 retry_limit)
1195 {
1196 u32 cnt, reg = 0;
1197
1198 for (cnt = 0; cnt < retry_limit; cnt++) {
1199 reg = rd32(hw, I40E_GLGEN_RSTAT);
1200 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1201 return 0;
1202 msleep(100);
1203 }
1204
1205 hw_dbg(hw, "Global reset failed.\n");
1206 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
1207
1208 return I40E_ERR_RESET_FAILED;
1209 }
1210
1211 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1212 #define I40E_PF_RESET_WAIT_COUNT 200
1213 /**
1214 * i40e_pf_reset - Reset the PF
1215 * @hw: pointer to the hardware structure
1216 *
1217 * Assuming someone else has triggered a global reset,
1218 * assure the global reset is complete and then reset the PF
1219 **/
1220 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1221 {
1222 u32 cnt = 0;
1223 u32 cnt1 = 0;
1224 u32 reg = 0;
1225 u32 grst_del;
1226
1227 /* Poll for Global Reset steady state in case of recent GRST.
1228 * The grst delay value is in 100ms units, and we'll wait a
1229 * couple counts longer to be sure we don't just miss the end.
1230 */
1231 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1232 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1233 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1234
1235 /* It can take upto 15 secs for GRST steady state.
1236 * Bump it to 16 secs max to be safe.
1237 */
1238 grst_del = grst_del * 20;
1239
1240 for (cnt = 0; cnt < grst_del; cnt++) {
1241 reg = rd32(hw, I40E_GLGEN_RSTAT);
1242 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1243 break;
1244 msleep(100);
1245 }
1246 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1247 hw_dbg(hw, "Global reset polling failed to complete.\n");
1248 return I40E_ERR_RESET_FAILED;
1249 }
1250
1251 /* Now Wait for the FW to be ready */
1252 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1253 reg = rd32(hw, I40E_GLNVM_ULD);
1254 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1255 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1256 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1257 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1258 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1259 break;
1260 }
1261 usleep_range(10000, 20000);
1262 }
1263 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1264 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1265 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1266 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1267 return I40E_ERR_RESET_FAILED;
1268 }
1269
1270 /* If there was a Global Reset in progress when we got here,
1271 * we don't need to do the PF Reset
1272 */
1273 if (!cnt) {
1274 u32 reg2 = 0;
1275 if (hw->revision_id == 0)
1276 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1277 else
1278 cnt = I40E_PF_RESET_WAIT_COUNT;
1279 reg = rd32(hw, I40E_PFGEN_CTRL);
1280 wr32(hw, I40E_PFGEN_CTRL,
1281 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1282 for (; cnt; cnt--) {
1283 reg = rd32(hw, I40E_PFGEN_CTRL);
1284 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1285 break;
1286 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1287 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1288 break;
1289 usleep_range(1000, 2000);
1290 }
1291 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1292 if (i40e_poll_globr(hw, grst_del))
1293 return I40E_ERR_RESET_FAILED;
1294 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1295 hw_dbg(hw, "PF reset polling failed to complete.\n");
1296 return I40E_ERR_RESET_FAILED;
1297 }
1298 }
1299
1300 i40e_clear_pxe_mode(hw);
1301
1302 return 0;
1303 }
1304
1305 /**
1306 * i40e_clear_hw - clear out any left over hw state
1307 * @hw: pointer to the hw struct
1308 *
1309 * Clear queues and interrupts, typically called at init time,
1310 * but after the capabilities have been found so we know how many
1311 * queues and msix vectors have been allocated.
1312 **/
1313 void i40e_clear_hw(struct i40e_hw *hw)
1314 {
1315 u32 num_queues, base_queue;
1316 u32 num_pf_int;
1317 u32 num_vf_int;
1318 u32 num_vfs;
1319 u32 i, j;
1320 u32 val;
1321 u32 eol = 0x7ff;
1322
1323 /* get number of interrupts, queues, and VFs */
1324 val = rd32(hw, I40E_GLPCI_CNF2);
1325 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1326 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1327 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1328 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1329
1330 val = rd32(hw, I40E_PFLAN_QALLOC);
1331 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1332 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1333 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1334 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1335 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1336 num_queues = (j - base_queue) + 1;
1337 else
1338 num_queues = 0;
1339
1340 val = rd32(hw, I40E_PF_VT_PFALLOC);
1341 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1342 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1343 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1344 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1345 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1346 num_vfs = (j - i) + 1;
1347 else
1348 num_vfs = 0;
1349
1350 /* stop all the interrupts */
1351 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1352 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1353 for (i = 0; i < num_pf_int - 2; i++)
1354 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1355
1356 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1357 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1358 wr32(hw, I40E_PFINT_LNKLST0, val);
1359 for (i = 0; i < num_pf_int - 2; i++)
1360 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1361 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1362 for (i = 0; i < num_vfs; i++)
1363 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1364 for (i = 0; i < num_vf_int - 2; i++)
1365 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1366
1367 /* warn the HW of the coming Tx disables */
1368 for (i = 0; i < num_queues; i++) {
1369 u32 abs_queue_idx = base_queue + i;
1370 u32 reg_block = 0;
1371
1372 if (abs_queue_idx >= 128) {
1373 reg_block = abs_queue_idx / 128;
1374 abs_queue_idx %= 128;
1375 }
1376
1377 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1378 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1379 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1380 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1381
1382 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1383 }
1384 udelay(400);
1385
1386 /* stop all the queues */
1387 for (i = 0; i < num_queues; i++) {
1388 wr32(hw, I40E_QINT_TQCTL(i), 0);
1389 wr32(hw, I40E_QTX_ENA(i), 0);
1390 wr32(hw, I40E_QINT_RQCTL(i), 0);
1391 wr32(hw, I40E_QRX_ENA(i), 0);
1392 }
1393
1394 /* short wait for all queue disables to settle */
1395 udelay(50);
1396 }
1397
1398 /**
1399 * i40e_clear_pxe_mode - clear pxe operations mode
1400 * @hw: pointer to the hw struct
1401 *
1402 * Make sure all PXE mode settings are cleared, including things
1403 * like descriptor fetch/write-back mode.
1404 **/
1405 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1406 {
1407 u32 reg;
1408
1409 if (i40e_check_asq_alive(hw))
1410 i40e_aq_clear_pxe_mode(hw, NULL);
1411
1412 /* Clear single descriptor fetch/write-back mode */
1413 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1414
1415 if (hw->revision_id == 0) {
1416 /* As a work around clear PXE_MODE instead of setting it */
1417 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1418 } else {
1419 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1420 }
1421 }
1422
1423 /**
1424 * i40e_led_is_mine - helper to find matching led
1425 * @hw: pointer to the hw struct
1426 * @idx: index into GPIO registers
1427 *
1428 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1429 */
1430 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1431 {
1432 u32 gpio_val = 0;
1433 u32 port;
1434
1435 if (!hw->func_caps.led[idx])
1436 return 0;
1437
1438 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1439 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1440 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1441
1442 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1443 * if it is not our port then ignore
1444 */
1445 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1446 (port != hw->port))
1447 return 0;
1448
1449 return gpio_val;
1450 }
1451
1452 #define I40E_COMBINED_ACTIVITY 0xA
1453 #define I40E_FILTER_ACTIVITY 0xE
1454 #define I40E_LINK_ACTIVITY 0xC
1455 #define I40E_MAC_ACTIVITY 0xD
1456 #define I40E_LED0 22
1457
1458 /**
1459 * i40e_led_get - return current on/off mode
1460 * @hw: pointer to the hw struct
1461 *
1462 * The value returned is the 'mode' field as defined in the
1463 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1464 * values are variations of possible behaviors relating to
1465 * blink, link, and wire.
1466 **/
1467 u32 i40e_led_get(struct i40e_hw *hw)
1468 {
1469 u32 current_mode = 0;
1470 u32 mode = 0;
1471 int i;
1472
1473 /* as per the documentation GPIO 22-29 are the LED
1474 * GPIO pins named LED0..LED7
1475 */
1476 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1477 u32 gpio_val = i40e_led_is_mine(hw, i);
1478
1479 if (!gpio_val)
1480 continue;
1481
1482 /* ignore gpio LED src mode entries related to the activity
1483 * LEDs
1484 */
1485 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1486 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1487 switch (current_mode) {
1488 case I40E_COMBINED_ACTIVITY:
1489 case I40E_FILTER_ACTIVITY:
1490 case I40E_MAC_ACTIVITY:
1491 case I40E_LINK_ACTIVITY:
1492 continue;
1493 default:
1494 break;
1495 }
1496
1497 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1498 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1499 break;
1500 }
1501
1502 return mode;
1503 }
1504
1505 /**
1506 * i40e_led_set - set new on/off mode
1507 * @hw: pointer to the hw struct
1508 * @mode: 0=off, 0xf=on (else see manual for mode details)
1509 * @blink: true if the LED should blink when on, false if steady
1510 *
1511 * if this function is used to turn on the blink it should
1512 * be used to disable the blink when restoring the original state.
1513 **/
1514 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1515 {
1516 u32 current_mode = 0;
1517 int i;
1518
1519 if (mode & 0xfffffff0)
1520 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1521
1522 /* as per the documentation GPIO 22-29 are the LED
1523 * GPIO pins named LED0..LED7
1524 */
1525 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1526 u32 gpio_val = i40e_led_is_mine(hw, i);
1527
1528 if (!gpio_val)
1529 continue;
1530
1531 /* ignore gpio LED src mode entries related to the activity
1532 * LEDs
1533 */
1534 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1535 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1536 switch (current_mode) {
1537 case I40E_COMBINED_ACTIVITY:
1538 case I40E_FILTER_ACTIVITY:
1539 case I40E_MAC_ACTIVITY:
1540 case I40E_LINK_ACTIVITY:
1541 continue;
1542 default:
1543 break;
1544 }
1545
1546 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1547 /* this & is a bit of paranoia, but serves as a range check */
1548 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1549 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1550
1551 if (blink)
1552 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1553 else
1554 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1555
1556 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1557 break;
1558 }
1559 }
1560
1561 /* Admin command wrappers */
1562
1563 /**
1564 * i40e_aq_get_phy_capabilities
1565 * @hw: pointer to the hw struct
1566 * @abilities: structure for PHY capabilities to be filled
1567 * @qualified_modules: report Qualified Modules
1568 * @report_init: report init capabilities (active are default)
1569 * @cmd_details: pointer to command details structure or NULL
1570 *
1571 * Returns the various PHY abilities supported on the Port.
1572 **/
1573 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1574 bool qualified_modules, bool report_init,
1575 struct i40e_aq_get_phy_abilities_resp *abilities,
1576 struct i40e_asq_cmd_details *cmd_details)
1577 {
1578 struct i40e_aq_desc desc;
1579 i40e_status status;
1580 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1581 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1582
1583 if (!abilities)
1584 return I40E_ERR_PARAM;
1585
1586 do {
1587 i40e_fill_default_direct_cmd_desc(&desc,
1588 i40e_aqc_opc_get_phy_abilities);
1589
1590 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1591 if (abilities_size > I40E_AQ_LARGE_BUF)
1592 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1593
1594 if (qualified_modules)
1595 desc.params.external.param0 |=
1596 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1597
1598 if (report_init)
1599 desc.params.external.param0 |=
1600 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1601
1602 status = i40e_asq_send_command(hw, &desc, abilities,
1603 abilities_size, cmd_details);
1604
1605 if (status)
1606 break;
1607
1608 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1609 status = I40E_ERR_UNKNOWN_PHY;
1610 break;
1611 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1612 usleep_range(1000, 2000);
1613 total_delay++;
1614 status = I40E_ERR_TIMEOUT;
1615 }
1616 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1617 (total_delay < max_delay));
1618
1619 if (status)
1620 return status;
1621
1622 if (report_init) {
1623 if (hw->mac.type == I40E_MAC_XL710 &&
1624 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1625 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1626 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1627 } else {
1628 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1629 hw->phy.phy_types |=
1630 ((u64)abilities->phy_type_ext << 32);
1631 }
1632 }
1633
1634 return status;
1635 }
1636
1637 /**
1638 * i40e_aq_set_phy_config
1639 * @hw: pointer to the hw struct
1640 * @config: structure with PHY configuration to be set
1641 * @cmd_details: pointer to command details structure or NULL
1642 *
1643 * Set the various PHY configuration parameters
1644 * supported on the Port.One or more of the Set PHY config parameters may be
1645 * ignored in an MFP mode as the PF may not have the privilege to set some
1646 * of the PHY Config parameters. This status will be indicated by the
1647 * command response.
1648 **/
1649 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1650 struct i40e_aq_set_phy_config *config,
1651 struct i40e_asq_cmd_details *cmd_details)
1652 {
1653 struct i40e_aq_desc desc;
1654 struct i40e_aq_set_phy_config *cmd =
1655 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1656 enum i40e_status_code status;
1657
1658 if (!config)
1659 return I40E_ERR_PARAM;
1660
1661 i40e_fill_default_direct_cmd_desc(&desc,
1662 i40e_aqc_opc_set_phy_config);
1663
1664 *cmd = *config;
1665
1666 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1667
1668 return status;
1669 }
1670
1671 static noinline_for_stack enum i40e_status_code
1672 i40e_set_fc_status(struct i40e_hw *hw,
1673 struct i40e_aq_get_phy_abilities_resp *abilities,
1674 bool atomic_restart)
1675 {
1676 struct i40e_aq_set_phy_config config;
1677 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1678 u8 pause_mask = 0x0;
1679
1680 switch (fc_mode) {
1681 case I40E_FC_FULL:
1682 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1683 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1684 break;
1685 case I40E_FC_RX_PAUSE:
1686 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1687 break;
1688 case I40E_FC_TX_PAUSE:
1689 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1690 break;
1691 default:
1692 break;
1693 }
1694
1695 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1696 /* clear the old pause settings */
1697 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1698 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1699 /* set the new abilities */
1700 config.abilities |= pause_mask;
1701 /* If the abilities have changed, then set the new config */
1702 if (config.abilities == abilities->abilities)
1703 return 0;
1704
1705 /* Auto restart link so settings take effect */
1706 if (atomic_restart)
1707 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1708 /* Copy over all the old settings */
1709 config.phy_type = abilities->phy_type;
1710 config.phy_type_ext = abilities->phy_type_ext;
1711 config.link_speed = abilities->link_speed;
1712 config.eee_capability = abilities->eee_capability;
1713 config.eeer = abilities->eeer_val;
1714 config.low_power_ctrl = abilities->d3_lpan;
1715 config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
1716 I40E_AQ_PHY_FEC_CONFIG_MASK;
1717
1718 return i40e_aq_set_phy_config(hw, &config, NULL);
1719 }
1720
1721 /**
1722 * i40e_set_fc
1723 * @hw: pointer to the hw struct
1724 * @aq_failures: buffer to return AdminQ failure information
1725 * @atomic_restart: whether to enable atomic link restart
1726 *
1727 * Set the requested flow control mode using set_phy_config.
1728 **/
1729 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1730 bool atomic_restart)
1731 {
1732 struct i40e_aq_get_phy_abilities_resp abilities;
1733 enum i40e_status_code status;
1734
1735 *aq_failures = 0x0;
1736
1737 /* Get the current phy config */
1738 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1739 NULL);
1740 if (status) {
1741 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1742 return status;
1743 }
1744
1745 status = i40e_set_fc_status(hw, &abilities, atomic_restart);
1746 if (status)
1747 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1748
1749 /* Update the link info */
1750 status = i40e_update_link_info(hw);
1751 if (status) {
1752 /* Wait a little bit (on 40G cards it sometimes takes a really
1753 * long time for link to come back from the atomic reset)
1754 * and try once more
1755 */
1756 msleep(1000);
1757 status = i40e_update_link_info(hw);
1758 }
1759 if (status)
1760 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1761
1762 return status;
1763 }
1764
1765 /**
1766 * i40e_aq_clear_pxe_mode
1767 * @hw: pointer to the hw struct
1768 * @cmd_details: pointer to command details structure or NULL
1769 *
1770 * Tell the firmware that the driver is taking over from PXE
1771 **/
1772 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1773 struct i40e_asq_cmd_details *cmd_details)
1774 {
1775 i40e_status status;
1776 struct i40e_aq_desc desc;
1777 struct i40e_aqc_clear_pxe *cmd =
1778 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1779
1780 i40e_fill_default_direct_cmd_desc(&desc,
1781 i40e_aqc_opc_clear_pxe_mode);
1782
1783 cmd->rx_cnt = 0x2;
1784
1785 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1786
1787 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1788
1789 return status;
1790 }
1791
1792 /**
1793 * i40e_aq_set_link_restart_an
1794 * @hw: pointer to the hw struct
1795 * @enable_link: if true: enable link, if false: disable link
1796 * @cmd_details: pointer to command details structure or NULL
1797 *
1798 * Sets up the link and restarts the Auto-Negotiation over the link.
1799 **/
1800 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1801 bool enable_link,
1802 struct i40e_asq_cmd_details *cmd_details)
1803 {
1804 struct i40e_aq_desc desc;
1805 struct i40e_aqc_set_link_restart_an *cmd =
1806 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1807 i40e_status status;
1808
1809 i40e_fill_default_direct_cmd_desc(&desc,
1810 i40e_aqc_opc_set_link_restart_an);
1811
1812 cmd->command = I40E_AQ_PHY_RESTART_AN;
1813 if (enable_link)
1814 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1815 else
1816 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1817
1818 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1819
1820 return status;
1821 }
1822
1823 /**
1824 * i40e_aq_get_link_info
1825 * @hw: pointer to the hw struct
1826 * @enable_lse: enable/disable LinkStatusEvent reporting
1827 * @link: pointer to link status structure - optional
1828 * @cmd_details: pointer to command details structure or NULL
1829 *
1830 * Returns the link status of the adapter.
1831 **/
1832 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1833 bool enable_lse, struct i40e_link_status *link,
1834 struct i40e_asq_cmd_details *cmd_details)
1835 {
1836 struct i40e_aq_desc desc;
1837 struct i40e_aqc_get_link_status *resp =
1838 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1839 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1840 i40e_status status;
1841 bool tx_pause, rx_pause;
1842 u16 command_flags;
1843
1844 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1845
1846 if (enable_lse)
1847 command_flags = I40E_AQ_LSE_ENABLE;
1848 else
1849 command_flags = I40E_AQ_LSE_DISABLE;
1850 resp->command_flags = cpu_to_le16(command_flags);
1851
1852 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1853
1854 if (status)
1855 goto aq_get_link_info_exit;
1856
1857 /* save off old link status information */
1858 hw->phy.link_info_old = *hw_link_info;
1859
1860 /* update link status */
1861 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1862 hw->phy.media_type = i40e_get_media_type(hw);
1863 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1864 hw_link_info->link_info = resp->link_info;
1865 hw_link_info->an_info = resp->an_info;
1866 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1867 I40E_AQ_CONFIG_FEC_RS_ENA);
1868 hw_link_info->ext_info = resp->ext_info;
1869 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1870 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1871 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1872
1873 /* update fc info */
1874 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1875 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1876 if (tx_pause & rx_pause)
1877 hw->fc.current_mode = I40E_FC_FULL;
1878 else if (tx_pause)
1879 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1880 else if (rx_pause)
1881 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1882 else
1883 hw->fc.current_mode = I40E_FC_NONE;
1884
1885 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1886 hw_link_info->crc_enable = true;
1887 else
1888 hw_link_info->crc_enable = false;
1889
1890 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1891 hw_link_info->lse_enable = true;
1892 else
1893 hw_link_info->lse_enable = false;
1894
1895 if ((hw->mac.type == I40E_MAC_XL710) &&
1896 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1897 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1898 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1899
1900 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1901 hw->aq.api_min_ver >= 7) {
1902 __le32 tmp;
1903
1904 memcpy(&tmp, resp->link_type, sizeof(tmp));
1905 hw->phy.phy_types = le32_to_cpu(tmp);
1906 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1907 }
1908
1909 /* save link status information */
1910 if (link)
1911 *link = *hw_link_info;
1912
1913 /* flag cleared so helper functions don't call AQ again */
1914 hw->phy.get_link_info = false;
1915
1916 aq_get_link_info_exit:
1917 return status;
1918 }
1919
1920 /**
1921 * i40e_aq_set_phy_int_mask
1922 * @hw: pointer to the hw struct
1923 * @mask: interrupt mask to be set
1924 * @cmd_details: pointer to command details structure or NULL
1925 *
1926 * Set link interrupt mask.
1927 **/
1928 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1929 u16 mask,
1930 struct i40e_asq_cmd_details *cmd_details)
1931 {
1932 struct i40e_aq_desc desc;
1933 struct i40e_aqc_set_phy_int_mask *cmd =
1934 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1935 i40e_status status;
1936
1937 i40e_fill_default_direct_cmd_desc(&desc,
1938 i40e_aqc_opc_set_phy_int_mask);
1939
1940 cmd->event_mask = cpu_to_le16(mask);
1941
1942 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1943
1944 return status;
1945 }
1946
1947 /**
1948 * i40e_aq_set_phy_debug
1949 * @hw: pointer to the hw struct
1950 * @cmd_flags: debug command flags
1951 * @cmd_details: pointer to command details structure or NULL
1952 *
1953 * Reset the external PHY.
1954 **/
1955 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1956 struct i40e_asq_cmd_details *cmd_details)
1957 {
1958 struct i40e_aq_desc desc;
1959 struct i40e_aqc_set_phy_debug *cmd =
1960 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1961 i40e_status status;
1962
1963 i40e_fill_default_direct_cmd_desc(&desc,
1964 i40e_aqc_opc_set_phy_debug);
1965
1966 cmd->command_flags = cmd_flags;
1967
1968 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1969
1970 return status;
1971 }
1972
1973 /**
1974 * i40e_aq_add_vsi
1975 * @hw: pointer to the hw struct
1976 * @vsi_ctx: pointer to a vsi context struct
1977 * @cmd_details: pointer to command details structure or NULL
1978 *
1979 * Add a VSI context to the hardware.
1980 **/
1981 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1982 struct i40e_vsi_context *vsi_ctx,
1983 struct i40e_asq_cmd_details *cmd_details)
1984 {
1985 struct i40e_aq_desc desc;
1986 struct i40e_aqc_add_get_update_vsi *cmd =
1987 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1988 struct i40e_aqc_add_get_update_vsi_completion *resp =
1989 (struct i40e_aqc_add_get_update_vsi_completion *)
1990 &desc.params.raw;
1991 i40e_status status;
1992
1993 i40e_fill_default_direct_cmd_desc(&desc,
1994 i40e_aqc_opc_add_vsi);
1995
1996 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1997 cmd->connection_type = vsi_ctx->connection_type;
1998 cmd->vf_id = vsi_ctx->vf_num;
1999 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
2000
2001 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2002
2003 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2004 sizeof(vsi_ctx->info), cmd_details);
2005
2006 if (status)
2007 goto aq_add_vsi_exit;
2008
2009 vsi_ctx->seid = le16_to_cpu(resp->seid);
2010 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2011 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2012 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2013
2014 aq_add_vsi_exit:
2015 return status;
2016 }
2017
2018 /**
2019 * i40e_aq_set_default_vsi
2020 * @hw: pointer to the hw struct
2021 * @seid: vsi number
2022 * @cmd_details: pointer to command details structure or NULL
2023 **/
2024 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
2025 u16 seid,
2026 struct i40e_asq_cmd_details *cmd_details)
2027 {
2028 struct i40e_aq_desc desc;
2029 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2030 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2031 &desc.params.raw;
2032 i40e_status status;
2033
2034 i40e_fill_default_direct_cmd_desc(&desc,
2035 i40e_aqc_opc_set_vsi_promiscuous_modes);
2036
2037 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2038 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2039 cmd->seid = cpu_to_le16(seid);
2040
2041 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2042
2043 return status;
2044 }
2045
2046 /**
2047 * i40e_aq_clear_default_vsi
2048 * @hw: pointer to the hw struct
2049 * @seid: vsi number
2050 * @cmd_details: pointer to command details structure or NULL
2051 **/
2052 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2053 u16 seid,
2054 struct i40e_asq_cmd_details *cmd_details)
2055 {
2056 struct i40e_aq_desc desc;
2057 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2058 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2059 &desc.params.raw;
2060 i40e_status status;
2061
2062 i40e_fill_default_direct_cmd_desc(&desc,
2063 i40e_aqc_opc_set_vsi_promiscuous_modes);
2064
2065 cmd->promiscuous_flags = cpu_to_le16(0);
2066 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2067 cmd->seid = cpu_to_le16(seid);
2068
2069 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2070
2071 return status;
2072 }
2073
2074 /**
2075 * i40e_aq_set_vsi_unicast_promiscuous
2076 * @hw: pointer to the hw struct
2077 * @seid: vsi number
2078 * @set: set unicast promiscuous enable/disable
2079 * @cmd_details: pointer to command details structure or NULL
2080 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2081 **/
2082 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2083 u16 seid, bool set,
2084 struct i40e_asq_cmd_details *cmd_details,
2085 bool rx_only_promisc)
2086 {
2087 struct i40e_aq_desc desc;
2088 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2089 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2090 i40e_status status;
2091 u16 flags = 0;
2092
2093 i40e_fill_default_direct_cmd_desc(&desc,
2094 i40e_aqc_opc_set_vsi_promiscuous_modes);
2095
2096 if (set) {
2097 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2098 if (rx_only_promisc &&
2099 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2100 (hw->aq.api_maj_ver > 1)))
2101 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2102 }
2103
2104 cmd->promiscuous_flags = cpu_to_le16(flags);
2105
2106 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2107 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2108 (hw->aq.api_maj_ver > 1))
2109 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
2110
2111 cmd->seid = cpu_to_le16(seid);
2112 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2113
2114 return status;
2115 }
2116
2117 /**
2118 * i40e_aq_set_vsi_multicast_promiscuous
2119 * @hw: pointer to the hw struct
2120 * @seid: vsi number
2121 * @set: set multicast promiscuous enable/disable
2122 * @cmd_details: pointer to command details structure or NULL
2123 **/
2124 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2125 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2126 {
2127 struct i40e_aq_desc desc;
2128 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2129 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2130 i40e_status status;
2131 u16 flags = 0;
2132
2133 i40e_fill_default_direct_cmd_desc(&desc,
2134 i40e_aqc_opc_set_vsi_promiscuous_modes);
2135
2136 if (set)
2137 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2138
2139 cmd->promiscuous_flags = cpu_to_le16(flags);
2140
2141 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2142
2143 cmd->seid = cpu_to_le16(seid);
2144 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2145
2146 return status;
2147 }
2148
2149 /**
2150 * i40e_aq_set_vsi_mc_promisc_on_vlan
2151 * @hw: pointer to the hw struct
2152 * @seid: vsi number
2153 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2154 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2155 * @cmd_details: pointer to command details structure or NULL
2156 **/
2157 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2158 u16 seid, bool enable,
2159 u16 vid,
2160 struct i40e_asq_cmd_details *cmd_details)
2161 {
2162 struct i40e_aq_desc desc;
2163 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2164 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2165 enum i40e_status_code status;
2166 u16 flags = 0;
2167
2168 i40e_fill_default_direct_cmd_desc(&desc,
2169 i40e_aqc_opc_set_vsi_promiscuous_modes);
2170
2171 if (enable)
2172 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2173
2174 cmd->promiscuous_flags = cpu_to_le16(flags);
2175 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2176 cmd->seid = cpu_to_le16(seid);
2177 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2178
2179 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2180
2181 return status;
2182 }
2183
2184 /**
2185 * i40e_aq_set_vsi_uc_promisc_on_vlan
2186 * @hw: pointer to the hw struct
2187 * @seid: vsi number
2188 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2189 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2190 * @cmd_details: pointer to command details structure or NULL
2191 **/
2192 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2193 u16 seid, bool enable,
2194 u16 vid,
2195 struct i40e_asq_cmd_details *cmd_details)
2196 {
2197 struct i40e_aq_desc desc;
2198 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2199 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2200 enum i40e_status_code status;
2201 u16 flags = 0;
2202
2203 i40e_fill_default_direct_cmd_desc(&desc,
2204 i40e_aqc_opc_set_vsi_promiscuous_modes);
2205
2206 if (enable)
2207 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2208
2209 cmd->promiscuous_flags = cpu_to_le16(flags);
2210 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2211 cmd->seid = cpu_to_le16(seid);
2212 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2213
2214 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2215
2216 return status;
2217 }
2218
2219 /**
2220 * i40e_aq_set_vsi_bc_promisc_on_vlan
2221 * @hw: pointer to the hw struct
2222 * @seid: vsi number
2223 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2224 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2225 * @cmd_details: pointer to command details structure or NULL
2226 **/
2227 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2228 u16 seid, bool enable, u16 vid,
2229 struct i40e_asq_cmd_details *cmd_details)
2230 {
2231 struct i40e_aq_desc desc;
2232 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2233 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2234 i40e_status status;
2235 u16 flags = 0;
2236
2237 i40e_fill_default_direct_cmd_desc(&desc,
2238 i40e_aqc_opc_set_vsi_promiscuous_modes);
2239
2240 if (enable)
2241 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2242
2243 cmd->promiscuous_flags = cpu_to_le16(flags);
2244 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2245 cmd->seid = cpu_to_le16(seid);
2246 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2247
2248 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2249
2250 return status;
2251 }
2252
2253 /**
2254 * i40e_aq_set_vsi_broadcast
2255 * @hw: pointer to the hw struct
2256 * @seid: vsi number
2257 * @set_filter: true to set filter, false to clear filter
2258 * @cmd_details: pointer to command details structure or NULL
2259 *
2260 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2261 **/
2262 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2263 u16 seid, bool set_filter,
2264 struct i40e_asq_cmd_details *cmd_details)
2265 {
2266 struct i40e_aq_desc desc;
2267 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2268 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2269 i40e_status status;
2270
2271 i40e_fill_default_direct_cmd_desc(&desc,
2272 i40e_aqc_opc_set_vsi_promiscuous_modes);
2273
2274 if (set_filter)
2275 cmd->promiscuous_flags
2276 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2277 else
2278 cmd->promiscuous_flags
2279 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2280
2281 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2282 cmd->seid = cpu_to_le16(seid);
2283 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2284
2285 return status;
2286 }
2287
2288 /**
2289 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2290 * @hw: pointer to the hw struct
2291 * @seid: vsi number
2292 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2293 * @cmd_details: pointer to command details structure or NULL
2294 **/
2295 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2296 u16 seid, bool enable,
2297 struct i40e_asq_cmd_details *cmd_details)
2298 {
2299 struct i40e_aq_desc desc;
2300 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2301 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2302 i40e_status status;
2303 u16 flags = 0;
2304
2305 i40e_fill_default_direct_cmd_desc(&desc,
2306 i40e_aqc_opc_set_vsi_promiscuous_modes);
2307 if (enable)
2308 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2309
2310 cmd->promiscuous_flags = cpu_to_le16(flags);
2311 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2312 cmd->seid = cpu_to_le16(seid);
2313
2314 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2315
2316 return status;
2317 }
2318
2319 /**
2320 * i40e_get_vsi_params - get VSI configuration info
2321 * @hw: pointer to the hw struct
2322 * @vsi_ctx: pointer to a vsi context struct
2323 * @cmd_details: pointer to command details structure or NULL
2324 **/
2325 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2326 struct i40e_vsi_context *vsi_ctx,
2327 struct i40e_asq_cmd_details *cmd_details)
2328 {
2329 struct i40e_aq_desc desc;
2330 struct i40e_aqc_add_get_update_vsi *cmd =
2331 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2332 struct i40e_aqc_add_get_update_vsi_completion *resp =
2333 (struct i40e_aqc_add_get_update_vsi_completion *)
2334 &desc.params.raw;
2335 i40e_status status;
2336
2337 i40e_fill_default_direct_cmd_desc(&desc,
2338 i40e_aqc_opc_get_vsi_parameters);
2339
2340 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2341
2342 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2343
2344 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2345 sizeof(vsi_ctx->info), NULL);
2346
2347 if (status)
2348 goto aq_get_vsi_params_exit;
2349
2350 vsi_ctx->seid = le16_to_cpu(resp->seid);
2351 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2352 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2353 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2354
2355 aq_get_vsi_params_exit:
2356 return status;
2357 }
2358
2359 /**
2360 * i40e_aq_update_vsi_params
2361 * @hw: pointer to the hw struct
2362 * @vsi_ctx: pointer to a vsi context struct
2363 * @cmd_details: pointer to command details structure or NULL
2364 *
2365 * Update a VSI context.
2366 **/
2367 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2368 struct i40e_vsi_context *vsi_ctx,
2369 struct i40e_asq_cmd_details *cmd_details)
2370 {
2371 struct i40e_aq_desc desc;
2372 struct i40e_aqc_add_get_update_vsi *cmd =
2373 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2374 struct i40e_aqc_add_get_update_vsi_completion *resp =
2375 (struct i40e_aqc_add_get_update_vsi_completion *)
2376 &desc.params.raw;
2377 i40e_status status;
2378
2379 i40e_fill_default_direct_cmd_desc(&desc,
2380 i40e_aqc_opc_update_vsi_parameters);
2381 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2382
2383 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2384
2385 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2386 sizeof(vsi_ctx->info), cmd_details);
2387
2388 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2389 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2390
2391 return status;
2392 }
2393
2394 /**
2395 * i40e_aq_get_switch_config
2396 * @hw: pointer to the hardware structure
2397 * @buf: pointer to the result buffer
2398 * @buf_size: length of input buffer
2399 * @start_seid: seid to start for the report, 0 == beginning
2400 * @cmd_details: pointer to command details structure or NULL
2401 *
2402 * Fill the buf with switch configuration returned from AdminQ command
2403 **/
2404 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2405 struct i40e_aqc_get_switch_config_resp *buf,
2406 u16 buf_size, u16 *start_seid,
2407 struct i40e_asq_cmd_details *cmd_details)
2408 {
2409 struct i40e_aq_desc desc;
2410 struct i40e_aqc_switch_seid *scfg =
2411 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2412 i40e_status status;
2413
2414 i40e_fill_default_direct_cmd_desc(&desc,
2415 i40e_aqc_opc_get_switch_config);
2416 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2417 if (buf_size > I40E_AQ_LARGE_BUF)
2418 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2419 scfg->seid = cpu_to_le16(*start_seid);
2420
2421 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2422 *start_seid = le16_to_cpu(scfg->seid);
2423
2424 return status;
2425 }
2426
2427 /**
2428 * i40e_aq_set_switch_config
2429 * @hw: pointer to the hardware structure
2430 * @flags: bit flag values to set
2431 * @mode: cloud filter mode
2432 * @valid_flags: which bit flags to set
2433 * @mode: cloud filter mode
2434 * @cmd_details: pointer to command details structure or NULL
2435 *
2436 * Set switch configuration bits
2437 **/
2438 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2439 u16 flags,
2440 u16 valid_flags, u8 mode,
2441 struct i40e_asq_cmd_details *cmd_details)
2442 {
2443 struct i40e_aq_desc desc;
2444 struct i40e_aqc_set_switch_config *scfg =
2445 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2446 enum i40e_status_code status;
2447
2448 i40e_fill_default_direct_cmd_desc(&desc,
2449 i40e_aqc_opc_set_switch_config);
2450 scfg->flags = cpu_to_le16(flags);
2451 scfg->valid_flags = cpu_to_le16(valid_flags);
2452 scfg->mode = mode;
2453 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2454 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
2455 scfg->first_tag = cpu_to_le16(hw->first_tag);
2456 scfg->second_tag = cpu_to_le16(hw->second_tag);
2457 }
2458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2459
2460 return status;
2461 }
2462
2463 /**
2464 * i40e_aq_get_firmware_version
2465 * @hw: pointer to the hw struct
2466 * @fw_major_version: firmware major version
2467 * @fw_minor_version: firmware minor version
2468 * @fw_build: firmware build number
2469 * @api_major_version: major queue version
2470 * @api_minor_version: minor queue version
2471 * @cmd_details: pointer to command details structure or NULL
2472 *
2473 * Get the firmware version from the admin queue commands
2474 **/
2475 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2476 u16 *fw_major_version, u16 *fw_minor_version,
2477 u32 *fw_build,
2478 u16 *api_major_version, u16 *api_minor_version,
2479 struct i40e_asq_cmd_details *cmd_details)
2480 {
2481 struct i40e_aq_desc desc;
2482 struct i40e_aqc_get_version *resp =
2483 (struct i40e_aqc_get_version *)&desc.params.raw;
2484 i40e_status status;
2485
2486 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2487
2488 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2489
2490 if (!status) {
2491 if (fw_major_version)
2492 *fw_major_version = le16_to_cpu(resp->fw_major);
2493 if (fw_minor_version)
2494 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2495 if (fw_build)
2496 *fw_build = le32_to_cpu(resp->fw_build);
2497 if (api_major_version)
2498 *api_major_version = le16_to_cpu(resp->api_major);
2499 if (api_minor_version)
2500 *api_minor_version = le16_to_cpu(resp->api_minor);
2501 }
2502
2503 return status;
2504 }
2505
2506 /**
2507 * i40e_aq_send_driver_version
2508 * @hw: pointer to the hw struct
2509 * @dv: driver's major, minor version
2510 * @cmd_details: pointer to command details structure or NULL
2511 *
2512 * Send the driver version to the firmware
2513 **/
2514 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2515 struct i40e_driver_version *dv,
2516 struct i40e_asq_cmd_details *cmd_details)
2517 {
2518 struct i40e_aq_desc desc;
2519 struct i40e_aqc_driver_version *cmd =
2520 (struct i40e_aqc_driver_version *)&desc.params.raw;
2521 i40e_status status;
2522 u16 len;
2523
2524 if (dv == NULL)
2525 return I40E_ERR_PARAM;
2526
2527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2528
2529 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2530 cmd->driver_major_ver = dv->major_version;
2531 cmd->driver_minor_ver = dv->minor_version;
2532 cmd->driver_build_ver = dv->build_version;
2533 cmd->driver_subbuild_ver = dv->subbuild_version;
2534
2535 len = 0;
2536 while (len < sizeof(dv->driver_string) &&
2537 (dv->driver_string[len] < 0x80) &&
2538 dv->driver_string[len])
2539 len++;
2540 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2541 len, cmd_details);
2542
2543 return status;
2544 }
2545
2546 /**
2547 * i40e_get_link_status - get status of the HW network link
2548 * @hw: pointer to the hw struct
2549 * @link_up: pointer to bool (true/false = linkup/linkdown)
2550 *
2551 * Variable link_up true if link is up, false if link is down.
2552 * The variable link_up is invalid if returned value of status != 0
2553 *
2554 * Side effect: LinkStatusEvent reporting becomes enabled
2555 **/
2556 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2557 {
2558 i40e_status status = 0;
2559
2560 if (hw->phy.get_link_info) {
2561 status = i40e_update_link_info(hw);
2562
2563 if (status)
2564 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2565 status);
2566 }
2567
2568 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2569
2570 return status;
2571 }
2572
2573 /**
2574 * i40e_updatelink_status - update status of the HW network link
2575 * @hw: pointer to the hw struct
2576 **/
2577 noinline_for_stack i40e_status i40e_update_link_info(struct i40e_hw *hw)
2578 {
2579 struct i40e_aq_get_phy_abilities_resp abilities;
2580 i40e_status status = 0;
2581
2582 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2583 if (status)
2584 return status;
2585
2586 /* extra checking needed to ensure link info to user is timely */
2587 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2588 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2589 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2590 status = i40e_aq_get_phy_capabilities(hw, false, false,
2591 &abilities, NULL);
2592 if (status)
2593 return status;
2594
2595 hw->phy.link_info.req_fec_info =
2596 abilities.fec_cfg_curr_mod_ext_info &
2597 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2598
2599 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2600 sizeof(hw->phy.link_info.module_type));
2601 }
2602
2603 return status;
2604 }
2605
2606 /**
2607 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2608 * @hw: pointer to the hw struct
2609 * @uplink_seid: the MAC or other gizmo SEID
2610 * @downlink_seid: the VSI SEID
2611 * @enabled_tc: bitmap of TCs to be enabled
2612 * @default_port: true for default port VSI, false for control port
2613 * @veb_seid: pointer to where to put the resulting VEB SEID
2614 * @enable_stats: true to turn on VEB stats
2615 * @cmd_details: pointer to command details structure or NULL
2616 *
2617 * This asks the FW to add a VEB between the uplink and downlink
2618 * elements. If the uplink SEID is 0, this will be a floating VEB.
2619 **/
2620 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2621 u16 downlink_seid, u8 enabled_tc,
2622 bool default_port, u16 *veb_seid,
2623 bool enable_stats,
2624 struct i40e_asq_cmd_details *cmd_details)
2625 {
2626 struct i40e_aq_desc desc;
2627 struct i40e_aqc_add_veb *cmd =
2628 (struct i40e_aqc_add_veb *)&desc.params.raw;
2629 struct i40e_aqc_add_veb_completion *resp =
2630 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2631 i40e_status status;
2632 u16 veb_flags = 0;
2633
2634 /* SEIDs need to either both be set or both be 0 for floating VEB */
2635 if (!!uplink_seid != !!downlink_seid)
2636 return I40E_ERR_PARAM;
2637
2638 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2639
2640 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2641 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2642 cmd->enable_tcs = enabled_tc;
2643 if (!uplink_seid)
2644 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2645 if (default_port)
2646 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2647 else
2648 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2649
2650 /* reverse logic here: set the bitflag to disable the stats */
2651 if (!enable_stats)
2652 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2653
2654 cmd->veb_flags = cpu_to_le16(veb_flags);
2655
2656 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2657
2658 if (!status && veb_seid)
2659 *veb_seid = le16_to_cpu(resp->veb_seid);
2660
2661 return status;
2662 }
2663
2664 /**
2665 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2666 * @hw: pointer to the hw struct
2667 * @veb_seid: the SEID of the VEB to query
2668 * @switch_id: the uplink switch id
2669 * @floating: set to true if the VEB is floating
2670 * @statistic_index: index of the stats counter block for this VEB
2671 * @vebs_used: number of VEB's used by function
2672 * @vebs_free: total VEB's not reserved by any function
2673 * @cmd_details: pointer to command details structure or NULL
2674 *
2675 * This retrieves the parameters for a particular VEB, specified by
2676 * uplink_seid, and returns them to the caller.
2677 **/
2678 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2679 u16 veb_seid, u16 *switch_id,
2680 bool *floating, u16 *statistic_index,
2681 u16 *vebs_used, u16 *vebs_free,
2682 struct i40e_asq_cmd_details *cmd_details)
2683 {
2684 struct i40e_aq_desc desc;
2685 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2686 (struct i40e_aqc_get_veb_parameters_completion *)
2687 &desc.params.raw;
2688 i40e_status status;
2689
2690 if (veb_seid == 0)
2691 return I40E_ERR_PARAM;
2692
2693 i40e_fill_default_direct_cmd_desc(&desc,
2694 i40e_aqc_opc_get_veb_parameters);
2695 cmd_resp->seid = cpu_to_le16(veb_seid);
2696
2697 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2698 if (status)
2699 goto get_veb_exit;
2700
2701 if (switch_id)
2702 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2703 if (statistic_index)
2704 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2705 if (vebs_used)
2706 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2707 if (vebs_free)
2708 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2709 if (floating) {
2710 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2711
2712 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2713 *floating = true;
2714 else
2715 *floating = false;
2716 }
2717
2718 get_veb_exit:
2719 return status;
2720 }
2721
2722 /**
2723 * i40e_aq_add_macvlan
2724 * @hw: pointer to the hw struct
2725 * @seid: VSI for the mac address
2726 * @mv_list: list of macvlans to be added
2727 * @count: length of the list
2728 * @cmd_details: pointer to command details structure or NULL
2729 *
2730 * Add MAC/VLAN addresses to the HW filtering
2731 **/
2732 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2733 struct i40e_aqc_add_macvlan_element_data *mv_list,
2734 u16 count, struct i40e_asq_cmd_details *cmd_details)
2735 {
2736 struct i40e_aq_desc desc;
2737 struct i40e_aqc_macvlan *cmd =
2738 (struct i40e_aqc_macvlan *)&desc.params.raw;
2739 i40e_status status;
2740 u16 buf_size;
2741 int i;
2742
2743 if (count == 0 || !mv_list || !hw)
2744 return I40E_ERR_PARAM;
2745
2746 buf_size = count * sizeof(*mv_list);
2747
2748 /* prep the rest of the request */
2749 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2750 cmd->num_addresses = cpu_to_le16(count);
2751 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2752 cmd->seid[1] = 0;
2753 cmd->seid[2] = 0;
2754
2755 for (i = 0; i < count; i++)
2756 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2757 mv_list[i].flags |=
2758 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2759
2760 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2761 if (buf_size > I40E_AQ_LARGE_BUF)
2762 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2763
2764 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2765 cmd_details);
2766
2767 return status;
2768 }
2769
2770 /**
2771 * i40e_aq_remove_macvlan
2772 * @hw: pointer to the hw struct
2773 * @seid: VSI for the mac address
2774 * @mv_list: list of macvlans to be removed
2775 * @count: length of the list
2776 * @cmd_details: pointer to command details structure or NULL
2777 *
2778 * Remove MAC/VLAN addresses from the HW filtering
2779 **/
2780 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2781 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2782 u16 count, struct i40e_asq_cmd_details *cmd_details)
2783 {
2784 struct i40e_aq_desc desc;
2785 struct i40e_aqc_macvlan *cmd =
2786 (struct i40e_aqc_macvlan *)&desc.params.raw;
2787 i40e_status status;
2788 u16 buf_size;
2789
2790 if (count == 0 || !mv_list || !hw)
2791 return I40E_ERR_PARAM;
2792
2793 buf_size = count * sizeof(*mv_list);
2794
2795 /* prep the rest of the request */
2796 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2797 cmd->num_addresses = cpu_to_le16(count);
2798 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2799 cmd->seid[1] = 0;
2800 cmd->seid[2] = 0;
2801
2802 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2803 if (buf_size > I40E_AQ_LARGE_BUF)
2804 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2805
2806 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2807 cmd_details);
2808
2809 return status;
2810 }
2811
2812 /**
2813 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2814 * @hw: pointer to the hw struct
2815 * @opcode: AQ opcode for add or delete mirror rule
2816 * @sw_seid: Switch SEID (to which rule refers)
2817 * @rule_type: Rule Type (ingress/egress/VLAN)
2818 * @id: Destination VSI SEID or Rule ID
2819 * @count: length of the list
2820 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2821 * @cmd_details: pointer to command details structure or NULL
2822 * @rule_id: Rule ID returned from FW
2823 * @rules_used: Number of rules used in internal switch
2824 * @rules_free: Number of rules free in internal switch
2825 *
2826 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2827 * VEBs/VEPA elements only
2828 **/
2829 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2830 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2831 u16 count, __le16 *mr_list,
2832 struct i40e_asq_cmd_details *cmd_details,
2833 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2834 {
2835 struct i40e_aq_desc desc;
2836 struct i40e_aqc_add_delete_mirror_rule *cmd =
2837 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2838 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2839 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2840 i40e_status status;
2841 u16 buf_size;
2842
2843 buf_size = count * sizeof(*mr_list);
2844
2845 /* prep the rest of the request */
2846 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2847 cmd->seid = cpu_to_le16(sw_seid);
2848 cmd->rule_type = cpu_to_le16(rule_type &
2849 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2850 cmd->num_entries = cpu_to_le16(count);
2851 /* Dest VSI for add, rule_id for delete */
2852 cmd->destination = cpu_to_le16(id);
2853 if (mr_list) {
2854 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2855 I40E_AQ_FLAG_RD));
2856 if (buf_size > I40E_AQ_LARGE_BUF)
2857 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2858 }
2859
2860 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2861 cmd_details);
2862 if (!status ||
2863 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2864 if (rule_id)
2865 *rule_id = le16_to_cpu(resp->rule_id);
2866 if (rules_used)
2867 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2868 if (rules_free)
2869 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2870 }
2871 return status;
2872 }
2873
2874 /**
2875 * i40e_aq_add_mirrorrule - add a mirror rule
2876 * @hw: pointer to the hw struct
2877 * @sw_seid: Switch SEID (to which rule refers)
2878 * @rule_type: Rule Type (ingress/egress/VLAN)
2879 * @dest_vsi: SEID of VSI to which packets will be mirrored
2880 * @count: length of the list
2881 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2882 * @cmd_details: pointer to command details structure or NULL
2883 * @rule_id: Rule ID returned from FW
2884 * @rules_used: Number of rules used in internal switch
2885 * @rules_free: Number of rules free in internal switch
2886 *
2887 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2888 **/
2889 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2890 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2891 struct i40e_asq_cmd_details *cmd_details,
2892 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2893 {
2894 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2895 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2896 if (count == 0 || !mr_list)
2897 return I40E_ERR_PARAM;
2898 }
2899
2900 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2901 rule_type, dest_vsi, count, mr_list,
2902 cmd_details, rule_id, rules_used, rules_free);
2903 }
2904
2905 /**
2906 * i40e_aq_delete_mirrorrule - delete a mirror rule
2907 * @hw: pointer to the hw struct
2908 * @sw_seid: Switch SEID (to which rule refers)
2909 * @rule_type: Rule Type (ingress/egress/VLAN)
2910 * @count: length of the list
2911 * @rule_id: Rule ID that is returned in the receive desc as part of
2912 * add_mirrorrule.
2913 * @mr_list: list of mirrored VLAN IDs to be removed
2914 * @cmd_details: pointer to command details structure or NULL
2915 * @rules_used: Number of rules used in internal switch
2916 * @rules_free: Number of rules free in internal switch
2917 *
2918 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2919 **/
2920 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2921 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2922 struct i40e_asq_cmd_details *cmd_details,
2923 u16 *rules_used, u16 *rules_free)
2924 {
2925 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2926 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2927 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2928 * mirroring. For other rule_type, count and rule_type should
2929 * not matter.
2930 */
2931 if (count == 0 || !mr_list)
2932 return I40E_ERR_PARAM;
2933 }
2934
2935 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2936 rule_type, rule_id, count, mr_list,
2937 cmd_details, NULL, rules_used, rules_free);
2938 }
2939
2940 /**
2941 * i40e_aq_send_msg_to_vf
2942 * @hw: pointer to the hardware structure
2943 * @vfid: VF id to send msg
2944 * @v_opcode: opcodes for VF-PF communication
2945 * @v_retval: return error code
2946 * @msg: pointer to the msg buffer
2947 * @msglen: msg length
2948 * @cmd_details: pointer to command details
2949 *
2950 * send msg to vf
2951 **/
2952 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2953 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2954 struct i40e_asq_cmd_details *cmd_details)
2955 {
2956 struct i40e_aq_desc desc;
2957 struct i40e_aqc_pf_vf_message *cmd =
2958 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2959 i40e_status status;
2960
2961 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2962 cmd->id = cpu_to_le32(vfid);
2963 desc.cookie_high = cpu_to_le32(v_opcode);
2964 desc.cookie_low = cpu_to_le32(v_retval);
2965 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2966 if (msglen) {
2967 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2968 I40E_AQ_FLAG_RD));
2969 if (msglen > I40E_AQ_LARGE_BUF)
2970 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2971 desc.datalen = cpu_to_le16(msglen);
2972 }
2973 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2974
2975 return status;
2976 }
2977
2978 /**
2979 * i40e_aq_debug_read_register
2980 * @hw: pointer to the hw struct
2981 * @reg_addr: register address
2982 * @reg_val: register value
2983 * @cmd_details: pointer to command details structure or NULL
2984 *
2985 * Read the register using the admin queue commands
2986 **/
2987 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2988 u32 reg_addr, u64 *reg_val,
2989 struct i40e_asq_cmd_details *cmd_details)
2990 {
2991 struct i40e_aq_desc desc;
2992 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2993 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2994 i40e_status status;
2995
2996 if (reg_val == NULL)
2997 return I40E_ERR_PARAM;
2998
2999 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3000
3001 cmd_resp->address = cpu_to_le32(reg_addr);
3002
3003 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3004
3005 if (!status) {
3006 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
3007 (u64)le32_to_cpu(cmd_resp->value_low);
3008 }
3009
3010 return status;
3011 }
3012
3013 /**
3014 * i40e_aq_debug_write_register
3015 * @hw: pointer to the hw struct
3016 * @reg_addr: register address
3017 * @reg_val: register value
3018 * @cmd_details: pointer to command details structure or NULL
3019 *
3020 * Write to a register using the admin queue commands
3021 **/
3022 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
3023 u32 reg_addr, u64 reg_val,
3024 struct i40e_asq_cmd_details *cmd_details)
3025 {
3026 struct i40e_aq_desc desc;
3027 struct i40e_aqc_debug_reg_read_write *cmd =
3028 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3029 i40e_status status;
3030
3031 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3032
3033 cmd->address = cpu_to_le32(reg_addr);
3034 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
3035 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
3036
3037 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3038
3039 return status;
3040 }
3041
3042 /**
3043 * i40e_aq_request_resource
3044 * @hw: pointer to the hw struct
3045 * @resource: resource id
3046 * @access: access type
3047 * @sdp_number: resource number
3048 * @timeout: the maximum time in ms that the driver may hold the resource
3049 * @cmd_details: pointer to command details structure or NULL
3050 *
3051 * requests common resource using the admin queue commands
3052 **/
3053 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
3054 enum i40e_aq_resources_ids resource,
3055 enum i40e_aq_resource_access_type access,
3056 u8 sdp_number, u64 *timeout,
3057 struct i40e_asq_cmd_details *cmd_details)
3058 {
3059 struct i40e_aq_desc desc;
3060 struct i40e_aqc_request_resource *cmd_resp =
3061 (struct i40e_aqc_request_resource *)&desc.params.raw;
3062 i40e_status status;
3063
3064 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3065
3066 cmd_resp->resource_id = cpu_to_le16(resource);
3067 cmd_resp->access_type = cpu_to_le16(access);
3068 cmd_resp->resource_number = cpu_to_le32(sdp_number);
3069
3070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3071 /* The completion specifies the maximum time in ms that the driver
3072 * may hold the resource in the Timeout field.
3073 * If the resource is held by someone else, the command completes with
3074 * busy return value and the timeout field indicates the maximum time
3075 * the current owner of the resource has to free it.
3076 */
3077 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3078 *timeout = le32_to_cpu(cmd_resp->timeout);
3079
3080 return status;
3081 }
3082
3083 /**
3084 * i40e_aq_release_resource
3085 * @hw: pointer to the hw struct
3086 * @resource: resource id
3087 * @sdp_number: resource number
3088 * @cmd_details: pointer to command details structure or NULL
3089 *
3090 * release common resource using the admin queue commands
3091 **/
3092 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3093 enum i40e_aq_resources_ids resource,
3094 u8 sdp_number,
3095 struct i40e_asq_cmd_details *cmd_details)
3096 {
3097 struct i40e_aq_desc desc;
3098 struct i40e_aqc_request_resource *cmd =
3099 (struct i40e_aqc_request_resource *)&desc.params.raw;
3100 i40e_status status;
3101
3102 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3103
3104 cmd->resource_id = cpu_to_le16(resource);
3105 cmd->resource_number = cpu_to_le32(sdp_number);
3106
3107 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3108
3109 return status;
3110 }
3111
3112 /**
3113 * i40e_aq_read_nvm
3114 * @hw: pointer to the hw struct
3115 * @module_pointer: module pointer location in words from the NVM beginning
3116 * @offset: byte offset from the module beginning
3117 * @length: length of the section to be read (in bytes from the offset)
3118 * @data: command buffer (size [bytes] = length)
3119 * @last_command: tells if this is the last command in a series
3120 * @cmd_details: pointer to command details structure or NULL
3121 *
3122 * Read the NVM using the admin queue commands
3123 **/
3124 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3125 u32 offset, u16 length, void *data,
3126 bool last_command,
3127 struct i40e_asq_cmd_details *cmd_details)
3128 {
3129 struct i40e_aq_desc desc;
3130 struct i40e_aqc_nvm_update *cmd =
3131 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3132 i40e_status status;
3133
3134 /* In offset the highest byte must be zeroed. */
3135 if (offset & 0xFF000000) {
3136 status = I40E_ERR_PARAM;
3137 goto i40e_aq_read_nvm_exit;
3138 }
3139
3140 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3141
3142 /* If this is the last command in a series, set the proper flag. */
3143 if (last_command)
3144 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3145 cmd->module_pointer = module_pointer;
3146 cmd->offset = cpu_to_le32(offset);
3147 cmd->length = cpu_to_le16(length);
3148
3149 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3150 if (length > I40E_AQ_LARGE_BUF)
3151 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3152
3153 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3154
3155 i40e_aq_read_nvm_exit:
3156 return status;
3157 }
3158
3159 /**
3160 * i40e_aq_erase_nvm
3161 * @hw: pointer to the hw struct
3162 * @module_pointer: module pointer location in words from the NVM beginning
3163 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3164 * @length: length of the section to be erased (expressed in 4 KB)
3165 * @last_command: tells if this is the last command in a series
3166 * @cmd_details: pointer to command details structure or NULL
3167 *
3168 * Erase the NVM sector using the admin queue commands
3169 **/
3170 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3171 u32 offset, u16 length, bool last_command,
3172 struct i40e_asq_cmd_details *cmd_details)
3173 {
3174 struct i40e_aq_desc desc;
3175 struct i40e_aqc_nvm_update *cmd =
3176 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3177 i40e_status status;
3178
3179 /* In offset the highest byte must be zeroed. */
3180 if (offset & 0xFF000000) {
3181 status = I40E_ERR_PARAM;
3182 goto i40e_aq_erase_nvm_exit;
3183 }
3184
3185 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3186
3187 /* If this is the last command in a series, set the proper flag. */
3188 if (last_command)
3189 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3190 cmd->module_pointer = module_pointer;
3191 cmd->offset = cpu_to_le32(offset);
3192 cmd->length = cpu_to_le16(length);
3193
3194 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3195
3196 i40e_aq_erase_nvm_exit:
3197 return status;
3198 }
3199
3200 /**
3201 * i40e_parse_discover_capabilities
3202 * @hw: pointer to the hw struct
3203 * @buff: pointer to a buffer containing device/function capability records
3204 * @cap_count: number of capability records in the list
3205 * @list_type_opc: type of capabilities list to parse
3206 *
3207 * Parse the device/function capabilities list.
3208 **/
3209 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3210 u32 cap_count,
3211 enum i40e_admin_queue_opc list_type_opc)
3212 {
3213 struct i40e_aqc_list_capabilities_element_resp *cap;
3214 u32 valid_functions, num_functions;
3215 u32 number, logical_id, phys_id;
3216 struct i40e_hw_capabilities *p;
3217 u16 id, ocp_cfg_word0;
3218 i40e_status status;
3219 u8 major_rev;
3220 u32 i = 0;
3221
3222 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3223
3224 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3225 p = &hw->dev_caps;
3226 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3227 p = &hw->func_caps;
3228 else
3229 return;
3230
3231 for (i = 0; i < cap_count; i++, cap++) {
3232 id = le16_to_cpu(cap->id);
3233 number = le32_to_cpu(cap->number);
3234 logical_id = le32_to_cpu(cap->logical_id);
3235 phys_id = le32_to_cpu(cap->phys_id);
3236 major_rev = cap->major_rev;
3237
3238 switch (id) {
3239 case I40E_AQ_CAP_ID_SWITCH_MODE:
3240 p->switch_mode = number;
3241 break;
3242 case I40E_AQ_CAP_ID_MNG_MODE:
3243 p->management_mode = number;
3244 if (major_rev > 1) {
3245 p->mng_protocols_over_mctp = logical_id;
3246 i40e_debug(hw, I40E_DEBUG_INIT,
3247 "HW Capability: Protocols over MCTP = %d\n",
3248 p->mng_protocols_over_mctp);
3249 } else {
3250 p->mng_protocols_over_mctp = 0;
3251 }
3252 break;
3253 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3254 p->npar_enable = number;
3255 break;
3256 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3257 p->os2bmc = number;
3258 break;
3259 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3260 p->valid_functions = number;
3261 break;
3262 case I40E_AQ_CAP_ID_SRIOV:
3263 if (number == 1)
3264 p->sr_iov_1_1 = true;
3265 break;
3266 case I40E_AQ_CAP_ID_VF:
3267 p->num_vfs = number;
3268 p->vf_base_id = logical_id;
3269 break;
3270 case I40E_AQ_CAP_ID_VMDQ:
3271 if (number == 1)
3272 p->vmdq = true;
3273 break;
3274 case I40E_AQ_CAP_ID_8021QBG:
3275 if (number == 1)
3276 p->evb_802_1_qbg = true;
3277 break;
3278 case I40E_AQ_CAP_ID_8021QBR:
3279 if (number == 1)
3280 p->evb_802_1_qbh = true;
3281 break;
3282 case I40E_AQ_CAP_ID_VSI:
3283 p->num_vsis = number;
3284 break;
3285 case I40E_AQ_CAP_ID_DCB:
3286 if (number == 1) {
3287 p->dcb = true;
3288 p->enabled_tcmap = logical_id;
3289 p->maxtc = phys_id;
3290 }
3291 break;
3292 case I40E_AQ_CAP_ID_FCOE:
3293 if (number == 1)
3294 p->fcoe = true;
3295 break;
3296 case I40E_AQ_CAP_ID_ISCSI:
3297 if (number == 1)
3298 p->iscsi = true;
3299 break;
3300 case I40E_AQ_CAP_ID_RSS:
3301 p->rss = true;
3302 p->rss_table_size = number;
3303 p->rss_table_entry_width = logical_id;
3304 break;
3305 case I40E_AQ_CAP_ID_RXQ:
3306 p->num_rx_qp = number;
3307 p->base_queue = phys_id;
3308 break;
3309 case I40E_AQ_CAP_ID_TXQ:
3310 p->num_tx_qp = number;
3311 p->base_queue = phys_id;
3312 break;
3313 case I40E_AQ_CAP_ID_MSIX:
3314 p->num_msix_vectors = number;
3315 i40e_debug(hw, I40E_DEBUG_INIT,
3316 "HW Capability: MSIX vector count = %d\n",
3317 p->num_msix_vectors);
3318 break;
3319 case I40E_AQ_CAP_ID_VF_MSIX:
3320 p->num_msix_vectors_vf = number;
3321 break;
3322 case I40E_AQ_CAP_ID_FLEX10:
3323 if (major_rev == 1) {
3324 if (number == 1) {
3325 p->flex10_enable = true;
3326 p->flex10_capable = true;
3327 }
3328 } else {
3329 /* Capability revision >= 2 */
3330 if (number & 1)
3331 p->flex10_enable = true;
3332 if (number & 2)
3333 p->flex10_capable = true;
3334 }
3335 p->flex10_mode = logical_id;
3336 p->flex10_status = phys_id;
3337 break;
3338 case I40E_AQ_CAP_ID_CEM:
3339 if (number == 1)
3340 p->mgmt_cem = true;
3341 break;
3342 case I40E_AQ_CAP_ID_IWARP:
3343 if (number == 1)
3344 p->iwarp = true;
3345 break;
3346 case I40E_AQ_CAP_ID_LED:
3347 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3348 p->led[phys_id] = true;
3349 break;
3350 case I40E_AQ_CAP_ID_SDP:
3351 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3352 p->sdp[phys_id] = true;
3353 break;
3354 case I40E_AQ_CAP_ID_MDIO:
3355 if (number == 1) {
3356 p->mdio_port_num = phys_id;
3357 p->mdio_port_mode = logical_id;
3358 }
3359 break;
3360 case I40E_AQ_CAP_ID_1588:
3361 if (number == 1)
3362 p->ieee_1588 = true;
3363 break;
3364 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3365 p->fd = true;
3366 p->fd_filters_guaranteed = number;
3367 p->fd_filters_best_effort = logical_id;
3368 break;
3369 case I40E_AQ_CAP_ID_WSR_PROT:
3370 p->wr_csr_prot = (u64)number;
3371 p->wr_csr_prot |= (u64)logical_id << 32;
3372 break;
3373 case I40E_AQ_CAP_ID_NVM_MGMT:
3374 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3375 p->sec_rev_disabled = true;
3376 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3377 p->update_disabled = true;
3378 break;
3379 default:
3380 break;
3381 }
3382 }
3383
3384 if (p->fcoe)
3385 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3386
3387 /* Software override ensuring FCoE is disabled if npar or mfp
3388 * mode because it is not supported in these modes.
3389 */
3390 if (p->npar_enable || p->flex10_enable)
3391 p->fcoe = false;
3392
3393 /* count the enabled ports (aka the "not disabled" ports) */
3394 hw->num_ports = 0;
3395 for (i = 0; i < 4; i++) {
3396 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3397 u64 port_cfg = 0;
3398
3399 /* use AQ read to get the physical register offset instead
3400 * of the port relative offset
3401 */
3402 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3403 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3404 hw->num_ports++;
3405 }
3406
3407 /* OCP cards case: if a mezz is removed the Ethernet port is at
3408 * disabled state in PRTGEN_CNF register. Additional NVM read is
3409 * needed in order to check if we are dealing with OCP card.
3410 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3411 * physical ports results in wrong partition id calculation and thus
3412 * not supporting WoL.
3413 */
3414 if (hw->mac.type == I40E_MAC_X722) {
3415 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3416 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3417 2 * I40E_SR_OCP_CFG_WORD0,
3418 sizeof(ocp_cfg_word0),
3419 &ocp_cfg_word0, true, NULL);
3420 if (!status &&
3421 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3422 hw->num_ports = 4;
3423 i40e_release_nvm(hw);
3424 }
3425 }
3426
3427 valid_functions = p->valid_functions;
3428 num_functions = 0;
3429 while (valid_functions) {
3430 if (valid_functions & 1)
3431 num_functions++;
3432 valid_functions >>= 1;
3433 }
3434
3435 /* partition id is 1-based, and functions are evenly spread
3436 * across the ports as partitions
3437 */
3438 if (hw->num_ports != 0) {
3439 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3440 hw->num_partitions = num_functions / hw->num_ports;
3441 }
3442
3443 /* additional HW specific goodies that might
3444 * someday be HW version specific
3445 */
3446 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3447 }
3448
3449 /**
3450 * i40e_aq_discover_capabilities
3451 * @hw: pointer to the hw struct
3452 * @buff: a virtual buffer to hold the capabilities
3453 * @buff_size: Size of the virtual buffer
3454 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3455 * @list_type_opc: capabilities type to discover - pass in the command opcode
3456 * @cmd_details: pointer to command details structure or NULL
3457 *
3458 * Get the device capabilities descriptions from the firmware
3459 **/
3460 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3461 void *buff, u16 buff_size, u16 *data_size,
3462 enum i40e_admin_queue_opc list_type_opc,
3463 struct i40e_asq_cmd_details *cmd_details)
3464 {
3465 struct i40e_aqc_list_capabilites *cmd;
3466 struct i40e_aq_desc desc;
3467 i40e_status status = 0;
3468
3469 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3470
3471 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3472 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3473 status = I40E_ERR_PARAM;
3474 goto exit;
3475 }
3476
3477 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3478
3479 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3480 if (buff_size > I40E_AQ_LARGE_BUF)
3481 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3482
3483 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3484 *data_size = le16_to_cpu(desc.datalen);
3485
3486 if (status)
3487 goto exit;
3488
3489 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3490 list_type_opc);
3491
3492 exit:
3493 return status;
3494 }
3495
3496 /**
3497 * i40e_aq_update_nvm
3498 * @hw: pointer to the hw struct
3499 * @module_pointer: module pointer location in words from the NVM beginning
3500 * @offset: byte offset from the module beginning
3501 * @length: length of the section to be written (in bytes from the offset)
3502 * @data: command buffer (size [bytes] = length)
3503 * @last_command: tells if this is the last command in a series
3504 * @preservation_flags: Preservation mode flags
3505 * @cmd_details: pointer to command details structure or NULL
3506 *
3507 * Update the NVM using the admin queue commands
3508 **/
3509 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3510 u32 offset, u16 length, void *data,
3511 bool last_command, u8 preservation_flags,
3512 struct i40e_asq_cmd_details *cmd_details)
3513 {
3514 struct i40e_aq_desc desc;
3515 struct i40e_aqc_nvm_update *cmd =
3516 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3517 i40e_status status;
3518
3519 /* In offset the highest byte must be zeroed. */
3520 if (offset & 0xFF000000) {
3521 status = I40E_ERR_PARAM;
3522 goto i40e_aq_update_nvm_exit;
3523 }
3524
3525 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3526
3527 /* If this is the last command in a series, set the proper flag. */
3528 if (last_command)
3529 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3530 if (hw->mac.type == I40E_MAC_X722) {
3531 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3532 cmd->command_flags |=
3533 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3534 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3535 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3536 cmd->command_flags |=
3537 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3538 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3539 }
3540 cmd->module_pointer = module_pointer;
3541 cmd->offset = cpu_to_le32(offset);
3542 cmd->length = cpu_to_le16(length);
3543
3544 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3545 if (length > I40E_AQ_LARGE_BUF)
3546 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3547
3548 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3549
3550 i40e_aq_update_nvm_exit:
3551 return status;
3552 }
3553
3554 /**
3555 * i40e_aq_rearrange_nvm
3556 * @hw: pointer to the hw struct
3557 * @rearrange_nvm: defines direction of rearrangement
3558 * @cmd_details: pointer to command details structure or NULL
3559 *
3560 * Rearrange NVM structure, available only for transition FW
3561 **/
3562 i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3563 u8 rearrange_nvm,
3564 struct i40e_asq_cmd_details *cmd_details)
3565 {
3566 struct i40e_aqc_nvm_update *cmd;
3567 i40e_status status;
3568 struct i40e_aq_desc desc;
3569
3570 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3571
3572 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3573
3574 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3575 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3576
3577 if (!rearrange_nvm) {
3578 status = I40E_ERR_PARAM;
3579 goto i40e_aq_rearrange_nvm_exit;
3580 }
3581
3582 cmd->command_flags |= rearrange_nvm;
3583 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3584
3585 i40e_aq_rearrange_nvm_exit:
3586 return status;
3587 }
3588
3589 /**
3590 * i40e_aq_get_lldp_mib
3591 * @hw: pointer to the hw struct
3592 * @bridge_type: type of bridge requested
3593 * @mib_type: Local, Remote or both Local and Remote MIBs
3594 * @buff: pointer to a user supplied buffer to store the MIB block
3595 * @buff_size: size of the buffer (in bytes)
3596 * @local_len : length of the returned Local LLDP MIB
3597 * @remote_len: length of the returned Remote LLDP MIB
3598 * @cmd_details: pointer to command details structure or NULL
3599 *
3600 * Requests the complete LLDP MIB (entire packet).
3601 **/
3602 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3603 u8 mib_type, void *buff, u16 buff_size,
3604 u16 *local_len, u16 *remote_len,
3605 struct i40e_asq_cmd_details *cmd_details)
3606 {
3607 struct i40e_aq_desc desc;
3608 struct i40e_aqc_lldp_get_mib *cmd =
3609 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3610 struct i40e_aqc_lldp_get_mib *resp =
3611 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3612 i40e_status status;
3613
3614 if (buff_size == 0 || !buff)
3615 return I40E_ERR_PARAM;
3616
3617 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3618 /* Indirect Command */
3619 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3620
3621 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3622 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3623 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3624
3625 desc.datalen = cpu_to_le16(buff_size);
3626
3627 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3628 if (buff_size > I40E_AQ_LARGE_BUF)
3629 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3630
3631 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3632 if (!status) {
3633 if (local_len != NULL)
3634 *local_len = le16_to_cpu(resp->local_len);
3635 if (remote_len != NULL)
3636 *remote_len = le16_to_cpu(resp->remote_len);
3637 }
3638
3639 return status;
3640 }
3641
3642 /**
3643 * i40e_aq_cfg_lldp_mib_change_event
3644 * @hw: pointer to the hw struct
3645 * @enable_update: Enable or Disable event posting
3646 * @cmd_details: pointer to command details structure or NULL
3647 *
3648 * Enable or Disable posting of an event on ARQ when LLDP MIB
3649 * associated with the interface changes
3650 **/
3651 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3652 bool enable_update,
3653 struct i40e_asq_cmd_details *cmd_details)
3654 {
3655 struct i40e_aq_desc desc;
3656 struct i40e_aqc_lldp_update_mib *cmd =
3657 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3658 i40e_status status;
3659
3660 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3661
3662 if (!enable_update)
3663 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3664
3665 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3666
3667 return status;
3668 }
3669
3670 /**
3671 * i40e_aq_stop_lldp
3672 * @hw: pointer to the hw struct
3673 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3674 * @cmd_details: pointer to command details structure or NULL
3675 *
3676 * Stop or Shutdown the embedded LLDP Agent
3677 **/
3678 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3679 struct i40e_asq_cmd_details *cmd_details)
3680 {
3681 struct i40e_aq_desc desc;
3682 struct i40e_aqc_lldp_stop *cmd =
3683 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3684 i40e_status status;
3685
3686 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3687
3688 if (shutdown_agent)
3689 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3690
3691 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3692
3693 return status;
3694 }
3695
3696 /**
3697 * i40e_aq_start_lldp
3698 * @hw: pointer to the hw struct
3699 * @buff: buffer for result
3700 * @buff_size: buffer size
3701 * @cmd_details: pointer to command details structure or NULL
3702 *
3703 * Start the embedded LLDP Agent on all ports.
3704 **/
3705 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3706 struct i40e_asq_cmd_details *cmd_details)
3707 {
3708 struct i40e_aq_desc desc;
3709 struct i40e_aqc_lldp_start *cmd =
3710 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3711 i40e_status status;
3712
3713 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3714
3715 cmd->command = I40E_AQ_LLDP_AGENT_START;
3716 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3717
3718 return status;
3719 }
3720
3721 /**
3722 * i40e_aq_set_dcb_parameters
3723 * @hw: pointer to the hw struct
3724 * @cmd_details: pointer to command details structure or NULL
3725 * @dcb_enable: True if DCB configuration needs to be applied
3726 *
3727 **/
3728 enum i40e_status_code
3729 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3730 struct i40e_asq_cmd_details *cmd_details)
3731 {
3732 struct i40e_aq_desc desc;
3733 struct i40e_aqc_set_dcb_parameters *cmd =
3734 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3735 i40e_status status;
3736
3737 i40e_fill_default_direct_cmd_desc(&desc,
3738 i40e_aqc_opc_set_dcb_parameters);
3739
3740 if (dcb_enable) {
3741 cmd->valid_flags = I40E_DCB_VALID;
3742 cmd->command = I40E_AQ_DCB_SET_AGENT;
3743 }
3744 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3745
3746 return status;
3747 }
3748
3749 /**
3750 * i40e_aq_get_cee_dcb_config
3751 * @hw: pointer to the hw struct
3752 * @buff: response buffer that stores CEE operational configuration
3753 * @buff_size: size of the buffer passed
3754 * @cmd_details: pointer to command details structure or NULL
3755 *
3756 * Get CEE DCBX mode operational configuration from firmware
3757 **/
3758 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3759 void *buff, u16 buff_size,
3760 struct i40e_asq_cmd_details *cmd_details)
3761 {
3762 struct i40e_aq_desc desc;
3763 i40e_status status;
3764
3765 if (buff_size == 0 || !buff)
3766 return I40E_ERR_PARAM;
3767
3768 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3769
3770 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3771 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3772 cmd_details);
3773
3774 return status;
3775 }
3776
3777 /**
3778 * i40e_aq_add_udp_tunnel
3779 * @hw: pointer to the hw struct
3780 * @udp_port: the UDP port to add in Host byte order
3781 * @protocol_index: protocol index type
3782 * @filter_index: pointer to filter index
3783 * @cmd_details: pointer to command details structure or NULL
3784 *
3785 * Note: Firmware expects the udp_port value to be in Little Endian format,
3786 * and this function will call cpu_to_le16 to convert from Host byte order to
3787 * Little Endian order.
3788 **/
3789 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3790 u16 udp_port, u8 protocol_index,
3791 u8 *filter_index,
3792 struct i40e_asq_cmd_details *cmd_details)
3793 {
3794 struct i40e_aq_desc desc;
3795 struct i40e_aqc_add_udp_tunnel *cmd =
3796 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3797 struct i40e_aqc_del_udp_tunnel_completion *resp =
3798 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3799 i40e_status status;
3800
3801 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3802
3803 cmd->udp_port = cpu_to_le16(udp_port);
3804 cmd->protocol_type = protocol_index;
3805
3806 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3807
3808 if (!status && filter_index)
3809 *filter_index = resp->index;
3810
3811 return status;
3812 }
3813
3814 /**
3815 * i40e_aq_del_udp_tunnel
3816 * @hw: pointer to the hw struct
3817 * @index: filter index
3818 * @cmd_details: pointer to command details structure or NULL
3819 **/
3820 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3821 struct i40e_asq_cmd_details *cmd_details)
3822 {
3823 struct i40e_aq_desc desc;
3824 struct i40e_aqc_remove_udp_tunnel *cmd =
3825 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3826 i40e_status status;
3827
3828 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3829
3830 cmd->index = index;
3831
3832 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3833
3834 return status;
3835 }
3836
3837 /**
3838 * i40e_aq_delete_element - Delete switch element
3839 * @hw: pointer to the hw struct
3840 * @seid: the SEID to delete from the switch
3841 * @cmd_details: pointer to command details structure or NULL
3842 *
3843 * This deletes a switch element from the switch.
3844 **/
3845 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3846 struct i40e_asq_cmd_details *cmd_details)
3847 {
3848 struct i40e_aq_desc desc;
3849 struct i40e_aqc_switch_seid *cmd =
3850 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3851 i40e_status status;
3852
3853 if (seid == 0)
3854 return I40E_ERR_PARAM;
3855
3856 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3857
3858 cmd->seid = cpu_to_le16(seid);
3859
3860 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3861
3862 return status;
3863 }
3864
3865 /**
3866 * i40e_aq_dcb_updated - DCB Updated Command
3867 * @hw: pointer to the hw struct
3868 * @cmd_details: pointer to command details structure or NULL
3869 *
3870 * EMP will return when the shared RPB settings have been
3871 * recomputed and modified. The retval field in the descriptor
3872 * will be set to 0 when RPB is modified.
3873 **/
3874 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3875 struct i40e_asq_cmd_details *cmd_details)
3876 {
3877 struct i40e_aq_desc desc;
3878 i40e_status status;
3879
3880 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3881
3882 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3883
3884 return status;
3885 }
3886
3887 /**
3888 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3889 * @hw: pointer to the hw struct
3890 * @seid: seid for the physical port/switching component/vsi
3891 * @buff: Indirect buffer to hold data parameters and response
3892 * @buff_size: Indirect buffer size
3893 * @opcode: Tx scheduler AQ command opcode
3894 * @cmd_details: pointer to command details structure or NULL
3895 *
3896 * Generic command handler for Tx scheduler AQ commands
3897 **/
3898 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3899 void *buff, u16 buff_size,
3900 enum i40e_admin_queue_opc opcode,
3901 struct i40e_asq_cmd_details *cmd_details)
3902 {
3903 struct i40e_aq_desc desc;
3904 struct i40e_aqc_tx_sched_ind *cmd =
3905 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3906 i40e_status status;
3907 bool cmd_param_flag = false;
3908
3909 switch (opcode) {
3910 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3911 case i40e_aqc_opc_configure_vsi_tc_bw:
3912 case i40e_aqc_opc_enable_switching_comp_ets:
3913 case i40e_aqc_opc_modify_switching_comp_ets:
3914 case i40e_aqc_opc_disable_switching_comp_ets:
3915 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3916 case i40e_aqc_opc_configure_switching_comp_bw_config:
3917 cmd_param_flag = true;
3918 break;
3919 case i40e_aqc_opc_query_vsi_bw_config:
3920 case i40e_aqc_opc_query_vsi_ets_sla_config:
3921 case i40e_aqc_opc_query_switching_comp_ets_config:
3922 case i40e_aqc_opc_query_port_ets_config:
3923 case i40e_aqc_opc_query_switching_comp_bw_config:
3924 cmd_param_flag = false;
3925 break;
3926 default:
3927 return I40E_ERR_PARAM;
3928 }
3929
3930 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3931
3932 /* Indirect command */
3933 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3934 if (cmd_param_flag)
3935 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3936 if (buff_size > I40E_AQ_LARGE_BUF)
3937 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3938
3939 desc.datalen = cpu_to_le16(buff_size);
3940
3941 cmd->vsi_seid = cpu_to_le16(seid);
3942
3943 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3944
3945 return status;
3946 }
3947
3948 /**
3949 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3950 * @hw: pointer to the hw struct
3951 * @seid: VSI seid
3952 * @credit: BW limit credits (0 = disabled)
3953 * @max_credit: Max BW limit credits
3954 * @cmd_details: pointer to command details structure or NULL
3955 **/
3956 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3957 u16 seid, u16 credit, u8 max_credit,
3958 struct i40e_asq_cmd_details *cmd_details)
3959 {
3960 struct i40e_aq_desc desc;
3961 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3962 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3963 i40e_status status;
3964
3965 i40e_fill_default_direct_cmd_desc(&desc,
3966 i40e_aqc_opc_configure_vsi_bw_limit);
3967
3968 cmd->vsi_seid = cpu_to_le16(seid);
3969 cmd->credit = cpu_to_le16(credit);
3970 cmd->max_credit = max_credit;
3971
3972 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3973
3974 return status;
3975 }
3976
3977 /**
3978 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3979 * @hw: pointer to the hw struct
3980 * @seid: VSI seid
3981 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3982 * @cmd_details: pointer to command details structure or NULL
3983 **/
3984 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3985 u16 seid,
3986 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3987 struct i40e_asq_cmd_details *cmd_details)
3988 {
3989 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3990 i40e_aqc_opc_configure_vsi_tc_bw,
3991 cmd_details);
3992 }
3993
3994 /**
3995 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3996 * @hw: pointer to the hw struct
3997 * @seid: seid of the switching component connected to Physical Port
3998 * @ets_data: Buffer holding ETS parameters
3999 * @opcode: Tx scheduler AQ command opcode
4000 * @cmd_details: pointer to command details structure or NULL
4001 **/
4002 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4003 u16 seid,
4004 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4005 enum i40e_admin_queue_opc opcode,
4006 struct i40e_asq_cmd_details *cmd_details)
4007 {
4008 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4009 sizeof(*ets_data), opcode, cmd_details);
4010 }
4011
4012 /**
4013 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4014 * @hw: pointer to the hw struct
4015 * @seid: seid of the switching component
4016 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4017 * @cmd_details: pointer to command details structure or NULL
4018 **/
4019 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4020 u16 seid,
4021 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4022 struct i40e_asq_cmd_details *cmd_details)
4023 {
4024 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4025 i40e_aqc_opc_configure_switching_comp_bw_config,
4026 cmd_details);
4027 }
4028
4029 /**
4030 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4031 * @hw: pointer to the hw struct
4032 * @seid: seid of the VSI
4033 * @bw_data: Buffer to hold VSI BW configuration
4034 * @cmd_details: pointer to command details structure or NULL
4035 **/
4036 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4037 u16 seid,
4038 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4039 struct i40e_asq_cmd_details *cmd_details)
4040 {
4041 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4042 i40e_aqc_opc_query_vsi_bw_config,
4043 cmd_details);
4044 }
4045
4046 /**
4047 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4048 * @hw: pointer to the hw struct
4049 * @seid: seid of the VSI
4050 * @bw_data: Buffer to hold VSI BW configuration per TC
4051 * @cmd_details: pointer to command details structure or NULL
4052 **/
4053 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4054 u16 seid,
4055 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4056 struct i40e_asq_cmd_details *cmd_details)
4057 {
4058 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4059 i40e_aqc_opc_query_vsi_ets_sla_config,
4060 cmd_details);
4061 }
4062
4063 /**
4064 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4065 * @hw: pointer to the hw struct
4066 * @seid: seid of the switching component
4067 * @bw_data: Buffer to hold switching component's per TC BW config
4068 * @cmd_details: pointer to command details structure or NULL
4069 **/
4070 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4071 u16 seid,
4072 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4073 struct i40e_asq_cmd_details *cmd_details)
4074 {
4075 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4076 i40e_aqc_opc_query_switching_comp_ets_config,
4077 cmd_details);
4078 }
4079
4080 /**
4081 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4082 * @hw: pointer to the hw struct
4083 * @seid: seid of the VSI or switching component connected to Physical Port
4084 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4085 * @cmd_details: pointer to command details structure or NULL
4086 **/
4087 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4088 u16 seid,
4089 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4090 struct i40e_asq_cmd_details *cmd_details)
4091 {
4092 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4093 i40e_aqc_opc_query_port_ets_config,
4094 cmd_details);
4095 }
4096
4097 /**
4098 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4099 * @hw: pointer to the hw struct
4100 * @seid: seid of the switching component
4101 * @bw_data: Buffer to hold switching component's BW configuration
4102 * @cmd_details: pointer to command details structure or NULL
4103 **/
4104 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4105 u16 seid,
4106 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4107 struct i40e_asq_cmd_details *cmd_details)
4108 {
4109 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4110 i40e_aqc_opc_query_switching_comp_bw_config,
4111 cmd_details);
4112 }
4113
4114 /**
4115 * i40e_validate_filter_settings
4116 * @hw: pointer to the hardware structure
4117 * @settings: Filter control settings
4118 *
4119 * Check and validate the filter control settings passed.
4120 * The function checks for the valid filter/context sizes being
4121 * passed for FCoE and PE.
4122 *
4123 * Returns 0 if the values passed are valid and within
4124 * range else returns an error.
4125 **/
4126 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
4127 struct i40e_filter_control_settings *settings)
4128 {
4129 u32 fcoe_cntx_size, fcoe_filt_size;
4130 u32 pe_cntx_size, pe_filt_size;
4131 u32 fcoe_fmax;
4132 u32 val;
4133
4134 /* Validate FCoE settings passed */
4135 switch (settings->fcoe_filt_num) {
4136 case I40E_HASH_FILTER_SIZE_1K:
4137 case I40E_HASH_FILTER_SIZE_2K:
4138 case I40E_HASH_FILTER_SIZE_4K:
4139 case I40E_HASH_FILTER_SIZE_8K:
4140 case I40E_HASH_FILTER_SIZE_16K:
4141 case I40E_HASH_FILTER_SIZE_32K:
4142 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4143 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4144 break;
4145 default:
4146 return I40E_ERR_PARAM;
4147 }
4148
4149 switch (settings->fcoe_cntx_num) {
4150 case I40E_DMA_CNTX_SIZE_512:
4151 case I40E_DMA_CNTX_SIZE_1K:
4152 case I40E_DMA_CNTX_SIZE_2K:
4153 case I40E_DMA_CNTX_SIZE_4K:
4154 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4155 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4156 break;
4157 default:
4158 return I40E_ERR_PARAM;
4159 }
4160
4161 /* Validate PE settings passed */
4162 switch (settings->pe_filt_num) {
4163 case I40E_HASH_FILTER_SIZE_1K:
4164 case I40E_HASH_FILTER_SIZE_2K:
4165 case I40E_HASH_FILTER_SIZE_4K:
4166 case I40E_HASH_FILTER_SIZE_8K:
4167 case I40E_HASH_FILTER_SIZE_16K:
4168 case I40E_HASH_FILTER_SIZE_32K:
4169 case I40E_HASH_FILTER_SIZE_64K:
4170 case I40E_HASH_FILTER_SIZE_128K:
4171 case I40E_HASH_FILTER_SIZE_256K:
4172 case I40E_HASH_FILTER_SIZE_512K:
4173 case I40E_HASH_FILTER_SIZE_1M:
4174 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4175 pe_filt_size <<= (u32)settings->pe_filt_num;
4176 break;
4177 default:
4178 return I40E_ERR_PARAM;
4179 }
4180
4181 switch (settings->pe_cntx_num) {
4182 case I40E_DMA_CNTX_SIZE_512:
4183 case I40E_DMA_CNTX_SIZE_1K:
4184 case I40E_DMA_CNTX_SIZE_2K:
4185 case I40E_DMA_CNTX_SIZE_4K:
4186 case I40E_DMA_CNTX_SIZE_8K:
4187 case I40E_DMA_CNTX_SIZE_16K:
4188 case I40E_DMA_CNTX_SIZE_32K:
4189 case I40E_DMA_CNTX_SIZE_64K:
4190 case I40E_DMA_CNTX_SIZE_128K:
4191 case I40E_DMA_CNTX_SIZE_256K:
4192 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4193 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4194 break;
4195 default:
4196 return I40E_ERR_PARAM;
4197 }
4198
4199 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4200 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4201 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4202 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4203 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4204 return I40E_ERR_INVALID_SIZE;
4205
4206 return 0;
4207 }
4208
4209 /**
4210 * i40e_set_filter_control
4211 * @hw: pointer to the hardware structure
4212 * @settings: Filter control settings
4213 *
4214 * Set the Queue Filters for PE/FCoE and enable filters required
4215 * for a single PF. It is expected that these settings are programmed
4216 * at the driver initialization time.
4217 **/
4218 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4219 struct i40e_filter_control_settings *settings)
4220 {
4221 i40e_status ret = 0;
4222 u32 hash_lut_size = 0;
4223 u32 val;
4224
4225 if (!settings)
4226 return I40E_ERR_PARAM;
4227
4228 /* Validate the input settings */
4229 ret = i40e_validate_filter_settings(hw, settings);
4230 if (ret)
4231 return ret;
4232
4233 /* Read the PF Queue Filter control register */
4234 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4235
4236 /* Program required PE hash buckets for the PF */
4237 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4238 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4239 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4240 /* Program required PE contexts for the PF */
4241 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4242 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4243 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4244
4245 /* Program required FCoE hash buckets for the PF */
4246 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4247 val |= ((u32)settings->fcoe_filt_num <<
4248 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4249 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4250 /* Program required FCoE DDP contexts for the PF */
4251 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4252 val |= ((u32)settings->fcoe_cntx_num <<
4253 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4254 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4255
4256 /* Program Hash LUT size for the PF */
4257 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4258 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4259 hash_lut_size = 1;
4260 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4261 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4262
4263 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4264 if (settings->enable_fdir)
4265 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4266 if (settings->enable_ethtype)
4267 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4268 if (settings->enable_macvlan)
4269 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4270
4271 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4272
4273 return 0;
4274 }
4275
4276 /**
4277 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4278 * @hw: pointer to the hw struct
4279 * @mac_addr: MAC address to use in the filter
4280 * @ethtype: Ethertype to use in the filter
4281 * @flags: Flags that needs to be applied to the filter
4282 * @vsi_seid: seid of the control VSI
4283 * @queue: VSI queue number to send the packet to
4284 * @is_add: Add control packet filter if True else remove
4285 * @stats: Structure to hold information on control filter counts
4286 * @cmd_details: pointer to command details structure or NULL
4287 *
4288 * This command will Add or Remove control packet filter for a control VSI.
4289 * In return it will update the total number of perfect filter count in
4290 * the stats member.
4291 **/
4292 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4293 u8 *mac_addr, u16 ethtype, u16 flags,
4294 u16 vsi_seid, u16 queue, bool is_add,
4295 struct i40e_control_filter_stats *stats,
4296 struct i40e_asq_cmd_details *cmd_details)
4297 {
4298 struct i40e_aq_desc desc;
4299 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4300 (struct i40e_aqc_add_remove_control_packet_filter *)
4301 &desc.params.raw;
4302 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4303 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4304 &desc.params.raw;
4305 i40e_status status;
4306
4307 if (vsi_seid == 0)
4308 return I40E_ERR_PARAM;
4309
4310 if (is_add) {
4311 i40e_fill_default_direct_cmd_desc(&desc,
4312 i40e_aqc_opc_add_control_packet_filter);
4313 cmd->queue = cpu_to_le16(queue);
4314 } else {
4315 i40e_fill_default_direct_cmd_desc(&desc,
4316 i40e_aqc_opc_remove_control_packet_filter);
4317 }
4318
4319 if (mac_addr)
4320 ether_addr_copy(cmd->mac, mac_addr);
4321
4322 cmd->etype = cpu_to_le16(ethtype);
4323 cmd->flags = cpu_to_le16(flags);
4324 cmd->seid = cpu_to_le16(vsi_seid);
4325
4326 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4327
4328 if (!status && stats) {
4329 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4330 stats->etype_used = le16_to_cpu(resp->etype_used);
4331 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4332 stats->etype_free = le16_to_cpu(resp->etype_free);
4333 }
4334
4335 return status;
4336 }
4337
4338 /**
4339 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4340 * @hw: pointer to the hw struct
4341 * @seid: VSI seid to add ethertype filter from
4342 **/
4343 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4344 u16 seid)
4345 {
4346 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4347 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4348 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4349 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4350 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4351 i40e_status status;
4352
4353 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4354 seid, 0, true, NULL,
4355 NULL);
4356 if (status)
4357 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4358 }
4359
4360 /**
4361 * i40e_aq_alternate_read
4362 * @hw: pointer to the hardware structure
4363 * @reg_addr0: address of first dword to be read
4364 * @reg_val0: pointer for data read from 'reg_addr0'
4365 * @reg_addr1: address of second dword to be read
4366 * @reg_val1: pointer for data read from 'reg_addr1'
4367 *
4368 * Read one or two dwords from alternate structure. Fields are indicated
4369 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4370 * is not passed then only register at 'reg_addr0' is read.
4371 *
4372 **/
4373 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4374 u32 reg_addr0, u32 *reg_val0,
4375 u32 reg_addr1, u32 *reg_val1)
4376 {
4377 struct i40e_aq_desc desc;
4378 struct i40e_aqc_alternate_write *cmd_resp =
4379 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4380 i40e_status status;
4381
4382 if (!reg_val0)
4383 return I40E_ERR_PARAM;
4384
4385 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4386 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4387 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4388
4389 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4390
4391 if (!status) {
4392 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4393
4394 if (reg_val1)
4395 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4396 }
4397
4398 return status;
4399 }
4400
4401 /**
4402 * i40e_aq_resume_port_tx
4403 * @hw: pointer to the hardware structure
4404 * @cmd_details: pointer to command details structure or NULL
4405 *
4406 * Resume port's Tx traffic
4407 **/
4408 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4409 struct i40e_asq_cmd_details *cmd_details)
4410 {
4411 struct i40e_aq_desc desc;
4412 i40e_status status;
4413
4414 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4415
4416 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4417
4418 return status;
4419 }
4420
4421 /**
4422 * i40e_set_pci_config_data - store PCI bus info
4423 * @hw: pointer to hardware structure
4424 * @link_status: the link status word from PCI config space
4425 *
4426 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4427 **/
4428 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4429 {
4430 hw->bus.type = i40e_bus_type_pci_express;
4431
4432 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4433 case PCI_EXP_LNKSTA_NLW_X1:
4434 hw->bus.width = i40e_bus_width_pcie_x1;
4435 break;
4436 case PCI_EXP_LNKSTA_NLW_X2:
4437 hw->bus.width = i40e_bus_width_pcie_x2;
4438 break;
4439 case PCI_EXP_LNKSTA_NLW_X4:
4440 hw->bus.width = i40e_bus_width_pcie_x4;
4441 break;
4442 case PCI_EXP_LNKSTA_NLW_X8:
4443 hw->bus.width = i40e_bus_width_pcie_x8;
4444 break;
4445 default:
4446 hw->bus.width = i40e_bus_width_unknown;
4447 break;
4448 }
4449
4450 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4451 case PCI_EXP_LNKSTA_CLS_2_5GB:
4452 hw->bus.speed = i40e_bus_speed_2500;
4453 break;
4454 case PCI_EXP_LNKSTA_CLS_5_0GB:
4455 hw->bus.speed = i40e_bus_speed_5000;
4456 break;
4457 case PCI_EXP_LNKSTA_CLS_8_0GB:
4458 hw->bus.speed = i40e_bus_speed_8000;
4459 break;
4460 default:
4461 hw->bus.speed = i40e_bus_speed_unknown;
4462 break;
4463 }
4464 }
4465
4466 /**
4467 * i40e_aq_debug_dump
4468 * @hw: pointer to the hardware structure
4469 * @cluster_id: specific cluster to dump
4470 * @table_id: table id within cluster
4471 * @start_index: index of line in the block to read
4472 * @buff_size: dump buffer size
4473 * @buff: dump buffer
4474 * @ret_buff_size: actual buffer size returned
4475 * @ret_next_table: next block to read
4476 * @ret_next_index: next index to read
4477 * @cmd_details: pointer to command details structure or NULL
4478 *
4479 * Dump internal FW/HW data for debug purposes.
4480 *
4481 **/
4482 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4483 u8 table_id, u32 start_index, u16 buff_size,
4484 void *buff, u16 *ret_buff_size,
4485 u8 *ret_next_table, u32 *ret_next_index,
4486 struct i40e_asq_cmd_details *cmd_details)
4487 {
4488 struct i40e_aq_desc desc;
4489 struct i40e_aqc_debug_dump_internals *cmd =
4490 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4491 struct i40e_aqc_debug_dump_internals *resp =
4492 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4493 i40e_status status;
4494
4495 if (buff_size == 0 || !buff)
4496 return I40E_ERR_PARAM;
4497
4498 i40e_fill_default_direct_cmd_desc(&desc,
4499 i40e_aqc_opc_debug_dump_internals);
4500 /* Indirect Command */
4501 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4502 if (buff_size > I40E_AQ_LARGE_BUF)
4503 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4504
4505 cmd->cluster_id = cluster_id;
4506 cmd->table_id = table_id;
4507 cmd->idx = cpu_to_le32(start_index);
4508
4509 desc.datalen = cpu_to_le16(buff_size);
4510
4511 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4512 if (!status) {
4513 if (ret_buff_size)
4514 *ret_buff_size = le16_to_cpu(desc.datalen);
4515 if (ret_next_table)
4516 *ret_next_table = resp->table_id;
4517 if (ret_next_index)
4518 *ret_next_index = le32_to_cpu(resp->idx);
4519 }
4520
4521 return status;
4522 }
4523
4524 /**
4525 * i40e_read_bw_from_alt_ram
4526 * @hw: pointer to the hardware structure
4527 * @max_bw: pointer for max_bw read
4528 * @min_bw: pointer for min_bw read
4529 * @min_valid: pointer for bool that is true if min_bw is a valid value
4530 * @max_valid: pointer for bool that is true if max_bw is a valid value
4531 *
4532 * Read bw from the alternate ram for the given pf
4533 **/
4534 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4535 u32 *max_bw, u32 *min_bw,
4536 bool *min_valid, bool *max_valid)
4537 {
4538 i40e_status status;
4539 u32 max_bw_addr, min_bw_addr;
4540
4541 /* Calculate the address of the min/max bw registers */
4542 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4543 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4544 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4545 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4546 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4547 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4548
4549 /* Read the bandwidths from alt ram */
4550 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4551 min_bw_addr, min_bw);
4552
4553 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4554 *min_valid = true;
4555 else
4556 *min_valid = false;
4557
4558 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4559 *max_valid = true;
4560 else
4561 *max_valid = false;
4562
4563 return status;
4564 }
4565
4566 /**
4567 * i40e_aq_configure_partition_bw
4568 * @hw: pointer to the hardware structure
4569 * @bw_data: Buffer holding valid pfs and bw limits
4570 * @cmd_details: pointer to command details
4571 *
4572 * Configure partitions guaranteed/max bw
4573 **/
4574 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4575 struct i40e_aqc_configure_partition_bw_data *bw_data,
4576 struct i40e_asq_cmd_details *cmd_details)
4577 {
4578 i40e_status status;
4579 struct i40e_aq_desc desc;
4580 u16 bwd_size = sizeof(*bw_data);
4581
4582 i40e_fill_default_direct_cmd_desc(&desc,
4583 i40e_aqc_opc_configure_partition_bw);
4584
4585 /* Indirect command */
4586 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4587 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4588
4589 if (bwd_size > I40E_AQ_LARGE_BUF)
4590 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4591
4592 desc.datalen = cpu_to_le16(bwd_size);
4593
4594 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4595 cmd_details);
4596
4597 return status;
4598 }
4599
4600 /**
4601 * i40e_read_phy_register_clause22
4602 * @hw: pointer to the HW structure
4603 * @reg: register address in the page
4604 * @phy_addr: PHY address on MDIO interface
4605 * @value: PHY register value
4606 *
4607 * Reads specified PHY register value
4608 **/
4609 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4610 u16 reg, u8 phy_addr, u16 *value)
4611 {
4612 i40e_status status = I40E_ERR_TIMEOUT;
4613 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4614 u32 command = 0;
4615 u16 retry = 1000;
4616
4617 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4618 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4619 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4620 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4621 (I40E_GLGEN_MSCA_MDICMD_MASK);
4622 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4623 do {
4624 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4625 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4626 status = 0;
4627 break;
4628 }
4629 udelay(10);
4630 retry--;
4631 } while (retry);
4632
4633 if (status) {
4634 i40e_debug(hw, I40E_DEBUG_PHY,
4635 "PHY: Can't write command to external PHY.\n");
4636 } else {
4637 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4638 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4639 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4640 }
4641
4642 return status;
4643 }
4644
4645 /**
4646 * i40e_write_phy_register_clause22
4647 * @hw: pointer to the HW structure
4648 * @reg: register address in the page
4649 * @phy_addr: PHY address on MDIO interface
4650 * @value: PHY register value
4651 *
4652 * Writes specified PHY register value
4653 **/
4654 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4655 u16 reg, u8 phy_addr, u16 value)
4656 {
4657 i40e_status status = I40E_ERR_TIMEOUT;
4658 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4659 u32 command = 0;
4660 u16 retry = 1000;
4661
4662 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4663 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4664
4665 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4666 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4667 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4668 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4669 (I40E_GLGEN_MSCA_MDICMD_MASK);
4670
4671 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4672 do {
4673 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4674 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4675 status = 0;
4676 break;
4677 }
4678 udelay(10);
4679 retry--;
4680 } while (retry);
4681
4682 return status;
4683 }
4684
4685 /**
4686 * i40e_read_phy_register_clause45
4687 * @hw: pointer to the HW structure
4688 * @page: registers page number
4689 * @reg: register address in the page
4690 * @phy_addr: PHY address on MDIO interface
4691 * @value: PHY register value
4692 *
4693 * Reads specified PHY register value
4694 **/
4695 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4696 u8 page, u16 reg, u8 phy_addr, u16 *value)
4697 {
4698 i40e_status status = I40E_ERR_TIMEOUT;
4699 u32 command = 0;
4700 u16 retry = 1000;
4701 u8 port_num = hw->func_caps.mdio_port_num;
4702
4703 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4704 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4705 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4706 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4707 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4708 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4709 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4710 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4711 do {
4712 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4713 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4714 status = 0;
4715 break;
4716 }
4717 usleep_range(10, 20);
4718 retry--;
4719 } while (retry);
4720
4721 if (status) {
4722 i40e_debug(hw, I40E_DEBUG_PHY,
4723 "PHY: Can't write command to external PHY.\n");
4724 goto phy_read_end;
4725 }
4726
4727 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4728 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4729 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4730 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4731 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4732 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4733 status = I40E_ERR_TIMEOUT;
4734 retry = 1000;
4735 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4736 do {
4737 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4738 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4739 status = 0;
4740 break;
4741 }
4742 usleep_range(10, 20);
4743 retry--;
4744 } while (retry);
4745
4746 if (!status) {
4747 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4748 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4749 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4750 } else {
4751 i40e_debug(hw, I40E_DEBUG_PHY,
4752 "PHY: Can't read register value from external PHY.\n");
4753 }
4754
4755 phy_read_end:
4756 return status;
4757 }
4758
4759 /**
4760 * i40e_write_phy_register_clause45
4761 * @hw: pointer to the HW structure
4762 * @page: registers page number
4763 * @reg: register address in the page
4764 * @phy_addr: PHY address on MDIO interface
4765 * @value: PHY register value
4766 *
4767 * Writes value to specified PHY register
4768 **/
4769 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4770 u8 page, u16 reg, u8 phy_addr, u16 value)
4771 {
4772 i40e_status status = I40E_ERR_TIMEOUT;
4773 u32 command = 0;
4774 u16 retry = 1000;
4775 u8 port_num = hw->func_caps.mdio_port_num;
4776
4777 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4778 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4779 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4780 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4781 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4782 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4783 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4784 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4785 do {
4786 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4787 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4788 status = 0;
4789 break;
4790 }
4791 usleep_range(10, 20);
4792 retry--;
4793 } while (retry);
4794 if (status) {
4795 i40e_debug(hw, I40E_DEBUG_PHY,
4796 "PHY: Can't write command to external PHY.\n");
4797 goto phy_write_end;
4798 }
4799
4800 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4801 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4802
4803 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4804 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4805 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4806 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4807 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4808 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4809 status = I40E_ERR_TIMEOUT;
4810 retry = 1000;
4811 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4812 do {
4813 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4814 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4815 status = 0;
4816 break;
4817 }
4818 usleep_range(10, 20);
4819 retry--;
4820 } while (retry);
4821
4822 phy_write_end:
4823 return status;
4824 }
4825
4826 /**
4827 * i40e_write_phy_register
4828 * @hw: pointer to the HW structure
4829 * @page: registers page number
4830 * @reg: register address in the page
4831 * @phy_addr: PHY address on MDIO interface
4832 * @value: PHY register value
4833 *
4834 * Writes value to specified PHY register
4835 **/
4836 i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4837 u8 page, u16 reg, u8 phy_addr, u16 value)
4838 {
4839 i40e_status status;
4840
4841 switch (hw->device_id) {
4842 case I40E_DEV_ID_1G_BASE_T_X722:
4843 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4844 value);
4845 break;
4846 case I40E_DEV_ID_10G_BASE_T:
4847 case I40E_DEV_ID_10G_BASE_T4:
4848 case I40E_DEV_ID_10G_BASE_T_X722:
4849 case I40E_DEV_ID_25G_B:
4850 case I40E_DEV_ID_25G_SFP28:
4851 status = i40e_write_phy_register_clause45(hw, page, reg,
4852 phy_addr, value);
4853 break;
4854 default:
4855 status = I40E_ERR_UNKNOWN_PHY;
4856 break;
4857 }
4858
4859 return status;
4860 }
4861
4862 /**
4863 * i40e_read_phy_register
4864 * @hw: pointer to the HW structure
4865 * @page: registers page number
4866 * @reg: register address in the page
4867 * @phy_addr: PHY address on MDIO interface
4868 * @value: PHY register value
4869 *
4870 * Reads specified PHY register value
4871 **/
4872 i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4873 u8 page, u16 reg, u8 phy_addr, u16 *value)
4874 {
4875 i40e_status status;
4876
4877 switch (hw->device_id) {
4878 case I40E_DEV_ID_1G_BASE_T_X722:
4879 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4880 value);
4881 break;
4882 case I40E_DEV_ID_10G_BASE_T:
4883 case I40E_DEV_ID_10G_BASE_T4:
4884 case I40E_DEV_ID_10G_BASE_T_X722:
4885 case I40E_DEV_ID_25G_B:
4886 case I40E_DEV_ID_25G_SFP28:
4887 status = i40e_read_phy_register_clause45(hw, page, reg,
4888 phy_addr, value);
4889 break;
4890 default:
4891 status = I40E_ERR_UNKNOWN_PHY;
4892 break;
4893 }
4894
4895 return status;
4896 }
4897
4898 /**
4899 * i40e_get_phy_address
4900 * @hw: pointer to the HW structure
4901 * @dev_num: PHY port num that address we want
4902 *
4903 * Gets PHY address for current port
4904 **/
4905 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4906 {
4907 u8 port_num = hw->func_caps.mdio_port_num;
4908 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4909
4910 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4911 }
4912
4913 /**
4914 * i40e_blink_phy_led
4915 * @hw: pointer to the HW structure
4916 * @time: time how long led will blinks in secs
4917 * @interval: gap between LED on and off in msecs
4918 *
4919 * Blinks PHY link LED
4920 **/
4921 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4922 u32 time, u32 interval)
4923 {
4924 i40e_status status = 0;
4925 u32 i;
4926 u16 led_ctl;
4927 u16 gpio_led_port;
4928 u16 led_reg;
4929 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4930 u8 phy_addr = 0;
4931 u8 port_num;
4932
4933 i = rd32(hw, I40E_PFGEN_PORTNUM);
4934 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4935 phy_addr = i40e_get_phy_address(hw, port_num);
4936
4937 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4938 led_addr++) {
4939 status = i40e_read_phy_register_clause45(hw,
4940 I40E_PHY_COM_REG_PAGE,
4941 led_addr, phy_addr,
4942 &led_reg);
4943 if (status)
4944 goto phy_blinking_end;
4945 led_ctl = led_reg;
4946 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4947 led_reg = 0;
4948 status = i40e_write_phy_register_clause45(hw,
4949 I40E_PHY_COM_REG_PAGE,
4950 led_addr, phy_addr,
4951 led_reg);
4952 if (status)
4953 goto phy_blinking_end;
4954 break;
4955 }
4956 }
4957
4958 if (time > 0 && interval > 0) {
4959 for (i = 0; i < time * 1000; i += interval) {
4960 status = i40e_read_phy_register_clause45(hw,
4961 I40E_PHY_COM_REG_PAGE,
4962 led_addr, phy_addr, &led_reg);
4963 if (status)
4964 goto restore_config;
4965 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4966 led_reg = 0;
4967 else
4968 led_reg = I40E_PHY_LED_MANUAL_ON;
4969 status = i40e_write_phy_register_clause45(hw,
4970 I40E_PHY_COM_REG_PAGE,
4971 led_addr, phy_addr, led_reg);
4972 if (status)
4973 goto restore_config;
4974 msleep(interval);
4975 }
4976 }
4977
4978 restore_config:
4979 status = i40e_write_phy_register_clause45(hw,
4980 I40E_PHY_COM_REG_PAGE,
4981 led_addr, phy_addr, led_ctl);
4982
4983 phy_blinking_end:
4984 return status;
4985 }
4986
4987 /**
4988 * i40e_led_get_reg - read LED register
4989 * @hw: pointer to the HW structure
4990 * @led_addr: LED register address
4991 * @reg_val: read register value
4992 **/
4993 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
4994 u32 *reg_val)
4995 {
4996 enum i40e_status_code status;
4997 u8 phy_addr = 0;
4998 u8 port_num;
4999 u32 i;
5000
5001 *reg_val = 0;
5002 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5003 status =
5004 i40e_aq_get_phy_register(hw,
5005 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5006 I40E_PHY_COM_REG_PAGE,
5007 I40E_PHY_LED_PROV_REG_1,
5008 reg_val, NULL);
5009 } else {
5010 i = rd32(hw, I40E_PFGEN_PORTNUM);
5011 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5012 phy_addr = i40e_get_phy_address(hw, port_num);
5013 status = i40e_read_phy_register_clause45(hw,
5014 I40E_PHY_COM_REG_PAGE,
5015 led_addr, phy_addr,
5016 (u16 *)reg_val);
5017 }
5018 return status;
5019 }
5020
5021 /**
5022 * i40e_led_set_reg - write LED register
5023 * @hw: pointer to the HW structure
5024 * @led_addr: LED register address
5025 * @reg_val: register value to write
5026 **/
5027 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
5028 u32 reg_val)
5029 {
5030 enum i40e_status_code status;
5031 u8 phy_addr = 0;
5032 u8 port_num;
5033 u32 i;
5034
5035 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5036 status =
5037 i40e_aq_set_phy_register(hw,
5038 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5039 I40E_PHY_COM_REG_PAGE,
5040 I40E_PHY_LED_PROV_REG_1,
5041 reg_val, NULL);
5042 } else {
5043 i = rd32(hw, I40E_PFGEN_PORTNUM);
5044 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5045 phy_addr = i40e_get_phy_address(hw, port_num);
5046 status = i40e_write_phy_register_clause45(hw,
5047 I40E_PHY_COM_REG_PAGE,
5048 led_addr, phy_addr,
5049 (u16)reg_val);
5050 }
5051
5052 return status;
5053 }
5054
5055 /**
5056 * i40e_led_get_phy - return current on/off mode
5057 * @hw: pointer to the hw struct
5058 * @led_addr: address of led register to use
5059 * @val: original value of register to use
5060 *
5061 **/
5062 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
5063 u16 *val)
5064 {
5065 i40e_status status = 0;
5066 u16 gpio_led_port;
5067 u8 phy_addr = 0;
5068 u16 reg_val;
5069 u16 temp_addr;
5070 u8 port_num;
5071 u32 i;
5072 u32 reg_val_aq;
5073
5074 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5075 status =
5076 i40e_aq_get_phy_register(hw,
5077 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5078 I40E_PHY_COM_REG_PAGE,
5079 I40E_PHY_LED_PROV_REG_1,
5080 &reg_val_aq, NULL);
5081 if (status == I40E_SUCCESS)
5082 *val = (u16)reg_val_aq;
5083 return status;
5084 }
5085 temp_addr = I40E_PHY_LED_PROV_REG_1;
5086 i = rd32(hw, I40E_PFGEN_PORTNUM);
5087 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5088 phy_addr = i40e_get_phy_address(hw, port_num);
5089
5090 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
5091 temp_addr++) {
5092 status = i40e_read_phy_register_clause45(hw,
5093 I40E_PHY_COM_REG_PAGE,
5094 temp_addr, phy_addr,
5095 &reg_val);
5096 if (status)
5097 return status;
5098 *val = reg_val;
5099 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
5100 *led_addr = temp_addr;
5101 break;
5102 }
5103 }
5104 return status;
5105 }
5106
5107 /**
5108 * i40e_led_set_phy
5109 * @hw: pointer to the HW structure
5110 * @on: true or false
5111 * @led_addr: address of led register to use
5112 * @mode: original val plus bit for set or ignore
5113 *
5114 * Set led's on or off when controlled by the PHY
5115 *
5116 **/
5117 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
5118 u16 led_addr, u32 mode)
5119 {
5120 i40e_status status = 0;
5121 u32 led_ctl = 0;
5122 u32 led_reg = 0;
5123
5124 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5125 if (status)
5126 return status;
5127 led_ctl = led_reg;
5128 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
5129 led_reg = 0;
5130 status = i40e_led_set_reg(hw, led_addr, led_reg);
5131 if (status)
5132 return status;
5133 }
5134 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5135 if (status)
5136 goto restore_config;
5137 if (on)
5138 led_reg = I40E_PHY_LED_MANUAL_ON;
5139 else
5140 led_reg = 0;
5141
5142 status = i40e_led_set_reg(hw, led_addr, led_reg);
5143 if (status)
5144 goto restore_config;
5145 if (mode & I40E_PHY_LED_MODE_ORIG) {
5146 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
5147 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5148 }
5149 return status;
5150
5151 restore_config:
5152 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5153 return status;
5154 }
5155
5156 /**
5157 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
5158 * @hw: pointer to the hw struct
5159 * @reg_addr: register address
5160 * @reg_val: ptr to register value
5161 * @cmd_details: pointer to command details structure or NULL
5162 *
5163 * Use the firmware to read the Rx control register,
5164 * especially useful if the Rx unit is under heavy pressure
5165 **/
5166 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
5167 u32 reg_addr, u32 *reg_val,
5168 struct i40e_asq_cmd_details *cmd_details)
5169 {
5170 struct i40e_aq_desc desc;
5171 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
5172 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5173 i40e_status status;
5174
5175 if (!reg_val)
5176 return I40E_ERR_PARAM;
5177
5178 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
5179
5180 cmd_resp->address = cpu_to_le32(reg_addr);
5181
5182 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5183
5184 if (status == 0)
5185 *reg_val = le32_to_cpu(cmd_resp->value);
5186
5187 return status;
5188 }
5189
5190 /**
5191 * i40e_read_rx_ctl - read from an Rx control register
5192 * @hw: pointer to the hw struct
5193 * @reg_addr: register address
5194 **/
5195 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
5196 {
5197 i40e_status status = 0;
5198 bool use_register;
5199 int retry = 5;
5200 u32 val = 0;
5201
5202 use_register = (((hw->aq.api_maj_ver == 1) &&
5203 (hw->aq.api_min_ver < 5)) ||
5204 (hw->mac.type == I40E_MAC_X722));
5205 if (!use_register) {
5206 do_retry:
5207 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
5208 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5209 usleep_range(1000, 2000);
5210 retry--;
5211 goto do_retry;
5212 }
5213 }
5214
5215 /* if the AQ access failed, try the old-fashioned way */
5216 if (status || use_register)
5217 val = rd32(hw, reg_addr);
5218
5219 return val;
5220 }
5221
5222 /**
5223 * i40e_aq_rx_ctl_write_register
5224 * @hw: pointer to the hw struct
5225 * @reg_addr: register address
5226 * @reg_val: register value
5227 * @cmd_details: pointer to command details structure or NULL
5228 *
5229 * Use the firmware to write to an Rx control register,
5230 * especially useful if the Rx unit is under heavy pressure
5231 **/
5232 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
5233 u32 reg_addr, u32 reg_val,
5234 struct i40e_asq_cmd_details *cmd_details)
5235 {
5236 struct i40e_aq_desc desc;
5237 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
5238 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5239 i40e_status status;
5240
5241 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
5242
5243 cmd->address = cpu_to_le32(reg_addr);
5244 cmd->value = cpu_to_le32(reg_val);
5245
5246 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5247
5248 return status;
5249 }
5250
5251 /**
5252 * i40e_write_rx_ctl - write to an Rx control register
5253 * @hw: pointer to the hw struct
5254 * @reg_addr: register address
5255 * @reg_val: register value
5256 **/
5257 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5258 {
5259 i40e_status status = 0;
5260 bool use_register;
5261 int retry = 5;
5262
5263 use_register = (((hw->aq.api_maj_ver == 1) &&
5264 (hw->aq.api_min_ver < 5)) ||
5265 (hw->mac.type == I40E_MAC_X722));
5266 if (!use_register) {
5267 do_retry:
5268 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5269 reg_val, NULL);
5270 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5271 usleep_range(1000, 2000);
5272 retry--;
5273 goto do_retry;
5274 }
5275 }
5276
5277 /* if the AQ access failed, try the old-fashioned way */
5278 if (status || use_register)
5279 wr32(hw, reg_addr, reg_val);
5280 }
5281
5282 /**
5283 * i40e_aq_set_phy_register
5284 * @hw: pointer to the hw struct
5285 * @phy_select: select which phy should be accessed
5286 * @dev_addr: PHY device address
5287 * @reg_addr: PHY register address
5288 * @reg_val: new register value
5289 * @cmd_details: pointer to command details structure or NULL
5290 *
5291 * Write the external PHY register.
5292 **/
5293 i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw,
5294 u8 phy_select, u8 dev_addr,
5295 u32 reg_addr, u32 reg_val,
5296 struct i40e_asq_cmd_details *cmd_details)
5297 {
5298 struct i40e_aq_desc desc;
5299 struct i40e_aqc_phy_register_access *cmd =
5300 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5301 i40e_status status;
5302
5303 i40e_fill_default_direct_cmd_desc(&desc,
5304 i40e_aqc_opc_set_phy_register);
5305
5306 cmd->phy_interface = phy_select;
5307 cmd->dev_address = dev_addr;
5308 cmd->reg_address = cpu_to_le32(reg_addr);
5309 cmd->reg_value = cpu_to_le32(reg_val);
5310
5311 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5312
5313 return status;
5314 }
5315
5316 /**
5317 * i40e_aq_get_phy_register
5318 * @hw: pointer to the hw struct
5319 * @phy_select: select which phy should be accessed
5320 * @dev_addr: PHY device address
5321 * @reg_addr: PHY register address
5322 * @reg_val: read register value
5323 * @cmd_details: pointer to command details structure or NULL
5324 *
5325 * Read the external PHY register.
5326 **/
5327 i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw,
5328 u8 phy_select, u8 dev_addr,
5329 u32 reg_addr, u32 *reg_val,
5330 struct i40e_asq_cmd_details *cmd_details)
5331 {
5332 struct i40e_aq_desc desc;
5333 struct i40e_aqc_phy_register_access *cmd =
5334 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5335 i40e_status status;
5336
5337 i40e_fill_default_direct_cmd_desc(&desc,
5338 i40e_aqc_opc_get_phy_register);
5339
5340 cmd->phy_interface = phy_select;
5341 cmd->dev_address = dev_addr;
5342 cmd->reg_address = cpu_to_le32(reg_addr);
5343
5344 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5345 if (!status)
5346 *reg_val = le32_to_cpu(cmd->reg_value);
5347
5348 return status;
5349 }
5350
5351 /**
5352 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
5353 * @hw: pointer to the hw struct
5354 * @buff: command buffer (size in bytes = buff_size)
5355 * @buff_size: buffer size in bytes
5356 * @track_id: package tracking id
5357 * @error_offset: returns error offset
5358 * @error_info: returns error information
5359 * @cmd_details: pointer to command details structure or NULL
5360 **/
5361 enum
5362 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5363 u16 buff_size, u32 track_id,
5364 u32 *error_offset, u32 *error_info,
5365 struct i40e_asq_cmd_details *cmd_details)
5366 {
5367 struct i40e_aq_desc desc;
5368 struct i40e_aqc_write_personalization_profile *cmd =
5369 (struct i40e_aqc_write_personalization_profile *)
5370 &desc.params.raw;
5371 struct i40e_aqc_write_ddp_resp *resp;
5372 i40e_status status;
5373
5374 i40e_fill_default_direct_cmd_desc(&desc,
5375 i40e_aqc_opc_write_personalization_profile);
5376
5377 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5378 if (buff_size > I40E_AQ_LARGE_BUF)
5379 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5380
5381 desc.datalen = cpu_to_le16(buff_size);
5382
5383 cmd->profile_track_id = cpu_to_le32(track_id);
5384
5385 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5386 if (!status) {
5387 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5388 if (error_offset)
5389 *error_offset = le32_to_cpu(resp->error_offset);
5390 if (error_info)
5391 *error_info = le32_to_cpu(resp->error_info);
5392 }
5393
5394 return status;
5395 }
5396
5397 /**
5398 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
5399 * @hw: pointer to the hw struct
5400 * @buff: command buffer (size in bytes = buff_size)
5401 * @buff_size: buffer size in bytes
5402 * @flags: AdminQ command flags
5403 * @cmd_details: pointer to command details structure or NULL
5404 **/
5405 enum
5406 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5407 u16 buff_size, u8 flags,
5408 struct i40e_asq_cmd_details *cmd_details)
5409 {
5410 struct i40e_aq_desc desc;
5411 struct i40e_aqc_get_applied_profiles *cmd =
5412 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5413 i40e_status status;
5414
5415 i40e_fill_default_direct_cmd_desc(&desc,
5416 i40e_aqc_opc_get_personalization_profile_list);
5417
5418 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5419 if (buff_size > I40E_AQ_LARGE_BUF)
5420 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5421 desc.datalen = cpu_to_le16(buff_size);
5422
5423 cmd->flags = flags;
5424
5425 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5426
5427 return status;
5428 }
5429
5430 /**
5431 * i40e_find_segment_in_package
5432 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5433 * @pkg_hdr: pointer to the package header to be searched
5434 *
5435 * This function searches a package file for a particular segment type. On
5436 * success it returns a pointer to the segment header, otherwise it will
5437 * return NULL.
5438 **/
5439 struct i40e_generic_seg_header *
5440 i40e_find_segment_in_package(u32 segment_type,
5441 struct i40e_package_header *pkg_hdr)
5442 {
5443 struct i40e_generic_seg_header *segment;
5444 u32 i;
5445
5446 /* Search all package segments for the requested segment type */
5447 for (i = 0; i < pkg_hdr->segment_count; i++) {
5448 segment =
5449 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5450 pkg_hdr->segment_offset[i]);
5451
5452 if (segment->type == segment_type)
5453 return segment;
5454 }
5455
5456 return NULL;
5457 }
5458
5459 /**
5460 * i40e_write_profile
5461 * @hw: pointer to the hardware structure
5462 * @profile: pointer to the profile segment of the package to be downloaded
5463 * @track_id: package tracking id
5464 *
5465 * Handles the download of a complete package.
5466 */
5467 enum i40e_status_code
5468 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5469 u32 track_id)
5470 {
5471 i40e_status status = 0;
5472 struct i40e_section_table *sec_tbl;
5473 struct i40e_profile_section_header *sec = NULL;
5474 u32 dev_cnt;
5475 u32 vendor_dev_id;
5476 u32 *nvm;
5477 u32 section_size = 0;
5478 u32 offset = 0, info = 0;
5479 u32 i;
5480
5481 dev_cnt = profile->device_table_count;
5482
5483 for (i = 0; i < dev_cnt; i++) {
5484 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5485 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL)
5486 if (hw->device_id == (vendor_dev_id & 0xFFFF))
5487 break;
5488 }
5489 if (i == dev_cnt) {
5490 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
5491 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5492 }
5493
5494 nvm = (u32 *)&profile->device_table[dev_cnt];
5495 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
5496
5497 for (i = 0; i < sec_tbl->section_count; i++) {
5498 sec = (struct i40e_profile_section_header *)((u8 *)profile +
5499 sec_tbl->section_offset[i]);
5500
5501 /* Skip 'AQ', 'note' and 'name' sections */
5502 if (sec->section.type != SECTION_TYPE_MMIO)
5503 continue;
5504
5505 section_size = sec->section.size +
5506 sizeof(struct i40e_profile_section_header);
5507
5508 /* Write profile */
5509 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5510 track_id, &offset, &info, NULL);
5511 if (status) {
5512 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5513 "Failed to write profile: offset %d, info %d",
5514 offset, info);
5515 break;
5516 }
5517 }
5518 return status;
5519 }
5520
5521 /**
5522 * i40e_add_pinfo_to_list
5523 * @hw: pointer to the hardware structure
5524 * @profile: pointer to the profile segment of the package
5525 * @profile_info_sec: buffer for information section
5526 * @track_id: package tracking id
5527 *
5528 * Register a profile to the list of loaded profiles.
5529 */
5530 enum i40e_status_code
5531 i40e_add_pinfo_to_list(struct i40e_hw *hw,
5532 struct i40e_profile_segment *profile,
5533 u8 *profile_info_sec, u32 track_id)
5534 {
5535 i40e_status status = 0;
5536 struct i40e_profile_section_header *sec = NULL;
5537 struct i40e_profile_info *pinfo;
5538 u32 offset = 0, info = 0;
5539
5540 sec = (struct i40e_profile_section_header *)profile_info_sec;
5541 sec->tbl_size = 1;
5542 sec->data_end = sizeof(struct i40e_profile_section_header) +
5543 sizeof(struct i40e_profile_info);
5544 sec->section.type = SECTION_TYPE_INFO;
5545 sec->section.offset = sizeof(struct i40e_profile_section_header);
5546 sec->section.size = sizeof(struct i40e_profile_info);
5547 pinfo = (struct i40e_profile_info *)(profile_info_sec +
5548 sec->section.offset);
5549 pinfo->track_id = track_id;
5550 pinfo->version = profile->version;
5551 pinfo->op = I40E_DDP_ADD_TRACKID;
5552 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5553
5554 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5555 track_id, &offset, &info, NULL);
5556
5557 return status;
5558 }
5559
5560 /**
5561 * i40e_aq_add_cloud_filters
5562 * @hw: pointer to the hardware structure
5563 * @seid: VSI seid to add cloud filters from
5564 * @filters: Buffer which contains the filters to be added
5565 * @filter_count: number of filters contained in the buffer
5566 *
5567 * Set the cloud filters for a given VSI. The contents of the
5568 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5569 * of the function.
5570 *
5571 **/
5572 enum i40e_status_code
5573 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5574 struct i40e_aqc_cloud_filters_element_data *filters,
5575 u8 filter_count)
5576 {
5577 struct i40e_aq_desc desc;
5578 struct i40e_aqc_add_remove_cloud_filters *cmd =
5579 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5580 enum i40e_status_code status;
5581 u16 buff_len;
5582
5583 i40e_fill_default_direct_cmd_desc(&desc,
5584 i40e_aqc_opc_add_cloud_filters);
5585
5586 buff_len = filter_count * sizeof(*filters);
5587 desc.datalen = cpu_to_le16(buff_len);
5588 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5589 cmd->num_filters = filter_count;
5590 cmd->seid = cpu_to_le16(seid);
5591
5592 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5593
5594 return status;
5595 }
5596
5597 /**
5598 * i40e_aq_add_cloud_filters_bb
5599 * @hw: pointer to the hardware structure
5600 * @seid: VSI seid to add cloud filters from
5601 * @filters: Buffer which contains the filters in big buffer to be added
5602 * @filter_count: number of filters contained in the buffer
5603 *
5604 * Set the big buffer cloud filters for a given VSI. The contents of the
5605 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5606 * function.
5607 *
5608 **/
5609 enum i40e_status_code
5610 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5611 struct i40e_aqc_cloud_filters_element_bb *filters,
5612 u8 filter_count)
5613 {
5614 struct i40e_aq_desc desc;
5615 struct i40e_aqc_add_remove_cloud_filters *cmd =
5616 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5617 i40e_status status;
5618 u16 buff_len;
5619 int i;
5620
5621 i40e_fill_default_direct_cmd_desc(&desc,
5622 i40e_aqc_opc_add_cloud_filters);
5623
5624 buff_len = filter_count * sizeof(*filters);
5625 desc.datalen = cpu_to_le16(buff_len);
5626 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5627 cmd->num_filters = filter_count;
5628 cmd->seid = cpu_to_le16(seid);
5629 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5630
5631 for (i = 0; i < filter_count; i++) {
5632 u16 tnl_type;
5633 u32 ti;
5634
5635 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5636 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5637 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5638
5639 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5640 * one more byte further than normally used for Tenant ID in
5641 * other tunnel types.
5642 */
5643 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5644 ti = le32_to_cpu(filters[i].element.tenant_id);
5645 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5646 }
5647 }
5648
5649 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5650
5651 return status;
5652 }
5653
5654 /**
5655 * i40e_aq_rem_cloud_filters
5656 * @hw: pointer to the hardware structure
5657 * @seid: VSI seid to remove cloud filters from
5658 * @filters: Buffer which contains the filters to be removed
5659 * @filter_count: number of filters contained in the buffer
5660 *
5661 * Remove the cloud filters for a given VSI. The contents of the
5662 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5663 * of the function.
5664 *
5665 **/
5666 enum i40e_status_code
5667 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5668 struct i40e_aqc_cloud_filters_element_data *filters,
5669 u8 filter_count)
5670 {
5671 struct i40e_aq_desc desc;
5672 struct i40e_aqc_add_remove_cloud_filters *cmd =
5673 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5674 enum i40e_status_code status;
5675 u16 buff_len;
5676
5677 i40e_fill_default_direct_cmd_desc(&desc,
5678 i40e_aqc_opc_remove_cloud_filters);
5679
5680 buff_len = filter_count * sizeof(*filters);
5681 desc.datalen = cpu_to_le16(buff_len);
5682 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5683 cmd->num_filters = filter_count;
5684 cmd->seid = cpu_to_le16(seid);
5685
5686 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5687
5688 return status;
5689 }
5690
5691 /**
5692 * i40e_aq_rem_cloud_filters_bb
5693 * @hw: pointer to the hardware structure
5694 * @seid: VSI seid to remove cloud filters from
5695 * @filters: Buffer which contains the filters in big buffer to be removed
5696 * @filter_count: number of filters contained in the buffer
5697 *
5698 * Remove the big buffer cloud filters for a given VSI. The contents of the
5699 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5700 * function.
5701 *
5702 **/
5703 enum i40e_status_code
5704 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5705 struct i40e_aqc_cloud_filters_element_bb *filters,
5706 u8 filter_count)
5707 {
5708 struct i40e_aq_desc desc;
5709 struct i40e_aqc_add_remove_cloud_filters *cmd =
5710 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5711 i40e_status status;
5712 u16 buff_len;
5713 int i;
5714
5715 i40e_fill_default_direct_cmd_desc(&desc,
5716 i40e_aqc_opc_remove_cloud_filters);
5717
5718 buff_len = filter_count * sizeof(*filters);
5719 desc.datalen = cpu_to_le16(buff_len);
5720 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5721 cmd->num_filters = filter_count;
5722 cmd->seid = cpu_to_le16(seid);
5723 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5724
5725 for (i = 0; i < filter_count; i++) {
5726 u16 tnl_type;
5727 u32 ti;
5728
5729 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5730 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5731 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5732
5733 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5734 * one more byte further than normally used for Tenant ID in
5735 * other tunnel types.
5736 */
5737 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5738 ti = le32_to_cpu(filters[i].element.tenant_id);
5739 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5740 }
5741 }
5742
5743 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5744
5745 return status;
5746 }
Linux with added FPC-III support