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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
blob4243ff4ec4b1d28303182b380a09821a4d4e4a57
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #include <linux/types.h>
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/netdevice.h>
8 #include <linux/vmalloc.h>
9 #include <linux/string.h>
10 #include <linux/in.h>
11 #include <linux/interrupt.h>
12 #include <linux/ip.h>
13 #include <linux/tcp.h>
14 #include <linux/sctp.h>
15 #include <linux/pkt_sched.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/etherdevice.h>
21 #include <linux/ethtool.h>
22 #include <linux/if.h>
23 #include <linux/if_vlan.h>
24 #include <linux/if_macvlan.h>
25 #include <linux/if_bridge.h>
26 #include <linux/prefetch.h>
27 #include <linux/bpf.h>
28 #include <linux/bpf_trace.h>
29 #include <linux/atomic.h>
30 #include <scsi/fc/fc_fcoe.h>
31 #include <net/udp_tunnel.h>
32 #include <net/pkt_cls.h>
33 #include <net/tc_act/tc_gact.h>
34 #include <net/tc_act/tc_mirred.h>
35 #include <net/vxlan.h>
36 #include <net/mpls.h>
37 #include <net/xfrm.h>
38
39 #include "ixgbe.h"
40 #include "ixgbe_common.h"
41 #include "ixgbe_dcb_82599.h"
42 #include "ixgbe_sriov.h"
43 #include "ixgbe_model.h"
44
45 char ixgbe_driver_name[] = "ixgbe";
46 static const char ixgbe_driver_string[] =
47 "Intel(R) 10 Gigabit PCI Express Network Driver";
48 #ifdef IXGBE_FCOE
49 char ixgbe_default_device_descr[] =
50 "Intel(R) 10 Gigabit Network Connection";
51 #else
52 static char ixgbe_default_device_descr[] =
53 "Intel(R) 10 Gigabit Network Connection";
54 #endif
55 #define DRV_VERSION "5.1.0-k"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static const char ixgbe_copyright[] =
58 "Copyright (c) 1999-2016 Intel Corporation.";
59
60 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
61
62 static const struct ixgbe_info *ixgbe_info_tbl[] = {
63 [board_82598] = &ixgbe_82598_info,
64 [board_82599] = &ixgbe_82599_info,
65 [board_X540] = &ixgbe_X540_info,
66 [board_X550] = &ixgbe_X550_info,
67 [board_X550EM_x] = &ixgbe_X550EM_x_info,
68 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info,
69 [board_x550em_a] = &ixgbe_x550em_a_info,
70 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info,
71 };
72
73 /* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
81 static const struct pci_device_id ixgbe_pci_tbl[] = {
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x},
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw},
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a},
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw },
129 /* required last entry */
130 {0, }
131 };
132 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
133
134 #ifdef CONFIG_IXGBE_DCA
135 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
136 void *p);
137 static struct notifier_block dca_notifier = {
138 .notifier_call = ixgbe_notify_dca,
139 .next = NULL,
140 .priority = 0
141 };
142 #endif
143
144 #ifdef CONFIG_PCI_IOV
145 static unsigned int max_vfs;
146 module_param(max_vfs, uint, 0);
147 MODULE_PARM_DESC(max_vfs,
148 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
149 #endif /* CONFIG_PCI_IOV */
150
151 static unsigned int allow_unsupported_sfp;
152 module_param(allow_unsupported_sfp, uint, 0);
153 MODULE_PARM_DESC(allow_unsupported_sfp,
154 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
155
156 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
157 static int debug = -1;
158 module_param(debug, int, 0);
159 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
160
161 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
162 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
163 MODULE_LICENSE("GPL");
164 MODULE_VERSION(DRV_VERSION);
165
166 static struct workqueue_struct *ixgbe_wq;
167
168 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
169 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *);
170
171 static const struct net_device_ops ixgbe_netdev_ops;
172
173 static bool netif_is_ixgbe(struct net_device *dev)
174 {
175 return dev && (dev->netdev_ops == &ixgbe_netdev_ops);
176 }
177
178 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
179 u32 reg, u16 *value)
180 {
181 struct pci_dev *parent_dev;
182 struct pci_bus *parent_bus;
183
184 parent_bus = adapter->pdev->bus->parent;
185 if (!parent_bus)
186 return -1;
187
188 parent_dev = parent_bus->self;
189 if (!parent_dev)
190 return -1;
191
192 if (!pci_is_pcie(parent_dev))
193 return -1;
194
195 pcie_capability_read_word(parent_dev, reg, value);
196 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
197 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
198 return -1;
199 return 0;
200 }
201
202 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
203 {
204 struct ixgbe_hw *hw = &adapter->hw;
205 u16 link_status = 0;
206 int err;
207
208 hw->bus.type = ixgbe_bus_type_pci_express;
209
210 /* Get the negotiated link width and speed from PCI config space of the
211 * parent, as this device is behind a switch
212 */
213 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
214
215 /* assume caller will handle error case */
216 if (err)
217 return err;
218
219 hw->bus.width = ixgbe_convert_bus_width(link_status);
220 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
221
222 return 0;
223 }
224
225 /**
226 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
227 * @hw: hw specific details
228 *
229 * This function is used by probe to determine whether a device's PCI-Express
230 * bandwidth details should be gathered from the parent bus instead of from the
231 * device. Used to ensure that various locations all have the correct device ID
232 * checks.
233 */
234 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
235 {
236 switch (hw->device_id) {
237 case IXGBE_DEV_ID_82599_SFP_SF_QP:
238 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
239 return true;
240 default:
241 return false;
242 }
243 }
244
245 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
246 int expected_gts)
247 {
248 struct ixgbe_hw *hw = &adapter->hw;
249 struct pci_dev *pdev;
250
251 /* Some devices are not connected over PCIe and thus do not negotiate
252 * speed. These devices do not have valid bus info, and thus any report
253 * we generate may not be correct.
254 */
255 if (hw->bus.type == ixgbe_bus_type_internal)
256 return;
257
258 /* determine whether to use the parent device */
259 if (ixgbe_pcie_from_parent(&adapter->hw))
260 pdev = adapter->pdev->bus->parent->self;
261 else
262 pdev = adapter->pdev;
263
264 pcie_print_link_status(pdev);
265 }
266
267 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
268 {
269 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
270 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
271 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
272 queue_work(ixgbe_wq, &adapter->service_task);
273 }
274
275 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
276 {
277 struct ixgbe_adapter *adapter = hw->back;
278
279 if (!hw->hw_addr)
280 return;
281 hw->hw_addr = NULL;
282 e_dev_err("Adapter removed\n");
283 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
284 ixgbe_service_event_schedule(adapter);
285 }
286
287 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
288 {
289 u8 __iomem *reg_addr;
290 u32 value;
291 int i;
292
293 reg_addr = READ_ONCE(hw->hw_addr);
294 if (ixgbe_removed(reg_addr))
295 return IXGBE_FAILED_READ_REG;
296
297 /* Register read of 0xFFFFFFF can indicate the adapter has been removed,
298 * so perform several status register reads to determine if the adapter
299 * has been removed.
300 */
301 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) {
302 value = readl(reg_addr + IXGBE_STATUS);
303 if (value != IXGBE_FAILED_READ_REG)
304 break;
305 mdelay(3);
306 }
307
308 if (value == IXGBE_FAILED_READ_REG)
309 ixgbe_remove_adapter(hw);
310 else
311 value = readl(reg_addr + reg);
312 return value;
313 }
314
315 /**
316 * ixgbe_read_reg - Read from device register
317 * @hw: hw specific details
318 * @reg: offset of register to read
319 *
320 * Returns : value read or IXGBE_FAILED_READ_REG if removed
321 *
322 * This function is used to read device registers. It checks for device
323 * removal by confirming any read that returns all ones by checking the
324 * status register value for all ones. This function avoids reading from
325 * the hardware if a removal was previously detected in which case it
326 * returns IXGBE_FAILED_READ_REG (all ones).
327 */
328 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
329 {
330 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
331 u32 value;
332
333 if (ixgbe_removed(reg_addr))
334 return IXGBE_FAILED_READ_REG;
335 if (unlikely(hw->phy.nw_mng_if_sel &
336 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) {
337 struct ixgbe_adapter *adapter;
338 int i;
339
340 for (i = 0; i < 200; ++i) {
341 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
342 if (likely(!value))
343 goto writes_completed;
344 if (value == IXGBE_FAILED_READ_REG) {
345 ixgbe_remove_adapter(hw);
346 return IXGBE_FAILED_READ_REG;
347 }
348 udelay(5);
349 }
350
351 adapter = hw->back;
352 e_warn(hw, "register writes incomplete %08x\n", value);
353 }
354
355 writes_completed:
356 value = readl(reg_addr + reg);
357 if (unlikely(value == IXGBE_FAILED_READ_REG))
358 value = ixgbe_check_remove(hw, reg);
359 return value;
360 }
361
362 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
363 {
364 u16 value;
365
366 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
367 if (value == IXGBE_FAILED_READ_CFG_WORD) {
368 ixgbe_remove_adapter(hw);
369 return true;
370 }
371 return false;
372 }
373
374 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
375 {
376 struct ixgbe_adapter *adapter = hw->back;
377 u16 value;
378
379 if (ixgbe_removed(hw->hw_addr))
380 return IXGBE_FAILED_READ_CFG_WORD;
381 pci_read_config_word(adapter->pdev, reg, &value);
382 if (value == IXGBE_FAILED_READ_CFG_WORD &&
383 ixgbe_check_cfg_remove(hw, adapter->pdev))
384 return IXGBE_FAILED_READ_CFG_WORD;
385 return value;
386 }
387
388 #ifdef CONFIG_PCI_IOV
389 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
390 {
391 struct ixgbe_adapter *adapter = hw->back;
392 u32 value;
393
394 if (ixgbe_removed(hw->hw_addr))
395 return IXGBE_FAILED_READ_CFG_DWORD;
396 pci_read_config_dword(adapter->pdev, reg, &value);
397 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
398 ixgbe_check_cfg_remove(hw, adapter->pdev))
399 return IXGBE_FAILED_READ_CFG_DWORD;
400 return value;
401 }
402 #endif /* CONFIG_PCI_IOV */
403
404 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
405 {
406 struct ixgbe_adapter *adapter = hw->back;
407
408 if (ixgbe_removed(hw->hw_addr))
409 return;
410 pci_write_config_word(adapter->pdev, reg, value);
411 }
412
413 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
414 {
415 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
416
417 /* flush memory to make sure state is correct before next watchdog */
418 smp_mb__before_atomic();
419 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
420 }
421
422 struct ixgbe_reg_info {
423 u32 ofs;
424 char *name;
425 };
426
427 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
428
429 /* General Registers */
430 {IXGBE_CTRL, "CTRL"},
431 {IXGBE_STATUS, "STATUS"},
432 {IXGBE_CTRL_EXT, "CTRL_EXT"},
433
434 /* Interrupt Registers */
435 {IXGBE_EICR, "EICR"},
436
437 /* RX Registers */
438 {IXGBE_SRRCTL(0), "SRRCTL"},
439 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
440 {IXGBE_RDLEN(0), "RDLEN"},
441 {IXGBE_RDH(0), "RDH"},
442 {IXGBE_RDT(0), "RDT"},
443 {IXGBE_RXDCTL(0), "RXDCTL"},
444 {IXGBE_RDBAL(0), "RDBAL"},
445 {IXGBE_RDBAH(0), "RDBAH"},
446
447 /* TX Registers */
448 {IXGBE_TDBAL(0), "TDBAL"},
449 {IXGBE_TDBAH(0), "TDBAH"},
450 {IXGBE_TDLEN(0), "TDLEN"},
451 {IXGBE_TDH(0), "TDH"},
452 {IXGBE_TDT(0), "TDT"},
453 {IXGBE_TXDCTL(0), "TXDCTL"},
454
455 /* List Terminator */
456 { .name = NULL }
457 };
458
459
460 /*
461 * ixgbe_regdump - register printout routine
462 */
463 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
464 {
465 int i;
466 char rname[16];
467 u32 regs[64];
468
469 switch (reginfo->ofs) {
470 case IXGBE_SRRCTL(0):
471 for (i = 0; i < 64; i++)
472 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
473 break;
474 case IXGBE_DCA_RXCTRL(0):
475 for (i = 0; i < 64; i++)
476 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
477 break;
478 case IXGBE_RDLEN(0):
479 for (i = 0; i < 64; i++)
480 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
481 break;
482 case IXGBE_RDH(0):
483 for (i = 0; i < 64; i++)
484 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
485 break;
486 case IXGBE_RDT(0):
487 for (i = 0; i < 64; i++)
488 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
489 break;
490 case IXGBE_RXDCTL(0):
491 for (i = 0; i < 64; i++)
492 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
493 break;
494 case IXGBE_RDBAL(0):
495 for (i = 0; i < 64; i++)
496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
497 break;
498 case IXGBE_RDBAH(0):
499 for (i = 0; i < 64; i++)
500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
501 break;
502 case IXGBE_TDBAL(0):
503 for (i = 0; i < 64; i++)
504 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
505 break;
506 case IXGBE_TDBAH(0):
507 for (i = 0; i < 64; i++)
508 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
509 break;
510 case IXGBE_TDLEN(0):
511 for (i = 0; i < 64; i++)
512 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
513 break;
514 case IXGBE_TDH(0):
515 for (i = 0; i < 64; i++)
516 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
517 break;
518 case IXGBE_TDT(0):
519 for (i = 0; i < 64; i++)
520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
521 break;
522 case IXGBE_TXDCTL(0):
523 for (i = 0; i < 64; i++)
524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
525 break;
526 default:
527 pr_info("%-15s %08x\n",
528 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs));
529 return;
530 }
531
532 i = 0;
533 while (i < 64) {
534 int j;
535 char buf[9 * 8 + 1];
536 char *p = buf;
537
538 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7);
539 for (j = 0; j < 8; j++)
540 p += sprintf(p, " %08x", regs[i++]);
541 pr_err("%-15s%s\n", rname, buf);
542 }
543
544 }
545
546 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n)
547 {
548 struct ixgbe_tx_buffer *tx_buffer;
549
550 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean];
551 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
552 n, ring->next_to_use, ring->next_to_clean,
553 (u64)dma_unmap_addr(tx_buffer, dma),
554 dma_unmap_len(tx_buffer, len),
555 tx_buffer->next_to_watch,
556 (u64)tx_buffer->time_stamp);
557 }
558
559 /*
560 * ixgbe_dump - Print registers, tx-rings and rx-rings
561 */
562 static void ixgbe_dump(struct ixgbe_adapter *adapter)
563 {
564 struct net_device *netdev = adapter->netdev;
565 struct ixgbe_hw *hw = &adapter->hw;
566 struct ixgbe_reg_info *reginfo;
567 int n = 0;
568 struct ixgbe_ring *ring;
569 struct ixgbe_tx_buffer *tx_buffer;
570 union ixgbe_adv_tx_desc *tx_desc;
571 struct my_u0 { u64 a; u64 b; } *u0;
572 struct ixgbe_ring *rx_ring;
573 union ixgbe_adv_rx_desc *rx_desc;
574 struct ixgbe_rx_buffer *rx_buffer_info;
575 int i = 0;
576
577 if (!netif_msg_hw(adapter))
578 return;
579
580 /* Print netdevice Info */
581 if (netdev) {
582 dev_info(&adapter->pdev->dev, "Net device Info\n");
583 pr_info("Device Name state "
584 "trans_start\n");
585 pr_info("%-15s %016lX %016lX\n",
586 netdev->name,
587 netdev->state,
588 dev_trans_start(netdev));
589 }
590
591 /* Print Registers */
592 dev_info(&adapter->pdev->dev, "Register Dump\n");
593 pr_info(" Register Name Value\n");
594 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
595 reginfo->name; reginfo++) {
596 ixgbe_regdump(hw, reginfo);
597 }
598
599 /* Print TX Ring Summary */
600 if (!netdev || !netif_running(netdev))
601 return;
602
603 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
604 pr_info(" %s %s %s %s\n",
605 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
606 "leng", "ntw", "timestamp");
607 for (n = 0; n < adapter->num_tx_queues; n++) {
608 ring = adapter->tx_ring[n];
609 ixgbe_print_buffer(ring, n);
610 }
611
612 for (n = 0; n < adapter->num_xdp_queues; n++) {
613 ring = adapter->xdp_ring[n];
614 ixgbe_print_buffer(ring, n);
615 }
616
617 /* Print TX Rings */
618 if (!netif_msg_tx_done(adapter))
619 goto rx_ring_summary;
620
621 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
622
623 /* Transmit Descriptor Formats
624 *
625 * 82598 Advanced Transmit Descriptor
626 * +--------------------------------------------------------------+
627 * 0 | Buffer Address [63:0] |
628 * +--------------------------------------------------------------+
629 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
630 * +--------------------------------------------------------------+
631 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
632 *
633 * 82598 Advanced Transmit Descriptor (Write-Back Format)
634 * +--------------------------------------------------------------+
635 * 0 | RSV [63:0] |
636 * +--------------------------------------------------------------+
637 * 8 | RSV | STA | NXTSEQ |
638 * +--------------------------------------------------------------+
639 * 63 36 35 32 31 0
640 *
641 * 82599+ Advanced Transmit Descriptor
642 * +--------------------------------------------------------------+
643 * 0 | Buffer Address [63:0] |
644 * +--------------------------------------------------------------+
645 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
646 * +--------------------------------------------------------------+
647 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
648 *
649 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
650 * +--------------------------------------------------------------+
651 * 0 | RSV [63:0] |
652 * +--------------------------------------------------------------+
653 * 8 | RSV | STA | RSV |
654 * +--------------------------------------------------------------+
655 * 63 36 35 32 31 0
656 */
657
658 for (n = 0; n < adapter->num_tx_queues; n++) {
659 ring = adapter->tx_ring[n];
660 pr_info("------------------------------------\n");
661 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index);
662 pr_info("------------------------------------\n");
663 pr_info("%s%s %s %s %s %s\n",
664 "T [desc] [address 63:0 ] ",
665 "[PlPOIdStDDt Ln] [bi->dma ] ",
666 "leng", "ntw", "timestamp", "bi->skb");
667
668 for (i = 0; ring->desc && (i < ring->count); i++) {
669 tx_desc = IXGBE_TX_DESC(ring, i);
670 tx_buffer = &ring->tx_buffer_info[i];
671 u0 = (struct my_u0 *)tx_desc;
672 if (dma_unmap_len(tx_buffer, len) > 0) {
673 const char *ring_desc;
674
675 if (i == ring->next_to_use &&
676 i == ring->next_to_clean)
677 ring_desc = " NTC/U";
678 else if (i == ring->next_to_use)
679 ring_desc = " NTU";
680 else if (i == ring->next_to_clean)
681 ring_desc = " NTC";
682 else
683 ring_desc = "";
684 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s",
685 i,
686 le64_to_cpu((__force __le64)u0->a),
687 le64_to_cpu((__force __le64)u0->b),
688 (u64)dma_unmap_addr(tx_buffer, dma),
689 dma_unmap_len(tx_buffer, len),
690 tx_buffer->next_to_watch,
691 (u64)tx_buffer->time_stamp,
692 tx_buffer->skb,
693 ring_desc);
694
695 if (netif_msg_pktdata(adapter) &&
696 tx_buffer->skb)
697 print_hex_dump(KERN_INFO, "",
698 DUMP_PREFIX_ADDRESS, 16, 1,
699 tx_buffer->skb->data,
700 dma_unmap_len(tx_buffer, len),
701 true);
702 }
703 }
704 }
705
706 /* Print RX Rings Summary */
707 rx_ring_summary:
708 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
709 pr_info("Queue [NTU] [NTC]\n");
710 for (n = 0; n < adapter->num_rx_queues; n++) {
711 rx_ring = adapter->rx_ring[n];
712 pr_info("%5d %5X %5X\n",
713 n, rx_ring->next_to_use, rx_ring->next_to_clean);
714 }
715
716 /* Print RX Rings */
717 if (!netif_msg_rx_status(adapter))
718 return;
719
720 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
721
722 /* Receive Descriptor Formats
723 *
724 * 82598 Advanced Receive Descriptor (Read) Format
725 * 63 1 0
726 * +-----------------------------------------------------+
727 * 0 | Packet Buffer Address [63:1] |A0/NSE|
728 * +----------------------------------------------+------+
729 * 8 | Header Buffer Address [63:1] | DD |
730 * +-----------------------------------------------------+
731 *
732 *
733 * 82598 Advanced Receive Descriptor (Write-Back) Format
734 *
735 * 63 48 47 32 31 30 21 20 16 15 4 3 0
736 * +------------------------------------------------------+
737 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
738 * | Packet | IP | | | | Type | Type |
739 * | Checksum | Ident | | | | | |
740 * +------------------------------------------------------+
741 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
742 * +------------------------------------------------------+
743 * 63 48 47 32 31 20 19 0
744 *
745 * 82599+ Advanced Receive Descriptor (Read) Format
746 * 63 1 0
747 * +-----------------------------------------------------+
748 * 0 | Packet Buffer Address [63:1] |A0/NSE|
749 * +----------------------------------------------+------+
750 * 8 | Header Buffer Address [63:1] | DD |
751 * +-----------------------------------------------------+
752 *
753 *
754 * 82599+ Advanced Receive Descriptor (Write-Back) Format
755 *
756 * 63 48 47 32 31 30 21 20 17 16 4 3 0
757 * +------------------------------------------------------+
758 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
759 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
760 * |/ Flow Dir Flt ID | | | | | |
761 * +------------------------------------------------------+
762 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
763 * +------------------------------------------------------+
764 * 63 48 47 32 31 20 19 0
765 */
766
767 for (n = 0; n < adapter->num_rx_queues; n++) {
768 rx_ring = adapter->rx_ring[n];
769 pr_info("------------------------------------\n");
770 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
771 pr_info("------------------------------------\n");
772 pr_info("%s%s%s\n",
773 "R [desc] [ PktBuf A0] ",
774 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
775 "<-- Adv Rx Read format");
776 pr_info("%s%s%s\n",
777 "RWB[desc] [PcsmIpSHl PtRs] ",
778 "[vl er S cks ln] ---------------- [bi->skb ] ",
779 "<-- Adv Rx Write-Back format");
780
781 for (i = 0; i < rx_ring->count; i++) {
782 const char *ring_desc;
783
784 if (i == rx_ring->next_to_use)
785 ring_desc = " NTU";
786 else if (i == rx_ring->next_to_clean)
787 ring_desc = " NTC";
788 else
789 ring_desc = "";
790
791 rx_buffer_info = &rx_ring->rx_buffer_info[i];
792 rx_desc = IXGBE_RX_DESC(rx_ring, i);
793 u0 = (struct my_u0 *)rx_desc;
794 if (rx_desc->wb.upper.length) {
795 /* Descriptor Done */
796 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n",
797 i,
798 le64_to_cpu((__force __le64)u0->a),
799 le64_to_cpu((__force __le64)u0->b),
800 rx_buffer_info->skb,
801 ring_desc);
802 } else {
803 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n",
804 i,
805 le64_to_cpu((__force __le64)u0->a),
806 le64_to_cpu((__force __le64)u0->b),
807 (u64)rx_buffer_info->dma,
808 rx_buffer_info->skb,
809 ring_desc);
810
811 if (netif_msg_pktdata(adapter) &&
812 rx_buffer_info->dma) {
813 print_hex_dump(KERN_INFO, "",
814 DUMP_PREFIX_ADDRESS, 16, 1,
815 page_address(rx_buffer_info->page) +
816 rx_buffer_info->page_offset,
817 ixgbe_rx_bufsz(rx_ring), true);
818 }
819 }
820 }
821 }
822 }
823
824 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
825 {
826 u32 ctrl_ext;
827
828 /* Let firmware take over control of h/w */
829 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
830 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
831 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
832 }
833
834 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
835 {
836 u32 ctrl_ext;
837
838 /* Let firmware know the driver has taken over */
839 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
840 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
841 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
842 }
843
844 /**
845 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
846 * @adapter: pointer to adapter struct
847 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
848 * @queue: queue to map the corresponding interrupt to
849 * @msix_vector: the vector to map to the corresponding queue
850 *
851 */
852 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
853 u8 queue, u8 msix_vector)
854 {
855 u32 ivar, index;
856 struct ixgbe_hw *hw = &adapter->hw;
857 switch (hw->mac.type) {
858 case ixgbe_mac_82598EB:
859 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
860 if (direction == -1)
861 direction = 0;
862 index = (((direction * 64) + queue) >> 2) & 0x1F;
863 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
864 ivar &= ~(0xFF << (8 * (queue & 0x3)));
865 ivar |= (msix_vector << (8 * (queue & 0x3)));
866 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
867 break;
868 case ixgbe_mac_82599EB:
869 case ixgbe_mac_X540:
870 case ixgbe_mac_X550:
871 case ixgbe_mac_X550EM_x:
872 case ixgbe_mac_x550em_a:
873 if (direction == -1) {
874 /* other causes */
875 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
876 index = ((queue & 1) * 8);
877 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
878 ivar &= ~(0xFF << index);
879 ivar |= (msix_vector << index);
880 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
881 break;
882 } else {
883 /* tx or rx causes */
884 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
885 index = ((16 * (queue & 1)) + (8 * direction));
886 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
887 ivar &= ~(0xFF << index);
888 ivar |= (msix_vector << index);
889 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
890 break;
891 }
892 default:
893 break;
894 }
895 }
896
897 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
898 u64 qmask)
899 {
900 u32 mask;
901
902 switch (adapter->hw.mac.type) {
903 case ixgbe_mac_82598EB:
904 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
905 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
906 break;
907 case ixgbe_mac_82599EB:
908 case ixgbe_mac_X540:
909 case ixgbe_mac_X550:
910 case ixgbe_mac_X550EM_x:
911 case ixgbe_mac_x550em_a:
912 mask = (qmask & 0xFFFFFFFF);
913 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
914 mask = (qmask >> 32);
915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
916 break;
917 default:
918 break;
919 }
920 }
921
922 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
923 {
924 struct ixgbe_hw *hw = &adapter->hw;
925 struct ixgbe_hw_stats *hwstats = &adapter->stats;
926 int i;
927 u32 data;
928
929 if ((hw->fc.current_mode != ixgbe_fc_full) &&
930 (hw->fc.current_mode != ixgbe_fc_rx_pause))
931 return;
932
933 switch (hw->mac.type) {
934 case ixgbe_mac_82598EB:
935 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
936 break;
937 default:
938 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
939 }
940 hwstats->lxoffrxc += data;
941
942 /* refill credits (no tx hang) if we received xoff */
943 if (!data)
944 return;
945
946 for (i = 0; i < adapter->num_tx_queues; i++)
947 clear_bit(__IXGBE_HANG_CHECK_ARMED,
948 &adapter->tx_ring[i]->state);
949
950 for (i = 0; i < adapter->num_xdp_queues; i++)
951 clear_bit(__IXGBE_HANG_CHECK_ARMED,
952 &adapter->xdp_ring[i]->state);
953 }
954
955 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
956 {
957 struct ixgbe_hw *hw = &adapter->hw;
958 struct ixgbe_hw_stats *hwstats = &adapter->stats;
959 u32 xoff[8] = {0};
960 u8 tc;
961 int i;
962 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
963
964 if (adapter->ixgbe_ieee_pfc)
965 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
966
967 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
968 ixgbe_update_xoff_rx_lfc(adapter);
969 return;
970 }
971
972 /* update stats for each tc, only valid with PFC enabled */
973 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
974 u32 pxoffrxc;
975
976 switch (hw->mac.type) {
977 case ixgbe_mac_82598EB:
978 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
979 break;
980 default:
981 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
982 }
983 hwstats->pxoffrxc[i] += pxoffrxc;
984 /* Get the TC for given UP */
985 tc = netdev_get_prio_tc_map(adapter->netdev, i);
986 xoff[tc] += pxoffrxc;
987 }
988
989 /* disarm tx queues that have received xoff frames */
990 for (i = 0; i < adapter->num_tx_queues; i++) {
991 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
992
993 tc = tx_ring->dcb_tc;
994 if (xoff[tc])
995 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
996 }
997
998 for (i = 0; i < adapter->num_xdp_queues; i++) {
999 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i];
1000
1001 tc = xdp_ring->dcb_tc;
1002 if (xoff[tc])
1003 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state);
1004 }
1005 }
1006
1007 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1008 {
1009 return ring->stats.packets;
1010 }
1011
1012 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1013 {
1014 unsigned int head, tail;
1015
1016 head = ring->next_to_clean;
1017 tail = ring->next_to_use;
1018
1019 return ((head <= tail) ? tail : tail + ring->count) - head;
1020 }
1021
1022 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1023 {
1024 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1025 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1026 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1027
1028 clear_check_for_tx_hang(tx_ring);
1029
1030 /*
1031 * Check for a hung queue, but be thorough. This verifies
1032 * that a transmit has been completed since the previous
1033 * check AND there is at least one packet pending. The
1034 * ARMED bit is set to indicate a potential hang. The
1035 * bit is cleared if a pause frame is received to remove
1036 * false hang detection due to PFC or 802.3x frames. By
1037 * requiring this to fail twice we avoid races with
1038 * pfc clearing the ARMED bit and conditions where we
1039 * run the check_tx_hang logic with a transmit completion
1040 * pending but without time to complete it yet.
1041 */
1042 if (tx_done_old == tx_done && tx_pending)
1043 /* make sure it is true for two checks in a row */
1044 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1045 &tx_ring->state);
1046 /* update completed stats and continue */
1047 tx_ring->tx_stats.tx_done_old = tx_done;
1048 /* reset the countdown */
1049 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1050
1051 return false;
1052 }
1053
1054 /**
1055 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1056 * @adapter: driver private struct
1057 **/
1058 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1059 {
1060
1061 /* Do the reset outside of interrupt context */
1062 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1063 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
1064 e_warn(drv, "initiating reset due to tx timeout\n");
1065 ixgbe_service_event_schedule(adapter);
1066 }
1067 }
1068
1069 /**
1070 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1071 * @netdev: network interface device structure
1072 * @queue_index: Tx queue to set
1073 * @maxrate: desired maximum transmit bitrate
1074 **/
1075 static int ixgbe_tx_maxrate(struct net_device *netdev,
1076 int queue_index, u32 maxrate)
1077 {
1078 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1079 struct ixgbe_hw *hw = &adapter->hw;
1080 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1081
1082 if (!maxrate)
1083 return 0;
1084
1085 /* Calculate the rate factor values to set */
1086 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1087 bcnrc_val /= maxrate;
1088
1089 /* clear everything but the rate factor */
1090 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1091 IXGBE_RTTBCNRC_RF_DEC_MASK;
1092
1093 /* enable the rate scheduler */
1094 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1095
1096 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1097 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1098
1099 return 0;
1100 }
1101
1102 /**
1103 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1104 * @q_vector: structure containing interrupt and ring information
1105 * @tx_ring: tx ring to clean
1106 * @napi_budget: Used to determine if we are in netpoll
1107 **/
1108 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1109 struct ixgbe_ring *tx_ring, int napi_budget)
1110 {
1111 struct ixgbe_adapter *adapter = q_vector->adapter;
1112 struct ixgbe_tx_buffer *tx_buffer;
1113 union ixgbe_adv_tx_desc *tx_desc;
1114 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0;
1115 unsigned int budget = q_vector->tx.work_limit;
1116 unsigned int i = tx_ring->next_to_clean;
1117
1118 if (test_bit(__IXGBE_DOWN, &adapter->state))
1119 return true;
1120
1121 tx_buffer = &tx_ring->tx_buffer_info[i];
1122 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1123 i -= tx_ring->count;
1124
1125 do {
1126 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1127
1128 /* if next_to_watch is not set then there is no work pending */
1129 if (!eop_desc)
1130 break;
1131
1132 /* prevent any other reads prior to eop_desc */
1133 smp_rmb();
1134
1135 /* if DD is not set pending work has not been completed */
1136 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1137 break;
1138
1139 /* clear next_to_watch to prevent false hangs */
1140 tx_buffer->next_to_watch = NULL;
1141
1142 /* update the statistics for this packet */
1143 total_bytes += tx_buffer->bytecount;
1144 total_packets += tx_buffer->gso_segs;
1145 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC)
1146 total_ipsec++;
1147
1148 /* free the skb */
1149 if (ring_is_xdp(tx_ring))
1150 xdp_return_frame(tx_buffer->xdpf);
1151 else
1152 napi_consume_skb(tx_buffer->skb, napi_budget);
1153
1154 /* unmap skb header data */
1155 dma_unmap_single(tx_ring->dev,
1156 dma_unmap_addr(tx_buffer, dma),
1157 dma_unmap_len(tx_buffer, len),
1158 DMA_TO_DEVICE);
1159
1160 /* clear tx_buffer data */
1161 dma_unmap_len_set(tx_buffer, len, 0);
1162
1163 /* unmap remaining buffers */
1164 while (tx_desc != eop_desc) {
1165 tx_buffer++;
1166 tx_desc++;
1167 i++;
1168 if (unlikely(!i)) {
1169 i -= tx_ring->count;
1170 tx_buffer = tx_ring->tx_buffer_info;
1171 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1172 }
1173
1174 /* unmap any remaining paged data */
1175 if (dma_unmap_len(tx_buffer, len)) {
1176 dma_unmap_page(tx_ring->dev,
1177 dma_unmap_addr(tx_buffer, dma),
1178 dma_unmap_len(tx_buffer, len),
1179 DMA_TO_DEVICE);
1180 dma_unmap_len_set(tx_buffer, len, 0);
1181 }
1182 }
1183
1184 /* move us one more past the eop_desc for start of next pkt */
1185 tx_buffer++;
1186 tx_desc++;
1187 i++;
1188 if (unlikely(!i)) {
1189 i -= tx_ring->count;
1190 tx_buffer = tx_ring->tx_buffer_info;
1191 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1192 }
1193
1194 /* issue prefetch for next Tx descriptor */
1195 prefetch(tx_desc);
1196
1197 /* update budget accounting */
1198 budget--;
1199 } while (likely(budget));
1200
1201 i += tx_ring->count;
1202 tx_ring->next_to_clean = i;
1203 u64_stats_update_begin(&tx_ring->syncp);
1204 tx_ring->stats.bytes += total_bytes;
1205 tx_ring->stats.packets += total_packets;
1206 u64_stats_update_end(&tx_ring->syncp);
1207 q_vector->tx.total_bytes += total_bytes;
1208 q_vector->tx.total_packets += total_packets;
1209 adapter->tx_ipsec += total_ipsec;
1210
1211 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1212 /* schedule immediate reset if we believe we hung */
1213 struct ixgbe_hw *hw = &adapter->hw;
1214 e_err(drv, "Detected Tx Unit Hang %s\n"
1215 " Tx Queue <%d>\n"
1216 " TDH, TDT <%x>, <%x>\n"
1217 " next_to_use <%x>\n"
1218 " next_to_clean <%x>\n"
1219 "tx_buffer_info[next_to_clean]\n"
1220 " time_stamp <%lx>\n"
1221 " jiffies <%lx>\n",
1222 ring_is_xdp(tx_ring) ? "(XDP)" : "",
1223 tx_ring->queue_index,
1224 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1225 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1226 tx_ring->next_to_use, i,
1227 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1228
1229 if (!ring_is_xdp(tx_ring))
1230 netif_stop_subqueue(tx_ring->netdev,
1231 tx_ring->queue_index);
1232
1233 e_info(probe,
1234 "tx hang %d detected on queue %d, resetting adapter\n",
1235 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1236
1237 /* schedule immediate reset if we believe we hung */
1238 ixgbe_tx_timeout_reset(adapter);
1239
1240 /* the adapter is about to reset, no point in enabling stuff */
1241 return true;
1242 }
1243
1244 if (ring_is_xdp(tx_ring))
1245 return !!budget;
1246
1247 netdev_tx_completed_queue(txring_txq(tx_ring),
1248 total_packets, total_bytes);
1249
1250 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1251 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1252 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1253 /* Make sure that anybody stopping the queue after this
1254 * sees the new next_to_clean.
1255 */
1256 smp_mb();
1257 if (__netif_subqueue_stopped(tx_ring->netdev,
1258 tx_ring->queue_index)
1259 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1260 netif_wake_subqueue(tx_ring->netdev,
1261 tx_ring->queue_index);
1262 ++tx_ring->tx_stats.restart_queue;
1263 }
1264 }
1265
1266 return !!budget;
1267 }
1268
1269 #ifdef CONFIG_IXGBE_DCA
1270 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1271 struct ixgbe_ring *tx_ring,
1272 int cpu)
1273 {
1274 struct ixgbe_hw *hw = &adapter->hw;
1275 u32 txctrl = 0;
1276 u16 reg_offset;
1277
1278 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1279 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1280
1281 switch (hw->mac.type) {
1282 case ixgbe_mac_82598EB:
1283 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1284 break;
1285 case ixgbe_mac_82599EB:
1286 case ixgbe_mac_X540:
1287 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1288 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1289 break;
1290 default:
1291 /* for unknown hardware do not write register */
1292 return;
1293 }
1294
1295 /*
1296 * We can enable relaxed ordering for reads, but not writes when
1297 * DCA is enabled. This is due to a known issue in some chipsets
1298 * which will cause the DCA tag to be cleared.
1299 */
1300 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1301 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1302 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1303
1304 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1305 }
1306
1307 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1308 struct ixgbe_ring *rx_ring,
1309 int cpu)
1310 {
1311 struct ixgbe_hw *hw = &adapter->hw;
1312 u32 rxctrl = 0;
1313 u8 reg_idx = rx_ring->reg_idx;
1314
1315 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1316 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1317
1318 switch (hw->mac.type) {
1319 case ixgbe_mac_82599EB:
1320 case ixgbe_mac_X540:
1321 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1322 break;
1323 default:
1324 break;
1325 }
1326
1327 /*
1328 * We can enable relaxed ordering for reads, but not writes when
1329 * DCA is enabled. This is due to a known issue in some chipsets
1330 * which will cause the DCA tag to be cleared.
1331 */
1332 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1333 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1334 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1335
1336 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1337 }
1338
1339 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1340 {
1341 struct ixgbe_adapter *adapter = q_vector->adapter;
1342 struct ixgbe_ring *ring;
1343 int cpu = get_cpu();
1344
1345 if (q_vector->cpu == cpu)
1346 goto out_no_update;
1347
1348 ixgbe_for_each_ring(ring, q_vector->tx)
1349 ixgbe_update_tx_dca(adapter, ring, cpu);
1350
1351 ixgbe_for_each_ring(ring, q_vector->rx)
1352 ixgbe_update_rx_dca(adapter, ring, cpu);
1353
1354 q_vector->cpu = cpu;
1355 out_no_update:
1356 put_cpu();
1357 }
1358
1359 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1360 {
1361 int i;
1362
1363 /* always use CB2 mode, difference is masked in the CB driver */
1364 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1365 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1366 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1367 else
1368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1369 IXGBE_DCA_CTRL_DCA_DISABLE);
1370
1371 for (i = 0; i < adapter->num_q_vectors; i++) {
1372 adapter->q_vector[i]->cpu = -1;
1373 ixgbe_update_dca(adapter->q_vector[i]);
1374 }
1375 }
1376
1377 static int __ixgbe_notify_dca(struct device *dev, void *data)
1378 {
1379 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1380 unsigned long event = *(unsigned long *)data;
1381
1382 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1383 return 0;
1384
1385 switch (event) {
1386 case DCA_PROVIDER_ADD:
1387 /* if we're already enabled, don't do it again */
1388 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1389 break;
1390 if (dca_add_requester(dev) == 0) {
1391 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1393 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1394 break;
1395 }
1396 /* fall through - DCA is disabled. */
1397 case DCA_PROVIDER_REMOVE:
1398 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1399 dca_remove_requester(dev);
1400 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1401 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1402 IXGBE_DCA_CTRL_DCA_DISABLE);
1403 }
1404 break;
1405 }
1406
1407 return 0;
1408 }
1409
1410 #endif /* CONFIG_IXGBE_DCA */
1411
1412 #define IXGBE_RSS_L4_TYPES_MASK \
1413 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1414 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1415 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1416 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1417
1418 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1419 union ixgbe_adv_rx_desc *rx_desc,
1420 struct sk_buff *skb)
1421 {
1422 u16 rss_type;
1423
1424 if (!(ring->netdev->features & NETIF_F_RXHASH))
1425 return;
1426
1427 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1428 IXGBE_RXDADV_RSSTYPE_MASK;
1429
1430 if (!rss_type)
1431 return;
1432
1433 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1434 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1435 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1436 }
1437
1438 #ifdef IXGBE_FCOE
1439 /**
1440 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1441 * @ring: structure containing ring specific data
1442 * @rx_desc: advanced rx descriptor
1443 *
1444 * Returns : true if it is FCoE pkt
1445 */
1446 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1447 union ixgbe_adv_rx_desc *rx_desc)
1448 {
1449 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1450
1451 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1452 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1453 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1454 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1455 }
1456
1457 #endif /* IXGBE_FCOE */
1458 /**
1459 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1460 * @ring: structure containing ring specific data
1461 * @rx_desc: current Rx descriptor being processed
1462 * @skb: skb currently being received and modified
1463 **/
1464 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1465 union ixgbe_adv_rx_desc *rx_desc,
1466 struct sk_buff *skb)
1467 {
1468 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1469 bool encap_pkt = false;
1470
1471 skb_checksum_none_assert(skb);
1472
1473 /* Rx csum disabled */
1474 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1475 return;
1476
1477 /* check for VXLAN and Geneve packets */
1478 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) {
1479 encap_pkt = true;
1480 skb->encapsulation = 1;
1481 }
1482
1483 /* if IP and error */
1484 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1485 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1486 ring->rx_stats.csum_err++;
1487 return;
1488 }
1489
1490 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1491 return;
1492
1493 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1494 /*
1495 * 82599 errata, UDP frames with a 0 checksum can be marked as
1496 * checksum errors.
1497 */
1498 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1499 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1500 return;
1501
1502 ring->rx_stats.csum_err++;
1503 return;
1504 }
1505
1506 /* It must be a TCP or UDP packet with a valid checksum */
1507 skb->ip_summed = CHECKSUM_UNNECESSARY;
1508 if (encap_pkt) {
1509 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1510 return;
1511
1512 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1513 skb->ip_summed = CHECKSUM_NONE;
1514 return;
1515 }
1516 /* If we checked the outer header let the stack know */
1517 skb->csum_level = 1;
1518 }
1519 }
1520
1521 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring)
1522 {
1523 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0;
1524 }
1525
1526 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1527 struct ixgbe_rx_buffer *bi)
1528 {
1529 struct page *page = bi->page;
1530 dma_addr_t dma;
1531
1532 /* since we are recycling buffers we should seldom need to alloc */
1533 if (likely(page))
1534 return true;
1535
1536 /* alloc new page for storage */
1537 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1538 if (unlikely(!page)) {
1539 rx_ring->rx_stats.alloc_rx_page_failed++;
1540 return false;
1541 }
1542
1543 /* map page for use */
1544 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1545 ixgbe_rx_pg_size(rx_ring),
1546 DMA_FROM_DEVICE,
1547 IXGBE_RX_DMA_ATTR);
1548
1549 /*
1550 * if mapping failed free memory back to system since
1551 * there isn't much point in holding memory we can't use
1552 */
1553 if (dma_mapping_error(rx_ring->dev, dma)) {
1554 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1555
1556 rx_ring->rx_stats.alloc_rx_page_failed++;
1557 return false;
1558 }
1559
1560 bi->dma = dma;
1561 bi->page = page;
1562 bi->page_offset = ixgbe_rx_offset(rx_ring);
1563 page_ref_add(page, USHRT_MAX - 1);
1564 bi->pagecnt_bias = USHRT_MAX;
1565 rx_ring->rx_stats.alloc_rx_page++;
1566
1567 return true;
1568 }
1569
1570 /**
1571 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1572 * @rx_ring: ring to place buffers on
1573 * @cleaned_count: number of buffers to replace
1574 **/
1575 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1576 {
1577 union ixgbe_adv_rx_desc *rx_desc;
1578 struct ixgbe_rx_buffer *bi;
1579 u16 i = rx_ring->next_to_use;
1580 u16 bufsz;
1581
1582 /* nothing to do */
1583 if (!cleaned_count)
1584 return;
1585
1586 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1587 bi = &rx_ring->rx_buffer_info[i];
1588 i -= rx_ring->count;
1589
1590 bufsz = ixgbe_rx_bufsz(rx_ring);
1591
1592 do {
1593 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1594 break;
1595
1596 /* sync the buffer for use by the device */
1597 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1598 bi->page_offset, bufsz,
1599 DMA_FROM_DEVICE);
1600
1601 /*
1602 * Refresh the desc even if buffer_addrs didn't change
1603 * because each write-back erases this info.
1604 */
1605 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1606
1607 rx_desc++;
1608 bi++;
1609 i++;
1610 if (unlikely(!i)) {
1611 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1612 bi = rx_ring->rx_buffer_info;
1613 i -= rx_ring->count;
1614 }
1615
1616 /* clear the length for the next_to_use descriptor */
1617 rx_desc->wb.upper.length = 0;
1618
1619 cleaned_count--;
1620 } while (cleaned_count);
1621
1622 i += rx_ring->count;
1623
1624 if (rx_ring->next_to_use != i) {
1625 rx_ring->next_to_use = i;
1626
1627 /* update next to alloc since we have filled the ring */
1628 rx_ring->next_to_alloc = i;
1629
1630 /* Force memory writes to complete before letting h/w
1631 * know there are new descriptors to fetch. (Only
1632 * applicable for weak-ordered memory model archs,
1633 * such as IA-64).
1634 */
1635 wmb();
1636 writel(i, rx_ring->tail);
1637 }
1638 }
1639
1640 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1641 struct sk_buff *skb)
1642 {
1643 u16 hdr_len = skb_headlen(skb);
1644
1645 /* set gso_size to avoid messing up TCP MSS */
1646 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1647 IXGBE_CB(skb)->append_cnt);
1648 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1649 }
1650
1651 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1652 struct sk_buff *skb)
1653 {
1654 /* if append_cnt is 0 then frame is not RSC */
1655 if (!IXGBE_CB(skb)->append_cnt)
1656 return;
1657
1658 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1659 rx_ring->rx_stats.rsc_flush++;
1660
1661 ixgbe_set_rsc_gso_size(rx_ring, skb);
1662
1663 /* gso_size is computed using append_cnt so always clear it last */
1664 IXGBE_CB(skb)->append_cnt = 0;
1665 }
1666
1667 /**
1668 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1669 * @rx_ring: rx descriptor ring packet is being transacted on
1670 * @rx_desc: pointer to the EOP Rx descriptor
1671 * @skb: pointer to current skb being populated
1672 *
1673 * This function checks the ring, descriptor, and packet information in
1674 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1675 * other fields within the skb.
1676 **/
1677 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1678 union ixgbe_adv_rx_desc *rx_desc,
1679 struct sk_buff *skb)
1680 {
1681 struct net_device *dev = rx_ring->netdev;
1682 u32 flags = rx_ring->q_vector->adapter->flags;
1683
1684 ixgbe_update_rsc_stats(rx_ring, skb);
1685
1686 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1687
1688 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1689
1690 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1691 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1692
1693 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1694 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1695 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1696 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1697 }
1698
1699 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP))
1700 ixgbe_ipsec_rx(rx_ring, rx_desc, skb);
1701
1702 /* record Rx queue, or update MACVLAN statistics */
1703 if (netif_is_ixgbe(dev))
1704 skb_record_rx_queue(skb, rx_ring->queue_index);
1705 else
1706 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true,
1707 false);
1708
1709 skb->protocol = eth_type_trans(skb, dev);
1710 }
1711
1712 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1713 struct sk_buff *skb)
1714 {
1715 napi_gro_receive(&q_vector->napi, skb);
1716 }
1717
1718 /**
1719 * ixgbe_is_non_eop - process handling of non-EOP buffers
1720 * @rx_ring: Rx ring being processed
1721 * @rx_desc: Rx descriptor for current buffer
1722 * @skb: Current socket buffer containing buffer in progress
1723 *
1724 * This function updates next to clean. If the buffer is an EOP buffer
1725 * this function exits returning false, otherwise it will place the
1726 * sk_buff in the next buffer to be chained and return true indicating
1727 * that this is in fact a non-EOP buffer.
1728 **/
1729 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1730 union ixgbe_adv_rx_desc *rx_desc,
1731 struct sk_buff *skb)
1732 {
1733 u32 ntc = rx_ring->next_to_clean + 1;
1734
1735 /* fetch, update, and store next to clean */
1736 ntc = (ntc < rx_ring->count) ? ntc : 0;
1737 rx_ring->next_to_clean = ntc;
1738
1739 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1740
1741 /* update RSC append count if present */
1742 if (ring_is_rsc_enabled(rx_ring)) {
1743 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1744 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1745
1746 if (unlikely(rsc_enabled)) {
1747 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1748
1749 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1750 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1751
1752 /* update ntc based on RSC value */
1753 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1754 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1755 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1756 }
1757 }
1758
1759 /* if we are the last buffer then there is nothing else to do */
1760 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1761 return false;
1762
1763 /* place skb in next buffer to be received */
1764 rx_ring->rx_buffer_info[ntc].skb = skb;
1765 rx_ring->rx_stats.non_eop_descs++;
1766
1767 return true;
1768 }
1769
1770 /**
1771 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1772 * @rx_ring: rx descriptor ring packet is being transacted on
1773 * @skb: pointer to current skb being adjusted
1774 *
1775 * This function is an ixgbe specific version of __pskb_pull_tail. The
1776 * main difference between this version and the original function is that
1777 * this function can make several assumptions about the state of things
1778 * that allow for significant optimizations versus the standard function.
1779 * As a result we can do things like drop a frag and maintain an accurate
1780 * truesize for the skb.
1781 */
1782 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1783 struct sk_buff *skb)
1784 {
1785 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1786 unsigned char *va;
1787 unsigned int pull_len;
1788
1789 /*
1790 * it is valid to use page_address instead of kmap since we are
1791 * working with pages allocated out of the lomem pool per
1792 * alloc_page(GFP_ATOMIC)
1793 */
1794 va = skb_frag_address(frag);
1795
1796 /*
1797 * we need the header to contain the greater of either ETH_HLEN or
1798 * 60 bytes if the skb->len is less than 60 for skb_pad.
1799 */
1800 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1801
1802 /* align pull length to size of long to optimize memcpy performance */
1803 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1804
1805 /* update all of the pointers */
1806 skb_frag_size_sub(frag, pull_len);
1807 frag->page_offset += pull_len;
1808 skb->data_len -= pull_len;
1809 skb->tail += pull_len;
1810 }
1811
1812 /**
1813 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1814 * @rx_ring: rx descriptor ring packet is being transacted on
1815 * @skb: pointer to current skb being updated
1816 *
1817 * This function provides a basic DMA sync up for the first fragment of an
1818 * skb. The reason for doing this is that the first fragment cannot be
1819 * unmapped until we have reached the end of packet descriptor for a buffer
1820 * chain.
1821 */
1822 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1823 struct sk_buff *skb)
1824 {
1825 if (ring_uses_build_skb(rx_ring)) {
1826 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK;
1827
1828 dma_sync_single_range_for_cpu(rx_ring->dev,
1829 IXGBE_CB(skb)->dma,
1830 offset,
1831 skb_headlen(skb),
1832 DMA_FROM_DEVICE);
1833 } else {
1834 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1835
1836 dma_sync_single_range_for_cpu(rx_ring->dev,
1837 IXGBE_CB(skb)->dma,
1838 frag->page_offset,
1839 skb_frag_size(frag),
1840 DMA_FROM_DEVICE);
1841 }
1842
1843 /* If the page was released, just unmap it. */
1844 if (unlikely(IXGBE_CB(skb)->page_released)) {
1845 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
1846 ixgbe_rx_pg_size(rx_ring),
1847 DMA_FROM_DEVICE,
1848 IXGBE_RX_DMA_ATTR);
1849 }
1850 }
1851
1852 /**
1853 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1854 * @rx_ring: rx descriptor ring packet is being transacted on
1855 * @rx_desc: pointer to the EOP Rx descriptor
1856 * @skb: pointer to current skb being fixed
1857 *
1858 * Check if the skb is valid in the XDP case it will be an error pointer.
1859 * Return true in this case to abort processing and advance to next
1860 * descriptor.
1861 *
1862 * Check for corrupted packet headers caused by senders on the local L2
1863 * embedded NIC switch not setting up their Tx Descriptors right. These
1864 * should be very rare.
1865 *
1866 * Also address the case where we are pulling data in on pages only
1867 * and as such no data is present in the skb header.
1868 *
1869 * In addition if skb is not at least 60 bytes we need to pad it so that
1870 * it is large enough to qualify as a valid Ethernet frame.
1871 *
1872 * Returns true if an error was encountered and skb was freed.
1873 **/
1874 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1875 union ixgbe_adv_rx_desc *rx_desc,
1876 struct sk_buff *skb)
1877 {
1878 struct net_device *netdev = rx_ring->netdev;
1879
1880 /* XDP packets use error pointer so abort at this point */
1881 if (IS_ERR(skb))
1882 return true;
1883
1884 /* Verify netdev is present, and that packet does not have any
1885 * errors that would be unacceptable to the netdev.
1886 */
1887 if (!netdev ||
1888 (unlikely(ixgbe_test_staterr(rx_desc,
1889 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1890 !(netdev->features & NETIF_F_RXALL)))) {
1891 dev_kfree_skb_any(skb);
1892 return true;
1893 }
1894
1895 /* place header in linear portion of buffer */
1896 if (!skb_headlen(skb))
1897 ixgbe_pull_tail(rx_ring, skb);
1898
1899 #ifdef IXGBE_FCOE
1900 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1901 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1902 return false;
1903
1904 #endif
1905 /* if eth_skb_pad returns an error the skb was freed */
1906 if (eth_skb_pad(skb))
1907 return true;
1908
1909 return false;
1910 }
1911
1912 /**
1913 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1914 * @rx_ring: rx descriptor ring to store buffers on
1915 * @old_buff: donor buffer to have page reused
1916 *
1917 * Synchronizes page for reuse by the adapter
1918 **/
1919 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1920 struct ixgbe_rx_buffer *old_buff)
1921 {
1922 struct ixgbe_rx_buffer *new_buff;
1923 u16 nta = rx_ring->next_to_alloc;
1924
1925 new_buff = &rx_ring->rx_buffer_info[nta];
1926
1927 /* update, and store next to alloc */
1928 nta++;
1929 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1930
1931 /* Transfer page from old buffer to new buffer.
1932 * Move each member individually to avoid possible store
1933 * forwarding stalls and unnecessary copy of skb.
1934 */
1935 new_buff->dma = old_buff->dma;
1936 new_buff->page = old_buff->page;
1937 new_buff->page_offset = old_buff->page_offset;
1938 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1939 }
1940
1941 static inline bool ixgbe_page_is_reserved(struct page *page)
1942 {
1943 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1944 }
1945
1946 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer)
1947 {
1948 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1949 struct page *page = rx_buffer->page;
1950
1951 /* avoid re-using remote pages */
1952 if (unlikely(ixgbe_page_is_reserved(page)))
1953 return false;
1954
1955 #if (PAGE_SIZE < 8192)
1956 /* if we are only owner of page we can reuse it */
1957 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1))
1958 return false;
1959 #else
1960 /* The last offset is a bit aggressive in that we assume the
1961 * worst case of FCoE being enabled and using a 3K buffer.
1962 * However this should have minimal impact as the 1K extra is
1963 * still less than one buffer in size.
1964 */
1965 #define IXGBE_LAST_OFFSET \
1966 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K)
1967 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET)
1968 return false;
1969 #endif
1970
1971 /* If we have drained the page fragment pool we need to update
1972 * the pagecnt_bias and page count so that we fully restock the
1973 * number of references the driver holds.
1974 */
1975 if (unlikely(pagecnt_bias == 1)) {
1976 page_ref_add(page, USHRT_MAX - 1);
1977 rx_buffer->pagecnt_bias = USHRT_MAX;
1978 }
1979
1980 return true;
1981 }
1982
1983 /**
1984 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1985 * @rx_ring: rx descriptor ring to transact packets on
1986 * @rx_buffer: buffer containing page to add
1987 * @skb: sk_buff to place the data into
1988 * @size: size of data in rx_buffer
1989 *
1990 * This function will add the data contained in rx_buffer->page to the skb.
1991 * This is done either through a direct copy if the data in the buffer is
1992 * less than the skb header size, otherwise it will just attach the page as
1993 * a frag to the skb.
1994 *
1995 * The function will then update the page offset if necessary and return
1996 * true if the buffer can be reused by the adapter.
1997 **/
1998 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1999 struct ixgbe_rx_buffer *rx_buffer,
2000 struct sk_buff *skb,
2001 unsigned int size)
2002 {
2003 #if (PAGE_SIZE < 8192)
2004 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2005 #else
2006 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
2007 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) :
2008 SKB_DATA_ALIGN(size);
2009 #endif
2010 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
2011 rx_buffer->page_offset, size, truesize);
2012 #if (PAGE_SIZE < 8192)
2013 rx_buffer->page_offset ^= truesize;
2014 #else
2015 rx_buffer->page_offset += truesize;
2016 #endif
2017 }
2018
2019 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring,
2020 union ixgbe_adv_rx_desc *rx_desc,
2021 struct sk_buff **skb,
2022 const unsigned int size)
2023 {
2024 struct ixgbe_rx_buffer *rx_buffer;
2025
2026 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2027 prefetchw(rx_buffer->page);
2028 *skb = rx_buffer->skb;
2029
2030 /* Delay unmapping of the first packet. It carries the header
2031 * information, HW may still access the header after the writeback.
2032 * Only unmap it when EOP is reached
2033 */
2034 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) {
2035 if (!*skb)
2036 goto skip_sync;
2037 } else {
2038 if (*skb)
2039 ixgbe_dma_sync_frag(rx_ring, *skb);
2040 }
2041
2042 /* we are reusing so sync this buffer for CPU use */
2043 dma_sync_single_range_for_cpu(rx_ring->dev,
2044 rx_buffer->dma,
2045 rx_buffer->page_offset,
2046 size,
2047 DMA_FROM_DEVICE);
2048 skip_sync:
2049 rx_buffer->pagecnt_bias--;
2050
2051 return rx_buffer;
2052 }
2053
2054 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring,
2055 struct ixgbe_rx_buffer *rx_buffer,
2056 struct sk_buff *skb)
2057 {
2058 if (ixgbe_can_reuse_rx_page(rx_buffer)) {
2059 /* hand second half of page back to the ring */
2060 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2061 } else {
2062 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) {
2063 /* the page has been released from the ring */
2064 IXGBE_CB(skb)->page_released = true;
2065 } else {
2066 /* we are not reusing the buffer so unmap it */
2067 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2068 ixgbe_rx_pg_size(rx_ring),
2069 DMA_FROM_DEVICE,
2070 IXGBE_RX_DMA_ATTR);
2071 }
2072 __page_frag_cache_drain(rx_buffer->page,
2073 rx_buffer->pagecnt_bias);
2074 }
2075
2076 /* clear contents of rx_buffer */
2077 rx_buffer->page = NULL;
2078 rx_buffer->skb = NULL;
2079 }
2080
2081 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring,
2082 struct ixgbe_rx_buffer *rx_buffer,
2083 struct xdp_buff *xdp,
2084 union ixgbe_adv_rx_desc *rx_desc)
2085 {
2086 unsigned int size = xdp->data_end - xdp->data;
2087 #if (PAGE_SIZE < 8192)
2088 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2089 #else
2090 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
2091 xdp->data_hard_start);
2092 #endif
2093 struct sk_buff *skb;
2094
2095 /* prefetch first cache line of first page */
2096 prefetch(xdp->data);
2097 #if L1_CACHE_BYTES < 128
2098 prefetch(xdp->data + L1_CACHE_BYTES);
2099 #endif
2100 /* Note, we get here by enabling legacy-rx via:
2101 *
2102 * ethtool --set-priv-flags <dev> legacy-rx on
2103 *
2104 * In this mode, we currently get 0 extra XDP headroom as
2105 * opposed to having legacy-rx off, where we process XDP
2106 * packets going to stack via ixgbe_build_skb(). The latter
2107 * provides us currently with 192 bytes of headroom.
2108 *
2109 * For ixgbe_construct_skb() mode it means that the
2110 * xdp->data_meta will always point to xdp->data, since
2111 * the helper cannot expand the head. Should this ever
2112 * change in future for legacy-rx mode on, then lets also
2113 * add xdp->data_meta handling here.
2114 */
2115
2116 /* allocate a skb to store the frags */
2117 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE);
2118 if (unlikely(!skb))
2119 return NULL;
2120
2121 if (size > IXGBE_RX_HDR_SIZE) {
2122 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2123 IXGBE_CB(skb)->dma = rx_buffer->dma;
2124
2125 skb_add_rx_frag(skb, 0, rx_buffer->page,
2126 xdp->data - page_address(rx_buffer->page),
2127 size, truesize);
2128 #if (PAGE_SIZE < 8192)
2129 rx_buffer->page_offset ^= truesize;
2130 #else
2131 rx_buffer->page_offset += truesize;
2132 #endif
2133 } else {
2134 memcpy(__skb_put(skb, size),
2135 xdp->data, ALIGN(size, sizeof(long)));
2136 rx_buffer->pagecnt_bias++;
2137 }
2138
2139 return skb;
2140 }
2141
2142 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring,
2143 struct ixgbe_rx_buffer *rx_buffer,
2144 struct xdp_buff *xdp,
2145 union ixgbe_adv_rx_desc *rx_desc)
2146 {
2147 unsigned int metasize = xdp->data - xdp->data_meta;
2148 #if (PAGE_SIZE < 8192)
2149 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2150 #else
2151 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2152 SKB_DATA_ALIGN(xdp->data_end -
2153 xdp->data_hard_start);
2154 #endif
2155 struct sk_buff *skb;
2156
2157 /* Prefetch first cache line of first page. If xdp->data_meta
2158 * is unused, this points extactly as xdp->data, otherwise we
2159 * likely have a consumer accessing first few bytes of meta
2160 * data, and then actual data.
2161 */
2162 prefetch(xdp->data_meta);
2163 #if L1_CACHE_BYTES < 128
2164 prefetch(xdp->data_meta + L1_CACHE_BYTES);
2165 #endif
2166
2167 /* build an skb to around the page buffer */
2168 skb = build_skb(xdp->data_hard_start, truesize);
2169 if (unlikely(!skb))
2170 return NULL;
2171
2172 /* update pointers within the skb to store the data */
2173 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2174 __skb_put(skb, xdp->data_end - xdp->data);
2175 if (metasize)
2176 skb_metadata_set(skb, metasize);
2177
2178 /* record DMA address if this is the start of a chain of buffers */
2179 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2180 IXGBE_CB(skb)->dma = rx_buffer->dma;
2181
2182 /* update buffer offset */
2183 #if (PAGE_SIZE < 8192)
2184 rx_buffer->page_offset ^= truesize;
2185 #else
2186 rx_buffer->page_offset += truesize;
2187 #endif
2188
2189 return skb;
2190 }
2191
2192 #define IXGBE_XDP_PASS 0
2193 #define IXGBE_XDP_CONSUMED BIT(0)
2194 #define IXGBE_XDP_TX BIT(1)
2195 #define IXGBE_XDP_REDIR BIT(2)
2196
2197 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter,
2198 struct xdp_frame *xdpf);
2199
2200 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter,
2201 struct ixgbe_ring *rx_ring,
2202 struct xdp_buff *xdp)
2203 {
2204 int err, result = IXGBE_XDP_PASS;
2205 struct bpf_prog *xdp_prog;
2206 struct xdp_frame *xdpf;
2207 u32 act;
2208
2209 rcu_read_lock();
2210 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2211
2212 if (!xdp_prog)
2213 goto xdp_out;
2214
2215 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2216
2217 act = bpf_prog_run_xdp(xdp_prog, xdp);
2218 switch (act) {
2219 case XDP_PASS:
2220 break;
2221 case XDP_TX:
2222 xdpf = convert_to_xdp_frame(xdp);
2223 if (unlikely(!xdpf)) {
2224 result = IXGBE_XDP_CONSUMED;
2225 break;
2226 }
2227 result = ixgbe_xmit_xdp_ring(adapter, xdpf);
2228 break;
2229 case XDP_REDIRECT:
2230 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
2231 if (!err)
2232 result = IXGBE_XDP_REDIR;
2233 else
2234 result = IXGBE_XDP_CONSUMED;
2235 break;
2236 default:
2237 bpf_warn_invalid_xdp_action(act);
2238 /* fallthrough */
2239 case XDP_ABORTED:
2240 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2241 /* fallthrough -- handle aborts by dropping packet */
2242 case XDP_DROP:
2243 result = IXGBE_XDP_CONSUMED;
2244 break;
2245 }
2246 xdp_out:
2247 rcu_read_unlock();
2248 return ERR_PTR(-result);
2249 }
2250
2251 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring,
2252 struct ixgbe_rx_buffer *rx_buffer,
2253 unsigned int size)
2254 {
2255 #if (PAGE_SIZE < 8192)
2256 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2257
2258 rx_buffer->page_offset ^= truesize;
2259 #else
2260 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
2261 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) +
2262 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
2263 SKB_DATA_ALIGN(size);
2264
2265 rx_buffer->page_offset += truesize;
2266 #endif
2267 }
2268
2269 /**
2270 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2271 * @q_vector: structure containing interrupt and ring information
2272 * @rx_ring: rx descriptor ring to transact packets on
2273 * @budget: Total limit on number of packets to process
2274 *
2275 * This function provides a "bounce buffer" approach to Rx interrupt
2276 * processing. The advantage to this is that on systems that have
2277 * expensive overhead for IOMMU access this provides a means of avoiding
2278 * it by maintaining the mapping of the page to the syste.
2279 *
2280 * Returns amount of work completed
2281 **/
2282 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2283 struct ixgbe_ring *rx_ring,
2284 const int budget)
2285 {
2286 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2287 struct ixgbe_adapter *adapter = q_vector->adapter;
2288 #ifdef IXGBE_FCOE
2289 int ddp_bytes;
2290 unsigned int mss = 0;
2291 #endif /* IXGBE_FCOE */
2292 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2293 unsigned int xdp_xmit = 0;
2294 struct xdp_buff xdp;
2295
2296 xdp.rxq = &rx_ring->xdp_rxq;
2297
2298 while (likely(total_rx_packets < budget)) {
2299 union ixgbe_adv_rx_desc *rx_desc;
2300 struct ixgbe_rx_buffer *rx_buffer;
2301 struct sk_buff *skb;
2302 unsigned int size;
2303
2304 /* return some buffers to hardware, one at a time is too slow */
2305 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2306 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2307 cleaned_count = 0;
2308 }
2309
2310 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2311 size = le16_to_cpu(rx_desc->wb.upper.length);
2312 if (!size)
2313 break;
2314
2315 /* This memory barrier is needed to keep us from reading
2316 * any other fields out of the rx_desc until we know the
2317 * descriptor has been written back
2318 */
2319 dma_rmb();
2320
2321 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size);
2322
2323 /* retrieve a buffer from the ring */
2324 if (!skb) {
2325 xdp.data = page_address(rx_buffer->page) +
2326 rx_buffer->page_offset;
2327 xdp.data_meta = xdp.data;
2328 xdp.data_hard_start = xdp.data -
2329 ixgbe_rx_offset(rx_ring);
2330 xdp.data_end = xdp.data + size;
2331
2332 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp);
2333 }
2334
2335 if (IS_ERR(skb)) {
2336 unsigned int xdp_res = -PTR_ERR(skb);
2337
2338 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) {
2339 xdp_xmit |= xdp_res;
2340 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size);
2341 } else {
2342 rx_buffer->pagecnt_bias++;
2343 }
2344 total_rx_packets++;
2345 total_rx_bytes += size;
2346 } else if (skb) {
2347 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size);
2348 } else if (ring_uses_build_skb(rx_ring)) {
2349 skb = ixgbe_build_skb(rx_ring, rx_buffer,
2350 &xdp, rx_desc);
2351 } else {
2352 skb = ixgbe_construct_skb(rx_ring, rx_buffer,
2353 &xdp, rx_desc);
2354 }
2355
2356 /* exit if we failed to retrieve a buffer */
2357 if (!skb) {
2358 rx_ring->rx_stats.alloc_rx_buff_failed++;
2359 rx_buffer->pagecnt_bias++;
2360 break;
2361 }
2362
2363 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb);
2364 cleaned_count++;
2365
2366 /* place incomplete frames back on ring for completion */
2367 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2368 continue;
2369
2370 /* verify the packet layout is correct */
2371 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2372 continue;
2373
2374 /* probably a little skewed due to removing CRC */
2375 total_rx_bytes += skb->len;
2376
2377 /* populate checksum, timestamp, VLAN, and protocol */
2378 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2379
2380 #ifdef IXGBE_FCOE
2381 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2382 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2383 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2384 /* include DDPed FCoE data */
2385 if (ddp_bytes > 0) {
2386 if (!mss) {
2387 mss = rx_ring->netdev->mtu -
2388 sizeof(struct fcoe_hdr) -
2389 sizeof(struct fc_frame_header) -
2390 sizeof(struct fcoe_crc_eof);
2391 if (mss > 512)
2392 mss &= ~511;
2393 }
2394 total_rx_bytes += ddp_bytes;
2395 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2396 mss);
2397 }
2398 if (!ddp_bytes) {
2399 dev_kfree_skb_any(skb);
2400 continue;
2401 }
2402 }
2403
2404 #endif /* IXGBE_FCOE */
2405 ixgbe_rx_skb(q_vector, skb);
2406
2407 /* update budget accounting */
2408 total_rx_packets++;
2409 }
2410
2411 if (xdp_xmit & IXGBE_XDP_REDIR)
2412 xdp_do_flush_map();
2413
2414 if (xdp_xmit & IXGBE_XDP_TX) {
2415 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
2416
2417 /* Force memory writes to complete before letting h/w
2418 * know there are new descriptors to fetch.
2419 */
2420 wmb();
2421 writel(ring->next_to_use, ring->tail);
2422 }
2423
2424 u64_stats_update_begin(&rx_ring->syncp);
2425 rx_ring->stats.packets += total_rx_packets;
2426 rx_ring->stats.bytes += total_rx_bytes;
2427 u64_stats_update_end(&rx_ring->syncp);
2428 q_vector->rx.total_packets += total_rx_packets;
2429 q_vector->rx.total_bytes += total_rx_bytes;
2430
2431 return total_rx_packets;
2432 }
2433
2434 /**
2435 * ixgbe_configure_msix - Configure MSI-X hardware
2436 * @adapter: board private structure
2437 *
2438 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2439 * interrupts.
2440 **/
2441 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2442 {
2443 struct ixgbe_q_vector *q_vector;
2444 int v_idx;
2445 u32 mask;
2446
2447 /* Populate MSIX to EITR Select */
2448 if (adapter->num_vfs > 32) {
2449 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
2450 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2451 }
2452
2453 /*
2454 * Populate the IVAR table and set the ITR values to the
2455 * corresponding register.
2456 */
2457 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2458 struct ixgbe_ring *ring;
2459 q_vector = adapter->q_vector[v_idx];
2460
2461 ixgbe_for_each_ring(ring, q_vector->rx)
2462 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2463
2464 ixgbe_for_each_ring(ring, q_vector->tx)
2465 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2466
2467 ixgbe_write_eitr(q_vector);
2468 }
2469
2470 switch (adapter->hw.mac.type) {
2471 case ixgbe_mac_82598EB:
2472 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2473 v_idx);
2474 break;
2475 case ixgbe_mac_82599EB:
2476 case ixgbe_mac_X540:
2477 case ixgbe_mac_X550:
2478 case ixgbe_mac_X550EM_x:
2479 case ixgbe_mac_x550em_a:
2480 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2481 break;
2482 default:
2483 break;
2484 }
2485 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2486
2487 /* set up to autoclear timer, and the vectors */
2488 mask = IXGBE_EIMS_ENABLE_MASK;
2489 mask &= ~(IXGBE_EIMS_OTHER |
2490 IXGBE_EIMS_MAILBOX |
2491 IXGBE_EIMS_LSC);
2492
2493 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2494 }
2495
2496 /**
2497 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2498 * @q_vector: structure containing interrupt and ring information
2499 * @ring_container: structure containing ring performance data
2500 *
2501 * Stores a new ITR value based on packets and byte
2502 * counts during the last interrupt. The advantage of per interrupt
2503 * computation is faster updates and more accurate ITR for the current
2504 * traffic pattern. Constants in this function were computed
2505 * based on theoretical maximum wire speed and thresholds were set based
2506 * on testing data as well as attempting to minimize response time
2507 * while increasing bulk throughput.
2508 **/
2509 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2510 struct ixgbe_ring_container *ring_container)
2511 {
2512 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS |
2513 IXGBE_ITR_ADAPTIVE_LATENCY;
2514 unsigned int avg_wire_size, packets, bytes;
2515 unsigned long next_update = jiffies;
2516
2517 /* If we don't have any rings just leave ourselves set for maximum
2518 * possible latency so we take ourselves out of the equation.
2519 */
2520 if (!ring_container->ring)
2521 return;
2522
2523 /* If we didn't update within up to 1 - 2 jiffies we can assume
2524 * that either packets are coming in so slow there hasn't been
2525 * any work, or that there is so much work that NAPI is dealing
2526 * with interrupt moderation and we don't need to do anything.
2527 */
2528 if (time_after(next_update, ring_container->next_update))
2529 goto clear_counts;
2530
2531 packets = ring_container->total_packets;
2532
2533 /* We have no packets to actually measure against. This means
2534 * either one of the other queues on this vector is active or
2535 * we are a Tx queue doing TSO with too high of an interrupt rate.
2536 *
2537 * When this occurs just tick up our delay by the minimum value
2538 * and hope that this extra delay will prevent us from being called
2539 * without any work on our queue.
2540 */
2541 if (!packets) {
2542 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2543 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2544 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2545 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY;
2546 goto clear_counts;
2547 }
2548
2549 bytes = ring_container->total_bytes;
2550
2551 /* If packets are less than 4 or bytes are less than 9000 assume
2552 * insufficient data to use bulk rate limiting approach. We are
2553 * likely latency driven.
2554 */
2555 if (packets < 4 && bytes < 9000) {
2556 itr = IXGBE_ITR_ADAPTIVE_LATENCY;
2557 goto adjust_by_size;
2558 }
2559
2560 /* Between 4 and 48 we can assume that our current interrupt delay
2561 * is only slightly too low. As such we should increase it by a small
2562 * fixed amount.
2563 */
2564 if (packets < 48) {
2565 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2566 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2567 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2568 goto clear_counts;
2569 }
2570
2571 /* Between 48 and 96 is our "goldilocks" zone where we are working
2572 * out "just right". Just report that our current ITR is good for us.
2573 */
2574 if (packets < 96) {
2575 itr = q_vector->itr >> 2;
2576 goto clear_counts;
2577 }
2578
2579 /* If packet count is 96 or greater we are likely looking at a slight
2580 * overrun of the delay we want. Try halving our delay to see if that
2581 * will cut the number of packets in half per interrupt.
2582 */
2583 if (packets < 256) {
2584 itr = q_vector->itr >> 3;
2585 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS)
2586 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS;
2587 goto clear_counts;
2588 }
2589
2590 /* The paths below assume we are dealing with a bulk ITR since number
2591 * of packets is 256 or greater. We are just going to have to compute
2592 * a value and try to bring the count under control, though for smaller
2593 * packet sizes there isn't much we can do as NAPI polling will likely
2594 * be kicking in sooner rather than later.
2595 */
2596 itr = IXGBE_ITR_ADAPTIVE_BULK;
2597
2598 adjust_by_size:
2599 /* If packet counts are 256 or greater we can assume we have a gross
2600 * overestimation of what the rate should be. Instead of trying to fine
2601 * tune it just use the formula below to try and dial in an exact value
2602 * give the current packet size of the frame.
2603 */
2604 avg_wire_size = bytes / packets;
2605
2606 /* The following is a crude approximation of:
2607 * wmem_default / (size + overhead) = desired_pkts_per_int
2608 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
2609 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
2610 *
2611 * Assuming wmem_default is 212992 and overhead is 640 bytes per
2612 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
2613 * formula down to
2614 *
2615 * (170 * (size + 24)) / (size + 640) = ITR
2616 *
2617 * We first do some math on the packet size and then finally bitshift
2618 * by 8 after rounding up. We also have to account for PCIe link speed
2619 * difference as ITR scales based on this.
2620 */
2621 if (avg_wire_size <= 60) {
2622 /* Start at 50k ints/sec */
2623 avg_wire_size = 5120;
2624 } else if (avg_wire_size <= 316) {
2625 /* 50K ints/sec to 16K ints/sec */
2626 avg_wire_size *= 40;
2627 avg_wire_size += 2720;
2628 } else if (avg_wire_size <= 1084) {
2629 /* 16K ints/sec to 9.2K ints/sec */
2630 avg_wire_size *= 15;
2631 avg_wire_size += 11452;
2632 } else if (avg_wire_size < 1968) {
2633 /* 9.2K ints/sec to 8K ints/sec */
2634 avg_wire_size *= 5;
2635 avg_wire_size += 22420;
2636 } else {
2637 /* plateau at a limit of 8K ints/sec */
2638 avg_wire_size = 32256;
2639 }
2640
2641 /* If we are in low latency mode half our delay which doubles the rate
2642 * to somewhere between 100K to 16K ints/sec
2643 */
2644 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY)
2645 avg_wire_size >>= 1;
2646
2647 /* Resultant value is 256 times larger than it needs to be. This
2648 * gives us room to adjust the value as needed to either increase
2649 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
2650 *
2651 * Use addition as we have already recorded the new latency flag
2652 * for the ITR value.
2653 */
2654 switch (q_vector->adapter->link_speed) {
2655 case IXGBE_LINK_SPEED_10GB_FULL:
2656 case IXGBE_LINK_SPEED_100_FULL:
2657 default:
2658 itr += DIV_ROUND_UP(avg_wire_size,
2659 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) *
2660 IXGBE_ITR_ADAPTIVE_MIN_INC;
2661 break;
2662 case IXGBE_LINK_SPEED_2_5GB_FULL:
2663 case IXGBE_LINK_SPEED_1GB_FULL:
2664 case IXGBE_LINK_SPEED_10_FULL:
2665 if (avg_wire_size > 8064)
2666 avg_wire_size = 8064;
2667 itr += DIV_ROUND_UP(avg_wire_size,
2668 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) *
2669 IXGBE_ITR_ADAPTIVE_MIN_INC;
2670 break;
2671 }
2672
2673 clear_counts:
2674 /* write back value */
2675 ring_container->itr = itr;
2676
2677 /* next update should occur within next jiffy */
2678 ring_container->next_update = next_update + 1;
2679
2680 ring_container->total_bytes = 0;
2681 ring_container->total_packets = 0;
2682 }
2683
2684 /**
2685 * ixgbe_write_eitr - write EITR register in hardware specific way
2686 * @q_vector: structure containing interrupt and ring information
2687 *
2688 * This function is made to be called by ethtool and by the driver
2689 * when it needs to update EITR registers at runtime. Hardware
2690 * specific quirks/differences are taken care of here.
2691 */
2692 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2693 {
2694 struct ixgbe_adapter *adapter = q_vector->adapter;
2695 struct ixgbe_hw *hw = &adapter->hw;
2696 int v_idx = q_vector->v_idx;
2697 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2698
2699 switch (adapter->hw.mac.type) {
2700 case ixgbe_mac_82598EB:
2701 /* must write high and low 16 bits to reset counter */
2702 itr_reg |= (itr_reg << 16);
2703 break;
2704 case ixgbe_mac_82599EB:
2705 case ixgbe_mac_X540:
2706 case ixgbe_mac_X550:
2707 case ixgbe_mac_X550EM_x:
2708 case ixgbe_mac_x550em_a:
2709 /*
2710 * set the WDIS bit to not clear the timer bits and cause an
2711 * immediate assertion of the interrupt
2712 */
2713 itr_reg |= IXGBE_EITR_CNT_WDIS;
2714 break;
2715 default:
2716 break;
2717 }
2718 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2719 }
2720
2721 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2722 {
2723 u32 new_itr;
2724
2725 ixgbe_update_itr(q_vector, &q_vector->tx);
2726 ixgbe_update_itr(q_vector, &q_vector->rx);
2727
2728 /* use the smallest value of new ITR delay calculations */
2729 new_itr = min(q_vector->rx.itr, q_vector->tx.itr);
2730
2731 /* Clear latency flag if set, shift into correct position */
2732 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY;
2733 new_itr <<= 2;
2734
2735 if (new_itr != q_vector->itr) {
2736 /* save the algorithm value here */
2737 q_vector->itr = new_itr;
2738
2739 ixgbe_write_eitr(q_vector);
2740 }
2741 }
2742
2743 /**
2744 * ixgbe_check_overtemp_subtask - check for over temperature
2745 * @adapter: pointer to adapter
2746 **/
2747 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2748 {
2749 struct ixgbe_hw *hw = &adapter->hw;
2750 u32 eicr = adapter->interrupt_event;
2751 s32 rc;
2752
2753 if (test_bit(__IXGBE_DOWN, &adapter->state))
2754 return;
2755
2756 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2757 return;
2758
2759 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2760
2761 switch (hw->device_id) {
2762 case IXGBE_DEV_ID_82599_T3_LOM:
2763 /*
2764 * Since the warning interrupt is for both ports
2765 * we don't have to check if:
2766 * - This interrupt wasn't for our port.
2767 * - We may have missed the interrupt so always have to
2768 * check if we got a LSC
2769 */
2770 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2771 !(eicr & IXGBE_EICR_LSC))
2772 return;
2773
2774 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2775 u32 speed;
2776 bool link_up = false;
2777
2778 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2779
2780 if (link_up)
2781 return;
2782 }
2783
2784 /* Check if this is not due to overtemp */
2785 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2786 return;
2787
2788 break;
2789 case IXGBE_DEV_ID_X550EM_A_1G_T:
2790 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2791 rc = hw->phy.ops.check_overtemp(hw);
2792 if (rc != IXGBE_ERR_OVERTEMP)
2793 return;
2794 break;
2795 default:
2796 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2797 return;
2798 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2799 return;
2800 break;
2801 }
2802 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2803
2804 adapter->interrupt_event = 0;
2805 }
2806
2807 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2808 {
2809 struct ixgbe_hw *hw = &adapter->hw;
2810
2811 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2812 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2813 e_crit(probe, "Fan has stopped, replace the adapter\n");
2814 /* write to clear the interrupt */
2815 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2816 }
2817 }
2818
2819 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2820 {
2821 struct ixgbe_hw *hw = &adapter->hw;
2822
2823 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2824 return;
2825
2826 switch (adapter->hw.mac.type) {
2827 case ixgbe_mac_82599EB:
2828 /*
2829 * Need to check link state so complete overtemp check
2830 * on service task
2831 */
2832 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2833 (eicr & IXGBE_EICR_LSC)) &&
2834 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2835 adapter->interrupt_event = eicr;
2836 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2837 ixgbe_service_event_schedule(adapter);
2838 return;
2839 }
2840 return;
2841 case ixgbe_mac_x550em_a:
2842 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) {
2843 adapter->interrupt_event = eicr;
2844 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2845 ixgbe_service_event_schedule(adapter);
2846 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
2847 IXGBE_EICR_GPI_SDP0_X550EM_a);
2848 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR,
2849 IXGBE_EICR_GPI_SDP0_X550EM_a);
2850 }
2851 return;
2852 case ixgbe_mac_X550:
2853 case ixgbe_mac_X540:
2854 if (!(eicr & IXGBE_EICR_TS))
2855 return;
2856 break;
2857 default:
2858 return;
2859 }
2860
2861 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2862 }
2863
2864 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2865 {
2866 switch (hw->mac.type) {
2867 case ixgbe_mac_82598EB:
2868 if (hw->phy.type == ixgbe_phy_nl)
2869 return true;
2870 return false;
2871 case ixgbe_mac_82599EB:
2872 case ixgbe_mac_X550EM_x:
2873 case ixgbe_mac_x550em_a:
2874 switch (hw->mac.ops.get_media_type(hw)) {
2875 case ixgbe_media_type_fiber:
2876 case ixgbe_media_type_fiber_qsfp:
2877 return true;
2878 default:
2879 return false;
2880 }
2881 default:
2882 return false;
2883 }
2884 }
2885
2886 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2887 {
2888 struct ixgbe_hw *hw = &adapter->hw;
2889 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2890
2891 if (!ixgbe_is_sfp(hw))
2892 return;
2893
2894 /* Later MAC's use different SDP */
2895 if (hw->mac.type >= ixgbe_mac_X540)
2896 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2897
2898 if (eicr & eicr_mask) {
2899 /* Clear the interrupt */
2900 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2901 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2902 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2903 adapter->sfp_poll_time = 0;
2904 ixgbe_service_event_schedule(adapter);
2905 }
2906 }
2907
2908 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2909 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2910 /* Clear the interrupt */
2911 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2912 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2913 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2914 ixgbe_service_event_schedule(adapter);
2915 }
2916 }
2917 }
2918
2919 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2920 {
2921 struct ixgbe_hw *hw = &adapter->hw;
2922
2923 adapter->lsc_int++;
2924 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2925 adapter->link_check_timeout = jiffies;
2926 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2927 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2928 IXGBE_WRITE_FLUSH(hw);
2929 ixgbe_service_event_schedule(adapter);
2930 }
2931 }
2932
2933 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2934 u64 qmask)
2935 {
2936 u32 mask;
2937 struct ixgbe_hw *hw = &adapter->hw;
2938
2939 switch (hw->mac.type) {
2940 case ixgbe_mac_82598EB:
2941 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2942 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2943 break;
2944 case ixgbe_mac_82599EB:
2945 case ixgbe_mac_X540:
2946 case ixgbe_mac_X550:
2947 case ixgbe_mac_X550EM_x:
2948 case ixgbe_mac_x550em_a:
2949 mask = (qmask & 0xFFFFFFFF);
2950 if (mask)
2951 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2952 mask = (qmask >> 32);
2953 if (mask)
2954 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2955 break;
2956 default:
2957 break;
2958 }
2959 /* skip the flush */
2960 }
2961
2962 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2963 u64 qmask)
2964 {
2965 u32 mask;
2966 struct ixgbe_hw *hw = &adapter->hw;
2967
2968 switch (hw->mac.type) {
2969 case ixgbe_mac_82598EB:
2970 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2971 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2972 break;
2973 case ixgbe_mac_82599EB:
2974 case ixgbe_mac_X540:
2975 case ixgbe_mac_X550:
2976 case ixgbe_mac_X550EM_x:
2977 case ixgbe_mac_x550em_a:
2978 mask = (qmask & 0xFFFFFFFF);
2979 if (mask)
2980 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2981 mask = (qmask >> 32);
2982 if (mask)
2983 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2984 break;
2985 default:
2986 break;
2987 }
2988 /* skip the flush */
2989 }
2990
2991 /**
2992 * ixgbe_irq_enable - Enable default interrupt generation settings
2993 * @adapter: board private structure
2994 * @queues: enable irqs for queues
2995 * @flush: flush register write
2996 **/
2997 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2998 bool flush)
2999 {
3000 struct ixgbe_hw *hw = &adapter->hw;
3001 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
3002
3003 /* don't reenable LSC while waiting for link */
3004 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
3005 mask &= ~IXGBE_EIMS_LSC;
3006
3007 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3008 switch (adapter->hw.mac.type) {
3009 case ixgbe_mac_82599EB:
3010 mask |= IXGBE_EIMS_GPI_SDP0(hw);
3011 break;
3012 case ixgbe_mac_X540:
3013 case ixgbe_mac_X550:
3014 case ixgbe_mac_X550EM_x:
3015 case ixgbe_mac_x550em_a:
3016 mask |= IXGBE_EIMS_TS;
3017 break;
3018 default:
3019 break;
3020 }
3021 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3022 mask |= IXGBE_EIMS_GPI_SDP1(hw);
3023 switch (adapter->hw.mac.type) {
3024 case ixgbe_mac_82599EB:
3025 mask |= IXGBE_EIMS_GPI_SDP1(hw);
3026 mask |= IXGBE_EIMS_GPI_SDP2(hw);
3027 /* fall through */
3028 case ixgbe_mac_X540:
3029 case ixgbe_mac_X550:
3030 case ixgbe_mac_X550EM_x:
3031 case ixgbe_mac_x550em_a:
3032 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
3033 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
3034 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
3035 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
3036 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
3037 mask |= IXGBE_EICR_GPI_SDP0_X540;
3038 mask |= IXGBE_EIMS_ECC;
3039 mask |= IXGBE_EIMS_MAILBOX;
3040 break;
3041 default:
3042 break;
3043 }
3044
3045 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
3046 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
3047 mask |= IXGBE_EIMS_FLOW_DIR;
3048
3049 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
3050 if (queues)
3051 ixgbe_irq_enable_queues(adapter, ~0);
3052 if (flush)
3053 IXGBE_WRITE_FLUSH(&adapter->hw);
3054 }
3055
3056 static irqreturn_t ixgbe_msix_other(int irq, void *data)
3057 {
3058 struct ixgbe_adapter *adapter = data;
3059 struct ixgbe_hw *hw = &adapter->hw;
3060 u32 eicr;
3061
3062 /*
3063 * Workaround for Silicon errata. Use clear-by-write instead
3064 * of clear-by-read. Reading with EICS will return the
3065 * interrupt causes without clearing, which later be done
3066 * with the write to EICR.
3067 */
3068 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
3069
3070 /* The lower 16bits of the EICR register are for the queue interrupts
3071 * which should be masked here in order to not accidentally clear them if
3072 * the bits are high when ixgbe_msix_other is called. There is a race
3073 * condition otherwise which results in possible performance loss
3074 * especially if the ixgbe_msix_other interrupt is triggering
3075 * consistently (as it would when PPS is turned on for the X540 device)
3076 */
3077 eicr &= 0xFFFF0000;
3078
3079 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3080
3081 if (eicr & IXGBE_EICR_LSC)
3082 ixgbe_check_lsc(adapter);
3083
3084 if (eicr & IXGBE_EICR_MAILBOX)
3085 ixgbe_msg_task(adapter);
3086
3087 switch (hw->mac.type) {
3088 case ixgbe_mac_82599EB:
3089 case ixgbe_mac_X540:
3090 case ixgbe_mac_X550:
3091 case ixgbe_mac_X550EM_x:
3092 case ixgbe_mac_x550em_a:
3093 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
3094 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
3095 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
3096 ixgbe_service_event_schedule(adapter);
3097 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3098 IXGBE_EICR_GPI_SDP0_X540);
3099 }
3100 if (eicr & IXGBE_EICR_ECC) {
3101 e_info(link, "Received ECC Err, initiating reset\n");
3102 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3103 ixgbe_service_event_schedule(adapter);
3104 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3105 }
3106 /* Handle Flow Director Full threshold interrupt */
3107 if (eicr & IXGBE_EICR_FLOW_DIR) {
3108 int reinit_count = 0;
3109 int i;
3110 for (i = 0; i < adapter->num_tx_queues; i++) {
3111 struct ixgbe_ring *ring = adapter->tx_ring[i];
3112 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
3113 &ring->state))
3114 reinit_count++;
3115 }
3116 if (reinit_count) {
3117 /* no more flow director interrupts until after init */
3118 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
3119 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
3120 ixgbe_service_event_schedule(adapter);
3121 }
3122 }
3123 ixgbe_check_sfp_event(adapter, eicr);
3124 ixgbe_check_overtemp_event(adapter, eicr);
3125 break;
3126 default:
3127 break;
3128 }
3129
3130 ixgbe_check_fan_failure(adapter, eicr);
3131
3132 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3133 ixgbe_ptp_check_pps_event(adapter);
3134
3135 /* re-enable the original interrupt state, no lsc, no queues */
3136 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3137 ixgbe_irq_enable(adapter, false, false);
3138
3139 return IRQ_HANDLED;
3140 }
3141
3142 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
3143 {
3144 struct ixgbe_q_vector *q_vector = data;
3145
3146 /* EIAM disabled interrupts (on this vector) for us */
3147
3148 if (q_vector->rx.ring || q_vector->tx.ring)
3149 napi_schedule_irqoff(&q_vector->napi);
3150
3151 return IRQ_HANDLED;
3152 }
3153
3154 /**
3155 * ixgbe_poll - NAPI Rx polling callback
3156 * @napi: structure for representing this polling device
3157 * @budget: how many packets driver is allowed to clean
3158 *
3159 * This function is used for legacy and MSI, NAPI mode
3160 **/
3161 int ixgbe_poll(struct napi_struct *napi, int budget)
3162 {
3163 struct ixgbe_q_vector *q_vector =
3164 container_of(napi, struct ixgbe_q_vector, napi);
3165 struct ixgbe_adapter *adapter = q_vector->adapter;
3166 struct ixgbe_ring *ring;
3167 int per_ring_budget, work_done = 0;
3168 bool clean_complete = true;
3169
3170 #ifdef CONFIG_IXGBE_DCA
3171 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3172 ixgbe_update_dca(q_vector);
3173 #endif
3174
3175 ixgbe_for_each_ring(ring, q_vector->tx) {
3176 if (!ixgbe_clean_tx_irq(q_vector, ring, budget))
3177 clean_complete = false;
3178 }
3179
3180 /* Exit if we are called by netpoll */
3181 if (budget <= 0)
3182 return budget;
3183
3184 /* attempt to distribute budget to each queue fairly, but don't allow
3185 * the budget to go below 1 because we'll exit polling */
3186 if (q_vector->rx.count > 1)
3187 per_ring_budget = max(budget/q_vector->rx.count, 1);
3188 else
3189 per_ring_budget = budget;
3190
3191 ixgbe_for_each_ring(ring, q_vector->rx) {
3192 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
3193 per_ring_budget);
3194
3195 work_done += cleaned;
3196 if (cleaned >= per_ring_budget)
3197 clean_complete = false;
3198 }
3199
3200 /* If all work not completed, return budget and keep polling */
3201 if (!clean_complete)
3202 return budget;
3203
3204 /* all work done, exit the polling mode */
3205 if (likely(napi_complete_done(napi, work_done))) {
3206 if (adapter->rx_itr_setting & 1)
3207 ixgbe_set_itr(q_vector);
3208 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3209 ixgbe_irq_enable_queues(adapter,
3210 BIT_ULL(q_vector->v_idx));
3211 }
3212
3213 return min(work_done, budget - 1);
3214 }
3215
3216 /**
3217 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
3218 * @adapter: board private structure
3219 *
3220 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
3221 * interrupts from the kernel.
3222 **/
3223 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
3224 {
3225 struct net_device *netdev = adapter->netdev;
3226 unsigned int ri = 0, ti = 0;
3227 int vector, err;
3228
3229 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3230 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3231 struct msix_entry *entry = &adapter->msix_entries[vector];
3232
3233 if (q_vector->tx.ring && q_vector->rx.ring) {
3234 snprintf(q_vector->name, sizeof(q_vector->name),
3235 "%s-TxRx-%u", netdev->name, ri++);
3236 ti++;
3237 } else if (q_vector->rx.ring) {
3238 snprintf(q_vector->name, sizeof(q_vector->name),
3239 "%s-rx-%u", netdev->name, ri++);
3240 } else if (q_vector->tx.ring) {
3241 snprintf(q_vector->name, sizeof(q_vector->name),
3242 "%s-tx-%u", netdev->name, ti++);
3243 } else {
3244 /* skip this unused q_vector */
3245 continue;
3246 }
3247 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
3248 q_vector->name, q_vector);
3249 if (err) {
3250 e_err(probe, "request_irq failed for MSIX interrupt "
3251 "Error: %d\n", err);
3252 goto free_queue_irqs;
3253 }
3254 /* If Flow Director is enabled, set interrupt affinity */
3255 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3256 /* assign the mask for this irq */
3257 irq_set_affinity_hint(entry->vector,
3258 &q_vector->affinity_mask);
3259 }
3260 }
3261
3262 err = request_irq(adapter->msix_entries[vector].vector,
3263 ixgbe_msix_other, 0, netdev->name, adapter);
3264 if (err) {
3265 e_err(probe, "request_irq for msix_other failed: %d\n", err);
3266 goto free_queue_irqs;
3267 }
3268
3269 return 0;
3270
3271 free_queue_irqs:
3272 while (vector) {
3273 vector--;
3274 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
3275 NULL);
3276 free_irq(adapter->msix_entries[vector].vector,
3277 adapter->q_vector[vector]);
3278 }
3279 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3280 pci_disable_msix(adapter->pdev);
3281 kfree(adapter->msix_entries);
3282 adapter->msix_entries = NULL;
3283 return err;
3284 }
3285
3286 /**
3287 * ixgbe_intr - legacy mode Interrupt Handler
3288 * @irq: interrupt number
3289 * @data: pointer to a network interface device structure
3290 **/
3291 static irqreturn_t ixgbe_intr(int irq, void *data)
3292 {
3293 struct ixgbe_adapter *adapter = data;
3294 struct ixgbe_hw *hw = &adapter->hw;
3295 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3296 u32 eicr;
3297
3298 /*
3299 * Workaround for silicon errata #26 on 82598. Mask the interrupt
3300 * before the read of EICR.
3301 */
3302 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
3303
3304 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
3305 * therefore no explicit interrupt disable is necessary */
3306 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3307 if (!eicr) {
3308 /*
3309 * shared interrupt alert!
3310 * make sure interrupts are enabled because the read will
3311 * have disabled interrupts due to EIAM
3312 * finish the workaround of silicon errata on 82598. Unmask
3313 * the interrupt that we masked before the EICR read.
3314 */
3315 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3316 ixgbe_irq_enable(adapter, true, true);
3317 return IRQ_NONE; /* Not our interrupt */
3318 }
3319
3320 if (eicr & IXGBE_EICR_LSC)
3321 ixgbe_check_lsc(adapter);
3322
3323 switch (hw->mac.type) {
3324 case ixgbe_mac_82599EB:
3325 ixgbe_check_sfp_event(adapter, eicr);
3326 /* Fall through */
3327 case ixgbe_mac_X540:
3328 case ixgbe_mac_X550:
3329 case ixgbe_mac_X550EM_x:
3330 case ixgbe_mac_x550em_a:
3331 if (eicr & IXGBE_EICR_ECC) {
3332 e_info(link, "Received ECC Err, initiating reset\n");
3333 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3334 ixgbe_service_event_schedule(adapter);
3335 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3336 }
3337 ixgbe_check_overtemp_event(adapter, eicr);
3338 break;
3339 default:
3340 break;
3341 }
3342
3343 ixgbe_check_fan_failure(adapter, eicr);
3344 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3345 ixgbe_ptp_check_pps_event(adapter);
3346
3347 /* would disable interrupts here but EIAM disabled it */
3348 napi_schedule_irqoff(&q_vector->napi);
3349
3350 /*
3351 * re-enable link(maybe) and non-queue interrupts, no flush.
3352 * ixgbe_poll will re-enable the queue interrupts
3353 */
3354 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3355 ixgbe_irq_enable(adapter, false, false);
3356
3357 return IRQ_HANDLED;
3358 }
3359
3360 /**
3361 * ixgbe_request_irq - initialize interrupts
3362 * @adapter: board private structure
3363 *
3364 * Attempts to configure interrupts using the best available
3365 * capabilities of the hardware and kernel.
3366 **/
3367 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
3368 {
3369 struct net_device *netdev = adapter->netdev;
3370 int err;
3371
3372 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3373 err = ixgbe_request_msix_irqs(adapter);
3374 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
3375 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
3376 netdev->name, adapter);
3377 else
3378 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
3379 netdev->name, adapter);
3380
3381 if (err)
3382 e_err(probe, "request_irq failed, Error %d\n", err);
3383
3384 return err;
3385 }
3386
3387 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3388 {
3389 int vector;
3390
3391 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3392 free_irq(adapter->pdev->irq, adapter);
3393 return;
3394 }
3395
3396 if (!adapter->msix_entries)
3397 return;
3398
3399 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3400 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3401 struct msix_entry *entry = &adapter->msix_entries[vector];
3402
3403 /* free only the irqs that were actually requested */
3404 if (!q_vector->rx.ring && !q_vector->tx.ring)
3405 continue;
3406
3407 /* clear the affinity_mask in the IRQ descriptor */
3408 irq_set_affinity_hint(entry->vector, NULL);
3409
3410 free_irq(entry->vector, q_vector);
3411 }
3412
3413 free_irq(adapter->msix_entries[vector].vector, adapter);
3414 }
3415
3416 /**
3417 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3418 * @adapter: board private structure
3419 **/
3420 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3421 {
3422 switch (adapter->hw.mac.type) {
3423 case ixgbe_mac_82598EB:
3424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3425 break;
3426 case ixgbe_mac_82599EB:
3427 case ixgbe_mac_X540:
3428 case ixgbe_mac_X550:
3429 case ixgbe_mac_X550EM_x:
3430 case ixgbe_mac_x550em_a:
3431 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3432 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3433 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3434 break;
3435 default:
3436 break;
3437 }
3438 IXGBE_WRITE_FLUSH(&adapter->hw);
3439 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3440 int vector;
3441
3442 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3443 synchronize_irq(adapter->msix_entries[vector].vector);
3444
3445 synchronize_irq(adapter->msix_entries[vector++].vector);
3446 } else {
3447 synchronize_irq(adapter->pdev->irq);
3448 }
3449 }
3450
3451 /**
3452 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3453 * @adapter: board private structure
3454 *
3455 **/
3456 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3457 {
3458 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3459
3460 ixgbe_write_eitr(q_vector);
3461
3462 ixgbe_set_ivar(adapter, 0, 0, 0);
3463 ixgbe_set_ivar(adapter, 1, 0, 0);
3464
3465 e_info(hw, "Legacy interrupt IVAR setup done\n");
3466 }
3467
3468 /**
3469 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3470 * @adapter: board private structure
3471 * @ring: structure containing ring specific data
3472 *
3473 * Configure the Tx descriptor ring after a reset.
3474 **/
3475 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3476 struct ixgbe_ring *ring)
3477 {
3478 struct ixgbe_hw *hw = &adapter->hw;
3479 u64 tdba = ring->dma;
3480 int wait_loop = 10;
3481 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3482 u8 reg_idx = ring->reg_idx;
3483
3484 /* disable queue to avoid issues while updating state */
3485 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3486 IXGBE_WRITE_FLUSH(hw);
3487
3488 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3489 (tdba & DMA_BIT_MASK(32)));
3490 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3491 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3492 ring->count * sizeof(union ixgbe_adv_tx_desc));
3493 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3494 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3495 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3496
3497 /*
3498 * set WTHRESH to encourage burst writeback, it should not be set
3499 * higher than 1 when:
3500 * - ITR is 0 as it could cause false TX hangs
3501 * - ITR is set to > 100k int/sec and BQL is enabled
3502 *
3503 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3504 * to or less than the number of on chip descriptors, which is
3505 * currently 40.
3506 */
3507 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3508 txdctl |= 1u << 16; /* WTHRESH = 1 */
3509 else
3510 txdctl |= 8u << 16; /* WTHRESH = 8 */
3511
3512 /*
3513 * Setting PTHRESH to 32 both improves performance
3514 * and avoids a TX hang with DFP enabled
3515 */
3516 txdctl |= (1u << 8) | /* HTHRESH = 1 */
3517 32; /* PTHRESH = 32 */
3518
3519 /* reinitialize flowdirector state */
3520 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3521 ring->atr_sample_rate = adapter->atr_sample_rate;
3522 ring->atr_count = 0;
3523 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3524 } else {
3525 ring->atr_sample_rate = 0;
3526 }
3527
3528 /* initialize XPS */
3529 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3530 struct ixgbe_q_vector *q_vector = ring->q_vector;
3531
3532 if (q_vector)
3533 netif_set_xps_queue(ring->netdev,
3534 &q_vector->affinity_mask,
3535 ring->queue_index);
3536 }
3537
3538 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3539
3540 /* reinitialize tx_buffer_info */
3541 memset(ring->tx_buffer_info, 0,
3542 sizeof(struct ixgbe_tx_buffer) * ring->count);
3543
3544 /* enable queue */
3545 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3546
3547 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3548 if (hw->mac.type == ixgbe_mac_82598EB &&
3549 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3550 return;
3551
3552 /* poll to verify queue is enabled */
3553 do {
3554 usleep_range(1000, 2000);
3555 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3556 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3557 if (!wait_loop)
3558 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx);
3559 }
3560
3561 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3562 {
3563 struct ixgbe_hw *hw = &adapter->hw;
3564 u32 rttdcs, mtqc;
3565 u8 tcs = adapter->hw_tcs;
3566
3567 if (hw->mac.type == ixgbe_mac_82598EB)
3568 return;
3569
3570 /* disable the arbiter while setting MTQC */
3571 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3572 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3573 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3574
3575 /* set transmit pool layout */
3576 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3577 mtqc = IXGBE_MTQC_VT_ENA;
3578 if (tcs > 4)
3579 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3580 else if (tcs > 1)
3581 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3582 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3583 IXGBE_82599_VMDQ_4Q_MASK)
3584 mtqc |= IXGBE_MTQC_32VF;
3585 else
3586 mtqc |= IXGBE_MTQC_64VF;
3587 } else {
3588 if (tcs > 4) {
3589 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3590 } else if (tcs > 1) {
3591 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3592 } else {
3593 u8 max_txq = adapter->num_tx_queues +
3594 adapter->num_xdp_queues;
3595 if (max_txq > 63)
3596 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3597 else
3598 mtqc = IXGBE_MTQC_64Q_1PB;
3599 }
3600 }
3601
3602 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3603
3604 /* Enable Security TX Buffer IFG for multiple pb */
3605 if (tcs) {
3606 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3607 sectx |= IXGBE_SECTX_DCB;
3608 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3609 }
3610
3611 /* re-enable the arbiter */
3612 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3613 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3614 }
3615
3616 /**
3617 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3618 * @adapter: board private structure
3619 *
3620 * Configure the Tx unit of the MAC after a reset.
3621 **/
3622 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3623 {
3624 struct ixgbe_hw *hw = &adapter->hw;
3625 u32 dmatxctl;
3626 u32 i;
3627
3628 ixgbe_setup_mtqc(adapter);
3629
3630 if (hw->mac.type != ixgbe_mac_82598EB) {
3631 /* DMATXCTL.EN must be before Tx queues are enabled */
3632 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3633 dmatxctl |= IXGBE_DMATXCTL_TE;
3634 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3635 }
3636
3637 /* Setup the HW Tx Head and Tail descriptor pointers */
3638 for (i = 0; i < adapter->num_tx_queues; i++)
3639 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3640 for (i = 0; i < adapter->num_xdp_queues; i++)
3641 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]);
3642 }
3643
3644 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3645 struct ixgbe_ring *ring)
3646 {
3647 struct ixgbe_hw *hw = &adapter->hw;
3648 u8 reg_idx = ring->reg_idx;
3649 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3650
3651 srrctl |= IXGBE_SRRCTL_DROP_EN;
3652
3653 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3654 }
3655
3656 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3657 struct ixgbe_ring *ring)
3658 {
3659 struct ixgbe_hw *hw = &adapter->hw;
3660 u8 reg_idx = ring->reg_idx;
3661 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3662
3663 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3664
3665 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3666 }
3667
3668 #ifdef CONFIG_IXGBE_DCB
3669 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3670 #else
3671 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3672 #endif
3673 {
3674 int i;
3675 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3676
3677 if (adapter->ixgbe_ieee_pfc)
3678 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3679
3680 /*
3681 * We should set the drop enable bit if:
3682 * SR-IOV is enabled
3683 * or
3684 * Number of Rx queues > 1 and flow control is disabled
3685 *
3686 * This allows us to avoid head of line blocking for security
3687 * and performance reasons.
3688 */
3689 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3690 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3691 for (i = 0; i < adapter->num_rx_queues; i++)
3692 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3693 } else {
3694 for (i = 0; i < adapter->num_rx_queues; i++)
3695 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3696 }
3697 }
3698
3699 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3700
3701 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3702 struct ixgbe_ring *rx_ring)
3703 {
3704 struct ixgbe_hw *hw = &adapter->hw;
3705 u32 srrctl;
3706 u8 reg_idx = rx_ring->reg_idx;
3707
3708 if (hw->mac.type == ixgbe_mac_82598EB) {
3709 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3710
3711 /*
3712 * if VMDq is not active we must program one srrctl register
3713 * per RSS queue since we have enabled RDRXCTL.MVMEN
3714 */
3715 reg_idx &= mask;
3716 }
3717
3718 /* configure header buffer length, needed for RSC */
3719 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3720
3721 /* configure the packet buffer length */
3722 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state))
3723 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3724 else
3725 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3726
3727 /* configure descriptor type */
3728 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3729
3730 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3731 }
3732
3733 /**
3734 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
3735 * @adapter: device handle
3736 *
3737 * - 82598/82599/X540: 128
3738 * - X550(non-SRIOV mode): 512
3739 * - X550(SRIOV mode): 64
3740 */
3741 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3742 {
3743 if (adapter->hw.mac.type < ixgbe_mac_X550)
3744 return 128;
3745 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3746 return 64;
3747 else
3748 return 512;
3749 }
3750
3751 /**
3752 * ixgbe_store_key - Write the RSS key to HW
3753 * @adapter: device handle
3754 *
3755 * Write the RSS key stored in adapter.rss_key to HW.
3756 */
3757 void ixgbe_store_key(struct ixgbe_adapter *adapter)
3758 {
3759 struct ixgbe_hw *hw = &adapter->hw;
3760 int i;
3761
3762 for (i = 0; i < 10; i++)
3763 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3764 }
3765
3766 /**
3767 * ixgbe_init_rss_key - Initialize adapter RSS key
3768 * @adapter: device handle
3769 *
3770 * Allocates and initializes the RSS key if it is not allocated.
3771 **/
3772 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter)
3773 {
3774 u32 *rss_key;
3775
3776 if (!adapter->rss_key) {
3777 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL);
3778 if (unlikely(!rss_key))
3779 return -ENOMEM;
3780
3781 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE);
3782 adapter->rss_key = rss_key;
3783 }
3784
3785 return 0;
3786 }
3787
3788 /**
3789 * ixgbe_store_reta - Write the RETA table to HW
3790 * @adapter: device handle
3791 *
3792 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3793 */
3794 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3795 {
3796 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3797 struct ixgbe_hw *hw = &adapter->hw;
3798 u32 reta = 0;
3799 u32 indices_multi;
3800 u8 *indir_tbl = adapter->rss_indir_tbl;
3801
3802 /* Fill out the redirection table as follows:
3803 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3804 * indices.
3805 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3806 * - X550: 8 bit wide entries containing 6 bit RSS index
3807 */
3808 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3809 indices_multi = 0x11;
3810 else
3811 indices_multi = 0x1;
3812
3813 /* Write redirection table to HW */
3814 for (i = 0; i < reta_entries; i++) {
3815 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3816 if ((i & 3) == 3) {
3817 if (i < 128)
3818 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3819 else
3820 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3821 reta);
3822 reta = 0;
3823 }
3824 }
3825 }
3826
3827 /**
3828 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
3829 * @adapter: device handle
3830 *
3831 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3832 */
3833 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3834 {
3835 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3836 struct ixgbe_hw *hw = &adapter->hw;
3837 u32 vfreta = 0;
3838
3839 /* Write redirection table to HW */
3840 for (i = 0; i < reta_entries; i++) {
3841 u16 pool = adapter->num_rx_pools;
3842
3843 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3844 if ((i & 3) != 3)
3845 continue;
3846
3847 while (pool--)
3848 IXGBE_WRITE_REG(hw,
3849 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)),
3850 vfreta);
3851 vfreta = 0;
3852 }
3853 }
3854
3855 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3856 {
3857 u32 i, j;
3858 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3859 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3860
3861 /* Program table for at least 4 queues w/ SR-IOV so that VFs can
3862 * make full use of any rings they may have. We will use the
3863 * PSRTYPE register to control how many rings we use within the PF.
3864 */
3865 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4))
3866 rss_i = 4;
3867
3868 /* Fill out hash function seeds */
3869 ixgbe_store_key(adapter);
3870
3871 /* Fill out redirection table */
3872 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3873
3874 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3875 if (j == rss_i)
3876 j = 0;
3877
3878 adapter->rss_indir_tbl[i] = j;
3879 }
3880
3881 ixgbe_store_reta(adapter);
3882 }
3883
3884 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3885 {
3886 struct ixgbe_hw *hw = &adapter->hw;
3887 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3888 int i, j;
3889
3890 /* Fill out hash function seeds */
3891 for (i = 0; i < 10; i++) {
3892 u16 pool = adapter->num_rx_pools;
3893
3894 while (pool--)
3895 IXGBE_WRITE_REG(hw,
3896 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)),
3897 *(adapter->rss_key + i));
3898 }
3899
3900 /* Fill out the redirection table */
3901 for (i = 0, j = 0; i < 64; i++, j++) {
3902 if (j == rss_i)
3903 j = 0;
3904
3905 adapter->rss_indir_tbl[i] = j;
3906 }
3907
3908 ixgbe_store_vfreta(adapter);
3909 }
3910
3911 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3912 {
3913 struct ixgbe_hw *hw = &adapter->hw;
3914 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3915 u32 rxcsum;
3916
3917 /* Disable indicating checksum in descriptor, enables RSS hash */
3918 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3919 rxcsum |= IXGBE_RXCSUM_PCSD;
3920 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3921
3922 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3923 if (adapter->ring_feature[RING_F_RSS].mask)
3924 mrqc = IXGBE_MRQC_RSSEN;
3925 } else {
3926 u8 tcs = adapter->hw_tcs;
3927
3928 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3929 if (tcs > 4)
3930 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3931 else if (tcs > 1)
3932 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3933 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3934 IXGBE_82599_VMDQ_4Q_MASK)
3935 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3936 else
3937 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3938
3939 /* Enable L3/L4 for Tx Switched packets only for X550,
3940 * older devices do not support this feature
3941 */
3942 if (hw->mac.type >= ixgbe_mac_X550)
3943 mrqc |= IXGBE_MRQC_L3L4TXSWEN;
3944 } else {
3945 if (tcs > 4)
3946 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3947 else if (tcs > 1)
3948 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3949 else
3950 mrqc = IXGBE_MRQC_RSSEN;
3951 }
3952 }
3953
3954 /* Perform hash on these packet types */
3955 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3956 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3957 IXGBE_MRQC_RSS_FIELD_IPV6 |
3958 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3959
3960 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3961 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3962 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3963 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3964
3965 if ((hw->mac.type >= ixgbe_mac_X550) &&
3966 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3967 u16 pool = adapter->num_rx_pools;
3968
3969 /* Enable VF RSS mode */
3970 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3971 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3972
3973 /* Setup RSS through the VF registers */
3974 ixgbe_setup_vfreta(adapter);
3975 vfmrqc = IXGBE_MRQC_RSSEN;
3976 vfmrqc |= rss_field;
3977
3978 while (pool--)
3979 IXGBE_WRITE_REG(hw,
3980 IXGBE_PFVFMRQC(VMDQ_P(pool)),
3981 vfmrqc);
3982 } else {
3983 ixgbe_setup_reta(adapter);
3984 mrqc |= rss_field;
3985 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3986 }
3987 }
3988
3989 /**
3990 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3991 * @adapter: address of board private structure
3992 * @ring: structure containing ring specific data
3993 **/
3994 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3995 struct ixgbe_ring *ring)
3996 {
3997 struct ixgbe_hw *hw = &adapter->hw;
3998 u32 rscctrl;
3999 u8 reg_idx = ring->reg_idx;
4000
4001 if (!ring_is_rsc_enabled(ring))
4002 return;
4003
4004 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
4005 rscctrl |= IXGBE_RSCCTL_RSCEN;
4006 /*
4007 * we must limit the number of descriptors so that the
4008 * total size of max desc * buf_len is not greater
4009 * than 65536
4010 */
4011 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
4012 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
4013 }
4014
4015 #define IXGBE_MAX_RX_DESC_POLL 10
4016 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
4017 struct ixgbe_ring *ring)
4018 {
4019 struct ixgbe_hw *hw = &adapter->hw;
4020 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
4021 u32 rxdctl;
4022 u8 reg_idx = ring->reg_idx;
4023
4024 if (ixgbe_removed(hw->hw_addr))
4025 return;
4026 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
4027 if (hw->mac.type == ixgbe_mac_82598EB &&
4028 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
4029 return;
4030
4031 do {
4032 usleep_range(1000, 2000);
4033 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4034 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4035
4036 if (!wait_loop) {
4037 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
4038 "the polling period\n", reg_idx);
4039 }
4040 }
4041
4042 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
4043 struct ixgbe_ring *ring)
4044 {
4045 struct ixgbe_hw *hw = &adapter->hw;
4046 union ixgbe_adv_rx_desc *rx_desc;
4047 u64 rdba = ring->dma;
4048 u32 rxdctl;
4049 u8 reg_idx = ring->reg_idx;
4050
4051 /* disable queue to avoid use of these values while updating state */
4052 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4053 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4054
4055 /* write value back with RXDCTL.ENABLE bit cleared */
4056 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4057 IXGBE_WRITE_FLUSH(hw);
4058
4059 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
4060 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
4061 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
4062 ring->count * sizeof(union ixgbe_adv_rx_desc));
4063 /* Force flushing of IXGBE_RDLEN to prevent MDD */
4064 IXGBE_WRITE_FLUSH(hw);
4065
4066 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
4067 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
4068 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
4069
4070 ixgbe_configure_srrctl(adapter, ring);
4071 ixgbe_configure_rscctl(adapter, ring);
4072
4073 if (hw->mac.type == ixgbe_mac_82598EB) {
4074 /*
4075 * enable cache line friendly hardware writes:
4076 * PTHRESH=32 descriptors (half the internal cache),
4077 * this also removes ugly rx_no_buffer_count increment
4078 * HTHRESH=4 descriptors (to minimize latency on fetch)
4079 * WTHRESH=8 burst writeback up to two cache lines
4080 */
4081 rxdctl &= ~0x3FFFFF;
4082 rxdctl |= 0x080420;
4083 #if (PAGE_SIZE < 8192)
4084 /* RXDCTL.RLPML does not work on 82599 */
4085 } else if (hw->mac.type != ixgbe_mac_82599EB) {
4086 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4087 IXGBE_RXDCTL_RLPML_EN);
4088
4089 /* Limit the maximum frame size so we don't overrun the skb.
4090 * This can happen in SRIOV mode when the MTU of the VF is
4091 * higher than the MTU of the PF.
4092 */
4093 if (ring_uses_build_skb(ring) &&
4094 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
4095 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB |
4096 IXGBE_RXDCTL_RLPML_EN;
4097 #endif
4098 }
4099
4100 /* initialize rx_buffer_info */
4101 memset(ring->rx_buffer_info, 0,
4102 sizeof(struct ixgbe_rx_buffer) * ring->count);
4103
4104 /* initialize Rx descriptor 0 */
4105 rx_desc = IXGBE_RX_DESC(ring, 0);
4106 rx_desc->wb.upper.length = 0;
4107
4108 /* enable receive descriptor ring */
4109 rxdctl |= IXGBE_RXDCTL_ENABLE;
4110 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4111
4112 ixgbe_rx_desc_queue_enable(adapter, ring);
4113 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
4114 }
4115
4116 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
4117 {
4118 struct ixgbe_hw *hw = &adapter->hw;
4119 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
4120 u16 pool = adapter->num_rx_pools;
4121
4122 /* PSRTYPE must be initialized in non 82598 adapters */
4123 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4124 IXGBE_PSRTYPE_UDPHDR |
4125 IXGBE_PSRTYPE_IPV4HDR |
4126 IXGBE_PSRTYPE_L2HDR |
4127 IXGBE_PSRTYPE_IPV6HDR;
4128
4129 if (hw->mac.type == ixgbe_mac_82598EB)
4130 return;
4131
4132 if (rss_i > 3)
4133 psrtype |= 2u << 29;
4134 else if (rss_i > 1)
4135 psrtype |= 1u << 29;
4136
4137 while (pool--)
4138 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4139 }
4140
4141 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
4142 {
4143 struct ixgbe_hw *hw = &adapter->hw;
4144 u16 pool = adapter->num_rx_pools;
4145 u32 reg_offset, vf_shift, vmolr;
4146 u32 gcr_ext, vmdctl;
4147 int i;
4148
4149 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
4150 return;
4151
4152 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4153 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
4154 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
4155 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
4156 vmdctl |= IXGBE_VT_CTL_REPLEN;
4157 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
4158
4159 /* accept untagged packets until a vlan tag is
4160 * specifically set for the VMDQ queue/pool
4161 */
4162 vmolr = IXGBE_VMOLR_AUPE;
4163 while (pool--)
4164 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr);
4165
4166 vf_shift = VMDQ_P(0) % 32;
4167 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
4168
4169 /* Enable only the PF's pool for Tx/Rx */
4170 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
4171 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
4172 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
4173 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
4174 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
4175 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4176
4177 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
4178 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
4179
4180 /* clear VLAN promisc flag so VFTA will be updated if necessary */
4181 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4182
4183 /*
4184 * Set up VF register offsets for selected VT Mode,
4185 * i.e. 32 or 64 VFs for SR-IOV
4186 */
4187 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4188 case IXGBE_82599_VMDQ_8Q_MASK:
4189 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
4190 break;
4191 case IXGBE_82599_VMDQ_4Q_MASK:
4192 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
4193 break;
4194 default:
4195 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
4196 break;
4197 }
4198
4199 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4200
4201 for (i = 0; i < adapter->num_vfs; i++) {
4202 /* configure spoof checking */
4203 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
4204 adapter->vfinfo[i].spoofchk_enabled);
4205
4206 /* Enable/Disable RSS query feature */
4207 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
4208 adapter->vfinfo[i].rss_query_enabled);
4209 }
4210 }
4211
4212 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
4213 {
4214 struct ixgbe_hw *hw = &adapter->hw;
4215 struct net_device *netdev = adapter->netdev;
4216 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4217 struct ixgbe_ring *rx_ring;
4218 int i;
4219 u32 mhadd, hlreg0;
4220
4221 #ifdef IXGBE_FCOE
4222 /* adjust max frame to be able to do baby jumbo for FCoE */
4223 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4224 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
4225 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4226
4227 #endif /* IXGBE_FCOE */
4228
4229 /* adjust max frame to be at least the size of a standard frame */
4230 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4231 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
4232
4233 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
4234 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
4235 mhadd &= ~IXGBE_MHADD_MFS_MASK;
4236 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
4237
4238 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
4239 }
4240
4241 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4242 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
4243 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4244 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4245
4246 /*
4247 * Setup the HW Rx Head and Tail Descriptor Pointers and
4248 * the Base and Length of the Rx Descriptor Ring
4249 */
4250 for (i = 0; i < adapter->num_rx_queues; i++) {
4251 rx_ring = adapter->rx_ring[i];
4252
4253 clear_ring_rsc_enabled(rx_ring);
4254 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4255 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4256
4257 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4258 set_ring_rsc_enabled(rx_ring);
4259
4260 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state))
4261 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4262
4263 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4264 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
4265 continue;
4266
4267 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4268
4269 #if (PAGE_SIZE < 8192)
4270 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4271 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4272
4273 if (IXGBE_2K_TOO_SMALL_WITH_PADDING ||
4274 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4275 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4276 #endif
4277 }
4278 }
4279
4280 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
4281 {
4282 struct ixgbe_hw *hw = &adapter->hw;
4283 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4284
4285 switch (hw->mac.type) {
4286 case ixgbe_mac_82598EB:
4287 /*
4288 * For VMDq support of different descriptor types or
4289 * buffer sizes through the use of multiple SRRCTL
4290 * registers, RDRXCTL.MVMEN must be set to 1
4291 *
4292 * also, the manual doesn't mention it clearly but DCA hints
4293 * will only use queue 0's tags unless this bit is set. Side
4294 * effects of setting this bit are only that SRRCTL must be
4295 * fully programmed [0..15]
4296 */
4297 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
4298 break;
4299 case ixgbe_mac_X550:
4300 case ixgbe_mac_X550EM_x:
4301 case ixgbe_mac_x550em_a:
4302 if (adapter->num_vfs)
4303 rdrxctl |= IXGBE_RDRXCTL_PSP;
4304 /* fall through */
4305 case ixgbe_mac_82599EB:
4306 case ixgbe_mac_X540:
4307 /* Disable RSC for ACK packets */
4308 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
4309 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
4310 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4311 /* hardware requires some bits to be set by default */
4312 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
4313 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4314 break;
4315 default:
4316 /* We should do nothing since we don't know this hardware */
4317 return;
4318 }
4319
4320 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4321 }
4322
4323 /**
4324 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
4325 * @adapter: board private structure
4326 *
4327 * Configure the Rx unit of the MAC after a reset.
4328 **/
4329 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
4330 {
4331 struct ixgbe_hw *hw = &adapter->hw;
4332 int i;
4333 u32 rxctrl, rfctl;
4334
4335 /* disable receives while setting up the descriptors */
4336 hw->mac.ops.disable_rx(hw);
4337
4338 ixgbe_setup_psrtype(adapter);
4339 ixgbe_setup_rdrxctl(adapter);
4340
4341 /* RSC Setup */
4342 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4343 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
4344 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
4345 rfctl |= IXGBE_RFCTL_RSC_DIS;
4346
4347 /* disable NFS filtering */
4348 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS);
4349 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4350
4351 /* Program registers for the distribution of queues */
4352 ixgbe_setup_mrqc(adapter);
4353
4354 /* set_rx_buffer_len must be called before ring initialization */
4355 ixgbe_set_rx_buffer_len(adapter);
4356
4357 /*
4358 * Setup the HW Rx Head and Tail Descriptor Pointers and
4359 * the Base and Length of the Rx Descriptor Ring
4360 */
4361 for (i = 0; i < adapter->num_rx_queues; i++)
4362 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
4363
4364 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4365 /* disable drop enable for 82598 parts */
4366 if (hw->mac.type == ixgbe_mac_82598EB)
4367 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4368
4369 /* enable all receives */
4370 rxctrl |= IXGBE_RXCTRL_RXEN;
4371 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4372 }
4373
4374 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
4375 __be16 proto, u16 vid)
4376 {
4377 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4378 struct ixgbe_hw *hw = &adapter->hw;
4379
4380 /* add VID to filter table */
4381 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4382 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
4383
4384 set_bit(vid, adapter->active_vlans);
4385
4386 return 0;
4387 }
4388
4389 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
4390 {
4391 u32 vlvf;
4392 int idx;
4393
4394 /* short cut the special case */
4395 if (vlan == 0)
4396 return 0;
4397
4398 /* Search for the vlan id in the VLVF entries */
4399 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
4400 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
4401 if ((vlvf & VLAN_VID_MASK) == vlan)
4402 break;
4403 }
4404
4405 return idx;
4406 }
4407
4408 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
4409 {
4410 struct ixgbe_hw *hw = &adapter->hw;
4411 u32 bits, word;
4412 int idx;
4413
4414 idx = ixgbe_find_vlvf_entry(hw, vid);
4415 if (!idx)
4416 return;
4417
4418 /* See if any other pools are set for this VLAN filter
4419 * entry other than the PF.
4420 */
4421 word = idx * 2 + (VMDQ_P(0) / 32);
4422 bits = ~BIT(VMDQ_P(0) % 32);
4423 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4424
4425 /* Disable the filter so this falls into the default pool. */
4426 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4427 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4428 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4429 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4430 }
4431 }
4432
4433 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4434 __be16 proto, u16 vid)
4435 {
4436 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4437 struct ixgbe_hw *hw = &adapter->hw;
4438
4439 /* remove VID from filter table */
4440 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4441 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4442
4443 clear_bit(vid, adapter->active_vlans);
4444
4445 return 0;
4446 }
4447
4448 /**
4449 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4450 * @adapter: driver data
4451 */
4452 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4453 {
4454 struct ixgbe_hw *hw = &adapter->hw;
4455 u32 vlnctrl;
4456 int i, j;
4457
4458 switch (hw->mac.type) {
4459 case ixgbe_mac_82598EB:
4460 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4461 vlnctrl &= ~IXGBE_VLNCTRL_VME;
4462 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4463 break;
4464 case ixgbe_mac_82599EB:
4465 case ixgbe_mac_X540:
4466 case ixgbe_mac_X550:
4467 case ixgbe_mac_X550EM_x:
4468 case ixgbe_mac_x550em_a:
4469 for (i = 0; i < adapter->num_rx_queues; i++) {
4470 struct ixgbe_ring *ring = adapter->rx_ring[i];
4471
4472 if (!netif_is_ixgbe(ring->netdev))
4473 continue;
4474
4475 j = ring->reg_idx;
4476 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4477 vlnctrl &= ~IXGBE_RXDCTL_VME;
4478 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4479 }
4480 break;
4481 default:
4482 break;
4483 }
4484 }
4485
4486 /**
4487 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
4488 * @adapter: driver data
4489 */
4490 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
4491 {
4492 struct ixgbe_hw *hw = &adapter->hw;
4493 u32 vlnctrl;
4494 int i, j;
4495
4496 switch (hw->mac.type) {
4497 case ixgbe_mac_82598EB:
4498 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4499 vlnctrl |= IXGBE_VLNCTRL_VME;
4500 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4501 break;
4502 case ixgbe_mac_82599EB:
4503 case ixgbe_mac_X540:
4504 case ixgbe_mac_X550:
4505 case ixgbe_mac_X550EM_x:
4506 case ixgbe_mac_x550em_a:
4507 for (i = 0; i < adapter->num_rx_queues; i++) {
4508 struct ixgbe_ring *ring = adapter->rx_ring[i];
4509
4510 if (!netif_is_ixgbe(ring->netdev))
4511 continue;
4512
4513 j = ring->reg_idx;
4514 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4515 vlnctrl |= IXGBE_RXDCTL_VME;
4516 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4517 }
4518 break;
4519 default:
4520 break;
4521 }
4522 }
4523
4524 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4525 {
4526 struct ixgbe_hw *hw = &adapter->hw;
4527 u32 vlnctrl, i;
4528
4529 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4530
4531 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
4532 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */
4533 vlnctrl |= IXGBE_VLNCTRL_VFE;
4534 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4535 } else {
4536 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
4537 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4538 return;
4539 }
4540
4541 /* Nothing to do for 82598 */
4542 if (hw->mac.type == ixgbe_mac_82598EB)
4543 return;
4544
4545 /* We are already in VLAN promisc, nothing to do */
4546 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4547 return;
4548
4549 /* Set flag so we don't redo unnecessary work */
4550 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4551
4552 /* Add PF to all active pools */
4553 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4554 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4555 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4556
4557 vlvfb |= BIT(VMDQ_P(0) % 32);
4558 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4559 }
4560
4561 /* Set all bits in the VLAN filter table array */
4562 for (i = hw->mac.vft_size; i--;)
4563 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4564 }
4565
4566 #define VFTA_BLOCK_SIZE 8
4567 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4568 {
4569 struct ixgbe_hw *hw = &adapter->hw;
4570 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4571 u32 vid_start = vfta_offset * 32;
4572 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4573 u32 i, vid, word, bits;
4574
4575 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4576 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4577
4578 /* pull VLAN ID from VLVF */
4579 vid = vlvf & VLAN_VID_MASK;
4580
4581 /* only concern outselves with a certain range */
4582 if (vid < vid_start || vid >= vid_end)
4583 continue;
4584
4585 if (vlvf) {
4586 /* record VLAN ID in VFTA */
4587 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4588
4589 /* if PF is part of this then continue */
4590 if (test_bit(vid, adapter->active_vlans))
4591 continue;
4592 }
4593
4594 /* remove PF from the pool */
4595 word = i * 2 + VMDQ_P(0) / 32;
4596 bits = ~BIT(VMDQ_P(0) % 32);
4597 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4598 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4599 }
4600
4601 /* extract values from active_vlans and write back to VFTA */
4602 for (i = VFTA_BLOCK_SIZE; i--;) {
4603 vid = (vfta_offset + i) * 32;
4604 word = vid / BITS_PER_LONG;
4605 bits = vid % BITS_PER_LONG;
4606
4607 vfta[i] |= adapter->active_vlans[word] >> bits;
4608
4609 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4610 }
4611 }
4612
4613 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4614 {
4615 struct ixgbe_hw *hw = &adapter->hw;
4616 u32 vlnctrl, i;
4617
4618 /* Set VLAN filtering to enabled */
4619 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4620 vlnctrl |= IXGBE_VLNCTRL_VFE;
4621 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4622
4623 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ||
4624 hw->mac.type == ixgbe_mac_82598EB)
4625 return;
4626
4627 /* We are not in VLAN promisc, nothing to do */
4628 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4629 return;
4630
4631 /* Set flag so we don't redo unnecessary work */
4632 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4633
4634 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4635 ixgbe_scrub_vfta(adapter, i);
4636 }
4637
4638 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4639 {
4640 u16 vid = 1;
4641
4642 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
4643
4644 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
4645 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4646 }
4647
4648 /**
4649 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4650 * @netdev: network interface device structure
4651 *
4652 * Writes multicast address list to the MTA hash table.
4653 * Returns: -ENOMEM on failure
4654 * 0 on no addresses written
4655 * X on writing X addresses to MTA
4656 **/
4657 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4658 {
4659 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4660 struct ixgbe_hw *hw = &adapter->hw;
4661
4662 if (!netif_running(netdev))
4663 return 0;
4664
4665 if (hw->mac.ops.update_mc_addr_list)
4666 hw->mac.ops.update_mc_addr_list(hw, netdev);
4667 else
4668 return -ENOMEM;
4669
4670 #ifdef CONFIG_PCI_IOV
4671 ixgbe_restore_vf_multicasts(adapter);
4672 #endif
4673
4674 return netdev_mc_count(netdev);
4675 }
4676
4677 #ifdef CONFIG_PCI_IOV
4678 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4679 {
4680 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4681 struct ixgbe_hw *hw = &adapter->hw;
4682 int i;
4683
4684 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4685 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4686
4687 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4688 hw->mac.ops.set_rar(hw, i,
4689 mac_table->addr,
4690 mac_table->pool,
4691 IXGBE_RAH_AV);
4692 else
4693 hw->mac.ops.clear_rar(hw, i);
4694 }
4695 }
4696
4697 #endif
4698 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4699 {
4700 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4701 struct ixgbe_hw *hw = &adapter->hw;
4702 int i;
4703
4704 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4705 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4706 continue;
4707
4708 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4709
4710 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4711 hw->mac.ops.set_rar(hw, i,
4712 mac_table->addr,
4713 mac_table->pool,
4714 IXGBE_RAH_AV);
4715 else
4716 hw->mac.ops.clear_rar(hw, i);
4717 }
4718 }
4719
4720 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4721 {
4722 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4723 struct ixgbe_hw *hw = &adapter->hw;
4724 int i;
4725
4726 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4727 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4728 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4729 }
4730
4731 ixgbe_sync_mac_table(adapter);
4732 }
4733
4734 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
4735 {
4736 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4737 struct ixgbe_hw *hw = &adapter->hw;
4738 int i, count = 0;
4739
4740 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4741 /* do not count default RAR as available */
4742 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4743 continue;
4744
4745 /* only count unused and addresses that belong to us */
4746 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4747 if (mac_table->pool != pool)
4748 continue;
4749 }
4750
4751 count++;
4752 }
4753
4754 return count;
4755 }
4756
4757 /* this function destroys the first RAR entry */
4758 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
4759 {
4760 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4761 struct ixgbe_hw *hw = &adapter->hw;
4762
4763 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4764 mac_table->pool = VMDQ_P(0);
4765
4766 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4767
4768 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
4769 IXGBE_RAH_AV);
4770 }
4771
4772 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4773 const u8 *addr, u16 pool)
4774 {
4775 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4776 struct ixgbe_hw *hw = &adapter->hw;
4777 int i;
4778
4779 if (is_zero_ether_addr(addr))
4780 return -EINVAL;
4781
4782 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4783 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4784 continue;
4785
4786 ether_addr_copy(mac_table->addr, addr);
4787 mac_table->pool = pool;
4788
4789 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4790 IXGBE_MAC_STATE_IN_USE;
4791
4792 ixgbe_sync_mac_table(adapter);
4793
4794 return i;
4795 }
4796
4797 return -ENOMEM;
4798 }
4799
4800 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4801 const u8 *addr, u16 pool)
4802 {
4803 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4804 struct ixgbe_hw *hw = &adapter->hw;
4805 int i;
4806
4807 if (is_zero_ether_addr(addr))
4808 return -EINVAL;
4809
4810 /* search table for addr, if found clear IN_USE flag and sync */
4811 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4812 /* we can only delete an entry if it is in use */
4813 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4814 continue;
4815 /* we only care about entries that belong to the given pool */
4816 if (mac_table->pool != pool)
4817 continue;
4818 /* we only care about a specific MAC address */
4819 if (!ether_addr_equal(addr, mac_table->addr))
4820 continue;
4821
4822 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4823 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4824
4825 ixgbe_sync_mac_table(adapter);
4826
4827 return 0;
4828 }
4829
4830 return -ENOMEM;
4831 }
4832
4833 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4834 {
4835 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4836 int ret;
4837
4838 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4839
4840 return min_t(int, ret, 0);
4841 }
4842
4843 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4844 {
4845 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4846
4847 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4848
4849 return 0;
4850 }
4851
4852 /**
4853 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4854 * @netdev: network interface device structure
4855 *
4856 * The set_rx_method entry point is called whenever the unicast/multicast
4857 * address list or the network interface flags are updated. This routine is
4858 * responsible for configuring the hardware for proper unicast, multicast and
4859 * promiscuous mode.
4860 **/
4861 void ixgbe_set_rx_mode(struct net_device *netdev)
4862 {
4863 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4864 struct ixgbe_hw *hw = &adapter->hw;
4865 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4866 netdev_features_t features = netdev->features;
4867 int count;
4868
4869 /* Check for Promiscuous and All Multicast modes */
4870 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4871
4872 /* set all bits that we expect to always be set */
4873 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4874 fctrl |= IXGBE_FCTRL_BAM;
4875 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4876 fctrl |= IXGBE_FCTRL_PMCF;
4877
4878 /* clear the bits we are changing the status of */
4879 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4880 if (netdev->flags & IFF_PROMISC) {
4881 hw->addr_ctrl.user_set_promisc = true;
4882 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4883 vmolr |= IXGBE_VMOLR_MPE;
4884 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4885 } else {
4886 if (netdev->flags & IFF_ALLMULTI) {
4887 fctrl |= IXGBE_FCTRL_MPE;
4888 vmolr |= IXGBE_VMOLR_MPE;
4889 }
4890 hw->addr_ctrl.user_set_promisc = false;
4891 }
4892
4893 /*
4894 * Write addresses to available RAR registers, if there is not
4895 * sufficient space to store all the addresses then enable
4896 * unicast promiscuous mode
4897 */
4898 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
4899 fctrl |= IXGBE_FCTRL_UPE;
4900 vmolr |= IXGBE_VMOLR_ROPE;
4901 }
4902
4903 /* Write addresses to the MTA, if the attempt fails
4904 * then we should just turn on promiscuous mode so
4905 * that we can at least receive multicast traffic
4906 */
4907 count = ixgbe_write_mc_addr_list(netdev);
4908 if (count < 0) {
4909 fctrl |= IXGBE_FCTRL_MPE;
4910 vmolr |= IXGBE_VMOLR_MPE;
4911 } else if (count) {
4912 vmolr |= IXGBE_VMOLR_ROMPE;
4913 }
4914
4915 if (hw->mac.type != ixgbe_mac_82598EB) {
4916 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4917 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4918 IXGBE_VMOLR_ROPE);
4919 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4920 }
4921
4922 /* This is useful for sniffing bad packets. */
4923 if (features & NETIF_F_RXALL) {
4924 /* UPE and MPE will be handled by normal PROMISC logic
4925 * in e1000e_set_rx_mode */
4926 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4927 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4928 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4929
4930 fctrl &= ~(IXGBE_FCTRL_DPF);
4931 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4932 }
4933
4934 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4935
4936 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4937 ixgbe_vlan_strip_enable(adapter);
4938 else
4939 ixgbe_vlan_strip_disable(adapter);
4940
4941 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4942 ixgbe_vlan_promisc_disable(adapter);
4943 else
4944 ixgbe_vlan_promisc_enable(adapter);
4945 }
4946
4947 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4948 {
4949 int q_idx;
4950
4951 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
4952 napi_enable(&adapter->q_vector[q_idx]->napi);
4953 }
4954
4955 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4956 {
4957 int q_idx;
4958
4959 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
4960 napi_disable(&adapter->q_vector[q_idx]->napi);
4961 }
4962
4963 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask)
4964 {
4965 struct ixgbe_hw *hw = &adapter->hw;
4966 u32 vxlanctrl;
4967
4968 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE |
4969 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)))
4970 return;
4971
4972 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask;
4973 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl);
4974
4975 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK)
4976 adapter->vxlan_port = 0;
4977
4978 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK)
4979 adapter->geneve_port = 0;
4980 }
4981
4982 #ifdef CONFIG_IXGBE_DCB
4983 /**
4984 * ixgbe_configure_dcb - Configure DCB hardware
4985 * @adapter: ixgbe adapter struct
4986 *
4987 * This is called by the driver on open to configure the DCB hardware.
4988 * This is also called by the gennetlink interface when reconfiguring
4989 * the DCB state.
4990 */
4991 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4992 {
4993 struct ixgbe_hw *hw = &adapter->hw;
4994 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4995
4996 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4997 if (hw->mac.type == ixgbe_mac_82598EB)
4998 netif_set_gso_max_size(adapter->netdev, 65536);
4999 return;
5000 }
5001
5002 if (hw->mac.type == ixgbe_mac_82598EB)
5003 netif_set_gso_max_size(adapter->netdev, 32768);
5004
5005 #ifdef IXGBE_FCOE
5006 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
5007 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
5008 #endif
5009
5010 /* reconfigure the hardware */
5011 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
5012 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5013 DCB_TX_CONFIG);
5014 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5015 DCB_RX_CONFIG);
5016 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
5017 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
5018 ixgbe_dcb_hw_ets(&adapter->hw,
5019 adapter->ixgbe_ieee_ets,
5020 max_frame);
5021 ixgbe_dcb_hw_pfc_config(&adapter->hw,
5022 adapter->ixgbe_ieee_pfc->pfc_en,
5023 adapter->ixgbe_ieee_ets->prio_tc);
5024 }
5025
5026 /* Enable RSS Hash per TC */
5027 if (hw->mac.type != ixgbe_mac_82598EB) {
5028 u32 msb = 0;
5029 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
5030
5031 while (rss_i) {
5032 msb++;
5033 rss_i >>= 1;
5034 }
5035
5036 /* write msb to all 8 TCs in one write */
5037 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
5038 }
5039 }
5040 #endif
5041
5042 /* Additional bittime to account for IXGBE framing */
5043 #define IXGBE_ETH_FRAMING 20
5044
5045 /**
5046 * ixgbe_hpbthresh - calculate high water mark for flow control
5047 *
5048 * @adapter: board private structure to calculate for
5049 * @pb: packet buffer to calculate
5050 */
5051 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
5052 {
5053 struct ixgbe_hw *hw = &adapter->hw;
5054 struct net_device *dev = adapter->netdev;
5055 int link, tc, kb, marker;
5056 u32 dv_id, rx_pba;
5057
5058 /* Calculate max LAN frame size */
5059 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
5060
5061 #ifdef IXGBE_FCOE
5062 /* FCoE traffic class uses FCOE jumbo frames */
5063 if ((dev->features & NETIF_F_FCOE_MTU) &&
5064 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5065 (pb == ixgbe_fcoe_get_tc(adapter)))
5066 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5067 #endif
5068
5069 /* Calculate delay value for device */
5070 switch (hw->mac.type) {
5071 case ixgbe_mac_X540:
5072 case ixgbe_mac_X550:
5073 case ixgbe_mac_X550EM_x:
5074 case ixgbe_mac_x550em_a:
5075 dv_id = IXGBE_DV_X540(link, tc);
5076 break;
5077 default:
5078 dv_id = IXGBE_DV(link, tc);
5079 break;
5080 }
5081
5082 /* Loopback switch introduces additional latency */
5083 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5084 dv_id += IXGBE_B2BT(tc);
5085
5086 /* Delay value is calculated in bit times convert to KB */
5087 kb = IXGBE_BT2KB(dv_id);
5088 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
5089
5090 marker = rx_pba - kb;
5091
5092 /* It is possible that the packet buffer is not large enough
5093 * to provide required headroom. In this case throw an error
5094 * to user and a do the best we can.
5095 */
5096 if (marker < 0) {
5097 e_warn(drv, "Packet Buffer(%i) can not provide enough"
5098 "headroom to support flow control."
5099 "Decrease MTU or number of traffic classes\n", pb);
5100 marker = tc + 1;
5101 }
5102
5103 return marker;
5104 }
5105
5106 /**
5107 * ixgbe_lpbthresh - calculate low water mark for for flow control
5108 *
5109 * @adapter: board private structure to calculate for
5110 * @pb: packet buffer to calculate
5111 */
5112 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
5113 {
5114 struct ixgbe_hw *hw = &adapter->hw;
5115 struct net_device *dev = adapter->netdev;
5116 int tc;
5117 u32 dv_id;
5118
5119 /* Calculate max LAN frame size */
5120 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5121
5122 #ifdef IXGBE_FCOE
5123 /* FCoE traffic class uses FCOE jumbo frames */
5124 if ((dev->features & NETIF_F_FCOE_MTU) &&
5125 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5126 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
5127 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5128 #endif
5129
5130 /* Calculate delay value for device */
5131 switch (hw->mac.type) {
5132 case ixgbe_mac_X540:
5133 case ixgbe_mac_X550:
5134 case ixgbe_mac_X550EM_x:
5135 case ixgbe_mac_x550em_a:
5136 dv_id = IXGBE_LOW_DV_X540(tc);
5137 break;
5138 default:
5139 dv_id = IXGBE_LOW_DV(tc);
5140 break;
5141 }
5142
5143 /* Delay value is calculated in bit times convert to KB */
5144 return IXGBE_BT2KB(dv_id);
5145 }
5146
5147 /*
5148 * ixgbe_pbthresh_setup - calculate and setup high low water marks
5149 */
5150 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
5151 {
5152 struct ixgbe_hw *hw = &adapter->hw;
5153 int num_tc = adapter->hw_tcs;
5154 int i;
5155
5156 if (!num_tc)
5157 num_tc = 1;
5158
5159 for (i = 0; i < num_tc; i++) {
5160 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
5161 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
5162
5163 /* Low water marks must not be larger than high water marks */
5164 if (hw->fc.low_water[i] > hw->fc.high_water[i])
5165 hw->fc.low_water[i] = 0;
5166 }
5167
5168 for (; i < MAX_TRAFFIC_CLASS; i++)
5169 hw->fc.high_water[i] = 0;
5170 }
5171
5172 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
5173 {
5174 struct ixgbe_hw *hw = &adapter->hw;
5175 int hdrm;
5176 u8 tc = adapter->hw_tcs;
5177
5178 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5179 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5180 hdrm = 32 << adapter->fdir_pballoc;
5181 else
5182 hdrm = 0;
5183
5184 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
5185 ixgbe_pbthresh_setup(adapter);
5186 }
5187
5188 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
5189 {
5190 struct ixgbe_hw *hw = &adapter->hw;
5191 struct hlist_node *node2;
5192 struct ixgbe_fdir_filter *filter;
5193 u8 queue;
5194
5195 spin_lock(&adapter->fdir_perfect_lock);
5196
5197 if (!hlist_empty(&adapter->fdir_filter_list))
5198 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
5199
5200 hlist_for_each_entry_safe(filter, node2,
5201 &adapter->fdir_filter_list, fdir_node) {
5202 if (filter->action == IXGBE_FDIR_DROP_QUEUE) {
5203 queue = IXGBE_FDIR_DROP_QUEUE;
5204 } else {
5205 u32 ring = ethtool_get_flow_spec_ring(filter->action);
5206 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action);
5207
5208 if (!vf && (ring >= adapter->num_rx_queues)) {
5209 e_err(drv, "FDIR restore failed without VF, ring: %u\n",
5210 ring);
5211 continue;
5212 } else if (vf &&
5213 ((vf > adapter->num_vfs) ||
5214 ring >= adapter->num_rx_queues_per_pool)) {
5215 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n",
5216 vf, ring);
5217 continue;
5218 }
5219
5220 /* Map the ring onto the absolute queue index */
5221 if (!vf)
5222 queue = adapter->rx_ring[ring]->reg_idx;
5223 else
5224 queue = ((vf - 1) *
5225 adapter->num_rx_queues_per_pool) + ring;
5226 }
5227
5228 ixgbe_fdir_write_perfect_filter_82599(hw,
5229 &filter->filter, filter->sw_idx, queue);
5230 }
5231
5232 spin_unlock(&adapter->fdir_perfect_lock);
5233 }
5234
5235 /**
5236 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
5237 * @rx_ring: ring to free buffers from
5238 **/
5239 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
5240 {
5241 u16 i = rx_ring->next_to_clean;
5242 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
5243
5244 /* Free all the Rx ring sk_buffs */
5245 while (i != rx_ring->next_to_alloc) {
5246 if (rx_buffer->skb) {
5247 struct sk_buff *skb = rx_buffer->skb;
5248 if (IXGBE_CB(skb)->page_released)
5249 dma_unmap_page_attrs(rx_ring->dev,
5250 IXGBE_CB(skb)->dma,
5251 ixgbe_rx_pg_size(rx_ring),
5252 DMA_FROM_DEVICE,
5253 IXGBE_RX_DMA_ATTR);
5254 dev_kfree_skb(skb);
5255 }
5256
5257 /* Invalidate cache lines that may have been written to by
5258 * device so that we avoid corrupting memory.
5259 */
5260 dma_sync_single_range_for_cpu(rx_ring->dev,
5261 rx_buffer->dma,
5262 rx_buffer->page_offset,
5263 ixgbe_rx_bufsz(rx_ring),
5264 DMA_FROM_DEVICE);
5265
5266 /* free resources associated with mapping */
5267 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
5268 ixgbe_rx_pg_size(rx_ring),
5269 DMA_FROM_DEVICE,
5270 IXGBE_RX_DMA_ATTR);
5271 __page_frag_cache_drain(rx_buffer->page,
5272 rx_buffer->pagecnt_bias);
5273
5274 i++;
5275 rx_buffer++;
5276 if (i == rx_ring->count) {
5277 i = 0;
5278 rx_buffer = rx_ring->rx_buffer_info;
5279 }
5280 }
5281
5282 rx_ring->next_to_alloc = 0;
5283 rx_ring->next_to_clean = 0;
5284 rx_ring->next_to_use = 0;
5285 }
5286
5287 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter,
5288 struct ixgbe_fwd_adapter *accel)
5289 {
5290 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
5291 int num_tc = netdev_get_num_tc(adapter->netdev);
5292 struct net_device *vdev = accel->netdev;
5293 int i, baseq, err;
5294
5295 baseq = accel->pool * adapter->num_rx_queues_per_pool;
5296 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n",
5297 accel->pool, adapter->num_rx_pools,
5298 baseq, baseq + adapter->num_rx_queues_per_pool);
5299
5300 accel->rx_base_queue = baseq;
5301 accel->tx_base_queue = baseq;
5302
5303 /* record configuration for macvlan interface in vdev */
5304 for (i = 0; i < num_tc; i++)
5305 netdev_bind_sb_channel_queue(adapter->netdev, vdev,
5306 i, rss_i, baseq + (rss_i * i));
5307
5308 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5309 adapter->rx_ring[baseq + i]->netdev = vdev;
5310
5311 /* Guarantee all rings are updated before we update the
5312 * MAC address filter.
5313 */
5314 wmb();
5315
5316 /* ixgbe_add_mac_filter will return an index if it succeeds, so we
5317 * need to only treat it as an error value if it is negative.
5318 */
5319 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr,
5320 VMDQ_P(accel->pool));
5321 if (err >= 0)
5322 return 0;
5323
5324 /* if we cannot add the MAC rule then disable the offload */
5325 macvlan_release_l2fw_offload(vdev);
5326
5327 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5328 adapter->rx_ring[baseq + i]->netdev = NULL;
5329
5330 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n");
5331
5332 /* unbind the queues and drop the subordinate channel config */
5333 netdev_unbind_sb_channel(adapter->netdev, vdev);
5334 netdev_set_sb_channel(vdev, 0);
5335
5336 clear_bit(accel->pool, adapter->fwd_bitmask);
5337 kfree(accel);
5338
5339 return err;
5340 }
5341
5342 static int ixgbe_macvlan_up(struct net_device *vdev, void *data)
5343 {
5344 struct ixgbe_adapter *adapter = data;
5345 struct ixgbe_fwd_adapter *accel;
5346
5347 if (!netif_is_macvlan(vdev))
5348 return 0;
5349
5350 accel = macvlan_accel_priv(vdev);
5351 if (!accel)
5352 return 0;
5353
5354 ixgbe_fwd_ring_up(adapter, accel);
5355
5356 return 0;
5357 }
5358
5359 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5360 {
5361 netdev_walk_all_upper_dev_rcu(adapter->netdev,
5362 ixgbe_macvlan_up, adapter);
5363 }
5364
5365 static void ixgbe_configure(struct ixgbe_adapter *adapter)
5366 {
5367 struct ixgbe_hw *hw = &adapter->hw;
5368
5369 ixgbe_configure_pb(adapter);
5370 #ifdef CONFIG_IXGBE_DCB
5371 ixgbe_configure_dcb(adapter);
5372 #endif
5373 /*
5374 * We must restore virtualization before VLANs or else
5375 * the VLVF registers will not be populated
5376 */
5377 ixgbe_configure_virtualization(adapter);
5378
5379 ixgbe_set_rx_mode(adapter->netdev);
5380 ixgbe_restore_vlan(adapter);
5381 ixgbe_ipsec_restore(adapter);
5382
5383 switch (hw->mac.type) {
5384 case ixgbe_mac_82599EB:
5385 case ixgbe_mac_X540:
5386 hw->mac.ops.disable_rx_buff(hw);
5387 break;
5388 default:
5389 break;
5390 }
5391
5392 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5393 ixgbe_init_fdir_signature_82599(&adapter->hw,
5394 adapter->fdir_pballoc);
5395 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5396 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5397 adapter->fdir_pballoc);
5398 ixgbe_fdir_filter_restore(adapter);
5399 }
5400
5401 switch (hw->mac.type) {
5402 case ixgbe_mac_82599EB:
5403 case ixgbe_mac_X540:
5404 hw->mac.ops.enable_rx_buff(hw);
5405 break;
5406 default:
5407 break;
5408 }
5409
5410 #ifdef CONFIG_IXGBE_DCA
5411 /* configure DCA */
5412 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5413 ixgbe_setup_dca(adapter);
5414 #endif /* CONFIG_IXGBE_DCA */
5415
5416 #ifdef IXGBE_FCOE
5417 /* configure FCoE L2 filters, redirection table, and Rx control */
5418 ixgbe_configure_fcoe(adapter);
5419
5420 #endif /* IXGBE_FCOE */
5421 ixgbe_configure_tx(adapter);
5422 ixgbe_configure_rx(adapter);
5423 ixgbe_configure_dfwd(adapter);
5424 }
5425
5426 /**
5427 * ixgbe_sfp_link_config - set up SFP+ link
5428 * @adapter: pointer to private adapter struct
5429 **/
5430 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5431 {
5432 /*
5433 * We are assuming the worst case scenario here, and that
5434 * is that an SFP was inserted/removed after the reset
5435 * but before SFP detection was enabled. As such the best
5436 * solution is to just start searching as soon as we start
5437 */
5438 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5439 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5440
5441 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5442 adapter->sfp_poll_time = 0;
5443 }
5444
5445 /**
5446 * ixgbe_non_sfp_link_config - set up non-SFP+ link
5447 * @hw: pointer to private hardware struct
5448 *
5449 * Returns 0 on success, negative on failure
5450 **/
5451 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
5452 {
5453 u32 speed;
5454 bool autoneg, link_up = false;
5455 int ret = IXGBE_ERR_LINK_SETUP;
5456
5457 if (hw->mac.ops.check_link)
5458 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
5459
5460 if (ret)
5461 return ret;
5462
5463 speed = hw->phy.autoneg_advertised;
5464 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5465 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5466 &autoneg);
5467 if (ret)
5468 return ret;
5469
5470 if (hw->mac.ops.setup_link)
5471 ret = hw->mac.ops.setup_link(hw, speed, link_up);
5472
5473 return ret;
5474 }
5475
5476 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
5477 {
5478 struct ixgbe_hw *hw = &adapter->hw;
5479 u32 gpie = 0;
5480
5481 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5482 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5483 IXGBE_GPIE_OCD;
5484 gpie |= IXGBE_GPIE_EIAME;
5485 /*
5486 * use EIAM to auto-mask when MSI-X interrupt is asserted
5487 * this saves a register write for every interrupt
5488 */
5489 switch (hw->mac.type) {
5490 case ixgbe_mac_82598EB:
5491 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5492 break;
5493 case ixgbe_mac_82599EB:
5494 case ixgbe_mac_X540:
5495 case ixgbe_mac_X550:
5496 case ixgbe_mac_X550EM_x:
5497 case ixgbe_mac_x550em_a:
5498 default:
5499 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5500 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5501 break;
5502 }
5503 } else {
5504 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5505 * specifically only auto mask tx and rx interrupts */
5506 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5507 }
5508
5509 /* XXX: to interrupt immediately for EICS writes, enable this */
5510 /* gpie |= IXGBE_GPIE_EIMEN; */
5511
5512 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5513 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
5514
5515 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5516 case IXGBE_82599_VMDQ_8Q_MASK:
5517 gpie |= IXGBE_GPIE_VTMODE_16;
5518 break;
5519 case IXGBE_82599_VMDQ_4Q_MASK:
5520 gpie |= IXGBE_GPIE_VTMODE_32;
5521 break;
5522 default:
5523 gpie |= IXGBE_GPIE_VTMODE_64;
5524 break;
5525 }
5526 }
5527
5528 /* Enable Thermal over heat sensor interrupt */
5529 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5530 switch (adapter->hw.mac.type) {
5531 case ixgbe_mac_82599EB:
5532 gpie |= IXGBE_SDP0_GPIEN_8259X;
5533 break;
5534 default:
5535 break;
5536 }
5537 }
5538
5539 /* Enable fan failure interrupt */
5540 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
5541 gpie |= IXGBE_SDP1_GPIEN(hw);
5542
5543 switch (hw->mac.type) {
5544 case ixgbe_mac_82599EB:
5545 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5546 break;
5547 case ixgbe_mac_X550EM_x:
5548 case ixgbe_mac_x550em_a:
5549 gpie |= IXGBE_SDP0_GPIEN_X540;
5550 break;
5551 default:
5552 break;
5553 }
5554
5555 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5556 }
5557
5558 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
5559 {
5560 struct ixgbe_hw *hw = &adapter->hw;
5561 int err;
5562 u32 ctrl_ext;
5563
5564 ixgbe_get_hw_control(adapter);
5565 ixgbe_setup_gpie(adapter);
5566
5567 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5568 ixgbe_configure_msix(adapter);
5569 else
5570 ixgbe_configure_msi_and_legacy(adapter);
5571
5572 /* enable the optics for 82599 SFP+ fiber */
5573 if (hw->mac.ops.enable_tx_laser)
5574 hw->mac.ops.enable_tx_laser(hw);
5575
5576 if (hw->phy.ops.set_phy_power)
5577 hw->phy.ops.set_phy_power(hw, true);
5578
5579 smp_mb__before_atomic();
5580 clear_bit(__IXGBE_DOWN, &adapter->state);
5581 ixgbe_napi_enable_all(adapter);
5582
5583 if (ixgbe_is_sfp(hw)) {
5584 ixgbe_sfp_link_config(adapter);
5585 } else {
5586 err = ixgbe_non_sfp_link_config(hw);
5587 if (err)
5588 e_err(probe, "link_config FAILED %d\n", err);
5589 }
5590
5591 /* clear any pending interrupts, may auto mask */
5592 IXGBE_READ_REG(hw, IXGBE_EICR);
5593 ixgbe_irq_enable(adapter, true, true);
5594
5595 /*
5596 * If this adapter has a fan, check to see if we had a failure
5597 * before we enabled the interrupt.
5598 */
5599 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5600 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5601 if (esdp & IXGBE_ESDP_SDP1)
5602 e_crit(drv, "Fan has stopped, replace the adapter\n");
5603 }
5604
5605 /* bring the link up in the watchdog, this could race with our first
5606 * link up interrupt but shouldn't be a problem */
5607 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5608 adapter->link_check_timeout = jiffies;
5609 mod_timer(&adapter->service_timer, jiffies);
5610
5611 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5612 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5613 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5614 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5615 }
5616
5617 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5618 {
5619 WARN_ON(in_interrupt());
5620 /* put off any impending NetWatchDogTimeout */
5621 netif_trans_update(adapter->netdev);
5622
5623 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5624 usleep_range(1000, 2000);
5625 if (adapter->hw.phy.type == ixgbe_phy_fw)
5626 ixgbe_watchdog_link_is_down(adapter);
5627 ixgbe_down(adapter);
5628 /*
5629 * If SR-IOV enabled then wait a bit before bringing the adapter
5630 * back up to give the VFs time to respond to the reset. The
5631 * two second wait is based upon the watchdog timer cycle in
5632 * the VF driver.
5633 */
5634 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5635 msleep(2000);
5636 ixgbe_up(adapter);
5637 clear_bit(__IXGBE_RESETTING, &adapter->state);
5638 }
5639
5640 void ixgbe_up(struct ixgbe_adapter *adapter)
5641 {
5642 /* hardware has been reset, we need to reload some things */
5643 ixgbe_configure(adapter);
5644
5645 ixgbe_up_complete(adapter);
5646 }
5647
5648 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter)
5649 {
5650 u16 devctl2;
5651
5652 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2);
5653
5654 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) {
5655 case IXGBE_PCIDEVCTRL2_17_34s:
5656 case IXGBE_PCIDEVCTRL2_4_8s:
5657 /* For now we cap the upper limit on delay to 2 seconds
5658 * as we end up going up to 34 seconds of delay in worst
5659 * case timeout value.
5660 */
5661 case IXGBE_PCIDEVCTRL2_1_2s:
5662 return 2000000ul; /* 2.0 s */
5663 case IXGBE_PCIDEVCTRL2_260_520ms:
5664 return 520000ul; /* 520 ms */
5665 case IXGBE_PCIDEVCTRL2_65_130ms:
5666 return 130000ul; /* 130 ms */
5667 case IXGBE_PCIDEVCTRL2_16_32ms:
5668 return 32000ul; /* 32 ms */
5669 case IXGBE_PCIDEVCTRL2_1_2ms:
5670 return 2000ul; /* 2 ms */
5671 case IXGBE_PCIDEVCTRL2_50_100us:
5672 return 100ul; /* 100 us */
5673 case IXGBE_PCIDEVCTRL2_16_32ms_def:
5674 return 32000ul; /* 32 ms */
5675 default:
5676 break;
5677 }
5678
5679 /* We shouldn't need to hit this path, but just in case default as
5680 * though completion timeout is not supported and support 32ms.
5681 */
5682 return 32000ul;
5683 }
5684
5685 void ixgbe_disable_rx(struct ixgbe_adapter *adapter)
5686 {
5687 unsigned long wait_delay, delay_interval;
5688 struct ixgbe_hw *hw = &adapter->hw;
5689 int i, wait_loop;
5690 u32 rxdctl;
5691
5692 /* disable receives */
5693 hw->mac.ops.disable_rx(hw);
5694
5695 if (ixgbe_removed(hw->hw_addr))
5696 return;
5697
5698 /* disable all enabled Rx queues */
5699 for (i = 0; i < adapter->num_rx_queues; i++) {
5700 struct ixgbe_ring *ring = adapter->rx_ring[i];
5701 u8 reg_idx = ring->reg_idx;
5702
5703 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5704 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5705 rxdctl |= IXGBE_RXDCTL_SWFLSH;
5706
5707 /* write value back with RXDCTL.ENABLE bit cleared */
5708 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
5709 }
5710
5711 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */
5712 if (hw->mac.type == ixgbe_mac_82598EB &&
5713 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5714 return;
5715
5716 /* Determine our minimum delay interval. We will increase this value
5717 * with each subsequent test. This way if the device returns quickly
5718 * we should spend as little time as possible waiting, however as
5719 * the time increases we will wait for larger periods of time.
5720 *
5721 * The trick here is that we increase the interval using the
5722 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5723 * of that wait is that it totals up to 100x whatever interval we
5724 * choose. Since our minimum wait is 100us we can just divide the
5725 * total timeout by 100 to get our minimum delay interval.
5726 */
5727 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5728
5729 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5730 wait_delay = delay_interval;
5731
5732 while (wait_loop--) {
5733 usleep_range(wait_delay, wait_delay + 10);
5734 wait_delay += delay_interval * 2;
5735 rxdctl = 0;
5736
5737 /* OR together the reading of all the active RXDCTL registers,
5738 * and then test the result. We need the disable to complete
5739 * before we start freeing the memory and invalidating the
5740 * DMA mappings.
5741 */
5742 for (i = 0; i < adapter->num_rx_queues; i++) {
5743 struct ixgbe_ring *ring = adapter->rx_ring[i];
5744 u8 reg_idx = ring->reg_idx;
5745
5746 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5747 }
5748
5749 if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
5750 return;
5751 }
5752
5753 e_err(drv,
5754 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5755 }
5756
5757 void ixgbe_disable_tx(struct ixgbe_adapter *adapter)
5758 {
5759 unsigned long wait_delay, delay_interval;
5760 struct ixgbe_hw *hw = &adapter->hw;
5761 int i, wait_loop;
5762 u32 txdctl;
5763
5764 if (ixgbe_removed(hw->hw_addr))
5765 return;
5766
5767 /* disable all enabled Tx queues */
5768 for (i = 0; i < adapter->num_tx_queues; i++) {
5769 struct ixgbe_ring *ring = adapter->tx_ring[i];
5770 u8 reg_idx = ring->reg_idx;
5771
5772 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5773 }
5774
5775 /* disable all enabled XDP Tx queues */
5776 for (i = 0; i < adapter->num_xdp_queues; i++) {
5777 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5778 u8 reg_idx = ring->reg_idx;
5779
5780 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5781 }
5782
5783 /* If the link is not up there shouldn't be much in the way of
5784 * pending transactions. Those that are left will be flushed out
5785 * when the reset logic goes through the flush sequence to clean out
5786 * the pending Tx transactions.
5787 */
5788 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5789 goto dma_engine_disable;
5790
5791 /* Determine our minimum delay interval. We will increase this value
5792 * with each subsequent test. This way if the device returns quickly
5793 * we should spend as little time as possible waiting, however as
5794 * the time increases we will wait for larger periods of time.
5795 *
5796 * The trick here is that we increase the interval using the
5797 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5798 * of that wait is that it totals up to 100x whatever interval we
5799 * choose. Since our minimum wait is 100us we can just divide the
5800 * total timeout by 100 to get our minimum delay interval.
5801 */
5802 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5803
5804 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5805 wait_delay = delay_interval;
5806
5807 while (wait_loop--) {
5808 usleep_range(wait_delay, wait_delay + 10);
5809 wait_delay += delay_interval * 2;
5810 txdctl = 0;
5811
5812 /* OR together the reading of all the active TXDCTL registers,
5813 * and then test the result. We need the disable to complete
5814 * before we start freeing the memory and invalidating the
5815 * DMA mappings.
5816 */
5817 for (i = 0; i < adapter->num_tx_queues; i++) {
5818 struct ixgbe_ring *ring = adapter->tx_ring[i];
5819 u8 reg_idx = ring->reg_idx;
5820
5821 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5822 }
5823 for (i = 0; i < adapter->num_xdp_queues; i++) {
5824 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5825 u8 reg_idx = ring->reg_idx;
5826
5827 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5828 }
5829
5830 if (!(txdctl & IXGBE_TXDCTL_ENABLE))
5831 goto dma_engine_disable;
5832 }
5833
5834 e_err(drv,
5835 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5836
5837 dma_engine_disable:
5838 /* Disable the Tx DMA engine on 82599 and later MAC */
5839 switch (hw->mac.type) {
5840 case ixgbe_mac_82599EB:
5841 case ixgbe_mac_X540:
5842 case ixgbe_mac_X550:
5843 case ixgbe_mac_X550EM_x:
5844 case ixgbe_mac_x550em_a:
5845 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5846 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5847 ~IXGBE_DMATXCTL_TE));
5848 /* fall through */
5849 default:
5850 break;
5851 }
5852 }
5853
5854 void ixgbe_reset(struct ixgbe_adapter *adapter)
5855 {
5856 struct ixgbe_hw *hw = &adapter->hw;
5857 struct net_device *netdev = adapter->netdev;
5858 int err;
5859
5860 if (ixgbe_removed(hw->hw_addr))
5861 return;
5862 /* lock SFP init bit to prevent race conditions with the watchdog */
5863 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5864 usleep_range(1000, 2000);
5865
5866 /* clear all SFP and link config related flags while holding SFP_INIT */
5867 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5868 IXGBE_FLAG2_SFP_NEEDS_RESET);
5869 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5870
5871 err = hw->mac.ops.init_hw(hw);
5872 switch (err) {
5873 case 0:
5874 case IXGBE_ERR_SFP_NOT_PRESENT:
5875 case IXGBE_ERR_SFP_NOT_SUPPORTED:
5876 break;
5877 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5878 e_dev_err("master disable timed out\n");
5879 break;
5880 case IXGBE_ERR_EEPROM_VERSION:
5881 /* We are running on a pre-production device, log a warning */
5882 e_dev_warn("This device is a pre-production adapter/LOM. "
5883 "Please be aware there may be issues associated with "
5884 "your hardware. If you are experiencing problems "
5885 "please contact your Intel or hardware "
5886 "representative who provided you with this "
5887 "hardware.\n");
5888 break;
5889 default:
5890 e_dev_err("Hardware Error: %d\n", err);
5891 }
5892
5893 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5894
5895 /* flush entries out of MAC table */
5896 ixgbe_flush_sw_mac_table(adapter);
5897 __dev_uc_unsync(netdev, NULL);
5898
5899 /* do not flush user set addresses */
5900 ixgbe_mac_set_default_filter(adapter);
5901
5902 /* update SAN MAC vmdq pool selection */
5903 if (hw->mac.san_mac_rar_index)
5904 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5905
5906 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5907 ixgbe_ptp_reset(adapter);
5908
5909 if (hw->phy.ops.set_phy_power) {
5910 if (!netif_running(adapter->netdev) && !adapter->wol)
5911 hw->phy.ops.set_phy_power(hw, false);
5912 else
5913 hw->phy.ops.set_phy_power(hw, true);
5914 }
5915 }
5916
5917 /**
5918 * ixgbe_clean_tx_ring - Free Tx Buffers
5919 * @tx_ring: ring to be cleaned
5920 **/
5921 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5922 {
5923 u16 i = tx_ring->next_to_clean;
5924 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
5925
5926 while (i != tx_ring->next_to_use) {
5927 union ixgbe_adv_tx_desc *eop_desc, *tx_desc;
5928
5929 /* Free all the Tx ring sk_buffs */
5930 if (ring_is_xdp(tx_ring))
5931 xdp_return_frame(tx_buffer->xdpf);
5932 else
5933 dev_kfree_skb_any(tx_buffer->skb);
5934
5935 /* unmap skb header data */
5936 dma_unmap_single(tx_ring->dev,
5937 dma_unmap_addr(tx_buffer, dma),
5938 dma_unmap_len(tx_buffer, len),
5939 DMA_TO_DEVICE);
5940
5941 /* check for eop_desc to determine the end of the packet */
5942 eop_desc = tx_buffer->next_to_watch;
5943 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5944
5945 /* unmap remaining buffers */
5946 while (tx_desc != eop_desc) {
5947 tx_buffer++;
5948 tx_desc++;
5949 i++;
5950 if (unlikely(i == tx_ring->count)) {
5951 i = 0;
5952 tx_buffer = tx_ring->tx_buffer_info;
5953 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5954 }
5955
5956 /* unmap any remaining paged data */
5957 if (dma_unmap_len(tx_buffer, len))
5958 dma_unmap_page(tx_ring->dev,
5959 dma_unmap_addr(tx_buffer, dma),
5960 dma_unmap_len(tx_buffer, len),
5961 DMA_TO_DEVICE);
5962 }
5963
5964 /* move us one more past the eop_desc for start of next pkt */
5965 tx_buffer++;
5966 i++;
5967 if (unlikely(i == tx_ring->count)) {
5968 i = 0;
5969 tx_buffer = tx_ring->tx_buffer_info;
5970 }
5971 }
5972
5973 /* reset BQL for queue */
5974 if (!ring_is_xdp(tx_ring))
5975 netdev_tx_reset_queue(txring_txq(tx_ring));
5976
5977 /* reset next_to_use and next_to_clean */
5978 tx_ring->next_to_use = 0;
5979 tx_ring->next_to_clean = 0;
5980 }
5981
5982 /**
5983 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
5984 * @adapter: board private structure
5985 **/
5986 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
5987 {
5988 int i;
5989
5990 for (i = 0; i < adapter->num_rx_queues; i++)
5991 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
5992 }
5993
5994 /**
5995 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
5996 * @adapter: board private structure
5997 **/
5998 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
5999 {
6000 int i;
6001
6002 for (i = 0; i < adapter->num_tx_queues; i++)
6003 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
6004 for (i = 0; i < adapter->num_xdp_queues; i++)
6005 ixgbe_clean_tx_ring(adapter->xdp_ring[i]);
6006 }
6007
6008 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
6009 {
6010 struct hlist_node *node2;
6011 struct ixgbe_fdir_filter *filter;
6012
6013 spin_lock(&adapter->fdir_perfect_lock);
6014
6015 hlist_for_each_entry_safe(filter, node2,
6016 &adapter->fdir_filter_list, fdir_node) {
6017 hlist_del(&filter->fdir_node);
6018 kfree(filter);
6019 }
6020 adapter->fdir_filter_count = 0;
6021
6022 spin_unlock(&adapter->fdir_perfect_lock);
6023 }
6024
6025 void ixgbe_down(struct ixgbe_adapter *adapter)
6026 {
6027 struct net_device *netdev = adapter->netdev;
6028 struct ixgbe_hw *hw = &adapter->hw;
6029 int i;
6030
6031 /* signal that we are down to the interrupt handler */
6032 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
6033 return; /* do nothing if already down */
6034
6035 /* Shut off incoming Tx traffic */
6036 netif_tx_stop_all_queues(netdev);
6037
6038 /* call carrier off first to avoid false dev_watchdog timeouts */
6039 netif_carrier_off(netdev);
6040 netif_tx_disable(netdev);
6041
6042 /* Disable Rx */
6043 ixgbe_disable_rx(adapter);
6044
6045 /* synchronize_sched() needed for pending XDP buffers to drain */
6046 if (adapter->xdp_ring[0])
6047 synchronize_sched();
6048
6049 ixgbe_irq_disable(adapter);
6050
6051 ixgbe_napi_disable_all(adapter);
6052
6053 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
6054 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6055 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6056
6057 del_timer_sync(&adapter->service_timer);
6058
6059 if (adapter->num_vfs) {
6060 /* Clear EITR Select mapping */
6061 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
6062
6063 /* Mark all the VFs as inactive */
6064 for (i = 0 ; i < adapter->num_vfs; i++)
6065 adapter->vfinfo[i].clear_to_send = false;
6066
6067 /* ping all the active vfs to let them know we are going down */
6068 ixgbe_ping_all_vfs(adapter);
6069
6070 /* Disable all VFTE/VFRE TX/RX */
6071 ixgbe_disable_tx_rx(adapter);
6072 }
6073
6074 /* disable transmits in the hardware now that interrupts are off */
6075 ixgbe_disable_tx(adapter);
6076
6077 if (!pci_channel_offline(adapter->pdev))
6078 ixgbe_reset(adapter);
6079
6080 /* power down the optics for 82599 SFP+ fiber */
6081 if (hw->mac.ops.disable_tx_laser)
6082 hw->mac.ops.disable_tx_laser(hw);
6083
6084 ixgbe_clean_all_tx_rings(adapter);
6085 ixgbe_clean_all_rx_rings(adapter);
6086 }
6087
6088 /**
6089 * ixgbe_eee_capable - helper function to determine EEE support on X550
6090 * @adapter: board private structure
6091 */
6092 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter)
6093 {
6094 struct ixgbe_hw *hw = &adapter->hw;
6095
6096 switch (hw->device_id) {
6097 case IXGBE_DEV_ID_X550EM_A_1G_T:
6098 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6099 if (!hw->phy.eee_speeds_supported)
6100 break;
6101 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE;
6102 if (!hw->phy.eee_speeds_advertised)
6103 break;
6104 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
6105 break;
6106 default:
6107 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE;
6108 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
6109 break;
6110 }
6111 }
6112
6113 /**
6114 * ixgbe_tx_timeout - Respond to a Tx Hang
6115 * @netdev: network interface device structure
6116 **/
6117 static void ixgbe_tx_timeout(struct net_device *netdev)
6118 {
6119 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6120
6121 /* Do the reset outside of interrupt context */
6122 ixgbe_tx_timeout_reset(adapter);
6123 }
6124
6125 #ifdef CONFIG_IXGBE_DCB
6126 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter)
6127 {
6128 struct ixgbe_hw *hw = &adapter->hw;
6129 struct tc_configuration *tc;
6130 int j;
6131
6132 switch (hw->mac.type) {
6133 case ixgbe_mac_82598EB:
6134 case ixgbe_mac_82599EB:
6135 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
6136 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
6137 break;
6138 case ixgbe_mac_X540:
6139 case ixgbe_mac_X550:
6140 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
6141 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
6142 break;
6143 case ixgbe_mac_X550EM_x:
6144 case ixgbe_mac_x550em_a:
6145 default:
6146 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS;
6147 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS;
6148 break;
6149 }
6150
6151 /* Configure DCB traffic classes */
6152 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
6153 tc = &adapter->dcb_cfg.tc_config[j];
6154 tc->path[DCB_TX_CONFIG].bwg_id = 0;
6155 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
6156 tc->path[DCB_RX_CONFIG].bwg_id = 0;
6157 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
6158 tc->dcb_pfc = pfc_disabled;
6159 }
6160
6161 /* Initialize default user to priority mapping, UPx->TC0 */
6162 tc = &adapter->dcb_cfg.tc_config[0];
6163 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
6164 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
6165
6166 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
6167 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
6168 adapter->dcb_cfg.pfc_mode_enable = false;
6169 adapter->dcb_set_bitmap = 0x00;
6170 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
6171 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
6172 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
6173 sizeof(adapter->temp_dcb_cfg));
6174 }
6175 #endif
6176
6177 /**
6178 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
6179 * @adapter: board private structure to initialize
6180 * @ii: pointer to ixgbe_info for device
6181 *
6182 * ixgbe_sw_init initializes the Adapter private data structure.
6183 * Fields are initialized based on PCI device information and
6184 * OS network device settings (MTU size).
6185 **/
6186 static int ixgbe_sw_init(struct ixgbe_adapter *adapter,
6187 const struct ixgbe_info *ii)
6188 {
6189 struct ixgbe_hw *hw = &adapter->hw;
6190 struct pci_dev *pdev = adapter->pdev;
6191 unsigned int rss, fdir;
6192 u32 fwsm;
6193 int i;
6194
6195 /* PCI config space info */
6196
6197 hw->vendor_id = pdev->vendor;
6198 hw->device_id = pdev->device;
6199 hw->revision_id = pdev->revision;
6200 hw->subsystem_vendor_id = pdev->subsystem_vendor;
6201 hw->subsystem_device_id = pdev->subsystem_device;
6202
6203 /* get_invariants needs the device IDs */
6204 ii->get_invariants(hw);
6205
6206 /* Set common capability flags and settings */
6207 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
6208 adapter->ring_feature[RING_F_RSS].limit = rss;
6209 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
6210 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
6211 adapter->atr_sample_rate = 20;
6212 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
6213 adapter->ring_feature[RING_F_FDIR].limit = fdir;
6214 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
6215 adapter->ring_feature[RING_F_VMDQ].limit = 1;
6216 #ifdef CONFIG_IXGBE_DCA
6217 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
6218 #endif
6219 #ifdef CONFIG_IXGBE_DCB
6220 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
6221 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6222 #endif
6223 #ifdef IXGBE_FCOE
6224 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
6225 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6226 #ifdef CONFIG_IXGBE_DCB
6227 /* Default traffic class to use for FCoE */
6228 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
6229 #endif /* CONFIG_IXGBE_DCB */
6230 #endif /* IXGBE_FCOE */
6231
6232 /* initialize static ixgbe jump table entries */
6233 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]),
6234 GFP_KERNEL);
6235 if (!adapter->jump_tables[0])
6236 return -ENOMEM;
6237 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields;
6238
6239 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++)
6240 adapter->jump_tables[i] = NULL;
6241
6242 adapter->mac_table = kcalloc(hw->mac.num_rar_entries,
6243 sizeof(struct ixgbe_mac_addr),
6244 GFP_KERNEL);
6245 if (!adapter->mac_table)
6246 return -ENOMEM;
6247
6248 if (ixgbe_init_rss_key(adapter))
6249 return -ENOMEM;
6250
6251 /* Set MAC specific capability flags and exceptions */
6252 switch (hw->mac.type) {
6253 case ixgbe_mac_82598EB:
6254 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
6255
6256 if (hw->device_id == IXGBE_DEV_ID_82598AT)
6257 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
6258
6259 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
6260 adapter->ring_feature[RING_F_FDIR].limit = 0;
6261 adapter->atr_sample_rate = 0;
6262 adapter->fdir_pballoc = 0;
6263 #ifdef IXGBE_FCOE
6264 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6265 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6266 #ifdef CONFIG_IXGBE_DCB
6267 adapter->fcoe.up = 0;
6268 #endif /* IXGBE_DCB */
6269 #endif /* IXGBE_FCOE */
6270 break;
6271 case ixgbe_mac_82599EB:
6272 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
6273 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6274 break;
6275 case ixgbe_mac_X540:
6276 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
6277 if (fwsm & IXGBE_FWSM_TS_ENABLED)
6278 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6279 break;
6280 case ixgbe_mac_x550em_a:
6281 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE;
6282 switch (hw->device_id) {
6283 case IXGBE_DEV_ID_X550EM_A_1G_T:
6284 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6285 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6286 break;
6287 default:
6288 break;
6289 }
6290 /* fall through */
6291 case ixgbe_mac_X550EM_x:
6292 #ifdef CONFIG_IXGBE_DCB
6293 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE;
6294 #endif
6295 #ifdef IXGBE_FCOE
6296 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6297 #ifdef CONFIG_IXGBE_DCB
6298 adapter->fcoe.up = 0;
6299 #endif /* IXGBE_DCB */
6300 #endif /* IXGBE_FCOE */
6301 /* Fall Through */
6302 case ixgbe_mac_X550:
6303 if (hw->mac.type == ixgbe_mac_X550)
6304 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6305 #ifdef CONFIG_IXGBE_DCA
6306 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
6307 #endif
6308 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
6309 break;
6310 default:
6311 break;
6312 }
6313
6314 #ifdef IXGBE_FCOE
6315 /* FCoE support exists, always init the FCoE lock */
6316 spin_lock_init(&adapter->fcoe.lock);
6317
6318 #endif
6319 /* n-tuple support exists, always init our spinlock */
6320 spin_lock_init(&adapter->fdir_perfect_lock);
6321
6322 #ifdef CONFIG_IXGBE_DCB
6323 ixgbe_init_dcb(adapter);
6324 #endif
6325 ixgbe_init_ipsec_offload(adapter);
6326
6327 /* default flow control settings */
6328 hw->fc.requested_mode = ixgbe_fc_full;
6329 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
6330 ixgbe_pbthresh_setup(adapter);
6331 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
6332 hw->fc.send_xon = true;
6333 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
6334
6335 #ifdef CONFIG_PCI_IOV
6336 if (max_vfs > 0)
6337 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
6338
6339 /* assign number of SR-IOV VFs */
6340 if (hw->mac.type != ixgbe_mac_82598EB) {
6341 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
6342 max_vfs = 0;
6343 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
6344 }
6345 }
6346 #endif /* CONFIG_PCI_IOV */
6347
6348 /* enable itr by default in dynamic mode */
6349 adapter->rx_itr_setting = 1;
6350 adapter->tx_itr_setting = 1;
6351
6352 /* set default ring sizes */
6353 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
6354 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
6355
6356 /* set default work limits */
6357 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
6358
6359 /* initialize eeprom parameters */
6360 if (ixgbe_init_eeprom_params_generic(hw)) {
6361 e_dev_err("EEPROM initialization failed\n");
6362 return -EIO;
6363 }
6364
6365 /* PF holds first pool slot */
6366 set_bit(0, adapter->fwd_bitmask);
6367 set_bit(__IXGBE_DOWN, &adapter->state);
6368
6369 return 0;
6370 }
6371
6372 /**
6373 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
6374 * @tx_ring: tx descriptor ring (for a specific queue) to setup
6375 *
6376 * Return 0 on success, negative on failure
6377 **/
6378 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
6379 {
6380 struct device *dev = tx_ring->dev;
6381 int orig_node = dev_to_node(dev);
6382 int ring_node = -1;
6383 int size;
6384
6385 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
6386
6387 if (tx_ring->q_vector)
6388 ring_node = tx_ring->q_vector->numa_node;
6389
6390 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node);
6391 if (!tx_ring->tx_buffer_info)
6392 tx_ring->tx_buffer_info = vmalloc(size);
6393 if (!tx_ring->tx_buffer_info)
6394 goto err;
6395
6396 /* round up to nearest 4K */
6397 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
6398 tx_ring->size = ALIGN(tx_ring->size, 4096);
6399
6400 set_dev_node(dev, ring_node);
6401 tx_ring->desc = dma_alloc_coherent(dev,
6402 tx_ring->size,
6403 &tx_ring->dma,
6404 GFP_KERNEL);
6405 set_dev_node(dev, orig_node);
6406 if (!tx_ring->desc)
6407 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
6408 &tx_ring->dma, GFP_KERNEL);
6409 if (!tx_ring->desc)
6410 goto err;
6411
6412 tx_ring->next_to_use = 0;
6413 tx_ring->next_to_clean = 0;
6414 return 0;
6415
6416 err:
6417 vfree(tx_ring->tx_buffer_info);
6418 tx_ring->tx_buffer_info = NULL;
6419 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
6420 return -ENOMEM;
6421 }
6422
6423 /**
6424 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
6425 * @adapter: board private structure
6426 *
6427 * If this function returns with an error, then it's possible one or
6428 * more of the rings is populated (while the rest are not). It is the
6429 * callers duty to clean those orphaned rings.
6430 *
6431 * Return 0 on success, negative on failure
6432 **/
6433 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
6434 {
6435 int i, j = 0, err = 0;
6436
6437 for (i = 0; i < adapter->num_tx_queues; i++) {
6438 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
6439 if (!err)
6440 continue;
6441
6442 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
6443 goto err_setup_tx;
6444 }
6445 for (j = 0; j < adapter->num_xdp_queues; j++) {
6446 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]);
6447 if (!err)
6448 continue;
6449
6450 e_err(probe, "Allocation for Tx Queue %u failed\n", j);
6451 goto err_setup_tx;
6452 }
6453
6454 return 0;
6455 err_setup_tx:
6456 /* rewind the index freeing the rings as we go */
6457 while (j--)
6458 ixgbe_free_tx_resources(adapter->xdp_ring[j]);
6459 while (i--)
6460 ixgbe_free_tx_resources(adapter->tx_ring[i]);
6461 return err;
6462 }
6463
6464 /**
6465 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
6466 * @adapter: pointer to ixgbe_adapter
6467 * @rx_ring: rx descriptor ring (for a specific queue) to setup
6468 *
6469 * Returns 0 on success, negative on failure
6470 **/
6471 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
6472 struct ixgbe_ring *rx_ring)
6473 {
6474 struct device *dev = rx_ring->dev;
6475 int orig_node = dev_to_node(dev);
6476 int ring_node = -1;
6477 int size, err;
6478
6479 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
6480
6481 if (rx_ring->q_vector)
6482 ring_node = rx_ring->q_vector->numa_node;
6483
6484 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node);
6485 if (!rx_ring->rx_buffer_info)
6486 rx_ring->rx_buffer_info = vmalloc(size);
6487 if (!rx_ring->rx_buffer_info)
6488 goto err;
6489
6490 /* Round up to nearest 4K */
6491 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
6492 rx_ring->size = ALIGN(rx_ring->size, 4096);
6493
6494 set_dev_node(dev, ring_node);
6495 rx_ring->desc = dma_alloc_coherent(dev,
6496 rx_ring->size,
6497 &rx_ring->dma,
6498 GFP_KERNEL);
6499 set_dev_node(dev, orig_node);
6500 if (!rx_ring->desc)
6501 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
6502 &rx_ring->dma, GFP_KERNEL);
6503 if (!rx_ring->desc)
6504 goto err;
6505
6506 rx_ring->next_to_clean = 0;
6507 rx_ring->next_to_use = 0;
6508
6509 /* XDP RX-queue info */
6510 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev,
6511 rx_ring->queue_index) < 0)
6512 goto err;
6513
6514 err = xdp_rxq_info_reg_mem_model(&rx_ring->xdp_rxq,
6515 MEM_TYPE_PAGE_SHARED, NULL);
6516 if (err) {
6517 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
6518 goto err;
6519 }
6520
6521 rx_ring->xdp_prog = adapter->xdp_prog;
6522
6523 return 0;
6524 err:
6525 vfree(rx_ring->rx_buffer_info);
6526 rx_ring->rx_buffer_info = NULL;
6527 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
6528 return -ENOMEM;
6529 }
6530
6531 /**
6532 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
6533 * @adapter: board private structure
6534 *
6535 * If this function returns with an error, then it's possible one or
6536 * more of the rings is populated (while the rest are not). It is the
6537 * callers duty to clean those orphaned rings.
6538 *
6539 * Return 0 on success, negative on failure
6540 **/
6541 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
6542 {
6543 int i, err = 0;
6544
6545 for (i = 0; i < adapter->num_rx_queues; i++) {
6546 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
6547 if (!err)
6548 continue;
6549
6550 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
6551 goto err_setup_rx;
6552 }
6553
6554 #ifdef IXGBE_FCOE
6555 err = ixgbe_setup_fcoe_ddp_resources(adapter);
6556 if (!err)
6557 #endif
6558 return 0;
6559 err_setup_rx:
6560 /* rewind the index freeing the rings as we go */
6561 while (i--)
6562 ixgbe_free_rx_resources(adapter->rx_ring[i]);
6563 return err;
6564 }
6565
6566 /**
6567 * ixgbe_free_tx_resources - Free Tx Resources per Queue
6568 * @tx_ring: Tx descriptor ring for a specific queue
6569 *
6570 * Free all transmit software resources
6571 **/
6572 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
6573 {
6574 ixgbe_clean_tx_ring(tx_ring);
6575
6576 vfree(tx_ring->tx_buffer_info);
6577 tx_ring->tx_buffer_info = NULL;
6578
6579 /* if not set, then don't free */
6580 if (!tx_ring->desc)
6581 return;
6582
6583 dma_free_coherent(tx_ring->dev, tx_ring->size,
6584 tx_ring->desc, tx_ring->dma);
6585
6586 tx_ring->desc = NULL;
6587 }
6588
6589 /**
6590 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
6591 * @adapter: board private structure
6592 *
6593 * Free all transmit software resources
6594 **/
6595 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
6596 {
6597 int i;
6598
6599 for (i = 0; i < adapter->num_tx_queues; i++)
6600 if (adapter->tx_ring[i]->desc)
6601 ixgbe_free_tx_resources(adapter->tx_ring[i]);
6602 for (i = 0; i < adapter->num_xdp_queues; i++)
6603 if (adapter->xdp_ring[i]->desc)
6604 ixgbe_free_tx_resources(adapter->xdp_ring[i]);
6605 }
6606
6607 /**
6608 * ixgbe_free_rx_resources - Free Rx Resources
6609 * @rx_ring: ring to clean the resources from
6610 *
6611 * Free all receive software resources
6612 **/
6613 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
6614 {
6615 ixgbe_clean_rx_ring(rx_ring);
6616
6617 rx_ring->xdp_prog = NULL;
6618 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
6619 vfree(rx_ring->rx_buffer_info);
6620 rx_ring->rx_buffer_info = NULL;
6621
6622 /* if not set, then don't free */
6623 if (!rx_ring->desc)
6624 return;
6625
6626 dma_free_coherent(rx_ring->dev, rx_ring->size,
6627 rx_ring->desc, rx_ring->dma);
6628
6629 rx_ring->desc = NULL;
6630 }
6631
6632 /**
6633 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6634 * @adapter: board private structure
6635 *
6636 * Free all receive software resources
6637 **/
6638 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6639 {
6640 int i;
6641
6642 #ifdef IXGBE_FCOE
6643 ixgbe_free_fcoe_ddp_resources(adapter);
6644
6645 #endif
6646 for (i = 0; i < adapter->num_rx_queues; i++)
6647 if (adapter->rx_ring[i]->desc)
6648 ixgbe_free_rx_resources(adapter->rx_ring[i]);
6649 }
6650
6651 /**
6652 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6653 * @netdev: network interface device structure
6654 * @new_mtu: new value for maximum frame size
6655 *
6656 * Returns 0 on success, negative on failure
6657 **/
6658 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6659 {
6660 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6661
6662 if (adapter->xdp_prog) {
6663 int new_frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN +
6664 VLAN_HLEN;
6665 int i;
6666
6667 for (i = 0; i < adapter->num_rx_queues; i++) {
6668 struct ixgbe_ring *ring = adapter->rx_ring[i];
6669
6670 if (new_frame_size > ixgbe_rx_bufsz(ring)) {
6671 e_warn(probe, "Requested MTU size is not supported with XDP\n");
6672 return -EINVAL;
6673 }
6674 }
6675 }
6676
6677 /*
6678 * For 82599EB we cannot allow legacy VFs to enable their receive
6679 * paths when MTU greater than 1500 is configured. So display a
6680 * warning that legacy VFs will be disabled.
6681 */
6682 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6683 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
6684 (new_mtu > ETH_DATA_LEN))
6685 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
6686
6687 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
6688
6689 /* must set new MTU before calling down or up */
6690 netdev->mtu = new_mtu;
6691
6692 if (netif_running(netdev))
6693 ixgbe_reinit_locked(adapter);
6694
6695 return 0;
6696 }
6697
6698 /**
6699 * ixgbe_open - Called when a network interface is made active
6700 * @netdev: network interface device structure
6701 *
6702 * Returns 0 on success, negative value on failure
6703 *
6704 * The open entry point is called when a network interface is made
6705 * active by the system (IFF_UP). At this point all resources needed
6706 * for transmit and receive operations are allocated, the interrupt
6707 * handler is registered with the OS, the watchdog timer is started,
6708 * and the stack is notified that the interface is ready.
6709 **/
6710 int ixgbe_open(struct net_device *netdev)
6711 {
6712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6713 struct ixgbe_hw *hw = &adapter->hw;
6714 int err, queues;
6715
6716 /* disallow open during test */
6717 if (test_bit(__IXGBE_TESTING, &adapter->state))
6718 return -EBUSY;
6719
6720 netif_carrier_off(netdev);
6721
6722 /* allocate transmit descriptors */
6723 err = ixgbe_setup_all_tx_resources(adapter);
6724 if (err)
6725 goto err_setup_tx;
6726
6727 /* allocate receive descriptors */
6728 err = ixgbe_setup_all_rx_resources(adapter);
6729 if (err)
6730 goto err_setup_rx;
6731
6732 ixgbe_configure(adapter);
6733
6734 err = ixgbe_request_irq(adapter);
6735 if (err)
6736 goto err_req_irq;
6737
6738 /* Notify the stack of the actual queue counts. */
6739 queues = adapter->num_tx_queues;
6740 err = netif_set_real_num_tx_queues(netdev, queues);
6741 if (err)
6742 goto err_set_queues;
6743
6744 queues = adapter->num_rx_queues;
6745 err = netif_set_real_num_rx_queues(netdev, queues);
6746 if (err)
6747 goto err_set_queues;
6748
6749 ixgbe_ptp_init(adapter);
6750
6751 ixgbe_up_complete(adapter);
6752
6753 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK);
6754 udp_tunnel_get_rx_info(netdev);
6755
6756 return 0;
6757
6758 err_set_queues:
6759 ixgbe_free_irq(adapter);
6760 err_req_irq:
6761 ixgbe_free_all_rx_resources(adapter);
6762 if (hw->phy.ops.set_phy_power && !adapter->wol)
6763 hw->phy.ops.set_phy_power(&adapter->hw, false);
6764 err_setup_rx:
6765 ixgbe_free_all_tx_resources(adapter);
6766 err_setup_tx:
6767 ixgbe_reset(adapter);
6768
6769 return err;
6770 }
6771
6772 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6773 {
6774 ixgbe_ptp_suspend(adapter);
6775
6776 if (adapter->hw.phy.ops.enter_lplu) {
6777 adapter->hw.phy.reset_disable = true;
6778 ixgbe_down(adapter);
6779 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6780 adapter->hw.phy.reset_disable = false;
6781 } else {
6782 ixgbe_down(adapter);
6783 }
6784
6785 ixgbe_free_irq(adapter);
6786
6787 ixgbe_free_all_tx_resources(adapter);
6788 ixgbe_free_all_rx_resources(adapter);
6789 }
6790
6791 /**
6792 * ixgbe_close - Disables a network interface
6793 * @netdev: network interface device structure
6794 *
6795 * Returns 0, this is not allowed to fail
6796 *
6797 * The close entry point is called when an interface is de-activated
6798 * by the OS. The hardware is still under the drivers control, but
6799 * needs to be disabled. A global MAC reset is issued to stop the
6800 * hardware, and all transmit and receive resources are freed.
6801 **/
6802 int ixgbe_close(struct net_device *netdev)
6803 {
6804 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6805
6806 ixgbe_ptp_stop(adapter);
6807
6808 if (netif_device_present(netdev))
6809 ixgbe_close_suspend(adapter);
6810
6811 ixgbe_fdir_filter_exit(adapter);
6812
6813 ixgbe_release_hw_control(adapter);
6814
6815 return 0;
6816 }
6817
6818 #ifdef CONFIG_PM
6819 static int ixgbe_resume(struct pci_dev *pdev)
6820 {
6821 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6822 struct net_device *netdev = adapter->netdev;
6823 u32 err;
6824
6825 adapter->hw.hw_addr = adapter->io_addr;
6826 pci_set_power_state(pdev, PCI_D0);
6827 pci_restore_state(pdev);
6828 /*
6829 * pci_restore_state clears dev->state_saved so call
6830 * pci_save_state to restore it.
6831 */
6832 pci_save_state(pdev);
6833
6834 err = pci_enable_device_mem(pdev);
6835 if (err) {
6836 e_dev_err("Cannot enable PCI device from suspend\n");
6837 return err;
6838 }
6839 smp_mb__before_atomic();
6840 clear_bit(__IXGBE_DISABLED, &adapter->state);
6841 pci_set_master(pdev);
6842
6843 pci_wake_from_d3(pdev, false);
6844
6845 ixgbe_reset(adapter);
6846
6847 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6848
6849 rtnl_lock();
6850 err = ixgbe_init_interrupt_scheme(adapter);
6851 if (!err && netif_running(netdev))
6852 err = ixgbe_open(netdev);
6853
6854
6855 if (!err)
6856 netif_device_attach(netdev);
6857 rtnl_unlock();
6858
6859 return err;
6860 }
6861 #endif /* CONFIG_PM */
6862
6863 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
6864 {
6865 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6866 struct net_device *netdev = adapter->netdev;
6867 struct ixgbe_hw *hw = &adapter->hw;
6868 u32 ctrl;
6869 u32 wufc = adapter->wol;
6870 #ifdef CONFIG_PM
6871 int retval = 0;
6872 #endif
6873
6874 rtnl_lock();
6875 netif_device_detach(netdev);
6876
6877 if (netif_running(netdev))
6878 ixgbe_close_suspend(adapter);
6879
6880 ixgbe_clear_interrupt_scheme(adapter);
6881 rtnl_unlock();
6882
6883 #ifdef CONFIG_PM
6884 retval = pci_save_state(pdev);
6885 if (retval)
6886 return retval;
6887
6888 #endif
6889 if (hw->mac.ops.stop_link_on_d3)
6890 hw->mac.ops.stop_link_on_d3(hw);
6891
6892 if (wufc) {
6893 u32 fctrl;
6894
6895 ixgbe_set_rx_mode(netdev);
6896
6897 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6898 if (hw->mac.ops.enable_tx_laser)
6899 hw->mac.ops.enable_tx_laser(hw);
6900
6901 /* enable the reception of multicast packets */
6902 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6903 fctrl |= IXGBE_FCTRL_MPE;
6904 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6905
6906 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6907 ctrl |= IXGBE_CTRL_GIO_DIS;
6908 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6909
6910 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6911 } else {
6912 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6913 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6914 }
6915
6916 switch (hw->mac.type) {
6917 case ixgbe_mac_82598EB:
6918 pci_wake_from_d3(pdev, false);
6919 break;
6920 case ixgbe_mac_82599EB:
6921 case ixgbe_mac_X540:
6922 case ixgbe_mac_X550:
6923 case ixgbe_mac_X550EM_x:
6924 case ixgbe_mac_x550em_a:
6925 pci_wake_from_d3(pdev, !!wufc);
6926 break;
6927 default:
6928 break;
6929 }
6930
6931 *enable_wake = !!wufc;
6932 if (hw->phy.ops.set_phy_power && !*enable_wake)
6933 hw->phy.ops.set_phy_power(hw, false);
6934
6935 ixgbe_release_hw_control(adapter);
6936
6937 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6938 pci_disable_device(pdev);
6939
6940 return 0;
6941 }
6942
6943 #ifdef CONFIG_PM
6944 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6945 {
6946 int retval;
6947 bool wake;
6948
6949 retval = __ixgbe_shutdown(pdev, &wake);
6950 if (retval)
6951 return retval;
6952
6953 if (wake) {
6954 pci_prepare_to_sleep(pdev);
6955 } else {
6956 pci_wake_from_d3(pdev, false);
6957 pci_set_power_state(pdev, PCI_D3hot);
6958 }
6959
6960 return 0;
6961 }
6962 #endif /* CONFIG_PM */
6963
6964 static void ixgbe_shutdown(struct pci_dev *pdev)
6965 {
6966 bool wake;
6967
6968 __ixgbe_shutdown(pdev, &wake);
6969
6970 if (system_state == SYSTEM_POWER_OFF) {
6971 pci_wake_from_d3(pdev, wake);
6972 pci_set_power_state(pdev, PCI_D3hot);
6973 }
6974 }
6975
6976 /**
6977 * ixgbe_update_stats - Update the board statistics counters.
6978 * @adapter: board private structure
6979 **/
6980 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6981 {
6982 struct net_device *netdev = adapter->netdev;
6983 struct ixgbe_hw *hw = &adapter->hw;
6984 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6985 u64 total_mpc = 0;
6986 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
6987 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6988 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
6989 u64 alloc_rx_page = 0;
6990 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
6991
6992 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6993 test_bit(__IXGBE_RESETTING, &adapter->state))
6994 return;
6995
6996 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
6997 u64 rsc_count = 0;
6998 u64 rsc_flush = 0;
6999 for (i = 0; i < adapter->num_rx_queues; i++) {
7000 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
7001 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
7002 }
7003 adapter->rsc_total_count = rsc_count;
7004 adapter->rsc_total_flush = rsc_flush;
7005 }
7006
7007 for (i = 0; i < adapter->num_rx_queues; i++) {
7008 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]);
7009
7010 if (!rx_ring)
7011 continue;
7012 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
7013 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page;
7014 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
7015 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
7016 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
7017 bytes += rx_ring->stats.bytes;
7018 packets += rx_ring->stats.packets;
7019 }
7020 adapter->non_eop_descs = non_eop_descs;
7021 adapter->alloc_rx_page = alloc_rx_page;
7022 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
7023 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
7024 adapter->hw_csum_rx_error = hw_csum_rx_error;
7025 netdev->stats.rx_bytes = bytes;
7026 netdev->stats.rx_packets = packets;
7027
7028 bytes = 0;
7029 packets = 0;
7030 /* gather some stats to the adapter struct that are per queue */
7031 for (i = 0; i < adapter->num_tx_queues; i++) {
7032 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]);
7033
7034 if (!tx_ring)
7035 continue;
7036 restart_queue += tx_ring->tx_stats.restart_queue;
7037 tx_busy += tx_ring->tx_stats.tx_busy;
7038 bytes += tx_ring->stats.bytes;
7039 packets += tx_ring->stats.packets;
7040 }
7041 for (i = 0; i < adapter->num_xdp_queues; i++) {
7042 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]);
7043
7044 if (!xdp_ring)
7045 continue;
7046 restart_queue += xdp_ring->tx_stats.restart_queue;
7047 tx_busy += xdp_ring->tx_stats.tx_busy;
7048 bytes += xdp_ring->stats.bytes;
7049 packets += xdp_ring->stats.packets;
7050 }
7051 adapter->restart_queue = restart_queue;
7052 adapter->tx_busy = tx_busy;
7053 netdev->stats.tx_bytes = bytes;
7054 netdev->stats.tx_packets = packets;
7055
7056 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
7057
7058 /* 8 register reads */
7059 for (i = 0; i < 8; i++) {
7060 /* for packet buffers not used, the register should read 0 */
7061 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
7062 missed_rx += mpc;
7063 hwstats->mpc[i] += mpc;
7064 total_mpc += hwstats->mpc[i];
7065 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
7066 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
7067 switch (hw->mac.type) {
7068 case ixgbe_mac_82598EB:
7069 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
7070 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
7071 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7072 hwstats->pxonrxc[i] +=
7073 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
7074 break;
7075 case ixgbe_mac_82599EB:
7076 case ixgbe_mac_X540:
7077 case ixgbe_mac_X550:
7078 case ixgbe_mac_X550EM_x:
7079 case ixgbe_mac_x550em_a:
7080 hwstats->pxonrxc[i] +=
7081 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
7082 break;
7083 default:
7084 break;
7085 }
7086 }
7087
7088 /*16 register reads */
7089 for (i = 0; i < 16; i++) {
7090 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
7091 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
7092 if ((hw->mac.type == ixgbe_mac_82599EB) ||
7093 (hw->mac.type == ixgbe_mac_X540) ||
7094 (hw->mac.type == ixgbe_mac_X550) ||
7095 (hw->mac.type == ixgbe_mac_X550EM_x) ||
7096 (hw->mac.type == ixgbe_mac_x550em_a)) {
7097 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
7098 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
7099 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
7100 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
7101 }
7102 }
7103
7104 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
7105 /* work around hardware counting issue */
7106 hwstats->gprc -= missed_rx;
7107
7108 ixgbe_update_xoff_received(adapter);
7109
7110 /* 82598 hardware only has a 32 bit counter in the high register */
7111 switch (hw->mac.type) {
7112 case ixgbe_mac_82598EB:
7113 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
7114 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
7115 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
7116 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
7117 break;
7118 case ixgbe_mac_X540:
7119 case ixgbe_mac_X550:
7120 case ixgbe_mac_X550EM_x:
7121 case ixgbe_mac_x550em_a:
7122 /* OS2BMC stats are X540 and later */
7123 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
7124 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
7125 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
7126 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
7127 /* fall through */
7128 case ixgbe_mac_82599EB:
7129 for (i = 0; i < 16; i++)
7130 adapter->hw_rx_no_dma_resources +=
7131 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7132 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
7133 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7134 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
7135 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7136 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
7137 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7138 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7139 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
7140 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
7141 #ifdef IXGBE_FCOE
7142 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
7143 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
7144 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
7145 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
7146 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
7147 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7148 /* Add up per cpu counters for total ddp aloc fail */
7149 if (adapter->fcoe.ddp_pool) {
7150 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
7151 struct ixgbe_fcoe_ddp_pool *ddp_pool;
7152 unsigned int cpu;
7153 u64 noddp = 0, noddp_ext_buff = 0;
7154 for_each_possible_cpu(cpu) {
7155 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
7156 noddp += ddp_pool->noddp;
7157 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7158 }
7159 hwstats->fcoe_noddp = noddp;
7160 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7161 }
7162 #endif /* IXGBE_FCOE */
7163 break;
7164 default:
7165 break;
7166 }
7167 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7168 hwstats->bprc += bprc;
7169 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
7170 if (hw->mac.type == ixgbe_mac_82598EB)
7171 hwstats->mprc -= bprc;
7172 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
7173 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
7174 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
7175 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
7176 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
7177 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
7178 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
7179 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
7180 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7181 hwstats->lxontxc += lxon;
7182 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7183 hwstats->lxofftxc += lxoff;
7184 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
7185 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
7186 /*
7187 * 82598 errata - tx of flow control packets is included in tx counters
7188 */
7189 xon_off_tot = lxon + lxoff;
7190 hwstats->gptc -= xon_off_tot;
7191 hwstats->mptc -= xon_off_tot;
7192 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
7193 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
7194 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
7195 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
7196 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
7197 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
7198 hwstats->ptc64 -= xon_off_tot;
7199 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
7200 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
7201 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
7202 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
7203 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
7204 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
7205
7206 /* Fill out the OS statistics structure */
7207 netdev->stats.multicast = hwstats->mprc;
7208
7209 /* Rx Errors */
7210 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
7211 netdev->stats.rx_dropped = 0;
7212 netdev->stats.rx_length_errors = hwstats->rlec;
7213 netdev->stats.rx_crc_errors = hwstats->crcerrs;
7214 netdev->stats.rx_missed_errors = total_mpc;
7215 }
7216
7217 /**
7218 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
7219 * @adapter: pointer to the device adapter structure
7220 **/
7221 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
7222 {
7223 struct ixgbe_hw *hw = &adapter->hw;
7224 int i;
7225
7226 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
7227 return;
7228
7229 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
7230
7231 /* if interface is down do nothing */
7232 if (test_bit(__IXGBE_DOWN, &adapter->state))
7233 return;
7234
7235 /* do nothing if we are not using signature filters */
7236 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
7237 return;
7238
7239 adapter->fdir_overflow++;
7240
7241 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
7242 for (i = 0; i < adapter->num_tx_queues; i++)
7243 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7244 &(adapter->tx_ring[i]->state));
7245 for (i = 0; i < adapter->num_xdp_queues; i++)
7246 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7247 &adapter->xdp_ring[i]->state);
7248 /* re-enable flow director interrupts */
7249 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
7250 } else {
7251 e_err(probe, "failed to finish FDIR re-initialization, "
7252 "ignored adding FDIR ATR filters\n");
7253 }
7254 }
7255
7256 /**
7257 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
7258 * @adapter: pointer to the device adapter structure
7259 *
7260 * This function serves two purposes. First it strobes the interrupt lines
7261 * in order to make certain interrupts are occurring. Secondly it sets the
7262 * bits needed to check for TX hangs. As a result we should immediately
7263 * determine if a hang has occurred.
7264 */
7265 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
7266 {
7267 struct ixgbe_hw *hw = &adapter->hw;
7268 u64 eics = 0;
7269 int i;
7270
7271 /* If we're down, removing or resetting, just bail */
7272 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7273 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7274 test_bit(__IXGBE_RESETTING, &adapter->state))
7275 return;
7276
7277 /* Force detection of hung controller */
7278 if (netif_carrier_ok(adapter->netdev)) {
7279 for (i = 0; i < adapter->num_tx_queues; i++)
7280 set_check_for_tx_hang(adapter->tx_ring[i]);
7281 for (i = 0; i < adapter->num_xdp_queues; i++)
7282 set_check_for_tx_hang(adapter->xdp_ring[i]);
7283 }
7284
7285 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7286 /*
7287 * for legacy and MSI interrupts don't set any bits
7288 * that are enabled for EIAM, because this operation
7289 * would set *both* EIMS and EICS for any bit in EIAM
7290 */
7291 IXGBE_WRITE_REG(hw, IXGBE_EICS,
7292 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
7293 } else {
7294 /* get one bit for every active tx/rx interrupt vector */
7295 for (i = 0; i < adapter->num_q_vectors; i++) {
7296 struct ixgbe_q_vector *qv = adapter->q_vector[i];
7297 if (qv->rx.ring || qv->tx.ring)
7298 eics |= BIT_ULL(i);
7299 }
7300 }
7301
7302 /* Cause software interrupt to ensure rings are cleaned */
7303 ixgbe_irq_rearm_queues(adapter, eics);
7304 }
7305
7306 /**
7307 * ixgbe_watchdog_update_link - update the link status
7308 * @adapter: pointer to the device adapter structure
7309 **/
7310 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
7311 {
7312 struct ixgbe_hw *hw = &adapter->hw;
7313 u32 link_speed = adapter->link_speed;
7314 bool link_up = adapter->link_up;
7315 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
7316
7317 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
7318 return;
7319
7320 if (hw->mac.ops.check_link) {
7321 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
7322 } else {
7323 /* always assume link is up, if no check link function */
7324 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
7325 link_up = true;
7326 }
7327
7328 if (adapter->ixgbe_ieee_pfc)
7329 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
7330
7331 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
7332 hw->mac.ops.fc_enable(hw);
7333 ixgbe_set_rx_drop_en(adapter);
7334 }
7335
7336 if (link_up ||
7337 time_after(jiffies, (adapter->link_check_timeout +
7338 IXGBE_TRY_LINK_TIMEOUT))) {
7339 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
7340 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
7341 IXGBE_WRITE_FLUSH(hw);
7342 }
7343
7344 adapter->link_up = link_up;
7345 adapter->link_speed = link_speed;
7346 }
7347
7348 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
7349 {
7350 #ifdef CONFIG_IXGBE_DCB
7351 struct net_device *netdev = adapter->netdev;
7352 struct dcb_app app = {
7353 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
7354 .protocol = 0,
7355 };
7356 u8 up = 0;
7357
7358 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
7359 up = dcb_ieee_getapp_mask(netdev, &app);
7360
7361 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
7362 #endif
7363 }
7364
7365 /**
7366 * ixgbe_watchdog_link_is_up - update netif_carrier status and
7367 * print link up message
7368 * @adapter: pointer to the device adapter structure
7369 **/
7370 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
7371 {
7372 struct net_device *netdev = adapter->netdev;
7373 struct ixgbe_hw *hw = &adapter->hw;
7374 u32 link_speed = adapter->link_speed;
7375 const char *speed_str;
7376 bool flow_rx, flow_tx;
7377
7378 /* only continue if link was previously down */
7379 if (netif_carrier_ok(netdev))
7380 return;
7381
7382 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7383
7384 switch (hw->mac.type) {
7385 case ixgbe_mac_82598EB: {
7386 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
7387 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
7388 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
7389 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
7390 }
7391 break;
7392 case ixgbe_mac_X540:
7393 case ixgbe_mac_X550:
7394 case ixgbe_mac_X550EM_x:
7395 case ixgbe_mac_x550em_a:
7396 case ixgbe_mac_82599EB: {
7397 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
7398 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
7399 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
7400 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
7401 }
7402 break;
7403 default:
7404 flow_tx = false;
7405 flow_rx = false;
7406 break;
7407 }
7408
7409 adapter->last_rx_ptp_check = jiffies;
7410
7411 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7412 ixgbe_ptp_start_cyclecounter(adapter);
7413
7414 switch (link_speed) {
7415 case IXGBE_LINK_SPEED_10GB_FULL:
7416 speed_str = "10 Gbps";
7417 break;
7418 case IXGBE_LINK_SPEED_5GB_FULL:
7419 speed_str = "5 Gbps";
7420 break;
7421 case IXGBE_LINK_SPEED_2_5GB_FULL:
7422 speed_str = "2.5 Gbps";
7423 break;
7424 case IXGBE_LINK_SPEED_1GB_FULL:
7425 speed_str = "1 Gbps";
7426 break;
7427 case IXGBE_LINK_SPEED_100_FULL:
7428 speed_str = "100 Mbps";
7429 break;
7430 case IXGBE_LINK_SPEED_10_FULL:
7431 speed_str = "10 Mbps";
7432 break;
7433 default:
7434 speed_str = "unknown speed";
7435 break;
7436 }
7437 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
7438 ((flow_rx && flow_tx) ? "RX/TX" :
7439 (flow_rx ? "RX" :
7440 (flow_tx ? "TX" : "None"))));
7441
7442 netif_carrier_on(netdev);
7443 ixgbe_check_vf_rate_limit(adapter);
7444
7445 /* enable transmits */
7446 netif_tx_wake_all_queues(adapter->netdev);
7447
7448 /* update the default user priority for VFs */
7449 ixgbe_update_default_up(adapter);
7450
7451 /* ping all the active vfs to let them know link has changed */
7452 ixgbe_ping_all_vfs(adapter);
7453 }
7454
7455 /**
7456 * ixgbe_watchdog_link_is_down - update netif_carrier status and
7457 * print link down message
7458 * @adapter: pointer to the adapter structure
7459 **/
7460 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
7461 {
7462 struct net_device *netdev = adapter->netdev;
7463 struct ixgbe_hw *hw = &adapter->hw;
7464
7465 adapter->link_up = false;
7466 adapter->link_speed = 0;
7467
7468 /* only continue if link was up previously */
7469 if (!netif_carrier_ok(netdev))
7470 return;
7471
7472 /* poll for SFP+ cable when link is down */
7473 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
7474 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
7475
7476 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7477 ixgbe_ptp_start_cyclecounter(adapter);
7478
7479 e_info(drv, "NIC Link is Down\n");
7480 netif_carrier_off(netdev);
7481
7482 /* ping all the active vfs to let them know link has changed */
7483 ixgbe_ping_all_vfs(adapter);
7484 }
7485
7486 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
7487 {
7488 int i;
7489
7490 for (i = 0; i < adapter->num_tx_queues; i++) {
7491 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
7492
7493 if (tx_ring->next_to_use != tx_ring->next_to_clean)
7494 return true;
7495 }
7496
7497 for (i = 0; i < adapter->num_xdp_queues; i++) {
7498 struct ixgbe_ring *ring = adapter->xdp_ring[i];
7499
7500 if (ring->next_to_use != ring->next_to_clean)
7501 return true;
7502 }
7503
7504 return false;
7505 }
7506
7507 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
7508 {
7509 struct ixgbe_hw *hw = &adapter->hw;
7510 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
7511 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
7512
7513 int i, j;
7514
7515 if (!adapter->num_vfs)
7516 return false;
7517
7518 /* resetting the PF is only needed for MAC before X550 */
7519 if (hw->mac.type >= ixgbe_mac_X550)
7520 return false;
7521
7522 for (i = 0; i < adapter->num_vfs; i++) {
7523 for (j = 0; j < q_per_pool; j++) {
7524 u32 h, t;
7525
7526 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
7527 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
7528
7529 if (h != t)
7530 return true;
7531 }
7532 }
7533
7534 return false;
7535 }
7536
7537 /**
7538 * ixgbe_watchdog_flush_tx - flush queues on link down
7539 * @adapter: pointer to the device adapter structure
7540 **/
7541 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
7542 {
7543 if (!netif_carrier_ok(adapter->netdev)) {
7544 if (ixgbe_ring_tx_pending(adapter) ||
7545 ixgbe_vf_tx_pending(adapter)) {
7546 /* We've lost link, so the controller stops DMA,
7547 * but we've got queued Tx work that's never going
7548 * to get done, so reset controller to flush Tx.
7549 * (Do the reset outside of interrupt context).
7550 */
7551 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
7552 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
7553 }
7554 }
7555 }
7556
7557 #ifdef CONFIG_PCI_IOV
7558 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
7559 {
7560 struct ixgbe_hw *hw = &adapter->hw;
7561 struct pci_dev *pdev = adapter->pdev;
7562 unsigned int vf;
7563 u32 gpc;
7564
7565 if (!(netif_carrier_ok(adapter->netdev)))
7566 return;
7567
7568 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
7569 if (gpc) /* If incrementing then no need for the check below */
7570 return;
7571 /* Check to see if a bad DMA write target from an errant or
7572 * malicious VF has caused a PCIe error. If so then we can
7573 * issue a VFLR to the offending VF(s) and then resume without
7574 * requesting a full slot reset.
7575 */
7576
7577 if (!pdev)
7578 return;
7579
7580 /* check status reg for all VFs owned by this PF */
7581 for (vf = 0; vf < adapter->num_vfs; ++vf) {
7582 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
7583 u16 status_reg;
7584
7585 if (!vfdev)
7586 continue;
7587 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
7588 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
7589 status_reg & PCI_STATUS_REC_MASTER_ABORT)
7590 pcie_flr(vfdev);
7591 }
7592 }
7593
7594 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
7595 {
7596 u32 ssvpc;
7597
7598 /* Do not perform spoof check for 82598 or if not in IOV mode */
7599 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7600 adapter->num_vfs == 0)
7601 return;
7602
7603 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
7604
7605 /*
7606 * ssvpc register is cleared on read, if zero then no
7607 * spoofed packets in the last interval.
7608 */
7609 if (!ssvpc)
7610 return;
7611
7612 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
7613 }
7614 #else
7615 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
7616 {
7617 }
7618
7619 static void
7620 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
7621 {
7622 }
7623 #endif /* CONFIG_PCI_IOV */
7624
7625
7626 /**
7627 * ixgbe_watchdog_subtask - check and bring link up
7628 * @adapter: pointer to the device adapter structure
7629 **/
7630 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7631 {
7632 /* if interface is down, removing or resetting, do nothing */
7633 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7634 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7635 test_bit(__IXGBE_RESETTING, &adapter->state))
7636 return;
7637
7638 ixgbe_watchdog_update_link(adapter);
7639
7640 if (adapter->link_up)
7641 ixgbe_watchdog_link_is_up(adapter);
7642 else
7643 ixgbe_watchdog_link_is_down(adapter);
7644
7645 ixgbe_check_for_bad_vf(adapter);
7646 ixgbe_spoof_check(adapter);
7647 ixgbe_update_stats(adapter);
7648
7649 ixgbe_watchdog_flush_tx(adapter);
7650 }
7651
7652 /**
7653 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
7654 * @adapter: the ixgbe adapter structure
7655 **/
7656 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
7657 {
7658 struct ixgbe_hw *hw = &adapter->hw;
7659 s32 err;
7660
7661 /* not searching for SFP so there is nothing to do here */
7662 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7663 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7664 return;
7665
7666 if (adapter->sfp_poll_time &&
7667 time_after(adapter->sfp_poll_time, jiffies))
7668 return; /* If not yet time to poll for SFP */
7669
7670 /* someone else is in init, wait until next service event */
7671 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7672 return;
7673
7674 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7675
7676 err = hw->phy.ops.identify_sfp(hw);
7677 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7678 goto sfp_out;
7679
7680 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7681 /* If no cable is present, then we need to reset
7682 * the next time we find a good cable. */
7683 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
7684 }
7685
7686 /* exit on error */
7687 if (err)
7688 goto sfp_out;
7689
7690 /* exit if reset not needed */
7691 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7692 goto sfp_out;
7693
7694 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
7695
7696 /*
7697 * A module may be identified correctly, but the EEPROM may not have
7698 * support for that module. setup_sfp() will fail in that case, so
7699 * we should not allow that module to load.
7700 */
7701 if (hw->mac.type == ixgbe_mac_82598EB)
7702 err = hw->phy.ops.reset(hw);
7703 else
7704 err = hw->mac.ops.setup_sfp(hw);
7705
7706 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7707 goto sfp_out;
7708
7709 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7710 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7711
7712 sfp_out:
7713 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7714
7715 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7716 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7717 e_dev_err("failed to initialize because an unsupported "
7718 "SFP+ module type was detected.\n");
7719 e_dev_err("Reload the driver after installing a "
7720 "supported module.\n");
7721 unregister_netdev(adapter->netdev);
7722 }
7723 }
7724
7725 /**
7726 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
7727 * @adapter: the ixgbe adapter structure
7728 **/
7729 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7730 {
7731 struct ixgbe_hw *hw = &adapter->hw;
7732 u32 cap_speed;
7733 u32 speed;
7734 bool autoneg = false;
7735
7736 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7737 return;
7738
7739 /* someone else is in init, wait until next service event */
7740 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7741 return;
7742
7743 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7744
7745 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg);
7746
7747 /* advertise highest capable link speed */
7748 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL))
7749 speed = IXGBE_LINK_SPEED_10GB_FULL;
7750 else
7751 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL |
7752 IXGBE_LINK_SPEED_1GB_FULL);
7753
7754 if (hw->mac.ops.setup_link)
7755 hw->mac.ops.setup_link(hw, speed, true);
7756
7757 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7758 adapter->link_check_timeout = jiffies;
7759 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7760 }
7761
7762 /**
7763 * ixgbe_service_timer - Timer Call-back
7764 * @t: pointer to timer_list structure
7765 **/
7766 static void ixgbe_service_timer(struct timer_list *t)
7767 {
7768 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer);
7769 unsigned long next_event_offset;
7770
7771 /* poll faster when waiting for link */
7772 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7773 next_event_offset = HZ / 10;
7774 else
7775 next_event_offset = HZ * 2;
7776
7777 /* Reset the timer */
7778 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7779
7780 ixgbe_service_event_schedule(adapter);
7781 }
7782
7783 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7784 {
7785 struct ixgbe_hw *hw = &adapter->hw;
7786 u32 status;
7787
7788 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7789 return;
7790
7791 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7792
7793 if (!hw->phy.ops.handle_lasi)
7794 return;
7795
7796 status = hw->phy.ops.handle_lasi(&adapter->hw);
7797 if (status != IXGBE_ERR_OVERTEMP)
7798 return;
7799
7800 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7801 }
7802
7803 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7804 {
7805 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state))
7806 return;
7807
7808 rtnl_lock();
7809 /* If we're already down, removing or resetting, just bail */
7810 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7811 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7812 test_bit(__IXGBE_RESETTING, &adapter->state)) {
7813 rtnl_unlock();
7814 return;
7815 }
7816
7817 ixgbe_dump(adapter);
7818 netdev_err(adapter->netdev, "Reset adapter\n");
7819 adapter->tx_timeout_count++;
7820
7821 ixgbe_reinit_locked(adapter);
7822 rtnl_unlock();
7823 }
7824
7825 /**
7826 * ixgbe_service_task - manages and runs subtasks
7827 * @work: pointer to work_struct containing our data
7828 **/
7829 static void ixgbe_service_task(struct work_struct *work)
7830 {
7831 struct ixgbe_adapter *adapter = container_of(work,
7832 struct ixgbe_adapter,
7833 service_task);
7834 if (ixgbe_removed(adapter->hw.hw_addr)) {
7835 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7836 rtnl_lock();
7837 ixgbe_down(adapter);
7838 rtnl_unlock();
7839 }
7840 ixgbe_service_event_complete(adapter);
7841 return;
7842 }
7843 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) {
7844 rtnl_lock();
7845 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
7846 udp_tunnel_get_rx_info(adapter->netdev);
7847 rtnl_unlock();
7848 }
7849 ixgbe_reset_subtask(adapter);
7850 ixgbe_phy_interrupt_subtask(adapter);
7851 ixgbe_sfp_detection_subtask(adapter);
7852 ixgbe_sfp_link_config_subtask(adapter);
7853 ixgbe_check_overtemp_subtask(adapter);
7854 ixgbe_watchdog_subtask(adapter);
7855 ixgbe_fdir_reinit_subtask(adapter);
7856 ixgbe_check_hang_subtask(adapter);
7857
7858 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
7859 ixgbe_ptp_overflow_check(adapter);
7860 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER)
7861 ixgbe_ptp_rx_hang(adapter);
7862 ixgbe_ptp_tx_hang(adapter);
7863 }
7864
7865 ixgbe_service_event_complete(adapter);
7866 }
7867
7868 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7869 struct ixgbe_tx_buffer *first,
7870 u8 *hdr_len,
7871 struct ixgbe_ipsec_tx_data *itd)
7872 {
7873 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
7874 struct sk_buff *skb = first->skb;
7875 union {
7876 struct iphdr *v4;
7877 struct ipv6hdr *v6;
7878 unsigned char *hdr;
7879 } ip;
7880 union {
7881 struct tcphdr *tcp;
7882 unsigned char *hdr;
7883 } l4;
7884 u32 paylen, l4_offset;
7885 u32 fceof_saidx = 0;
7886 int err;
7887
7888 if (skb->ip_summed != CHECKSUM_PARTIAL)
7889 return 0;
7890
7891 if (!skb_is_gso(skb))
7892 return 0;
7893
7894 err = skb_cow_head(skb, 0);
7895 if (err < 0)
7896 return err;
7897
7898 if (eth_p_mpls(first->protocol))
7899 ip.hdr = skb_inner_network_header(skb);
7900 else
7901 ip.hdr = skb_network_header(skb);
7902 l4.hdr = skb_checksum_start(skb);
7903
7904 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7905 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7906
7907 /* initialize outer IP header fields */
7908 if (ip.v4->version == 4) {
7909 unsigned char *csum_start = skb_checksum_start(skb);
7910 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
7911 int len = csum_start - trans_start;
7912
7913 /* IP header will have to cancel out any data that
7914 * is not a part of the outer IP header, so set to
7915 * a reverse csum if needed, else init check to 0.
7916 */
7917 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ?
7918 csum_fold(csum_partial(trans_start,
7919 len, 0)) : 0;
7920 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7921
7922 ip.v4->tot_len = 0;
7923 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7924 IXGBE_TX_FLAGS_CSUM |
7925 IXGBE_TX_FLAGS_IPV4;
7926 } else {
7927 ip.v6->payload_len = 0;
7928 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7929 IXGBE_TX_FLAGS_CSUM;
7930 }
7931
7932 /* determine offset of inner transport header */
7933 l4_offset = l4.hdr - skb->data;
7934
7935 /* compute length of segmentation header */
7936 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
7937
7938 /* remove payload length from inner checksum */
7939 paylen = skb->len - l4_offset;
7940 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
7941
7942 /* update gso size and bytecount with header size */
7943 first->gso_segs = skb_shinfo(skb)->gso_segs;
7944 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7945
7946 /* mss_l4len_id: use 0 as index for TSO */
7947 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
7948 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
7949
7950 fceof_saidx |= itd->sa_idx;
7951 type_tucmd |= itd->flags | itd->trailer_len;
7952
7953 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7954 vlan_macip_lens = l4.hdr - ip.hdr;
7955 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
7956 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7957
7958 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd,
7959 mss_l4len_idx);
7960
7961 return 1;
7962 }
7963
7964 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
7965 {
7966 unsigned int offset = 0;
7967
7968 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
7969
7970 return offset == skb_checksum_start_offset(skb);
7971 }
7972
7973 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7974 struct ixgbe_tx_buffer *first,
7975 struct ixgbe_ipsec_tx_data *itd)
7976 {
7977 struct sk_buff *skb = first->skb;
7978 u32 vlan_macip_lens = 0;
7979 u32 fceof_saidx = 0;
7980 u32 type_tucmd = 0;
7981
7982 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7983 csum_failed:
7984 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
7985 IXGBE_TX_FLAGS_CC)))
7986 return;
7987 goto no_csum;
7988 }
7989
7990 switch (skb->csum_offset) {
7991 case offsetof(struct tcphdr, check):
7992 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7993 /* fall through */
7994 case offsetof(struct udphdr, check):
7995 break;
7996 case offsetof(struct sctphdr, checksum):
7997 /* validate that this is actually an SCTP request */
7998 if (((first->protocol == htons(ETH_P_IP)) &&
7999 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
8000 ((first->protocol == htons(ETH_P_IPV6)) &&
8001 ixgbe_ipv6_csum_is_sctp(skb))) {
8002 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
8003 break;
8004 }
8005 /* fall through */
8006 default:
8007 skb_checksum_help(skb);
8008 goto csum_failed;
8009 }
8010
8011 /* update TX checksum flag */
8012 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
8013 vlan_macip_lens = skb_checksum_start_offset(skb) -
8014 skb_network_offset(skb);
8015 no_csum:
8016 /* vlan_macip_lens: MACLEN, VLAN tag */
8017 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
8018 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
8019
8020 fceof_saidx |= itd->sa_idx;
8021 type_tucmd |= itd->flags | itd->trailer_len;
8022
8023 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0);
8024 }
8025
8026 #define IXGBE_SET_FLAG(_input, _flag, _result) \
8027 ((_flag <= _result) ? \
8028 ((u32)(_input & _flag) * (_result / _flag)) : \
8029 ((u32)(_input & _flag) / (_flag / _result)))
8030
8031 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
8032 {
8033 /* set type for advanced descriptor with frame checksum insertion */
8034 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8035 IXGBE_ADVTXD_DCMD_DEXT |
8036 IXGBE_ADVTXD_DCMD_IFCS;
8037
8038 /* set HW vlan bit if vlan is present */
8039 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
8040 IXGBE_ADVTXD_DCMD_VLE);
8041
8042 /* set segmentation enable bits for TSO/FSO */
8043 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
8044 IXGBE_ADVTXD_DCMD_TSE);
8045
8046 /* set timestamp bit if present */
8047 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
8048 IXGBE_ADVTXD_MAC_TSTAMP);
8049
8050 /* insert frame checksum */
8051 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
8052
8053 return cmd_type;
8054 }
8055
8056 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
8057 u32 tx_flags, unsigned int paylen)
8058 {
8059 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
8060
8061 /* enable L4 checksum for TSO and TX checksum offload */
8062 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8063 IXGBE_TX_FLAGS_CSUM,
8064 IXGBE_ADVTXD_POPTS_TXSM);
8065
8066 /* enable IPv4 checksum for TSO */
8067 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8068 IXGBE_TX_FLAGS_IPV4,
8069 IXGBE_ADVTXD_POPTS_IXSM);
8070
8071 /* enable IPsec */
8072 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8073 IXGBE_TX_FLAGS_IPSEC,
8074 IXGBE_ADVTXD_POPTS_IPSEC);
8075
8076 /*
8077 * Check Context must be set if Tx switch is enabled, which it
8078 * always is for case where virtual functions are running
8079 */
8080 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8081 IXGBE_TX_FLAGS_CC,
8082 IXGBE_ADVTXD_CC);
8083
8084 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
8085 }
8086
8087 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8088 {
8089 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
8090
8091 /* Herbert's original patch had:
8092 * smp_mb__after_netif_stop_queue();
8093 * but since that doesn't exist yet, just open code it.
8094 */
8095 smp_mb();
8096
8097 /* We need to check again in a case another CPU has just
8098 * made room available.
8099 */
8100 if (likely(ixgbe_desc_unused(tx_ring) < size))
8101 return -EBUSY;
8102
8103 /* A reprieve! - use start_queue because it doesn't call schedule */
8104 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
8105 ++tx_ring->tx_stats.restart_queue;
8106 return 0;
8107 }
8108
8109 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8110 {
8111 if (likely(ixgbe_desc_unused(tx_ring) >= size))
8112 return 0;
8113
8114 return __ixgbe_maybe_stop_tx(tx_ring, size);
8115 }
8116
8117 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
8118 IXGBE_TXD_CMD_RS)
8119
8120 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring,
8121 struct ixgbe_tx_buffer *first,
8122 const u8 hdr_len)
8123 {
8124 struct sk_buff *skb = first->skb;
8125 struct ixgbe_tx_buffer *tx_buffer;
8126 union ixgbe_adv_tx_desc *tx_desc;
8127 struct skb_frag_struct *frag;
8128 dma_addr_t dma;
8129 unsigned int data_len, size;
8130 u32 tx_flags = first->tx_flags;
8131 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
8132 u16 i = tx_ring->next_to_use;
8133
8134 tx_desc = IXGBE_TX_DESC(tx_ring, i);
8135
8136 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
8137
8138 size = skb_headlen(skb);
8139 data_len = skb->data_len;
8140
8141 #ifdef IXGBE_FCOE
8142 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
8143 if (data_len < sizeof(struct fcoe_crc_eof)) {
8144 size -= sizeof(struct fcoe_crc_eof) - data_len;
8145 data_len = 0;
8146 } else {
8147 data_len -= sizeof(struct fcoe_crc_eof);
8148 }
8149 }
8150
8151 #endif
8152 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8153
8154 tx_buffer = first;
8155
8156 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
8157 if (dma_mapping_error(tx_ring->dev, dma))
8158 goto dma_error;
8159
8160 /* record length, and DMA address */
8161 dma_unmap_len_set(tx_buffer, len, size);
8162 dma_unmap_addr_set(tx_buffer, dma, dma);
8163
8164 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8165
8166 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
8167 tx_desc->read.cmd_type_len =
8168 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
8169
8170 i++;
8171 tx_desc++;
8172 if (i == tx_ring->count) {
8173 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8174 i = 0;
8175 }
8176 tx_desc->read.olinfo_status = 0;
8177
8178 dma += IXGBE_MAX_DATA_PER_TXD;
8179 size -= IXGBE_MAX_DATA_PER_TXD;
8180
8181 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8182 }
8183
8184 if (likely(!data_len))
8185 break;
8186
8187 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
8188
8189 i++;
8190 tx_desc++;
8191 if (i == tx_ring->count) {
8192 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8193 i = 0;
8194 }
8195 tx_desc->read.olinfo_status = 0;
8196
8197 #ifdef IXGBE_FCOE
8198 size = min_t(unsigned int, data_len, skb_frag_size(frag));
8199 #else
8200 size = skb_frag_size(frag);
8201 #endif
8202 data_len -= size;
8203
8204 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
8205 DMA_TO_DEVICE);
8206
8207 tx_buffer = &tx_ring->tx_buffer_info[i];
8208 }
8209
8210 /* write last descriptor with RS and EOP bits */
8211 cmd_type |= size | IXGBE_TXD_CMD;
8212 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8213
8214 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
8215
8216 /* set the timestamp */
8217 first->time_stamp = jiffies;
8218
8219 /*
8220 * Force memory writes to complete before letting h/w know there
8221 * are new descriptors to fetch. (Only applicable for weak-ordered
8222 * memory model archs, such as IA-64).
8223 *
8224 * We also need this memory barrier to make certain all of the
8225 * status bits have been updated before next_to_watch is written.
8226 */
8227 wmb();
8228
8229 /* set next_to_watch value indicating a packet is present */
8230 first->next_to_watch = tx_desc;
8231
8232 i++;
8233 if (i == tx_ring->count)
8234 i = 0;
8235
8236 tx_ring->next_to_use = i;
8237
8238 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
8239
8240 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
8241 writel(i, tx_ring->tail);
8242
8243 /* we need this if more than one processor can write to our tail
8244 * at a time, it synchronizes IO on IA64/Altix systems
8245 */
8246 mmiowb();
8247 }
8248
8249 return 0;
8250 dma_error:
8251 dev_err(tx_ring->dev, "TX DMA map failed\n");
8252
8253 /* clear dma mappings for failed tx_buffer_info map */
8254 for (;;) {
8255 tx_buffer = &tx_ring->tx_buffer_info[i];
8256 if (dma_unmap_len(tx_buffer, len))
8257 dma_unmap_page(tx_ring->dev,
8258 dma_unmap_addr(tx_buffer, dma),
8259 dma_unmap_len(tx_buffer, len),
8260 DMA_TO_DEVICE);
8261 dma_unmap_len_set(tx_buffer, len, 0);
8262 if (tx_buffer == first)
8263 break;
8264 if (i == 0)
8265 i += tx_ring->count;
8266 i--;
8267 }
8268
8269 dev_kfree_skb_any(first->skb);
8270 first->skb = NULL;
8271
8272 tx_ring->next_to_use = i;
8273
8274 return -1;
8275 }
8276
8277 static void ixgbe_atr(struct ixgbe_ring *ring,
8278 struct ixgbe_tx_buffer *first)
8279 {
8280 struct ixgbe_q_vector *q_vector = ring->q_vector;
8281 union ixgbe_atr_hash_dword input = { .dword = 0 };
8282 union ixgbe_atr_hash_dword common = { .dword = 0 };
8283 union {
8284 unsigned char *network;
8285 struct iphdr *ipv4;
8286 struct ipv6hdr *ipv6;
8287 } hdr;
8288 struct tcphdr *th;
8289 unsigned int hlen;
8290 struct sk_buff *skb;
8291 __be16 vlan_id;
8292 int l4_proto;
8293
8294 /* if ring doesn't have a interrupt vector, cannot perform ATR */
8295 if (!q_vector)
8296 return;
8297
8298 /* do nothing if sampling is disabled */
8299 if (!ring->atr_sample_rate)
8300 return;
8301
8302 ring->atr_count++;
8303
8304 /* currently only IPv4/IPv6 with TCP is supported */
8305 if ((first->protocol != htons(ETH_P_IP)) &&
8306 (first->protocol != htons(ETH_P_IPV6)))
8307 return;
8308
8309 /* snag network header to get L4 type and address */
8310 skb = first->skb;
8311 hdr.network = skb_network_header(skb);
8312 if (unlikely(hdr.network <= skb->data))
8313 return;
8314 if (skb->encapsulation &&
8315 first->protocol == htons(ETH_P_IP) &&
8316 hdr.ipv4->protocol == IPPROTO_UDP) {
8317 struct ixgbe_adapter *adapter = q_vector->adapter;
8318
8319 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8320 VXLAN_HEADROOM))
8321 return;
8322
8323 /* verify the port is recognized as VXLAN */
8324 if (adapter->vxlan_port &&
8325 udp_hdr(skb)->dest == adapter->vxlan_port)
8326 hdr.network = skb_inner_network_header(skb);
8327
8328 if (adapter->geneve_port &&
8329 udp_hdr(skb)->dest == adapter->geneve_port)
8330 hdr.network = skb_inner_network_header(skb);
8331 }
8332
8333 /* Make sure we have at least [minimum IPv4 header + TCP]
8334 * or [IPv6 header] bytes
8335 */
8336 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40))
8337 return;
8338
8339 /* Currently only IPv4/IPv6 with TCP is supported */
8340 switch (hdr.ipv4->version) {
8341 case IPVERSION:
8342 /* access ihl as u8 to avoid unaligned access on ia64 */
8343 hlen = (hdr.network[0] & 0x0F) << 2;
8344 l4_proto = hdr.ipv4->protocol;
8345 break;
8346 case 6:
8347 hlen = hdr.network - skb->data;
8348 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
8349 hlen -= hdr.network - skb->data;
8350 break;
8351 default:
8352 return;
8353 }
8354
8355 if (l4_proto != IPPROTO_TCP)
8356 return;
8357
8358 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8359 hlen + sizeof(struct tcphdr)))
8360 return;
8361
8362 th = (struct tcphdr *)(hdr.network + hlen);
8363
8364 /* skip this packet since the socket is closing */
8365 if (th->fin)
8366 return;
8367
8368 /* sample on all syn packets or once every atr sample count */
8369 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
8370 return;
8371
8372 /* reset sample count */
8373 ring->atr_count = 0;
8374
8375 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
8376
8377 /*
8378 * src and dst are inverted, think how the receiver sees them
8379 *
8380 * The input is broken into two sections, a non-compressed section
8381 * containing vm_pool, vlan_id, and flow_type. The rest of the data
8382 * is XORed together and stored in the compressed dword.
8383 */
8384 input.formatted.vlan_id = vlan_id;
8385
8386 /*
8387 * since src port and flex bytes occupy the same word XOR them together
8388 * and write the value to source port portion of compressed dword
8389 */
8390 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
8391 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
8392 else
8393 common.port.src ^= th->dest ^ first->protocol;
8394 common.port.dst ^= th->source;
8395
8396 switch (hdr.ipv4->version) {
8397 case IPVERSION:
8398 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
8399 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
8400 break;
8401 case 6:
8402 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
8403 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
8404 hdr.ipv6->saddr.s6_addr32[1] ^
8405 hdr.ipv6->saddr.s6_addr32[2] ^
8406 hdr.ipv6->saddr.s6_addr32[3] ^
8407 hdr.ipv6->daddr.s6_addr32[0] ^
8408 hdr.ipv6->daddr.s6_addr32[1] ^
8409 hdr.ipv6->daddr.s6_addr32[2] ^
8410 hdr.ipv6->daddr.s6_addr32[3];
8411 break;
8412 default:
8413 break;
8414 }
8415
8416 if (hdr.network != skb_network_header(skb))
8417 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
8418
8419 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
8420 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
8421 input, common, ring->queue_index);
8422 }
8423
8424 #ifdef IXGBE_FCOE
8425 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
8426 struct net_device *sb_dev,
8427 select_queue_fallback_t fallback)
8428 {
8429 struct ixgbe_adapter *adapter;
8430 struct ixgbe_ring_feature *f;
8431 int txq;
8432
8433 if (sb_dev) {
8434 u8 tc = netdev_get_prio_tc_map(dev, skb->priority);
8435 struct net_device *vdev = sb_dev;
8436
8437 txq = vdev->tc_to_txq[tc].offset;
8438 txq += reciprocal_scale(skb_get_hash(skb),
8439 vdev->tc_to_txq[tc].count);
8440
8441 return txq;
8442 }
8443
8444 /*
8445 * only execute the code below if protocol is FCoE
8446 * or FIP and we have FCoE enabled on the adapter
8447 */
8448 switch (vlan_get_protocol(skb)) {
8449 case htons(ETH_P_FCOE):
8450 case htons(ETH_P_FIP):
8451 adapter = netdev_priv(dev);
8452
8453 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
8454 break;
8455 /* fall through */
8456 default:
8457 return fallback(dev, skb, sb_dev);
8458 }
8459
8460 f = &adapter->ring_feature[RING_F_FCOE];
8461
8462 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
8463 smp_processor_id();
8464
8465 while (txq >= f->indices)
8466 txq -= f->indices;
8467
8468 return txq + f->offset;
8469 }
8470
8471 #endif
8472 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter,
8473 struct xdp_frame *xdpf)
8474 {
8475 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
8476 struct ixgbe_tx_buffer *tx_buffer;
8477 union ixgbe_adv_tx_desc *tx_desc;
8478 u32 len, cmd_type;
8479 dma_addr_t dma;
8480 u16 i;
8481
8482 len = xdpf->len;
8483
8484 if (unlikely(!ixgbe_desc_unused(ring)))
8485 return IXGBE_XDP_CONSUMED;
8486
8487 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE);
8488 if (dma_mapping_error(ring->dev, dma))
8489 return IXGBE_XDP_CONSUMED;
8490
8491 /* record the location of the first descriptor for this packet */
8492 tx_buffer = &ring->tx_buffer_info[ring->next_to_use];
8493 tx_buffer->bytecount = len;
8494 tx_buffer->gso_segs = 1;
8495 tx_buffer->protocol = 0;
8496
8497 i = ring->next_to_use;
8498 tx_desc = IXGBE_TX_DESC(ring, i);
8499
8500 dma_unmap_len_set(tx_buffer, len, len);
8501 dma_unmap_addr_set(tx_buffer, dma, dma);
8502 tx_buffer->xdpf = xdpf;
8503
8504 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8505
8506 /* put descriptor type bits */
8507 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8508 IXGBE_ADVTXD_DCMD_DEXT |
8509 IXGBE_ADVTXD_DCMD_IFCS;
8510 cmd_type |= len | IXGBE_TXD_CMD;
8511 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8512 tx_desc->read.olinfo_status =
8513 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT);
8514
8515 /* Avoid any potential race with xdp_xmit and cleanup */
8516 smp_wmb();
8517
8518 /* set next_to_watch value indicating a packet is present */
8519 i++;
8520 if (i == ring->count)
8521 i = 0;
8522
8523 tx_buffer->next_to_watch = tx_desc;
8524 ring->next_to_use = i;
8525
8526 return IXGBE_XDP_TX;
8527 }
8528
8529 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
8530 struct ixgbe_adapter *adapter,
8531 struct ixgbe_ring *tx_ring)
8532 {
8533 struct ixgbe_tx_buffer *first;
8534 int tso;
8535 u32 tx_flags = 0;
8536 unsigned short f;
8537 u16 count = TXD_USE_COUNT(skb_headlen(skb));
8538 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 };
8539 __be16 protocol = skb->protocol;
8540 u8 hdr_len = 0;
8541
8542 /*
8543 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
8544 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
8545 * + 2 desc gap to keep tail from touching head,
8546 * + 1 desc for context descriptor,
8547 * otherwise try next time
8548 */
8549 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
8550 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
8551
8552 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
8553 tx_ring->tx_stats.tx_busy++;
8554 return NETDEV_TX_BUSY;
8555 }
8556
8557 /* record the location of the first descriptor for this packet */
8558 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
8559 first->skb = skb;
8560 first->bytecount = skb->len;
8561 first->gso_segs = 1;
8562
8563 /* if we have a HW VLAN tag being added default to the HW one */
8564 if (skb_vlan_tag_present(skb)) {
8565 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
8566 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8567 /* else if it is a SW VLAN check the next protocol and store the tag */
8568 } else if (protocol == htons(ETH_P_8021Q)) {
8569 struct vlan_hdr *vhdr, _vhdr;
8570 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
8571 if (!vhdr)
8572 goto out_drop;
8573
8574 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
8575 IXGBE_TX_FLAGS_VLAN_SHIFT;
8576 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
8577 }
8578 protocol = vlan_get_protocol(skb);
8579
8580 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
8581 adapter->ptp_clock) {
8582 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
8583 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
8584 &adapter->state)) {
8585 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8586 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
8587
8588 /* schedule check for Tx timestamp */
8589 adapter->ptp_tx_skb = skb_get(skb);
8590 adapter->ptp_tx_start = jiffies;
8591 schedule_work(&adapter->ptp_tx_work);
8592 } else {
8593 adapter->tx_hwtstamp_skipped++;
8594 }
8595 }
8596
8597 skb_tx_timestamp(skb);
8598
8599 #ifdef CONFIG_PCI_IOV
8600 /*
8601 * Use the l2switch_enable flag - would be false if the DMA
8602 * Tx switch had been disabled.
8603 */
8604 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8605 tx_flags |= IXGBE_TX_FLAGS_CC;
8606
8607 #endif
8608 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
8609 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8610 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
8611 (skb->priority != TC_PRIO_CONTROL))) {
8612 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
8613 tx_flags |= (skb->priority & 0x7) <<
8614 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
8615 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
8616 struct vlan_ethhdr *vhdr;
8617
8618 if (skb_cow_head(skb, 0))
8619 goto out_drop;
8620 vhdr = (struct vlan_ethhdr *)skb->data;
8621 vhdr->h_vlan_TCI = htons(tx_flags >>
8622 IXGBE_TX_FLAGS_VLAN_SHIFT);
8623 } else {
8624 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8625 }
8626 }
8627
8628 /* record initial flags and protocol */
8629 first->tx_flags = tx_flags;
8630 first->protocol = protocol;
8631
8632 #ifdef IXGBE_FCOE
8633 /* setup tx offload for FCoE */
8634 if ((protocol == htons(ETH_P_FCOE)) &&
8635 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
8636 tso = ixgbe_fso(tx_ring, first, &hdr_len);
8637 if (tso < 0)
8638 goto out_drop;
8639
8640 goto xmit_fcoe;
8641 }
8642
8643 #endif /* IXGBE_FCOE */
8644
8645 #ifdef CONFIG_XFRM_OFFLOAD
8646 if (xfrm_offload(skb) &&
8647 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx))
8648 goto out_drop;
8649 #endif
8650 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx);
8651 if (tso < 0)
8652 goto out_drop;
8653 else if (!tso)
8654 ixgbe_tx_csum(tx_ring, first, &ipsec_tx);
8655
8656 /* add the ATR filter if ATR is on */
8657 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
8658 ixgbe_atr(tx_ring, first);
8659
8660 #ifdef IXGBE_FCOE
8661 xmit_fcoe:
8662 #endif /* IXGBE_FCOE */
8663 if (ixgbe_tx_map(tx_ring, first, hdr_len))
8664 goto cleanup_tx_timestamp;
8665
8666 return NETDEV_TX_OK;
8667
8668 out_drop:
8669 dev_kfree_skb_any(first->skb);
8670 first->skb = NULL;
8671 cleanup_tx_timestamp:
8672 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) {
8673 dev_kfree_skb_any(adapter->ptp_tx_skb);
8674 adapter->ptp_tx_skb = NULL;
8675 cancel_work_sync(&adapter->ptp_tx_work);
8676 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
8677 }
8678
8679 return NETDEV_TX_OK;
8680 }
8681
8682 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
8683 struct net_device *netdev,
8684 struct ixgbe_ring *ring)
8685 {
8686 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8687 struct ixgbe_ring *tx_ring;
8688
8689 /*
8690 * The minimum packet size for olinfo paylen is 17 so pad the skb
8691 * in order to meet this minimum size requirement.
8692 */
8693 if (skb_put_padto(skb, 17))
8694 return NETDEV_TX_OK;
8695
8696 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
8697
8698 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
8699 }
8700
8701 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
8702 struct net_device *netdev)
8703 {
8704 return __ixgbe_xmit_frame(skb, netdev, NULL);
8705 }
8706
8707 /**
8708 * ixgbe_set_mac - Change the Ethernet Address of the NIC
8709 * @netdev: network interface device structure
8710 * @p: pointer to an address structure
8711 *
8712 * Returns 0 on success, negative on failure
8713 **/
8714 static int ixgbe_set_mac(struct net_device *netdev, void *p)
8715 {
8716 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8717 struct ixgbe_hw *hw = &adapter->hw;
8718 struct sockaddr *addr = p;
8719
8720 if (!is_valid_ether_addr(addr->sa_data))
8721 return -EADDRNOTAVAIL;
8722
8723 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
8724 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
8725
8726 ixgbe_mac_set_default_filter(adapter);
8727
8728 return 0;
8729 }
8730
8731 static int
8732 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
8733 {
8734 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8735 struct ixgbe_hw *hw = &adapter->hw;
8736 u16 value;
8737 int rc;
8738
8739 if (prtad != hw->phy.mdio.prtad)
8740 return -EINVAL;
8741 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
8742 if (!rc)
8743 rc = value;
8744 return rc;
8745 }
8746
8747 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8748 u16 addr, u16 value)
8749 {
8750 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8751 struct ixgbe_hw *hw = &adapter->hw;
8752
8753 if (prtad != hw->phy.mdio.prtad)
8754 return -EINVAL;
8755 return hw->phy.ops.write_reg(hw, addr, devad, value);
8756 }
8757
8758 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8759 {
8760 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8761
8762 switch (cmd) {
8763 case SIOCSHWTSTAMP:
8764 return ixgbe_ptp_set_ts_config(adapter, req);
8765 case SIOCGHWTSTAMP:
8766 return ixgbe_ptp_get_ts_config(adapter, req);
8767 case SIOCGMIIPHY:
8768 if (!adapter->hw.phy.ops.read_reg)
8769 return -EOPNOTSUPP;
8770 /* fall through */
8771 default:
8772 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
8773 }
8774 }
8775
8776 /**
8777 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
8778 * netdev->dev_addrs
8779 * @dev: network interface device structure
8780 *
8781 * Returns non-zero on failure
8782 **/
8783 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
8784 {
8785 int err = 0;
8786 struct ixgbe_adapter *adapter = netdev_priv(dev);
8787 struct ixgbe_hw *hw = &adapter->hw;
8788
8789 if (is_valid_ether_addr(hw->mac.san_addr)) {
8790 rtnl_lock();
8791 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
8792 rtnl_unlock();
8793
8794 /* update SAN MAC vmdq pool selection */
8795 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
8796 }
8797 return err;
8798 }
8799
8800 /**
8801 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
8802 * netdev->dev_addrs
8803 * @dev: network interface device structure
8804 *
8805 * Returns non-zero on failure
8806 **/
8807 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8808 {
8809 int err = 0;
8810 struct ixgbe_adapter *adapter = netdev_priv(dev);
8811 struct ixgbe_mac_info *mac = &adapter->hw.mac;
8812
8813 if (is_valid_ether_addr(mac->san_addr)) {
8814 rtnl_lock();
8815 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8816 rtnl_unlock();
8817 }
8818 return err;
8819 }
8820
8821 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats,
8822 struct ixgbe_ring *ring)
8823 {
8824 u64 bytes, packets;
8825 unsigned int start;
8826
8827 if (ring) {
8828 do {
8829 start = u64_stats_fetch_begin_irq(&ring->syncp);
8830 packets = ring->stats.packets;
8831 bytes = ring->stats.bytes;
8832 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8833 stats->tx_packets += packets;
8834 stats->tx_bytes += bytes;
8835 }
8836 }
8837
8838 static void ixgbe_get_stats64(struct net_device *netdev,
8839 struct rtnl_link_stats64 *stats)
8840 {
8841 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8842 int i;
8843
8844 rcu_read_lock();
8845 for (i = 0; i < adapter->num_rx_queues; i++) {
8846 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]);
8847 u64 bytes, packets;
8848 unsigned int start;
8849
8850 if (ring) {
8851 do {
8852 start = u64_stats_fetch_begin_irq(&ring->syncp);
8853 packets = ring->stats.packets;
8854 bytes = ring->stats.bytes;
8855 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8856 stats->rx_packets += packets;
8857 stats->rx_bytes += bytes;
8858 }
8859 }
8860
8861 for (i = 0; i < adapter->num_tx_queues; i++) {
8862 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]);
8863
8864 ixgbe_get_ring_stats64(stats, ring);
8865 }
8866 for (i = 0; i < adapter->num_xdp_queues; i++) {
8867 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]);
8868
8869 ixgbe_get_ring_stats64(stats, ring);
8870 }
8871 rcu_read_unlock();
8872
8873 /* following stats updated by ixgbe_watchdog_task() */
8874 stats->multicast = netdev->stats.multicast;
8875 stats->rx_errors = netdev->stats.rx_errors;
8876 stats->rx_length_errors = netdev->stats.rx_length_errors;
8877 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8878 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8879 }
8880
8881 #ifdef CONFIG_IXGBE_DCB
8882 /**
8883 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8884 * @adapter: pointer to ixgbe_adapter
8885 * @tc: number of traffic classes currently enabled
8886 *
8887 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8888 * 802.1Q priority maps to a packet buffer that exists.
8889 */
8890 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8891 {
8892 struct ixgbe_hw *hw = &adapter->hw;
8893 u32 reg, rsave;
8894 int i;
8895
8896 /* 82598 have a static priority to TC mapping that can not
8897 * be changed so no validation is needed.
8898 */
8899 if (hw->mac.type == ixgbe_mac_82598EB)
8900 return;
8901
8902 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8903 rsave = reg;
8904
8905 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8906 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8907
8908 /* If up2tc is out of bounds default to zero */
8909 if (up2tc > tc)
8910 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8911 }
8912
8913 if (reg != rsave)
8914 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8915
8916 return;
8917 }
8918
8919 /**
8920 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8921 * @adapter: Pointer to adapter struct
8922 *
8923 * Populate the netdev user priority to tc map
8924 */
8925 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8926 {
8927 struct net_device *dev = adapter->netdev;
8928 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8929 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8930 u8 prio;
8931
8932 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8933 u8 tc = 0;
8934
8935 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8936 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8937 else if (ets)
8938 tc = ets->prio_tc[prio];
8939
8940 netdev_set_prio_tc_map(dev, prio, tc);
8941 }
8942 }
8943
8944 #endif /* CONFIG_IXGBE_DCB */
8945 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, void *data)
8946 {
8947 struct ixgbe_adapter *adapter = data;
8948 struct ixgbe_fwd_adapter *accel;
8949 int pool;
8950
8951 /* we only care about macvlans... */
8952 if (!netif_is_macvlan(vdev))
8953 return 0;
8954
8955 /* that have hardware offload enabled... */
8956 accel = macvlan_accel_priv(vdev);
8957 if (!accel)
8958 return 0;
8959
8960 /* If we can relocate to a different bit do so */
8961 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
8962 if (pool < adapter->num_rx_pools) {
8963 set_bit(pool, adapter->fwd_bitmask);
8964 accel->pool = pool;
8965 return 0;
8966 }
8967
8968 /* if we cannot find a free pool then disable the offload */
8969 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n");
8970 macvlan_release_l2fw_offload(vdev);
8971
8972 /* unbind the queues and drop the subordinate channel config */
8973 netdev_unbind_sb_channel(adapter->netdev, vdev);
8974 netdev_set_sb_channel(vdev, 0);
8975
8976 kfree(accel);
8977
8978 return 0;
8979 }
8980
8981 static void ixgbe_defrag_macvlan_pools(struct net_device *dev)
8982 {
8983 struct ixgbe_adapter *adapter = netdev_priv(dev);
8984
8985 /* flush any stale bits out of the fwd bitmask */
8986 bitmap_clear(adapter->fwd_bitmask, 1, 63);
8987
8988 /* walk through upper devices reassigning pools */
8989 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool,
8990 adapter);
8991 }
8992
8993 /**
8994 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8995 *
8996 * @dev: net device to configure
8997 * @tc: number of traffic classes to enable
8998 */
8999 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
9000 {
9001 struct ixgbe_adapter *adapter = netdev_priv(dev);
9002 struct ixgbe_hw *hw = &adapter->hw;
9003
9004 /* Hardware supports up to 8 traffic classes */
9005 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
9006 return -EINVAL;
9007
9008 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
9009 return -EINVAL;
9010
9011 /* Hardware has to reinitialize queues and interrupts to
9012 * match packet buffer alignment. Unfortunately, the
9013 * hardware is not flexible enough to do this dynamically.
9014 */
9015 if (netif_running(dev))
9016 ixgbe_close(dev);
9017 else
9018 ixgbe_reset(adapter);
9019
9020 ixgbe_clear_interrupt_scheme(adapter);
9021
9022 #ifdef CONFIG_IXGBE_DCB
9023 if (tc) {
9024 if (adapter->xdp_prog) {
9025 e_warn(probe, "DCB is not supported with XDP\n");
9026
9027 ixgbe_init_interrupt_scheme(adapter);
9028 if (netif_running(dev))
9029 ixgbe_open(dev);
9030 return -EINVAL;
9031 }
9032
9033 netdev_set_num_tc(dev, tc);
9034 ixgbe_set_prio_tc_map(adapter);
9035
9036 adapter->hw_tcs = tc;
9037 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
9038
9039 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
9040 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
9041 adapter->hw.fc.requested_mode = ixgbe_fc_none;
9042 }
9043 } else {
9044 netdev_reset_tc(dev);
9045
9046 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9047 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
9048
9049 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
9050 adapter->hw_tcs = tc;
9051
9052 adapter->temp_dcb_cfg.pfc_mode_enable = false;
9053 adapter->dcb_cfg.pfc_mode_enable = false;
9054 }
9055
9056 ixgbe_validate_rtr(adapter, tc);
9057
9058 #endif /* CONFIG_IXGBE_DCB */
9059 ixgbe_init_interrupt_scheme(adapter);
9060
9061 ixgbe_defrag_macvlan_pools(dev);
9062
9063 if (netif_running(dev))
9064 return ixgbe_open(dev);
9065
9066 return 0;
9067 }
9068
9069 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
9070 struct tc_cls_u32_offload *cls)
9071 {
9072 u32 hdl = cls->knode.handle;
9073 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
9074 u32 loc = cls->knode.handle & 0xfffff;
9075 int err = 0, i, j;
9076 struct ixgbe_jump_table *jump = NULL;
9077
9078 if (loc > IXGBE_MAX_HW_ENTRIES)
9079 return -EINVAL;
9080
9081 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
9082 return -EINVAL;
9083
9084 /* Clear this filter in the link data it is associated with */
9085 if (uhtid != 0x800) {
9086 jump = adapter->jump_tables[uhtid];
9087 if (!jump)
9088 return -EINVAL;
9089 if (!test_bit(loc - 1, jump->child_loc_map))
9090 return -EINVAL;
9091 clear_bit(loc - 1, jump->child_loc_map);
9092 }
9093
9094 /* Check if the filter being deleted is a link */
9095 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9096 jump = adapter->jump_tables[i];
9097 if (jump && jump->link_hdl == hdl) {
9098 /* Delete filters in the hardware in the child hash
9099 * table associated with this link
9100 */
9101 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) {
9102 if (!test_bit(j, jump->child_loc_map))
9103 continue;
9104 spin_lock(&adapter->fdir_perfect_lock);
9105 err = ixgbe_update_ethtool_fdir_entry(adapter,
9106 NULL,
9107 j + 1);
9108 spin_unlock(&adapter->fdir_perfect_lock);
9109 clear_bit(j, jump->child_loc_map);
9110 }
9111 /* Remove resources for this link */
9112 kfree(jump->input);
9113 kfree(jump->mask);
9114 kfree(jump);
9115 adapter->jump_tables[i] = NULL;
9116 return err;
9117 }
9118 }
9119
9120 spin_lock(&adapter->fdir_perfect_lock);
9121 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
9122 spin_unlock(&adapter->fdir_perfect_lock);
9123 return err;
9124 }
9125
9126 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
9127 struct tc_cls_u32_offload *cls)
9128 {
9129 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9130
9131 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9132 return -EINVAL;
9133
9134 /* This ixgbe devices do not support hash tables at the moment
9135 * so abort when given hash tables.
9136 */
9137 if (cls->hnode.divisor > 0)
9138 return -EINVAL;
9139
9140 set_bit(uhtid - 1, &adapter->tables);
9141 return 0;
9142 }
9143
9144 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
9145 struct tc_cls_u32_offload *cls)
9146 {
9147 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9148
9149 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9150 return -EINVAL;
9151
9152 clear_bit(uhtid - 1, &adapter->tables);
9153 return 0;
9154 }
9155
9156 #ifdef CONFIG_NET_CLS_ACT
9157 struct upper_walk_data {
9158 struct ixgbe_adapter *adapter;
9159 u64 action;
9160 int ifindex;
9161 u8 queue;
9162 };
9163
9164 static int get_macvlan_queue(struct net_device *upper, void *_data)
9165 {
9166 if (netif_is_macvlan(upper)) {
9167 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper);
9168 struct upper_walk_data *data = _data;
9169 struct ixgbe_adapter *adapter = data->adapter;
9170 int ifindex = data->ifindex;
9171
9172 if (vadapter && upper->ifindex == ifindex) {
9173 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx;
9174 data->action = data->queue;
9175 return 1;
9176 }
9177 }
9178
9179 return 0;
9180 }
9181
9182 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex,
9183 u8 *queue, u64 *action)
9184 {
9185 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
9186 unsigned int num_vfs = adapter->num_vfs, vf;
9187 struct upper_walk_data data;
9188 struct net_device *upper;
9189
9190 /* redirect to a SRIOV VF */
9191 for (vf = 0; vf < num_vfs; ++vf) {
9192 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev);
9193 if (upper->ifindex == ifindex) {
9194 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask);
9195 *action = vf + 1;
9196 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
9197 return 0;
9198 }
9199 }
9200
9201 /* redirect to a offloaded macvlan netdev */
9202 data.adapter = adapter;
9203 data.ifindex = ifindex;
9204 data.action = 0;
9205 data.queue = 0;
9206 if (netdev_walk_all_upper_dev_rcu(adapter->netdev,
9207 get_macvlan_queue, &data)) {
9208 *action = data.action;
9209 *queue = data.queue;
9210
9211 return 0;
9212 }
9213
9214 return -EINVAL;
9215 }
9216
9217 static int parse_tc_actions(struct ixgbe_adapter *adapter,
9218 struct tcf_exts *exts, u64 *action, u8 *queue)
9219 {
9220 const struct tc_action *a;
9221 int i;
9222
9223 if (!tcf_exts_has_actions(exts))
9224 return -EINVAL;
9225
9226 tcf_exts_for_each_action(i, a, exts) {
9227 /* Drop action */
9228 if (is_tcf_gact_shot(a)) {
9229 *action = IXGBE_FDIR_DROP_QUEUE;
9230 *queue = IXGBE_FDIR_DROP_QUEUE;
9231 return 0;
9232 }
9233
9234 /* Redirect to a VF or a offloaded macvlan */
9235 if (is_tcf_mirred_egress_redirect(a)) {
9236 struct net_device *dev = tcf_mirred_dev(a);
9237
9238 if (!dev)
9239 return -EINVAL;
9240 return handle_redirect_action(adapter, dev->ifindex,
9241 queue, action);
9242 }
9243
9244 return -EINVAL;
9245 }
9246
9247 return -EINVAL;
9248 }
9249 #else
9250 static int parse_tc_actions(struct ixgbe_adapter *adapter,
9251 struct tcf_exts *exts, u64 *action, u8 *queue)
9252 {
9253 return -EINVAL;
9254 }
9255 #endif /* CONFIG_NET_CLS_ACT */
9256
9257 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
9258 union ixgbe_atr_input *mask,
9259 struct tc_cls_u32_offload *cls,
9260 struct ixgbe_mat_field *field_ptr,
9261 struct ixgbe_nexthdr *nexthdr)
9262 {
9263 int i, j, off;
9264 __be32 val, m;
9265 bool found_entry = false, found_jump_field = false;
9266
9267 for (i = 0; i < cls->knode.sel->nkeys; i++) {
9268 off = cls->knode.sel->keys[i].off;
9269 val = cls->knode.sel->keys[i].val;
9270 m = cls->knode.sel->keys[i].mask;
9271
9272 for (j = 0; field_ptr[j].val; j++) {
9273 if (field_ptr[j].off == off) {
9274 field_ptr[j].val(input, mask, (__force u32)val,
9275 (__force u32)m);
9276 input->filter.formatted.flow_type |=
9277 field_ptr[j].type;
9278 found_entry = true;
9279 break;
9280 }
9281 }
9282 if (nexthdr) {
9283 if (nexthdr->off == cls->knode.sel->keys[i].off &&
9284 nexthdr->val ==
9285 (__force u32)cls->knode.sel->keys[i].val &&
9286 nexthdr->mask ==
9287 (__force u32)cls->knode.sel->keys[i].mask)
9288 found_jump_field = true;
9289 else
9290 continue;
9291 }
9292 }
9293
9294 if (nexthdr && !found_jump_field)
9295 return -EINVAL;
9296
9297 if (!found_entry)
9298 return 0;
9299
9300 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
9301 IXGBE_ATR_L4TYPE_MASK;
9302
9303 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
9304 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
9305
9306 return 0;
9307 }
9308
9309 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
9310 struct tc_cls_u32_offload *cls)
9311 {
9312 __be16 protocol = cls->common.protocol;
9313 u32 loc = cls->knode.handle & 0xfffff;
9314 struct ixgbe_hw *hw = &adapter->hw;
9315 struct ixgbe_mat_field *field_ptr;
9316 struct ixgbe_fdir_filter *input = NULL;
9317 union ixgbe_atr_input *mask = NULL;
9318 struct ixgbe_jump_table *jump = NULL;
9319 int i, err = -EINVAL;
9320 u8 queue;
9321 u32 uhtid, link_uhtid;
9322
9323 uhtid = TC_U32_USERHTID(cls->knode.handle);
9324 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
9325
9326 /* At the moment cls_u32 jumps to network layer and skips past
9327 * L2 headers. The canonical method to match L2 frames is to use
9328 * negative values. However this is error prone at best but really
9329 * just broken because there is no way to "know" what sort of hdr
9330 * is in front of the network layer. Fix cls_u32 to support L2
9331 * headers when needed.
9332 */
9333 if (protocol != htons(ETH_P_IP))
9334 return err;
9335
9336 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
9337 e_err(drv, "Location out of range\n");
9338 return err;
9339 }
9340
9341 /* cls u32 is a graph starting at root node 0x800. The driver tracks
9342 * links and also the fields used to advance the parser across each
9343 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
9344 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
9345 * To add support for new nodes update ixgbe_model.h parse structures
9346 * this function _should_ be generic try not to hardcode values here.
9347 */
9348 if (uhtid == 0x800) {
9349 field_ptr = (adapter->jump_tables[0])->mat;
9350 } else {
9351 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9352 return err;
9353 if (!adapter->jump_tables[uhtid])
9354 return err;
9355 field_ptr = (adapter->jump_tables[uhtid])->mat;
9356 }
9357
9358 if (!field_ptr)
9359 return err;
9360
9361 /* At this point we know the field_ptr is valid and need to either
9362 * build cls_u32 link or attach filter. Because adding a link to
9363 * a handle that does not exist is invalid and the same for adding
9364 * rules to handles that don't exist.
9365 */
9366
9367 if (link_uhtid) {
9368 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
9369
9370 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
9371 return err;
9372
9373 if (!test_bit(link_uhtid - 1, &adapter->tables))
9374 return err;
9375
9376 /* Multiple filters as links to the same hash table are not
9377 * supported. To add a new filter with the same next header
9378 * but different match/jump conditions, create a new hash table
9379 * and link to it.
9380 */
9381 if (adapter->jump_tables[link_uhtid] &&
9382 (adapter->jump_tables[link_uhtid])->link_hdl) {
9383 e_err(drv, "Link filter exists for link: %x\n",
9384 link_uhtid);
9385 return err;
9386 }
9387
9388 for (i = 0; nexthdr[i].jump; i++) {
9389 if (nexthdr[i].o != cls->knode.sel->offoff ||
9390 nexthdr[i].s != cls->knode.sel->offshift ||
9391 nexthdr[i].m !=
9392 (__force u32)cls->knode.sel->offmask)
9393 return err;
9394
9395 jump = kzalloc(sizeof(*jump), GFP_KERNEL);
9396 if (!jump)
9397 return -ENOMEM;
9398 input = kzalloc(sizeof(*input), GFP_KERNEL);
9399 if (!input) {
9400 err = -ENOMEM;
9401 goto free_jump;
9402 }
9403 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9404 if (!mask) {
9405 err = -ENOMEM;
9406 goto free_input;
9407 }
9408 jump->input = input;
9409 jump->mask = mask;
9410 jump->link_hdl = cls->knode.handle;
9411
9412 err = ixgbe_clsu32_build_input(input, mask, cls,
9413 field_ptr, &nexthdr[i]);
9414 if (!err) {
9415 jump->mat = nexthdr[i].jump;
9416 adapter->jump_tables[link_uhtid] = jump;
9417 break;
9418 }
9419 }
9420 return 0;
9421 }
9422
9423 input = kzalloc(sizeof(*input), GFP_KERNEL);
9424 if (!input)
9425 return -ENOMEM;
9426 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9427 if (!mask) {
9428 err = -ENOMEM;
9429 goto free_input;
9430 }
9431
9432 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) {
9433 if ((adapter->jump_tables[uhtid])->input)
9434 memcpy(input, (adapter->jump_tables[uhtid])->input,
9435 sizeof(*input));
9436 if ((adapter->jump_tables[uhtid])->mask)
9437 memcpy(mask, (adapter->jump_tables[uhtid])->mask,
9438 sizeof(*mask));
9439
9440 /* Lookup in all child hash tables if this location is already
9441 * filled with a filter
9442 */
9443 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9444 struct ixgbe_jump_table *link = adapter->jump_tables[i];
9445
9446 if (link && (test_bit(loc - 1, link->child_loc_map))) {
9447 e_err(drv, "Filter exists in location: %x\n",
9448 loc);
9449 err = -EINVAL;
9450 goto err_out;
9451 }
9452 }
9453 }
9454 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL);
9455 if (err)
9456 goto err_out;
9457
9458 err = parse_tc_actions(adapter, cls->knode.exts, &input->action,
9459 &queue);
9460 if (err < 0)
9461 goto err_out;
9462
9463 input->sw_idx = loc;
9464
9465 spin_lock(&adapter->fdir_perfect_lock);
9466
9467 if (hlist_empty(&adapter->fdir_filter_list)) {
9468 memcpy(&adapter->fdir_mask, mask, sizeof(*mask));
9469 err = ixgbe_fdir_set_input_mask_82599(hw, mask);
9470 if (err)
9471 goto err_out_w_lock;
9472 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) {
9473 err = -EINVAL;
9474 goto err_out_w_lock;
9475 }
9476
9477 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask);
9478 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
9479 input->sw_idx, queue);
9480 if (!err)
9481 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
9482 spin_unlock(&adapter->fdir_perfect_lock);
9483
9484 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid]))
9485 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map);
9486
9487 kfree(mask);
9488 return err;
9489 err_out_w_lock:
9490 spin_unlock(&adapter->fdir_perfect_lock);
9491 err_out:
9492 kfree(mask);
9493 free_input:
9494 kfree(input);
9495 free_jump:
9496 kfree(jump);
9497 return err;
9498 }
9499
9500 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter,
9501 struct tc_cls_u32_offload *cls_u32)
9502 {
9503 switch (cls_u32->command) {
9504 case TC_CLSU32_NEW_KNODE:
9505 case TC_CLSU32_REPLACE_KNODE:
9506 return ixgbe_configure_clsu32(adapter, cls_u32);
9507 case TC_CLSU32_DELETE_KNODE:
9508 return ixgbe_delete_clsu32(adapter, cls_u32);
9509 case TC_CLSU32_NEW_HNODE:
9510 case TC_CLSU32_REPLACE_HNODE:
9511 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32);
9512 case TC_CLSU32_DELETE_HNODE:
9513 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32);
9514 default:
9515 return -EOPNOTSUPP;
9516 }
9517 }
9518
9519 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9520 void *cb_priv)
9521 {
9522 struct ixgbe_adapter *adapter = cb_priv;
9523
9524 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
9525 return -EOPNOTSUPP;
9526
9527 switch (type) {
9528 case TC_SETUP_CLSU32:
9529 return ixgbe_setup_tc_cls_u32(adapter, type_data);
9530 default:
9531 return -EOPNOTSUPP;
9532 }
9533 }
9534
9535 static int ixgbe_setup_tc_block(struct net_device *dev,
9536 struct tc_block_offload *f)
9537 {
9538 struct ixgbe_adapter *adapter = netdev_priv(dev);
9539
9540 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
9541 return -EOPNOTSUPP;
9542
9543 switch (f->command) {
9544 case TC_BLOCK_BIND:
9545 return tcf_block_cb_register(f->block, ixgbe_setup_tc_block_cb,
9546 adapter, adapter, f->extack);
9547 case TC_BLOCK_UNBIND:
9548 tcf_block_cb_unregister(f->block, ixgbe_setup_tc_block_cb,
9549 adapter);
9550 return 0;
9551 default:
9552 return -EOPNOTSUPP;
9553 }
9554 }
9555
9556 static int ixgbe_setup_tc_mqprio(struct net_device *dev,
9557 struct tc_mqprio_qopt *mqprio)
9558 {
9559 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9560 return ixgbe_setup_tc(dev, mqprio->num_tc);
9561 }
9562
9563 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type,
9564 void *type_data)
9565 {
9566 switch (type) {
9567 case TC_SETUP_BLOCK:
9568 return ixgbe_setup_tc_block(dev, type_data);
9569 case TC_SETUP_QDISC_MQPRIO:
9570 return ixgbe_setup_tc_mqprio(dev, type_data);
9571 default:
9572 return -EOPNOTSUPP;
9573 }
9574 }
9575
9576 #ifdef CONFIG_PCI_IOV
9577 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
9578 {
9579 struct net_device *netdev = adapter->netdev;
9580
9581 rtnl_lock();
9582 ixgbe_setup_tc(netdev, adapter->hw_tcs);
9583 rtnl_unlock();
9584 }
9585
9586 #endif
9587 void ixgbe_do_reset(struct net_device *netdev)
9588 {
9589 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9590
9591 if (netif_running(netdev))
9592 ixgbe_reinit_locked(adapter);
9593 else
9594 ixgbe_reset(adapter);
9595 }
9596
9597 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
9598 netdev_features_t features)
9599 {
9600 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9601
9602 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
9603 if (!(features & NETIF_F_RXCSUM))
9604 features &= ~NETIF_F_LRO;
9605
9606 /* Turn off LRO if not RSC capable */
9607 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
9608 features &= ~NETIF_F_LRO;
9609
9610 if (adapter->xdp_prog && (features & NETIF_F_LRO)) {
9611 e_dev_err("LRO is not supported with XDP\n");
9612 features &= ~NETIF_F_LRO;
9613 }
9614
9615 return features;
9616 }
9617
9618 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter)
9619 {
9620 int rss = min_t(int, ixgbe_max_rss_indices(adapter),
9621 num_online_cpus());
9622
9623 /* go back to full RSS if we're not running SR-IOV */
9624 if (!adapter->ring_feature[RING_F_VMDQ].offset)
9625 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED |
9626 IXGBE_FLAG_SRIOV_ENABLED);
9627
9628 adapter->ring_feature[RING_F_RSS].limit = rss;
9629 adapter->ring_feature[RING_F_VMDQ].limit = 1;
9630
9631 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs);
9632 }
9633
9634 static int ixgbe_set_features(struct net_device *netdev,
9635 netdev_features_t features)
9636 {
9637 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9638 netdev_features_t changed = netdev->features ^ features;
9639 bool need_reset = false;
9640
9641 /* Make sure RSC matches LRO, reset if change */
9642 if (!(features & NETIF_F_LRO)) {
9643 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
9644 need_reset = true;
9645 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
9646 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
9647 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
9648 if (adapter->rx_itr_setting == 1 ||
9649 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
9650 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9651 need_reset = true;
9652 } else if ((changed ^ features) & NETIF_F_LRO) {
9653 e_info(probe, "rx-usecs set too low, "
9654 "disabling RSC\n");
9655 }
9656 }
9657
9658 /*
9659 * Check if Flow Director n-tuple support or hw_tc support was
9660 * enabled or disabled. If the state changed, we need to reset.
9661 */
9662 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
9663 /* turn off ATR, enable perfect filters and reset */
9664 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
9665 need_reset = true;
9666
9667 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
9668 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9669 } else {
9670 /* turn off perfect filters, enable ATR and reset */
9671 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
9672 need_reset = true;
9673
9674 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9675
9676 /* We cannot enable ATR if SR-IOV is enabled */
9677 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
9678 /* We cannot enable ATR if we have 2 or more tcs */
9679 (adapter->hw_tcs > 1) ||
9680 /* We cannot enable ATR if RSS is disabled */
9681 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
9682 /* A sample rate of 0 indicates ATR disabled */
9683 (!adapter->atr_sample_rate))
9684 ; /* do nothing not supported */
9685 else /* otherwise supported and set the flag */
9686 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
9687 }
9688
9689 if (changed & NETIF_F_RXALL)
9690 need_reset = true;
9691
9692 netdev->features = features;
9693
9694 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
9695 if (features & NETIF_F_RXCSUM) {
9696 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
9697 } else {
9698 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK;
9699
9700 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9701 }
9702 }
9703
9704 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) {
9705 if (features & NETIF_F_RXCSUM) {
9706 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
9707 } else {
9708 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK;
9709
9710 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9711 }
9712 }
9713
9714 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1)
9715 ixgbe_reset_l2fw_offload(adapter);
9716 else if (need_reset)
9717 ixgbe_do_reset(netdev);
9718 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
9719 NETIF_F_HW_VLAN_CTAG_FILTER))
9720 ixgbe_set_rx_mode(netdev);
9721
9722 return 0;
9723 }
9724
9725 /**
9726 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports
9727 * @dev: The port's netdev
9728 * @ti: Tunnel endpoint information
9729 **/
9730 static void ixgbe_add_udp_tunnel_port(struct net_device *dev,
9731 struct udp_tunnel_info *ti)
9732 {
9733 struct ixgbe_adapter *adapter = netdev_priv(dev);
9734 struct ixgbe_hw *hw = &adapter->hw;
9735 __be16 port = ti->port;
9736 u32 port_shift = 0;
9737 u32 reg;
9738
9739 if (ti->sa_family != AF_INET)
9740 return;
9741
9742 switch (ti->type) {
9743 case UDP_TUNNEL_TYPE_VXLAN:
9744 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
9745 return;
9746
9747 if (adapter->vxlan_port == port)
9748 return;
9749
9750 if (adapter->vxlan_port) {
9751 netdev_info(dev,
9752 "VXLAN port %d set, not adding port %d\n",
9753 ntohs(adapter->vxlan_port),
9754 ntohs(port));
9755 return;
9756 }
9757
9758 adapter->vxlan_port = port;
9759 break;
9760 case UDP_TUNNEL_TYPE_GENEVE:
9761 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))
9762 return;
9763
9764 if (adapter->geneve_port == port)
9765 return;
9766
9767 if (adapter->geneve_port) {
9768 netdev_info(dev,
9769 "GENEVE port %d set, not adding port %d\n",
9770 ntohs(adapter->geneve_port),
9771 ntohs(port));
9772 return;
9773 }
9774
9775 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT;
9776 adapter->geneve_port = port;
9777 break;
9778 default:
9779 return;
9780 }
9781
9782 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift;
9783 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg);
9784 }
9785
9786 /**
9787 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports
9788 * @dev: The port's netdev
9789 * @ti: Tunnel endpoint information
9790 **/
9791 static void ixgbe_del_udp_tunnel_port(struct net_device *dev,
9792 struct udp_tunnel_info *ti)
9793 {
9794 struct ixgbe_adapter *adapter = netdev_priv(dev);
9795 u32 port_mask;
9796
9797 if (ti->type != UDP_TUNNEL_TYPE_VXLAN &&
9798 ti->type != UDP_TUNNEL_TYPE_GENEVE)
9799 return;
9800
9801 if (ti->sa_family != AF_INET)
9802 return;
9803
9804 switch (ti->type) {
9805 case UDP_TUNNEL_TYPE_VXLAN:
9806 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
9807 return;
9808
9809 if (adapter->vxlan_port != ti->port) {
9810 netdev_info(dev, "VXLAN port %d not found\n",
9811 ntohs(ti->port));
9812 return;
9813 }
9814
9815 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK;
9816 break;
9817 case UDP_TUNNEL_TYPE_GENEVE:
9818 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))
9819 return;
9820
9821 if (adapter->geneve_port != ti->port) {
9822 netdev_info(dev, "GENEVE port %d not found\n",
9823 ntohs(ti->port));
9824 return;
9825 }
9826
9827 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK;
9828 break;
9829 default:
9830 return;
9831 }
9832
9833 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9834 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
9835 }
9836
9837 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
9838 struct net_device *dev,
9839 const unsigned char *addr, u16 vid,
9840 u16 flags)
9841 {
9842 /* guarantee we can provide a unique filter for the unicast address */
9843 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
9844 struct ixgbe_adapter *adapter = netdev_priv(dev);
9845 u16 pool = VMDQ_P(0);
9846
9847 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
9848 return -ENOMEM;
9849 }
9850
9851 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
9852 }
9853
9854 /**
9855 * ixgbe_configure_bridge_mode - set various bridge modes
9856 * @adapter: the private structure
9857 * @mode: requested bridge mode
9858 *
9859 * Configure some settings require for various bridge modes.
9860 **/
9861 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
9862 __u16 mode)
9863 {
9864 struct ixgbe_hw *hw = &adapter->hw;
9865 unsigned int p, num_pools;
9866 u32 vmdctl;
9867
9868 switch (mode) {
9869 case BRIDGE_MODE_VEPA:
9870 /* disable Tx loopback, rely on switch hairpin mode */
9871 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
9872
9873 /* must enable Rx switching replication to allow multicast
9874 * packet reception on all VFs, and to enable source address
9875 * pruning.
9876 */
9877 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9878 vmdctl |= IXGBE_VT_CTL_REPLEN;
9879 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9880
9881 /* enable Rx source address pruning. Note, this requires
9882 * replication to be enabled or else it does nothing.
9883 */
9884 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9885 for (p = 0; p < num_pools; p++) {
9886 if (hw->mac.ops.set_source_address_pruning)
9887 hw->mac.ops.set_source_address_pruning(hw,
9888 true,
9889 p);
9890 }
9891 break;
9892 case BRIDGE_MODE_VEB:
9893 /* enable Tx loopback for internal VF/PF communication */
9894 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
9895 IXGBE_PFDTXGSWC_VT_LBEN);
9896
9897 /* disable Rx switching replication unless we have SR-IOV
9898 * virtual functions
9899 */
9900 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9901 if (!adapter->num_vfs)
9902 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
9903 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9904
9905 /* disable Rx source address pruning, since we don't expect to
9906 * be receiving external loopback of our transmitted frames.
9907 */
9908 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9909 for (p = 0; p < num_pools; p++) {
9910 if (hw->mac.ops.set_source_address_pruning)
9911 hw->mac.ops.set_source_address_pruning(hw,
9912 false,
9913 p);
9914 }
9915 break;
9916 default:
9917 return -EINVAL;
9918 }
9919
9920 adapter->bridge_mode = mode;
9921
9922 e_info(drv, "enabling bridge mode: %s\n",
9923 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
9924
9925 return 0;
9926 }
9927
9928 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
9929 struct nlmsghdr *nlh, u16 flags)
9930 {
9931 struct ixgbe_adapter *adapter = netdev_priv(dev);
9932 struct nlattr *attr, *br_spec;
9933 int rem;
9934
9935 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9936 return -EOPNOTSUPP;
9937
9938 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
9939 if (!br_spec)
9940 return -EINVAL;
9941
9942 nla_for_each_nested(attr, br_spec, rem) {
9943 int status;
9944 __u16 mode;
9945
9946 if (nla_type(attr) != IFLA_BRIDGE_MODE)
9947 continue;
9948
9949 if (nla_len(attr) < sizeof(mode))
9950 return -EINVAL;
9951
9952 mode = nla_get_u16(attr);
9953 status = ixgbe_configure_bridge_mode(adapter, mode);
9954 if (status)
9955 return status;
9956
9957 break;
9958 }
9959
9960 return 0;
9961 }
9962
9963 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
9964 struct net_device *dev,
9965 u32 filter_mask, int nlflags)
9966 {
9967 struct ixgbe_adapter *adapter = netdev_priv(dev);
9968
9969 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9970 return 0;
9971
9972 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
9973 adapter->bridge_mode, 0, 0, nlflags,
9974 filter_mask, NULL);
9975 }
9976
9977 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
9978 {
9979 struct ixgbe_adapter *adapter = netdev_priv(pdev);
9980 struct ixgbe_fwd_adapter *accel;
9981 int tcs = adapter->hw_tcs ? : 1;
9982 int pool, err;
9983
9984 if (adapter->xdp_prog) {
9985 e_warn(probe, "L2FW offload is not supported with XDP\n");
9986 return ERR_PTR(-EINVAL);
9987 }
9988
9989 /* The hardware supported by ixgbe only filters on the destination MAC
9990 * address. In order to avoid issues we only support offloading modes
9991 * where the hardware can actually provide the functionality.
9992 */
9993 if (!macvlan_supports_dest_filter(vdev))
9994 return ERR_PTR(-EMEDIUMTYPE);
9995
9996 /* We need to lock down the macvlan to be a single queue device so that
9997 * we can reuse the tc_to_txq field in the macvlan netdev to represent
9998 * the queue mapping to our netdev.
9999 */
10000 if (netif_is_multiqueue(vdev))
10001 return ERR_PTR(-ERANGE);
10002
10003 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
10004 if (pool == adapter->num_rx_pools) {
10005 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools;
10006 u16 reserved_pools;
10007
10008 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
10009 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) ||
10010 adapter->num_rx_pools > IXGBE_MAX_MACVLANS)
10011 return ERR_PTR(-EBUSY);
10012
10013 /* Hardware has a limited number of available pools. Each VF,
10014 * and the PF require a pool. Check to ensure we don't
10015 * attempt to use more then the available number of pools.
10016 */
10017 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
10018 return ERR_PTR(-EBUSY);
10019
10020 /* Enable VMDq flag so device will be set in VM mode */
10021 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED |
10022 IXGBE_FLAG_SRIOV_ENABLED;
10023
10024 /* Try to reserve as many queues per pool as possible,
10025 * we start with the configurations that support 4 queues
10026 * per pools, followed by 2, and then by just 1 per pool.
10027 */
10028 if (used_pools < 32 && adapter->num_rx_pools < 16)
10029 reserved_pools = min_t(u16,
10030 32 - used_pools,
10031 16 - adapter->num_rx_pools);
10032 else if (adapter->num_rx_pools < 32)
10033 reserved_pools = min_t(u16,
10034 64 - used_pools,
10035 32 - adapter->num_rx_pools);
10036 else
10037 reserved_pools = 64 - used_pools;
10038
10039
10040 if (!reserved_pools)
10041 return ERR_PTR(-EBUSY);
10042
10043 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools;
10044
10045 /* Force reinit of ring allocation with VMDQ enabled */
10046 err = ixgbe_setup_tc(pdev, adapter->hw_tcs);
10047 if (err)
10048 return ERR_PTR(err);
10049
10050 if (pool >= adapter->num_rx_pools)
10051 return ERR_PTR(-ENOMEM);
10052 }
10053
10054 accel = kzalloc(sizeof(*accel), GFP_KERNEL);
10055 if (!accel)
10056 return ERR_PTR(-ENOMEM);
10057
10058 set_bit(pool, adapter->fwd_bitmask);
10059 netdev_set_sb_channel(vdev, pool);
10060 accel->pool = pool;
10061 accel->netdev = vdev;
10062
10063 if (!netif_running(pdev))
10064 return accel;
10065
10066 err = ixgbe_fwd_ring_up(adapter, accel);
10067 if (err)
10068 return ERR_PTR(err);
10069
10070 return accel;
10071 }
10072
10073 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
10074 {
10075 struct ixgbe_fwd_adapter *accel = priv;
10076 struct ixgbe_adapter *adapter = netdev_priv(pdev);
10077 unsigned int rxbase = accel->rx_base_queue;
10078 unsigned int i;
10079
10080 /* delete unicast filter associated with offloaded interface */
10081 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr,
10082 VMDQ_P(accel->pool));
10083
10084 /* Allow remaining Rx packets to get flushed out of the
10085 * Rx FIFO before we drop the netdev for the ring.
10086 */
10087 usleep_range(10000, 20000);
10088
10089 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
10090 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i];
10091 struct ixgbe_q_vector *qv = ring->q_vector;
10092
10093 /* Make sure we aren't processing any packets and clear
10094 * netdev to shut down the ring.
10095 */
10096 if (netif_running(adapter->netdev))
10097 napi_synchronize(&qv->napi);
10098 ring->netdev = NULL;
10099 }
10100
10101 /* unbind the queues and drop the subordinate channel config */
10102 netdev_unbind_sb_channel(pdev, accel->netdev);
10103 netdev_set_sb_channel(accel->netdev, 0);
10104
10105 clear_bit(accel->pool, adapter->fwd_bitmask);
10106 kfree(accel);
10107 }
10108
10109 #define IXGBE_MAX_MAC_HDR_LEN 127
10110 #define IXGBE_MAX_NETWORK_HDR_LEN 511
10111
10112 static netdev_features_t
10113 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
10114 netdev_features_t features)
10115 {
10116 unsigned int network_hdr_len, mac_hdr_len;
10117
10118 /* Make certain the headers can be described by a context descriptor */
10119 mac_hdr_len = skb_network_header(skb) - skb->data;
10120 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
10121 return features & ~(NETIF_F_HW_CSUM |
10122 NETIF_F_SCTP_CRC |
10123 NETIF_F_HW_VLAN_CTAG_TX |
10124 NETIF_F_TSO |
10125 NETIF_F_TSO6);
10126
10127 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
10128 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN))
10129 return features & ~(NETIF_F_HW_CSUM |
10130 NETIF_F_SCTP_CRC |
10131 NETIF_F_TSO |
10132 NETIF_F_TSO6);
10133
10134 /* We can only support IPV4 TSO in tunnels if we can mangle the
10135 * inner IP ID field, so strip TSO if MANGLEID is not supported.
10136 * IPsec offoad sets skb->encapsulation but still can handle
10137 * the TSO, so it's the exception.
10138 */
10139 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) {
10140 #ifdef CONFIG_XFRM_OFFLOAD
10141 if (!skb->sp)
10142 #endif
10143 features &= ~NETIF_F_TSO;
10144 }
10145
10146 return features;
10147 }
10148
10149 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog)
10150 {
10151 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
10152 struct ixgbe_adapter *adapter = netdev_priv(dev);
10153 struct bpf_prog *old_prog;
10154
10155 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
10156 return -EINVAL;
10157
10158 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
10159 return -EINVAL;
10160
10161 /* verify ixgbe ring attributes are sufficient for XDP */
10162 for (i = 0; i < adapter->num_rx_queues; i++) {
10163 struct ixgbe_ring *ring = adapter->rx_ring[i];
10164
10165 if (ring_is_rsc_enabled(ring))
10166 return -EINVAL;
10167
10168 if (frame_size > ixgbe_rx_bufsz(ring))
10169 return -EINVAL;
10170 }
10171
10172 if (nr_cpu_ids > MAX_XDP_QUEUES)
10173 return -ENOMEM;
10174
10175 old_prog = xchg(&adapter->xdp_prog, prog);
10176
10177 /* If transitioning XDP modes reconfigure rings */
10178 if (!!prog != !!old_prog) {
10179 int err = ixgbe_setup_tc(dev, adapter->hw_tcs);
10180
10181 if (err) {
10182 rcu_assign_pointer(adapter->xdp_prog, old_prog);
10183 return -EINVAL;
10184 }
10185 } else {
10186 for (i = 0; i < adapter->num_rx_queues; i++)
10187 (void)xchg(&adapter->rx_ring[i]->xdp_prog,
10188 adapter->xdp_prog);
10189 }
10190
10191 if (old_prog)
10192 bpf_prog_put(old_prog);
10193
10194 return 0;
10195 }
10196
10197 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp)
10198 {
10199 struct ixgbe_adapter *adapter = netdev_priv(dev);
10200
10201 switch (xdp->command) {
10202 case XDP_SETUP_PROG:
10203 return ixgbe_xdp_setup(dev, xdp->prog);
10204 case XDP_QUERY_PROG:
10205 xdp->prog_id = adapter->xdp_prog ?
10206 adapter->xdp_prog->aux->id : 0;
10207 return 0;
10208 default:
10209 return -EINVAL;
10210 }
10211 }
10212
10213 static void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring)
10214 {
10215 /* Force memory writes to complete before letting h/w know there
10216 * are new descriptors to fetch.
10217 */
10218 wmb();
10219 writel(ring->next_to_use, ring->tail);
10220 }
10221
10222 static int ixgbe_xdp_xmit(struct net_device *dev, int n,
10223 struct xdp_frame **frames, u32 flags)
10224 {
10225 struct ixgbe_adapter *adapter = netdev_priv(dev);
10226 struct ixgbe_ring *ring;
10227 int drops = 0;
10228 int i;
10229
10230 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state)))
10231 return -ENETDOWN;
10232
10233 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
10234 return -EINVAL;
10235
10236 /* During program transitions its possible adapter->xdp_prog is assigned
10237 * but ring has not been configured yet. In this case simply abort xmit.
10238 */
10239 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL;
10240 if (unlikely(!ring))
10241 return -ENXIO;
10242
10243 for (i = 0; i < n; i++) {
10244 struct xdp_frame *xdpf = frames[i];
10245 int err;
10246
10247 err = ixgbe_xmit_xdp_ring(adapter, xdpf);
10248 if (err != IXGBE_XDP_TX) {
10249 xdp_return_frame_rx_napi(xdpf);
10250 drops++;
10251 }
10252 }
10253
10254 if (unlikely(flags & XDP_XMIT_FLUSH))
10255 ixgbe_xdp_ring_update_tail(ring);
10256
10257 return n - drops;
10258 }
10259
10260 static const struct net_device_ops ixgbe_netdev_ops = {
10261 .ndo_open = ixgbe_open,
10262 .ndo_stop = ixgbe_close,
10263 .ndo_start_xmit = ixgbe_xmit_frame,
10264 .ndo_set_rx_mode = ixgbe_set_rx_mode,
10265 .ndo_validate_addr = eth_validate_addr,
10266 .ndo_set_mac_address = ixgbe_set_mac,
10267 .ndo_change_mtu = ixgbe_change_mtu,
10268 .ndo_tx_timeout = ixgbe_tx_timeout,
10269 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
10270 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
10271 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
10272 .ndo_do_ioctl = ixgbe_ioctl,
10273 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
10274 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
10275 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
10276 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
10277 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
10278 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
10279 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
10280 .ndo_get_stats64 = ixgbe_get_stats64,
10281 .ndo_setup_tc = __ixgbe_setup_tc,
10282 #ifdef IXGBE_FCOE
10283 .ndo_select_queue = ixgbe_select_queue,
10284 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
10285 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
10286 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
10287 .ndo_fcoe_enable = ixgbe_fcoe_enable,
10288 .ndo_fcoe_disable = ixgbe_fcoe_disable,
10289 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
10290 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
10291 #endif /* IXGBE_FCOE */
10292 .ndo_set_features = ixgbe_set_features,
10293 .ndo_fix_features = ixgbe_fix_features,
10294 .ndo_fdb_add = ixgbe_ndo_fdb_add,
10295 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
10296 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
10297 .ndo_dfwd_add_station = ixgbe_fwd_add,
10298 .ndo_dfwd_del_station = ixgbe_fwd_del,
10299 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port,
10300 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port,
10301 .ndo_features_check = ixgbe_features_check,
10302 .ndo_bpf = ixgbe_xdp,
10303 .ndo_xdp_xmit = ixgbe_xdp_xmit,
10304 };
10305
10306 /**
10307 * ixgbe_enumerate_functions - Get the number of ports this device has
10308 * @adapter: adapter structure
10309 *
10310 * This function enumerates the phsyical functions co-located on a single slot,
10311 * in order to determine how many ports a device has. This is most useful in
10312 * determining the required GT/s of PCIe bandwidth necessary for optimal
10313 * performance.
10314 **/
10315 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
10316 {
10317 struct pci_dev *entry, *pdev = adapter->pdev;
10318 int physfns = 0;
10319
10320 /* Some cards can not use the generic count PCIe functions method,
10321 * because they are behind a parent switch, so we hardcode these with
10322 * the correct number of functions.
10323 */
10324 if (ixgbe_pcie_from_parent(&adapter->hw))
10325 physfns = 4;
10326
10327 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
10328 /* don't count virtual functions */
10329 if (entry->is_virtfn)
10330 continue;
10331
10332 /* When the devices on the bus don't all match our device ID,
10333 * we can't reliably determine the correct number of
10334 * functions. This can occur if a function has been direct
10335 * attached to a virtual machine using VT-d, for example. In
10336 * this case, simply return -1 to indicate this.
10337 */
10338 if ((entry->vendor != pdev->vendor) ||
10339 (entry->device != pdev->device))
10340 return -1;
10341
10342 physfns++;
10343 }
10344
10345 return physfns;
10346 }
10347
10348 /**
10349 * ixgbe_wol_supported - Check whether device supports WoL
10350 * @adapter: the adapter private structure
10351 * @device_id: the device ID
10352 * @subdevice_id: the subsystem device ID
10353 *
10354 * This function is used by probe and ethtool to determine
10355 * which devices have WoL support
10356 *
10357 **/
10358 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
10359 u16 subdevice_id)
10360 {
10361 struct ixgbe_hw *hw = &adapter->hw;
10362 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
10363
10364 /* WOL not supported on 82598 */
10365 if (hw->mac.type == ixgbe_mac_82598EB)
10366 return false;
10367
10368 /* check eeprom to see if WOL is enabled for X540 and newer */
10369 if (hw->mac.type >= ixgbe_mac_X540) {
10370 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
10371 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
10372 (hw->bus.func == 0)))
10373 return true;
10374 }
10375
10376 /* WOL is determined based on device IDs for 82599 MACs */
10377 switch (device_id) {
10378 case IXGBE_DEV_ID_82599_SFP:
10379 /* Only these subdevices could supports WOL */
10380 switch (subdevice_id) {
10381 case IXGBE_SUBDEV_ID_82599_560FLR:
10382 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
10383 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
10384 case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
10385 /* only support first port */
10386 if (hw->bus.func != 0)
10387 break;
10388 /* fall through */
10389 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
10390 case IXGBE_SUBDEV_ID_82599_SFP:
10391 case IXGBE_SUBDEV_ID_82599_RNDC:
10392 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
10393 case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
10394 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
10395 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
10396 return true;
10397 }
10398 break;
10399 case IXGBE_DEV_ID_82599EN_SFP:
10400 /* Only these subdevices support WOL */
10401 switch (subdevice_id) {
10402 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
10403 return true;
10404 }
10405 break;
10406 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
10407 /* All except this subdevice support WOL */
10408 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
10409 return true;
10410 break;
10411 case IXGBE_DEV_ID_82599_KX4:
10412 return true;
10413 default:
10414 break;
10415 }
10416
10417 return false;
10418 }
10419
10420 /**
10421 * ixgbe_set_fw_version - Set FW version
10422 * @adapter: the adapter private structure
10423 *
10424 * This function is used by probe and ethtool to determine the FW version to
10425 * format to display. The FW version is taken from the EEPROM/NVM.
10426 */
10427 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter)
10428 {
10429 struct ixgbe_hw *hw = &adapter->hw;
10430 struct ixgbe_nvm_version nvm_ver;
10431
10432 ixgbe_get_oem_prod_version(hw, &nvm_ver);
10433 if (nvm_ver.oem_valid) {
10434 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10435 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor,
10436 nvm_ver.oem_release);
10437 return;
10438 }
10439
10440 ixgbe_get_etk_id(hw, &nvm_ver);
10441 ixgbe_get_orom_version(hw, &nvm_ver);
10442
10443 if (nvm_ver.or_valid) {
10444 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10445 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major,
10446 nvm_ver.or_build, nvm_ver.or_patch);
10447 return;
10448 }
10449
10450 /* Set ETrack ID format */
10451 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10452 "0x%08x", nvm_ver.etk_id);
10453 }
10454
10455 /**
10456 * ixgbe_probe - Device Initialization Routine
10457 * @pdev: PCI device information struct
10458 * @ent: entry in ixgbe_pci_tbl
10459 *
10460 * Returns 0 on success, negative on failure
10461 *
10462 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
10463 * The OS initialization, configuring of the adapter private structure,
10464 * and a hardware reset occur.
10465 **/
10466 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10467 {
10468 struct net_device *netdev;
10469 struct ixgbe_adapter *adapter = NULL;
10470 struct ixgbe_hw *hw;
10471 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
10472 int i, err, pci_using_dac, expected_gts;
10473 unsigned int indices = MAX_TX_QUEUES;
10474 u8 part_str[IXGBE_PBANUM_LENGTH];
10475 bool disable_dev = false;
10476 #ifdef IXGBE_FCOE
10477 u16 device_caps;
10478 #endif
10479 u32 eec;
10480
10481 /* Catch broken hardware that put the wrong VF device ID in
10482 * the PCIe SR-IOV capability.
10483 */
10484 if (pdev->is_virtfn) {
10485 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
10486 pci_name(pdev), pdev->vendor, pdev->device);
10487 return -EINVAL;
10488 }
10489
10490 err = pci_enable_device_mem(pdev);
10491 if (err)
10492 return err;
10493
10494 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
10495 pci_using_dac = 1;
10496 } else {
10497 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10498 if (err) {
10499 dev_err(&pdev->dev,
10500 "No usable DMA configuration, aborting\n");
10501 goto err_dma;
10502 }
10503 pci_using_dac = 0;
10504 }
10505
10506 err = pci_request_mem_regions(pdev, ixgbe_driver_name);
10507 if (err) {
10508 dev_err(&pdev->dev,
10509 "pci_request_selected_regions failed 0x%x\n", err);
10510 goto err_pci_reg;
10511 }
10512
10513 pci_enable_pcie_error_reporting(pdev);
10514
10515 pci_set_master(pdev);
10516 pci_save_state(pdev);
10517
10518 if (ii->mac == ixgbe_mac_82598EB) {
10519 #ifdef CONFIG_IXGBE_DCB
10520 /* 8 TC w/ 4 queues per TC */
10521 indices = 4 * MAX_TRAFFIC_CLASS;
10522 #else
10523 indices = IXGBE_MAX_RSS_INDICES;
10524 #endif
10525 }
10526
10527 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
10528 if (!netdev) {
10529 err = -ENOMEM;
10530 goto err_alloc_etherdev;
10531 }
10532
10533 SET_NETDEV_DEV(netdev, &pdev->dev);
10534
10535 adapter = netdev_priv(netdev);
10536
10537 adapter->netdev = netdev;
10538 adapter->pdev = pdev;
10539 hw = &adapter->hw;
10540 hw->back = adapter;
10541 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
10542
10543 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
10544 pci_resource_len(pdev, 0));
10545 adapter->io_addr = hw->hw_addr;
10546 if (!hw->hw_addr) {
10547 err = -EIO;
10548 goto err_ioremap;
10549 }
10550
10551 netdev->netdev_ops = &ixgbe_netdev_ops;
10552 ixgbe_set_ethtool_ops(netdev);
10553 netdev->watchdog_timeo = 5 * HZ;
10554 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
10555
10556 /* Setup hw api */
10557 hw->mac.ops = *ii->mac_ops;
10558 hw->mac.type = ii->mac;
10559 hw->mvals = ii->mvals;
10560 if (ii->link_ops)
10561 hw->link.ops = *ii->link_ops;
10562
10563 /* EEPROM */
10564 hw->eeprom.ops = *ii->eeprom_ops;
10565 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
10566 if (ixgbe_removed(hw->hw_addr)) {
10567 err = -EIO;
10568 goto err_ioremap;
10569 }
10570 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
10571 if (!(eec & BIT(8)))
10572 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
10573
10574 /* PHY */
10575 hw->phy.ops = *ii->phy_ops;
10576 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
10577 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
10578 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
10579 hw->phy.mdio.mmds = 0;
10580 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10581 hw->phy.mdio.dev = netdev;
10582 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
10583 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
10584
10585 /* setup the private structure */
10586 err = ixgbe_sw_init(adapter, ii);
10587 if (err)
10588 goto err_sw_init;
10589
10590 /* Make sure the SWFW semaphore is in a valid state */
10591 if (hw->mac.ops.init_swfw_sync)
10592 hw->mac.ops.init_swfw_sync(hw);
10593
10594 /* Make it possible the adapter to be woken up via WOL */
10595 switch (adapter->hw.mac.type) {
10596 case ixgbe_mac_82599EB:
10597 case ixgbe_mac_X540:
10598 case ixgbe_mac_X550:
10599 case ixgbe_mac_X550EM_x:
10600 case ixgbe_mac_x550em_a:
10601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
10602 break;
10603 default:
10604 break;
10605 }
10606
10607 /*
10608 * If there is a fan on this device and it has failed log the
10609 * failure.
10610 */
10611 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
10612 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
10613 if (esdp & IXGBE_ESDP_SDP1)
10614 e_crit(probe, "Fan has stopped, replace the adapter\n");
10615 }
10616
10617 if (allow_unsupported_sfp)
10618 hw->allow_unsupported_sfp = allow_unsupported_sfp;
10619
10620 /* reset_hw fills in the perm_addr as well */
10621 hw->phy.reset_if_overtemp = true;
10622 err = hw->mac.ops.reset_hw(hw);
10623 hw->phy.reset_if_overtemp = false;
10624 ixgbe_set_eee_capable(adapter);
10625 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
10626 err = 0;
10627 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
10628 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
10629 e_dev_err("Reload the driver after installing a supported module.\n");
10630 goto err_sw_init;
10631 } else if (err) {
10632 e_dev_err("HW Init failed: %d\n", err);
10633 goto err_sw_init;
10634 }
10635
10636 #ifdef CONFIG_PCI_IOV
10637 /* SR-IOV not supported on the 82598 */
10638 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
10639 goto skip_sriov;
10640 /* Mailbox */
10641 ixgbe_init_mbx_params_pf(hw);
10642 hw->mbx.ops = ii->mbx_ops;
10643 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
10644 ixgbe_enable_sriov(adapter, max_vfs);
10645 skip_sriov:
10646
10647 #endif
10648 netdev->features = NETIF_F_SG |
10649 NETIF_F_TSO |
10650 NETIF_F_TSO6 |
10651 NETIF_F_RXHASH |
10652 NETIF_F_RXCSUM |
10653 NETIF_F_HW_CSUM;
10654
10655 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
10656 NETIF_F_GSO_GRE_CSUM | \
10657 NETIF_F_GSO_IPXIP4 | \
10658 NETIF_F_GSO_IPXIP6 | \
10659 NETIF_F_GSO_UDP_TUNNEL | \
10660 NETIF_F_GSO_UDP_TUNNEL_CSUM)
10661
10662 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
10663 netdev->features |= NETIF_F_GSO_PARTIAL |
10664 IXGBE_GSO_PARTIAL_FEATURES;
10665
10666 if (hw->mac.type >= ixgbe_mac_82599EB)
10667 netdev->features |= NETIF_F_SCTP_CRC;
10668
10669 #ifdef CONFIG_XFRM_OFFLOAD
10670 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \
10671 NETIF_F_HW_ESP_TX_CSUM | \
10672 NETIF_F_GSO_ESP)
10673
10674 if (adapter->ipsec)
10675 netdev->features |= IXGBE_ESP_FEATURES;
10676 #endif
10677 /* copy netdev features into list of user selectable features */
10678 netdev->hw_features |= netdev->features |
10679 NETIF_F_HW_VLAN_CTAG_FILTER |
10680 NETIF_F_HW_VLAN_CTAG_RX |
10681 NETIF_F_HW_VLAN_CTAG_TX |
10682 NETIF_F_RXALL |
10683 NETIF_F_HW_L2FW_DOFFLOAD;
10684
10685 if (hw->mac.type >= ixgbe_mac_82599EB)
10686 netdev->hw_features |= NETIF_F_NTUPLE |
10687 NETIF_F_HW_TC;
10688
10689 if (pci_using_dac)
10690 netdev->features |= NETIF_F_HIGHDMA;
10691
10692 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
10693 netdev->hw_enc_features |= netdev->vlan_features;
10694 netdev->mpls_features |= NETIF_F_SG |
10695 NETIF_F_TSO |
10696 NETIF_F_TSO6 |
10697 NETIF_F_HW_CSUM;
10698 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES;
10699
10700 /* set this bit last since it cannot be part of vlan_features */
10701 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
10702 NETIF_F_HW_VLAN_CTAG_RX |
10703 NETIF_F_HW_VLAN_CTAG_TX;
10704
10705 netdev->priv_flags |= IFF_UNICAST_FLT;
10706 netdev->priv_flags |= IFF_SUPP_NOFCS;
10707
10708 /* MTU range: 68 - 9710 */
10709 netdev->min_mtu = ETH_MIN_MTU;
10710 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
10711
10712 #ifdef CONFIG_IXGBE_DCB
10713 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
10714 netdev->dcbnl_ops = &ixgbe_dcbnl_ops;
10715 #endif
10716
10717 #ifdef IXGBE_FCOE
10718 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
10719 unsigned int fcoe_l;
10720
10721 if (hw->mac.ops.get_device_caps) {
10722 hw->mac.ops.get_device_caps(hw, &device_caps);
10723 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
10724 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
10725 }
10726
10727
10728 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
10729 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
10730
10731 netdev->features |= NETIF_F_FSO |
10732 NETIF_F_FCOE_CRC;
10733
10734 netdev->vlan_features |= NETIF_F_FSO |
10735 NETIF_F_FCOE_CRC |
10736 NETIF_F_FCOE_MTU;
10737 }
10738 #endif /* IXGBE_FCOE */
10739 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
10740 netdev->hw_features |= NETIF_F_LRO;
10741 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
10742 netdev->features |= NETIF_F_LRO;
10743
10744 /* make sure the EEPROM is good */
10745 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
10746 e_dev_err("The EEPROM Checksum Is Not Valid\n");
10747 err = -EIO;
10748 goto err_sw_init;
10749 }
10750
10751 eth_platform_get_mac_address(&adapter->pdev->dev,
10752 adapter->hw.mac.perm_addr);
10753
10754 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
10755
10756 if (!is_valid_ether_addr(netdev->dev_addr)) {
10757 e_dev_err("invalid MAC address\n");
10758 err = -EIO;
10759 goto err_sw_init;
10760 }
10761
10762 /* Set hw->mac.addr to permanent MAC address */
10763 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
10764 ixgbe_mac_set_default_filter(adapter);
10765
10766 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0);
10767
10768 if (ixgbe_removed(hw->hw_addr)) {
10769 err = -EIO;
10770 goto err_sw_init;
10771 }
10772 INIT_WORK(&adapter->service_task, ixgbe_service_task);
10773 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
10774 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
10775
10776 err = ixgbe_init_interrupt_scheme(adapter);
10777 if (err)
10778 goto err_sw_init;
10779
10780 for (i = 0; i < adapter->num_rx_queues; i++)
10781 u64_stats_init(&adapter->rx_ring[i]->syncp);
10782 for (i = 0; i < adapter->num_tx_queues; i++)
10783 u64_stats_init(&adapter->tx_ring[i]->syncp);
10784 for (i = 0; i < adapter->num_xdp_queues; i++)
10785 u64_stats_init(&adapter->xdp_ring[i]->syncp);
10786
10787 /* WOL not supported for all devices */
10788 adapter->wol = 0;
10789 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
10790 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
10791 pdev->subsystem_device);
10792 if (hw->wol_enabled)
10793 adapter->wol = IXGBE_WUFC_MAG;
10794
10795 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
10796
10797 /* save off EEPROM version number */
10798 ixgbe_set_fw_version(adapter);
10799
10800 /* pick up the PCI bus settings for reporting later */
10801 if (ixgbe_pcie_from_parent(hw))
10802 ixgbe_get_parent_bus_info(adapter);
10803 else
10804 hw->mac.ops.get_bus_info(hw);
10805
10806 /* calculate the expected PCIe bandwidth required for optimal
10807 * performance. Note that some older parts will never have enough
10808 * bandwidth due to being older generation PCIe parts. We clamp these
10809 * parts to ensure no warning is displayed if it can't be fixed.
10810 */
10811 switch (hw->mac.type) {
10812 case ixgbe_mac_82598EB:
10813 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
10814 break;
10815 default:
10816 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
10817 break;
10818 }
10819
10820 /* don't check link if we failed to enumerate functions */
10821 if (expected_gts > 0)
10822 ixgbe_check_minimum_link(adapter, expected_gts);
10823
10824 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
10825 if (err)
10826 strlcpy(part_str, "Unknown", sizeof(part_str));
10827 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
10828 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
10829 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
10830 part_str);
10831 else
10832 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
10833 hw->mac.type, hw->phy.type, part_str);
10834
10835 e_dev_info("%pM\n", netdev->dev_addr);
10836
10837 /* reset the hardware with the new settings */
10838 err = hw->mac.ops.start_hw(hw);
10839 if (err == IXGBE_ERR_EEPROM_VERSION) {
10840 /* We are running on a pre-production device, log a warning */
10841 e_dev_warn("This device is a pre-production adapter/LOM. "
10842 "Please be aware there may be issues associated "
10843 "with your hardware. If you are experiencing "
10844 "problems please contact your Intel or hardware "
10845 "representative who provided you with this "
10846 "hardware.\n");
10847 }
10848 strcpy(netdev->name, "eth%d");
10849 pci_set_drvdata(pdev, adapter);
10850 err = register_netdev(netdev);
10851 if (err)
10852 goto err_register;
10853
10854
10855 /* power down the optics for 82599 SFP+ fiber */
10856 if (hw->mac.ops.disable_tx_laser)
10857 hw->mac.ops.disable_tx_laser(hw);
10858
10859 /* carrier off reporting is important to ethtool even BEFORE open */
10860 netif_carrier_off(netdev);
10861
10862 #ifdef CONFIG_IXGBE_DCA
10863 if (dca_add_requester(&pdev->dev) == 0) {
10864 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
10865 ixgbe_setup_dca(adapter);
10866 }
10867 #endif
10868 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
10869 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
10870 for (i = 0; i < adapter->num_vfs; i++)
10871 ixgbe_vf_configuration(pdev, (i | 0x10000000));
10872 }
10873
10874 /* firmware requires driver version to be 0xFFFFFFFF
10875 * since os does not support feature
10876 */
10877 if (hw->mac.ops.set_fw_drv_ver)
10878 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF,
10879 sizeof(ixgbe_driver_version) - 1,
10880 ixgbe_driver_version);
10881
10882 /* add san mac addr to netdev */
10883 ixgbe_add_sanmac_netdev(netdev);
10884
10885 e_dev_info("%s\n", ixgbe_default_device_descr);
10886
10887 #ifdef CONFIG_IXGBE_HWMON
10888 if (ixgbe_sysfs_init(adapter))
10889 e_err(probe, "failed to allocate sysfs resources\n");
10890 #endif /* CONFIG_IXGBE_HWMON */
10891
10892 ixgbe_dbg_adapter_init(adapter);
10893
10894 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
10895 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
10896 hw->mac.ops.setup_link(hw,
10897 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
10898 true);
10899
10900 return 0;
10901
10902 err_register:
10903 ixgbe_release_hw_control(adapter);
10904 ixgbe_clear_interrupt_scheme(adapter);
10905 err_sw_init:
10906 ixgbe_disable_sriov(adapter);
10907 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
10908 iounmap(adapter->io_addr);
10909 kfree(adapter->jump_tables[0]);
10910 kfree(adapter->mac_table);
10911 kfree(adapter->rss_key);
10912 err_ioremap:
10913 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
10914 free_netdev(netdev);
10915 err_alloc_etherdev:
10916 pci_release_mem_regions(pdev);
10917 err_pci_reg:
10918 err_dma:
10919 if (!adapter || disable_dev)
10920 pci_disable_device(pdev);
10921 return err;
10922 }
10923
10924 /**
10925 * ixgbe_remove - Device Removal Routine
10926 * @pdev: PCI device information struct
10927 *
10928 * ixgbe_remove is called by the PCI subsystem to alert the driver
10929 * that it should release a PCI device. The could be caused by a
10930 * Hot-Plug event, or because the driver is going to be removed from
10931 * memory.
10932 **/
10933 static void ixgbe_remove(struct pci_dev *pdev)
10934 {
10935 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
10936 struct net_device *netdev;
10937 bool disable_dev;
10938 int i;
10939
10940 /* if !adapter then we already cleaned up in probe */
10941 if (!adapter)
10942 return;
10943
10944 netdev = adapter->netdev;
10945 ixgbe_dbg_adapter_exit(adapter);
10946
10947 set_bit(__IXGBE_REMOVING, &adapter->state);
10948 cancel_work_sync(&adapter->service_task);
10949
10950
10951 #ifdef CONFIG_IXGBE_DCA
10952 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
10953 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
10954 dca_remove_requester(&pdev->dev);
10955 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
10956 IXGBE_DCA_CTRL_DCA_DISABLE);
10957 }
10958
10959 #endif
10960 #ifdef CONFIG_IXGBE_HWMON
10961 ixgbe_sysfs_exit(adapter);
10962 #endif /* CONFIG_IXGBE_HWMON */
10963
10964 /* remove the added san mac */
10965 ixgbe_del_sanmac_netdev(netdev);
10966
10967 #ifdef CONFIG_PCI_IOV
10968 ixgbe_disable_sriov(adapter);
10969 #endif
10970 if (netdev->reg_state == NETREG_REGISTERED)
10971 unregister_netdev(netdev);
10972
10973 ixgbe_stop_ipsec_offload(adapter);
10974 ixgbe_clear_interrupt_scheme(adapter);
10975
10976 ixgbe_release_hw_control(adapter);
10977
10978 #ifdef CONFIG_DCB
10979 kfree(adapter->ixgbe_ieee_pfc);
10980 kfree(adapter->ixgbe_ieee_ets);
10981
10982 #endif
10983 iounmap(adapter->io_addr);
10984 pci_release_mem_regions(pdev);
10985
10986 e_dev_info("complete\n");
10987
10988 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) {
10989 if (adapter->jump_tables[i]) {
10990 kfree(adapter->jump_tables[i]->input);
10991 kfree(adapter->jump_tables[i]->mask);
10992 }
10993 kfree(adapter->jump_tables[i]);
10994 }
10995
10996 kfree(adapter->mac_table);
10997 kfree(adapter->rss_key);
10998 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
10999 free_netdev(netdev);
11000
11001 pci_disable_pcie_error_reporting(pdev);
11002
11003 if (disable_dev)
11004 pci_disable_device(pdev);
11005 }
11006
11007 /**
11008 * ixgbe_io_error_detected - called when PCI error is detected
11009 * @pdev: Pointer to PCI device
11010 * @state: The current pci connection state
11011 *
11012 * This function is called after a PCI bus error affecting
11013 * this device has been detected.
11014 */
11015 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
11016 pci_channel_state_t state)
11017 {
11018 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11019 struct net_device *netdev = adapter->netdev;
11020
11021 #ifdef CONFIG_PCI_IOV
11022 struct ixgbe_hw *hw = &adapter->hw;
11023 struct pci_dev *bdev, *vfdev;
11024 u32 dw0, dw1, dw2, dw3;
11025 int vf, pos;
11026 u16 req_id, pf_func;
11027
11028 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
11029 adapter->num_vfs == 0)
11030 goto skip_bad_vf_detection;
11031
11032 bdev = pdev->bus->self;
11033 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
11034 bdev = bdev->bus->self;
11035
11036 if (!bdev)
11037 goto skip_bad_vf_detection;
11038
11039 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
11040 if (!pos)
11041 goto skip_bad_vf_detection;
11042
11043 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
11044 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
11045 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
11046 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
11047 if (ixgbe_removed(hw->hw_addr))
11048 goto skip_bad_vf_detection;
11049
11050 req_id = dw1 >> 16;
11051 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
11052 if (!(req_id & 0x0080))
11053 goto skip_bad_vf_detection;
11054
11055 pf_func = req_id & 0x01;
11056 if ((pf_func & 1) == (pdev->devfn & 1)) {
11057 unsigned int device_id;
11058
11059 vf = (req_id & 0x7F) >> 1;
11060 e_dev_err("VF %d has caused a PCIe error\n", vf);
11061 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
11062 "%8.8x\tdw3: %8.8x\n",
11063 dw0, dw1, dw2, dw3);
11064 switch (adapter->hw.mac.type) {
11065 case ixgbe_mac_82599EB:
11066 device_id = IXGBE_82599_VF_DEVICE_ID;
11067 break;
11068 case ixgbe_mac_X540:
11069 device_id = IXGBE_X540_VF_DEVICE_ID;
11070 break;
11071 case ixgbe_mac_X550:
11072 device_id = IXGBE_DEV_ID_X550_VF;
11073 break;
11074 case ixgbe_mac_X550EM_x:
11075 device_id = IXGBE_DEV_ID_X550EM_X_VF;
11076 break;
11077 case ixgbe_mac_x550em_a:
11078 device_id = IXGBE_DEV_ID_X550EM_A_VF;
11079 break;
11080 default:
11081 device_id = 0;
11082 break;
11083 }
11084
11085 /* Find the pci device of the offending VF */
11086 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
11087 while (vfdev) {
11088 if (vfdev->devfn == (req_id & 0xFF))
11089 break;
11090 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
11091 device_id, vfdev);
11092 }
11093 /*
11094 * There's a slim chance the VF could have been hot plugged,
11095 * so if it is no longer present we don't need to issue the
11096 * VFLR. Just clean up the AER in that case.
11097 */
11098 if (vfdev) {
11099 pcie_flr(vfdev);
11100 /* Free device reference count */
11101 pci_dev_put(vfdev);
11102 }
11103
11104 pci_cleanup_aer_uncorrect_error_status(pdev);
11105 }
11106
11107 /*
11108 * Even though the error may have occurred on the other port
11109 * we still need to increment the vf error reference count for
11110 * both ports because the I/O resume function will be called
11111 * for both of them.
11112 */
11113 adapter->vferr_refcount++;
11114
11115 return PCI_ERS_RESULT_RECOVERED;
11116
11117 skip_bad_vf_detection:
11118 #endif /* CONFIG_PCI_IOV */
11119 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
11120 return PCI_ERS_RESULT_DISCONNECT;
11121
11122 if (!netif_device_present(netdev))
11123 return PCI_ERS_RESULT_DISCONNECT;
11124
11125 rtnl_lock();
11126 netif_device_detach(netdev);
11127
11128 if (netif_running(netdev))
11129 ixgbe_close_suspend(adapter);
11130
11131 if (state == pci_channel_io_perm_failure) {
11132 rtnl_unlock();
11133 return PCI_ERS_RESULT_DISCONNECT;
11134 }
11135
11136 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
11137 pci_disable_device(pdev);
11138 rtnl_unlock();
11139
11140 /* Request a slot reset. */
11141 return PCI_ERS_RESULT_NEED_RESET;
11142 }
11143
11144 /**
11145 * ixgbe_io_slot_reset - called after the pci bus has been reset.
11146 * @pdev: Pointer to PCI device
11147 *
11148 * Restart the card from scratch, as if from a cold-boot.
11149 */
11150 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
11151 {
11152 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11153 pci_ers_result_t result;
11154 int err;
11155
11156 if (pci_enable_device_mem(pdev)) {
11157 e_err(probe, "Cannot re-enable PCI device after reset.\n");
11158 result = PCI_ERS_RESULT_DISCONNECT;
11159 } else {
11160 smp_mb__before_atomic();
11161 clear_bit(__IXGBE_DISABLED, &adapter->state);
11162 adapter->hw.hw_addr = adapter->io_addr;
11163 pci_set_master(pdev);
11164 pci_restore_state(pdev);
11165 pci_save_state(pdev);
11166
11167 pci_wake_from_d3(pdev, false);
11168
11169 ixgbe_reset(adapter);
11170 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
11171 result = PCI_ERS_RESULT_RECOVERED;
11172 }
11173
11174 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11175 if (err) {
11176 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
11177 "failed 0x%0x\n", err);
11178 /* non-fatal, continue */
11179 }
11180
11181 return result;
11182 }
11183
11184 /**
11185 * ixgbe_io_resume - called when traffic can start flowing again.
11186 * @pdev: Pointer to PCI device
11187 *
11188 * This callback is called when the error recovery driver tells us that
11189 * its OK to resume normal operation.
11190 */
11191 static void ixgbe_io_resume(struct pci_dev *pdev)
11192 {
11193 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11194 struct net_device *netdev = adapter->netdev;
11195
11196 #ifdef CONFIG_PCI_IOV
11197 if (adapter->vferr_refcount) {
11198 e_info(drv, "Resuming after VF err\n");
11199 adapter->vferr_refcount--;
11200 return;
11201 }
11202
11203 #endif
11204 rtnl_lock();
11205 if (netif_running(netdev))
11206 ixgbe_open(netdev);
11207
11208 netif_device_attach(netdev);
11209 rtnl_unlock();
11210 }
11211
11212 static const struct pci_error_handlers ixgbe_err_handler = {
11213 .error_detected = ixgbe_io_error_detected,
11214 .slot_reset = ixgbe_io_slot_reset,
11215 .resume = ixgbe_io_resume,
11216 };
11217
11218 static struct pci_driver ixgbe_driver = {
11219 .name = ixgbe_driver_name,
11220 .id_table = ixgbe_pci_tbl,
11221 .probe = ixgbe_probe,
11222 .remove = ixgbe_remove,
11223 #ifdef CONFIG_PM
11224 .suspend = ixgbe_suspend,
11225 .resume = ixgbe_resume,
11226 #endif
11227 .shutdown = ixgbe_shutdown,
11228 .sriov_configure = ixgbe_pci_sriov_configure,
11229 .err_handler = &ixgbe_err_handler
11230 };
11231
11232 /**
11233 * ixgbe_init_module - Driver Registration Routine
11234 *
11235 * ixgbe_init_module is the first routine called when the driver is
11236 * loaded. All it does is register with the PCI subsystem.
11237 **/
11238 static int __init ixgbe_init_module(void)
11239 {
11240 int ret;
11241 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
11242 pr_info("%s\n", ixgbe_copyright);
11243
11244 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
11245 if (!ixgbe_wq) {
11246 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
11247 return -ENOMEM;
11248 }
11249
11250 ixgbe_dbg_init();
11251
11252 ret = pci_register_driver(&ixgbe_driver);
11253 if (ret) {
11254 destroy_workqueue(ixgbe_wq);
11255 ixgbe_dbg_exit();
11256 return ret;
11257 }
11258
11259 #ifdef CONFIG_IXGBE_DCA
11260 dca_register_notify(&dca_notifier);
11261 #endif
11262
11263 return 0;
11264 }
11265
11266 module_init(ixgbe_init_module);
11267
11268 /**
11269 * ixgbe_exit_module - Driver Exit Cleanup Routine
11270 *
11271 * ixgbe_exit_module is called just before the driver is removed
11272 * from memory.
11273 **/
11274 static void __exit ixgbe_exit_module(void)
11275 {
11276 #ifdef CONFIG_IXGBE_DCA
11277 dca_unregister_notify(&dca_notifier);
11278 #endif
11279 pci_unregister_driver(&ixgbe_driver);
11280
11281 ixgbe_dbg_exit();
11282 if (ixgbe_wq) {
11283 destroy_workqueue(ixgbe_wq);
11284 ixgbe_wq = NULL;
11285 }
11286 }
11287
11288 #ifdef CONFIG_IXGBE_DCA
11289 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
11290 void *p)
11291 {
11292 int ret_val;
11293
11294 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
11295 __ixgbe_notify_dca);
11296
11297 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
11298 }
11299
11300 #endif /* CONFIG_IXGBE_DCA */
11301
11302 module_exit(ixgbe_exit_module);
11303
11304 /* ixgbe_main.c */
Linux with added FPC-III support