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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / marvell / sky2.c
blobd013f30019b69f61617157304974649de6359ae1
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/slab.h>
38 #include <net/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/in.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
47 #include <linux/of_device.h>
48 #include <linux/of_net.h>
49 #include <linux/dmi.h>
50
51 #include <asm/irq.h>
52
53 #include "sky2.h"
54
55 #define DRV_NAME "sky2"
56 #define DRV_VERSION "1.30"
57
58 /*
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
61 * similar to Tigon3.
62 */
63
64 #define RX_LE_SIZE 1024
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68
69 /* This is the worst case number of transmit list elements for a single skb:
70 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
71 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
72 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
73 #define TX_MAX_PENDING 1024
74 #define TX_DEF_PENDING 63
75
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
79
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
81
82 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = -1;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static int legacy_pme = 0;
102 module_param(legacy_pme, int, 0);
103 MODULE_PARM_DESC(legacy_pme, "Legacy power management");
104
105 static const struct pci_device_id sky2_id_table[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
108 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
112 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
145 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
146 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
147 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
148 { 0 }
149 };
150
151 MODULE_DEVICE_TABLE(pci, sky2_id_table);
152
153 /* Avoid conditionals by using array */
154 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
155 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
156 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
157
158 static void sky2_set_multicast(struct net_device *dev);
159 static irqreturn_t sky2_intr(int irq, void *dev_id);
160
161 /* Access to PHY via serial interconnect */
162 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
163 {
164 int i;
165
166 gma_write16(hw, port, GM_SMI_DATA, val);
167 gma_write16(hw, port, GM_SMI_CTRL,
168 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
169
170 for (i = 0; i < PHY_RETRIES; i++) {
171 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
172 if (ctrl == 0xffff)
173 goto io_error;
174
175 if (!(ctrl & GM_SMI_CT_BUSY))
176 return 0;
177
178 udelay(10);
179 }
180
181 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
182 return -ETIMEDOUT;
183
184 io_error:
185 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
186 return -EIO;
187 }
188
189 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
190 {
191 int i;
192
193 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
194 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
195
196 for (i = 0; i < PHY_RETRIES; i++) {
197 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
198 if (ctrl == 0xffff)
199 goto io_error;
200
201 if (ctrl & GM_SMI_CT_RD_VAL) {
202 *val = gma_read16(hw, port, GM_SMI_DATA);
203 return 0;
204 }
205
206 udelay(10);
207 }
208
209 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
210 return -ETIMEDOUT;
211 io_error:
212 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
213 return -EIO;
214 }
215
216 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
217 {
218 u16 v;
219 __gm_phy_read(hw, port, reg, &v);
220 return v;
221 }
222
223
224 static void sky2_power_on(struct sky2_hw *hw)
225 {
226 /* switch power to VCC (WA for VAUX problem) */
227 sky2_write8(hw, B0_POWER_CTRL,
228 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
229
230 /* disable Core Clock Division, */
231 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
232
233 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239 else
240 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
241
242 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
243 u32 reg;
244
245 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
246
247 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
248 /* set all bits to 0 except bits 15..12 and 8 */
249 reg &= P_ASPM_CONTROL_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
251
252 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
253 /* set all bits to 0 except bits 28 & 27 */
254 reg &= P_CTL_TIM_VMAIN_AV_MSK;
255 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
256
257 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
258
259 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
260
261 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
262 reg = sky2_read32(hw, B2_GP_IO);
263 reg |= GLB_GPIO_STAT_RACE_DIS;
264 sky2_write32(hw, B2_GP_IO, reg);
265
266 sky2_read32(hw, B2_GP_IO);
267 }
268
269 /* Turn on "driver loaded" LED */
270 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
271 }
272
273 static void sky2_power_aux(struct sky2_hw *hw)
274 {
275 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
276 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
277 else
278 /* enable bits are inverted */
279 sky2_write8(hw, B2_Y2_CLK_GATE,
280 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
281 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
282 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
283
284 /* switch power to VAUX if supported and PME from D3cold */
285 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
286 pci_pme_capable(hw->pdev, PCI_D3cold))
287 sky2_write8(hw, B0_POWER_CTRL,
288 (PC_VAUX_ENA | PC_VCC_ENA |
289 PC_VAUX_ON | PC_VCC_OFF));
290
291 /* turn off "driver loaded LED" */
292 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
293 }
294
295 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
296 {
297 u16 reg;
298
299 /* disable all GMAC IRQ's */
300 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
301
302 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
303 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
304 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
305 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
306
307 reg = gma_read16(hw, port, GM_RX_CTRL);
308 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
309 gma_write16(hw, port, GM_RX_CTRL, reg);
310 }
311
312 /* flow control to advertise bits */
313 static const u16 copper_fc_adv[] = {
314 [FC_NONE] = 0,
315 [FC_TX] = PHY_M_AN_ASP,
316 [FC_RX] = PHY_M_AN_PC,
317 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
318 };
319
320 /* flow control to advertise bits when using 1000BaseX */
321 static const u16 fiber_fc_adv[] = {
322 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
323 [FC_TX] = PHY_M_P_ASYM_MD_X,
324 [FC_RX] = PHY_M_P_SYM_MD_X,
325 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
326 };
327
328 /* flow control to GMA disable bits */
329 static const u16 gm_fc_disable[] = {
330 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
331 [FC_TX] = GM_GPCR_FC_RX_DIS,
332 [FC_RX] = GM_GPCR_FC_TX_DIS,
333 [FC_BOTH] = 0,
334 };
335
336
337 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
338 {
339 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
340 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
341
342 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
343 !(hw->flags & SKY2_HW_NEWER_PHY)) {
344 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
345
346 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
347 PHY_M_EC_MAC_S_MSK);
348 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
349
350 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
351 if (hw->chip_id == CHIP_ID_YUKON_EC)
352 /* set downshift counter to 3x and enable downshift */
353 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
354 else
355 /* set master & slave downshift counter to 1x */
356 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
357
358 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
359 }
360
361 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
362 if (sky2_is_copper(hw)) {
363 if (!(hw->flags & SKY2_HW_GIGABIT)) {
364 /* enable automatic crossover */
365 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
366
367 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
368 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
369 u16 spec;
370
371 /* Enable Class A driver for FE+ A0 */
372 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
373 spec |= PHY_M_FESC_SEL_CL_A;
374 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
375 }
376 } else {
377 /* disable energy detect */
378 ctrl &= ~PHY_M_PC_EN_DET_MSK;
379
380 /* enable automatic crossover */
381 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
382
383 /* downshift on PHY 88E1112 and 88E1149 is changed */
384 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
385 (hw->flags & SKY2_HW_NEWER_PHY)) {
386 /* set downshift counter to 3x and enable downshift */
387 ctrl &= ~PHY_M_PC_DSC_MSK;
388 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
389 }
390 }
391 } else {
392 /* workaround for deviation #4.88 (CRC errors) */
393 /* disable Automatic Crossover */
394
395 ctrl &= ~PHY_M_PC_MDIX_MSK;
396 }
397
398 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
399
400 /* special setup for PHY 88E1112 Fiber */
401 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
402 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
403
404 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
406 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
407 ctrl &= ~PHY_M_MAC_MD_MSK;
408 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
410
411 if (hw->pmd_type == 'P') {
412 /* select page 1 to access Fiber registers */
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
414
415 /* for SFP-module set SIGDET polarity to low */
416 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
417 ctrl |= PHY_M_FIB_SIGD_POL;
418 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
419 }
420
421 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
422 }
423
424 ctrl = PHY_CT_RESET;
425 ct1000 = 0;
426 adv = PHY_AN_CSMA;
427 reg = 0;
428
429 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
430 if (sky2_is_copper(hw)) {
431 if (sky2->advertising & ADVERTISED_1000baseT_Full)
432 ct1000 |= PHY_M_1000C_AFD;
433 if (sky2->advertising & ADVERTISED_1000baseT_Half)
434 ct1000 |= PHY_M_1000C_AHD;
435 if (sky2->advertising & ADVERTISED_100baseT_Full)
436 adv |= PHY_M_AN_100_FD;
437 if (sky2->advertising & ADVERTISED_100baseT_Half)
438 adv |= PHY_M_AN_100_HD;
439 if (sky2->advertising & ADVERTISED_10baseT_Full)
440 adv |= PHY_M_AN_10_FD;
441 if (sky2->advertising & ADVERTISED_10baseT_Half)
442 adv |= PHY_M_AN_10_HD;
443
444 } else { /* special defines for FIBER (88E1040S only) */
445 if (sky2->advertising & ADVERTISED_1000baseT_Full)
446 adv |= PHY_M_AN_1000X_AFD;
447 if (sky2->advertising & ADVERTISED_1000baseT_Half)
448 adv |= PHY_M_AN_1000X_AHD;
449 }
450
451 /* Restart Auto-negotiation */
452 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
453 } else {
454 /* forced speed/duplex settings */
455 ct1000 = PHY_M_1000C_MSE;
456
457 /* Disable auto update for duplex flow control and duplex */
458 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
459
460 switch (sky2->speed) {
461 case SPEED_1000:
462 ctrl |= PHY_CT_SP1000;
463 reg |= GM_GPCR_SPEED_1000;
464 break;
465 case SPEED_100:
466 ctrl |= PHY_CT_SP100;
467 reg |= GM_GPCR_SPEED_100;
468 break;
469 }
470
471 if (sky2->duplex == DUPLEX_FULL) {
472 reg |= GM_GPCR_DUP_FULL;
473 ctrl |= PHY_CT_DUP_MD;
474 } else if (sky2->speed < SPEED_1000)
475 sky2->flow_mode = FC_NONE;
476 }
477
478 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
479 if (sky2_is_copper(hw))
480 adv |= copper_fc_adv[sky2->flow_mode];
481 else
482 adv |= fiber_fc_adv[sky2->flow_mode];
483 } else {
484 reg |= GM_GPCR_AU_FCT_DIS;
485 reg |= gm_fc_disable[sky2->flow_mode];
486
487 /* Forward pause packets to GMAC? */
488 if (sky2->flow_mode & FC_RX)
489 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
490 else
491 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
492 }
493
494 gma_write16(hw, port, GM_GP_CTRL, reg);
495
496 if (hw->flags & SKY2_HW_GIGABIT)
497 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
498
499 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
500 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
501
502 /* Setup Phy LED's */
503 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
504 ledover = 0;
505
506 switch (hw->chip_id) {
507 case CHIP_ID_YUKON_FE:
508 /* on 88E3082 these bits are at 11..9 (shifted left) */
509 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
510
511 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
512
513 /* delete ACT LED control bits */
514 ctrl &= ~PHY_M_FELP_LED1_MSK;
515 /* change ACT LED control to blink mode */
516 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
517 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
518 break;
519
520 case CHIP_ID_YUKON_FE_P:
521 /* Enable Link Partner Next Page */
522 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
523 ctrl |= PHY_M_PC_ENA_LIP_NP;
524
525 /* disable Energy Detect and enable scrambler */
526 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
527 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
528
529 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
530 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
531 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
532 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
533
534 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
535 break;
536
537 case CHIP_ID_YUKON_XL:
538 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
539
540 /* select page 3 to access LED control register */
541 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
542
543 /* set LED Function Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
545 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
546 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
547 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
548 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
549
550 /* set Polarity Control register */
551 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
552 (PHY_M_POLC_LS1_P_MIX(4) |
553 PHY_M_POLC_IS0_P_MIX(4) |
554 PHY_M_POLC_LOS_CTRL(2) |
555 PHY_M_POLC_INIT_CTRL(2) |
556 PHY_M_POLC_STA1_CTRL(2) |
557 PHY_M_POLC_STA0_CTRL(2)));
558
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
562
563 case CHIP_ID_YUKON_EC_U:
564 case CHIP_ID_YUKON_EX:
565 case CHIP_ID_YUKON_SUPR:
566 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
567
568 /* select page 3 to access LED control register */
569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
570
571 /* set LED Function Control register */
572 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
573 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
574 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
575 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
576 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
577
578 /* set Blink Rate in LED Timer Control Register */
579 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
580 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
581 /* restore page register */
582 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
583 break;
584
585 default:
586 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
587 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
588
589 /* turn off the Rx LED (LED_RX) */
590 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
591 }
592
593 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
594 /* apply fixes in PHY AFE */
595 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
596
597 /* increase differential signal amplitude in 10BASE-T */
598 gm_phy_write(hw, port, 0x18, 0xaa99);
599 gm_phy_write(hw, port, 0x17, 0x2011);
600
601 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
602 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
603 gm_phy_write(hw, port, 0x18, 0xa204);
604 gm_phy_write(hw, port, 0x17, 0x2002);
605 }
606
607 /* set page register to 0 */
608 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
609 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
610 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
611 /* apply workaround for integrated resistors calibration */
612 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
613 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
614 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
615 /* apply fixes in PHY AFE */
616 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
617
618 /* apply RDAC termination workaround */
619 gm_phy_write(hw, port, 24, 0x2800);
620 gm_phy_write(hw, port, 23, 0x2001);
621
622 /* set page register back to 0 */
623 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
624 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
625 hw->chip_id < CHIP_ID_YUKON_SUPR) {
626 /* no effect on Yukon-XL */
627 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
628
629 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
630 sky2->speed == SPEED_100) {
631 /* turn on 100 Mbps LED (LED_LINK100) */
632 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
633 }
634
635 if (ledover)
636 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
637
638 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
639 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
640 int i;
641 /* This a phy register setup workaround copied from vendor driver. */
642 static const struct {
643 u16 reg, val;
644 } eee_afe[] = {
645 { 0x156, 0x58ce },
646 { 0x153, 0x99eb },
647 { 0x141, 0x8064 },
648 /* { 0x155, 0x130b },*/
649 { 0x000, 0x0000 },
650 { 0x151, 0x8433 },
651 { 0x14b, 0x8c44 },
652 { 0x14c, 0x0f90 },
653 { 0x14f, 0x39aa },
654 /* { 0x154, 0x2f39 },*/
655 { 0x14d, 0xba33 },
656 { 0x144, 0x0048 },
657 { 0x152, 0x2010 },
658 /* { 0x158, 0x1223 },*/
659 { 0x140, 0x4444 },
660 { 0x154, 0x2f3b },
661 { 0x158, 0xb203 },
662 { 0x157, 0x2029 },
663 };
664
665 /* Start Workaround for OptimaEEE Rev.Z0 */
666 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
667
668 gm_phy_write(hw, port, 1, 0x4099);
669 gm_phy_write(hw, port, 3, 0x1120);
670 gm_phy_write(hw, port, 11, 0x113c);
671 gm_phy_write(hw, port, 14, 0x8100);
672 gm_phy_write(hw, port, 15, 0x112a);
673 gm_phy_write(hw, port, 17, 0x1008);
674
675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
676 gm_phy_write(hw, port, 1, 0x20b0);
677
678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
679
680 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
681 /* apply AFE settings */
682 gm_phy_write(hw, port, 17, eee_afe[i].val);
683 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
684 }
685
686 /* End Workaround for OptimaEEE */
687 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
688
689 /* Enable 10Base-Te (EEE) */
690 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
691 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
692 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
693 reg | PHY_M_10B_TE_ENABLE);
694 }
695 }
696
697 /* Enable phy interrupt on auto-negotiation complete (or link up) */
698 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
699 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
700 else
701 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
702 }
703
704 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
705 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
706
707 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
708 {
709 u32 reg1;
710
711 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
712 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
713 reg1 &= ~phy_power[port];
714
715 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
716 reg1 |= coma_mode[port];
717
718 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
719 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
720 sky2_pci_read32(hw, PCI_DEV_REG1);
721
722 if (hw->chip_id == CHIP_ID_YUKON_FE)
723 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
724 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
725 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
726 }
727
728 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
729 {
730 u32 reg1;
731 u16 ctrl;
732
733 /* release GPHY Control reset */
734 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
735
736 /* release GMAC reset */
737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
738
739 if (hw->flags & SKY2_HW_NEWER_PHY) {
740 /* select page 2 to access MAC control register */
741 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
742
743 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
744 /* allow GMII Power Down */
745 ctrl &= ~PHY_M_MAC_GMIF_PUP;
746 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
747
748 /* set page register back to 0 */
749 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
750 }
751
752 /* setup General Purpose Control Register */
753 gma_write16(hw, port, GM_GP_CTRL,
754 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
755 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
756 GM_GPCR_AU_SPD_DIS);
757
758 if (hw->chip_id != CHIP_ID_YUKON_EC) {
759 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
760 /* select page 2 to access MAC control register */
761 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
762
763 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
764 /* enable Power Down */
765 ctrl |= PHY_M_PC_POW_D_ENA;
766 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
767
768 /* set page register back to 0 */
769 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
770 }
771
772 /* set IEEE compatible Power Down Mode (dev. #4.99) */
773 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
774 }
775
776 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
777 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
778 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
779 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
780 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
781 }
782
783 /* configure IPG according to used link speed */
784 static void sky2_set_ipg(struct sky2_port *sky2)
785 {
786 u16 reg;
787
788 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
789 reg &= ~GM_SMOD_IPG_MSK;
790 if (sky2->speed > SPEED_100)
791 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
792 else
793 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
794 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
795 }
796
797 /* Enable Rx/Tx */
798 static void sky2_enable_rx_tx(struct sky2_port *sky2)
799 {
800 struct sky2_hw *hw = sky2->hw;
801 unsigned port = sky2->port;
802 u16 reg;
803
804 reg = gma_read16(hw, port, GM_GP_CTRL);
805 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
806 gma_write16(hw, port, GM_GP_CTRL, reg);
807 }
808
809 /* Force a renegotiation */
810 static void sky2_phy_reinit(struct sky2_port *sky2)
811 {
812 spin_lock_bh(&sky2->phy_lock);
813 sky2_phy_init(sky2->hw, sky2->port);
814 sky2_enable_rx_tx(sky2);
815 spin_unlock_bh(&sky2->phy_lock);
816 }
817
818 /* Put device in state to listen for Wake On Lan */
819 static void sky2_wol_init(struct sky2_port *sky2)
820 {
821 struct sky2_hw *hw = sky2->hw;
822 unsigned port = sky2->port;
823 enum flow_control save_mode;
824 u16 ctrl;
825
826 /* Bring hardware out of reset */
827 sky2_write16(hw, B0_CTST, CS_RST_CLR);
828 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
829
830 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
831 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
832
833 /* Force to 10/100
834 * sky2_reset will re-enable on resume
835 */
836 save_mode = sky2->flow_mode;
837 ctrl = sky2->advertising;
838
839 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
840 sky2->flow_mode = FC_NONE;
841
842 spin_lock_bh(&sky2->phy_lock);
843 sky2_phy_power_up(hw, port);
844 sky2_phy_init(hw, port);
845 spin_unlock_bh(&sky2->phy_lock);
846
847 sky2->flow_mode = save_mode;
848 sky2->advertising = ctrl;
849
850 /* Set GMAC to no flow control and auto update for speed/duplex */
851 gma_write16(hw, port, GM_GP_CTRL,
852 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
853 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
854
855 /* Set WOL address */
856 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
857 sky2->netdev->dev_addr, ETH_ALEN);
858
859 /* Turn on appropriate WOL control bits */
860 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
861 ctrl = 0;
862 if (sky2->wol & WAKE_PHY)
863 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
864 else
865 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
866
867 if (sky2->wol & WAKE_MAGIC)
868 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
869 else
870 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
871
872 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
873 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
874
875 /* Disable PiG firmware */
876 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
877
878 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
879 if (legacy_pme) {
880 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
881 reg1 |= PCI_Y2_PME_LEGACY;
882 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
883 }
884
885 /* block receiver */
886 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
887 sky2_read32(hw, B0_CTST);
888 }
889
890 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
891 {
892 struct net_device *dev = hw->dev[port];
893
894 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
895 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
896 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
897 /* Yukon-Extreme B0 and further Extreme devices */
898 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
899 } else if (dev->mtu > ETH_DATA_LEN) {
900 /* set Tx GMAC FIFO Almost Empty Threshold */
901 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
902 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
903
904 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
905 } else
906 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
907 }
908
909 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
910 {
911 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
912 u16 reg;
913 u32 rx_reg;
914 int i;
915 const u8 *addr = hw->dev[port]->dev_addr;
916
917 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
918 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
919
920 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
921
922 if (hw->chip_id == CHIP_ID_YUKON_XL &&
923 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
924 port == 1) {
925 /* WA DEV_472 -- looks like crossed wires on port 2 */
926 /* clear GMAC 1 Control reset */
927 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
928 do {
929 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
930 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
931 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
932 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
933 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
934 }
935
936 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
937
938 /* Enable Transmit FIFO Underrun */
939 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
940
941 spin_lock_bh(&sky2->phy_lock);
942 sky2_phy_power_up(hw, port);
943 sky2_phy_init(hw, port);
944 spin_unlock_bh(&sky2->phy_lock);
945
946 /* MIB clear */
947 reg = gma_read16(hw, port, GM_PHY_ADDR);
948 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
949
950 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
951 gma_read16(hw, port, i);
952 gma_write16(hw, port, GM_PHY_ADDR, reg);
953
954 /* transmit control */
955 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
956
957 /* receive control reg: unicast + multicast + no FCS */
958 gma_write16(hw, port, GM_RX_CTRL,
959 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
960
961 /* transmit flow control */
962 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
963
964 /* transmit parameter */
965 gma_write16(hw, port, GM_TX_PARAM,
966 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
967 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
968 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
969 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
970
971 /* serial mode register */
972 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
973 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
974
975 if (hw->dev[port]->mtu > ETH_DATA_LEN)
976 reg |= GM_SMOD_JUMBO_ENA;
977
978 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
979 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
980 reg |= GM_NEW_FLOW_CTRL;
981
982 gma_write16(hw, port, GM_SERIAL_MODE, reg);
983
984 /* virtual address for data */
985 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
986
987 /* physical address: used for pause frames */
988 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
989
990 /* ignore counter overflows */
991 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
992 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
993 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
994
995 /* Configure Rx MAC FIFO */
996 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
997 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
998 if (hw->chip_id == CHIP_ID_YUKON_EX ||
999 hw->chip_id == CHIP_ID_YUKON_FE_P)
1000 rx_reg |= GMF_RX_OVER_ON;
1001
1002 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
1003
1004 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1005 /* Hardware errata - clear flush mask */
1006 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
1007 } else {
1008 /* Flush Rx MAC FIFO on any flow control or error */
1009 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
1010 }
1011
1012 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
1013 reg = RX_GMF_FL_THR_DEF + 1;
1014 /* Another magic mystery workaround from sk98lin */
1015 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1016 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1017 reg = 0x178;
1018 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1019
1020 /* Configure Tx MAC FIFO */
1021 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1022 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1023
1024 /* On chips without ram buffer, pause is controlled by MAC level */
1025 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1026 /* Pause threshold is scaled by 8 in bytes */
1027 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1028 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1029 reg = 1568 / 8;
1030 else
1031 reg = 1024 / 8;
1032 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1033 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1034
1035 sky2_set_tx_stfwd(hw, port);
1036 }
1037
1038 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1039 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1040 /* disable dynamic watermark */
1041 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1042 reg &= ~TX_DYN_WM_ENA;
1043 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1044 }
1045 }
1046
1047 /* Assign Ram Buffer allocation to queue */
1048 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1049 {
1050 u32 end;
1051
1052 /* convert from K bytes to qwords used for hw register */
1053 start *= 1024/8;
1054 space *= 1024/8;
1055 end = start + space - 1;
1056
1057 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1058 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1059 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1060 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1061 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1062
1063 if (q == Q_R1 || q == Q_R2) {
1064 u32 tp = space - space/4;
1065
1066 /* On receive queue's set the thresholds
1067 * give receiver priority when > 3/4 full
1068 * send pause when down to 2K
1069 */
1070 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1071 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1072
1073 tp = space - 8192/8;
1074 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1075 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1076 } else {
1077 /* Enable store & forward on Tx queue's because
1078 * Tx FIFO is only 1K on Yukon
1079 */
1080 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1081 }
1082
1083 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1084 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1085 }
1086
1087 /* Setup Bus Memory Interface */
1088 static void sky2_qset(struct sky2_hw *hw, u16 q)
1089 {
1090 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1091 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1092 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1093 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1094 }
1095
1096 /* Setup prefetch unit registers. This is the interface between
1097 * hardware and driver list elements
1098 */
1099 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1100 dma_addr_t addr, u32 last)
1101 {
1102 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1103 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1104 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1105 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1106 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1107 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1108
1109 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1110 }
1111
1112 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1113 {
1114 struct sky2_tx_le *le = sky2->tx_le + *slot;
1115
1116 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1117 le->ctrl = 0;
1118 return le;
1119 }
1120
1121 static void tx_init(struct sky2_port *sky2)
1122 {
1123 struct sky2_tx_le *le;
1124
1125 sky2->tx_prod = sky2->tx_cons = 0;
1126 sky2->tx_tcpsum = 0;
1127 sky2->tx_last_mss = 0;
1128 netdev_reset_queue(sky2->netdev);
1129
1130 le = get_tx_le(sky2, &sky2->tx_prod);
1131 le->addr = 0;
1132 le->opcode = OP_ADDR64 | HW_OWNER;
1133 sky2->tx_last_upper = 0;
1134 }
1135
1136 /* Update chip's next pointer */
1137 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1138 {
1139 /* Make sure write' to descriptors are complete before we tell hardware */
1140 wmb();
1141 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1142
1143 /* Synchronize I/O on since next processor may write to tail */
1144 mmiowb();
1145 }
1146
1147
1148 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1149 {
1150 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1151 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1152 le->ctrl = 0;
1153 return le;
1154 }
1155
1156 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1157 {
1158 unsigned size;
1159
1160 /* Space needed for frame data + headers rounded up */
1161 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1162
1163 /* Stopping point for hardware truncation */
1164 return (size - 8) / sizeof(u32);
1165 }
1166
1167 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1168 {
1169 struct rx_ring_info *re;
1170 unsigned size;
1171
1172 /* Space needed for frame data + headers rounded up */
1173 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1174
1175 sky2->rx_nfrags = size >> PAGE_SHIFT;
1176 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1177
1178 /* Compute residue after pages */
1179 size -= sky2->rx_nfrags << PAGE_SHIFT;
1180
1181 /* Optimize to handle small packets and headers */
1182 if (size < copybreak)
1183 size = copybreak;
1184 if (size < ETH_HLEN)
1185 size = ETH_HLEN;
1186
1187 return size;
1188 }
1189
1190 /* Build description to hardware for one receive segment */
1191 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1192 dma_addr_t map, unsigned len)
1193 {
1194 struct sky2_rx_le *le;
1195
1196 if (sizeof(dma_addr_t) > sizeof(u32)) {
1197 le = sky2_next_rx(sky2);
1198 le->addr = cpu_to_le32(upper_32_bits(map));
1199 le->opcode = OP_ADDR64 | HW_OWNER;
1200 }
1201
1202 le = sky2_next_rx(sky2);
1203 le->addr = cpu_to_le32(lower_32_bits(map));
1204 le->length = cpu_to_le16(len);
1205 le->opcode = op | HW_OWNER;
1206 }
1207
1208 /* Build description to hardware for one possibly fragmented skb */
1209 static void sky2_rx_submit(struct sky2_port *sky2,
1210 const struct rx_ring_info *re)
1211 {
1212 int i;
1213
1214 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1215
1216 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1217 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1218 }
1219
1220
1221 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1222 unsigned size)
1223 {
1224 struct sk_buff *skb = re->skb;
1225 int i;
1226
1227 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1228 if (pci_dma_mapping_error(pdev, re->data_addr))
1229 goto mapping_error;
1230
1231 dma_unmap_len_set(re, data_size, size);
1232
1233 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1234 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1235
1236 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1237 skb_frag_size(frag),
1238 DMA_FROM_DEVICE);
1239
1240 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
1241 goto map_page_error;
1242 }
1243 return 0;
1244
1245 map_page_error:
1246 while (--i >= 0) {
1247 pci_unmap_page(pdev, re->frag_addr[i],
1248 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1249 PCI_DMA_FROMDEVICE);
1250 }
1251
1252 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1253 PCI_DMA_FROMDEVICE);
1254
1255 mapping_error:
1256 if (net_ratelimit())
1257 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1258 skb->dev->name);
1259 return -EIO;
1260 }
1261
1262 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1263 {
1264 struct sk_buff *skb = re->skb;
1265 int i;
1266
1267 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1268 PCI_DMA_FROMDEVICE);
1269
1270 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1271 pci_unmap_page(pdev, re->frag_addr[i],
1272 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1273 PCI_DMA_FROMDEVICE);
1274 }
1275
1276 /* Tell chip where to start receive checksum.
1277 * Actually has two checksums, but set both same to avoid possible byte
1278 * order problems.
1279 */
1280 static void rx_set_checksum(struct sky2_port *sky2)
1281 {
1282 struct sky2_rx_le *le = sky2_next_rx(sky2);
1283
1284 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1285 le->ctrl = 0;
1286 le->opcode = OP_TCPSTART | HW_OWNER;
1287
1288 sky2_write32(sky2->hw,
1289 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1290 (sky2->netdev->features & NETIF_F_RXCSUM)
1291 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1292 }
1293
1294 /* Enable/disable receive hash calculation (RSS) */
1295 static void rx_set_rss(struct net_device *dev, netdev_features_t features)
1296 {
1297 struct sky2_port *sky2 = netdev_priv(dev);
1298 struct sky2_hw *hw = sky2->hw;
1299 int i, nkeys = 4;
1300
1301 /* Supports IPv6 and other modes */
1302 if (hw->flags & SKY2_HW_NEW_LE) {
1303 nkeys = 10;
1304 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1305 }
1306
1307 /* Program RSS initial values */
1308 if (features & NETIF_F_RXHASH) {
1309 u32 rss_key[10];
1310
1311 netdev_rss_key_fill(rss_key, sizeof(rss_key));
1312 for (i = 0; i < nkeys; i++)
1313 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1314 rss_key[i]);
1315
1316 /* Need to turn on (undocumented) flag to make hashing work */
1317 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1318 RX_STFW_ENA);
1319
1320 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1321 BMU_ENA_RX_RSS_HASH);
1322 } else
1323 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1324 BMU_DIS_RX_RSS_HASH);
1325 }
1326
1327 /*
1328 * The RX Stop command will not work for Yukon-2 if the BMU does not
1329 * reach the end of packet and since we can't make sure that we have
1330 * incoming data, we must reset the BMU while it is not doing a DMA
1331 * transfer. Since it is possible that the RX path is still active,
1332 * the RX RAM buffer will be stopped first, so any possible incoming
1333 * data will not trigger a DMA. After the RAM buffer is stopped, the
1334 * BMU is polled until any DMA in progress is ended and only then it
1335 * will be reset.
1336 */
1337 static void sky2_rx_stop(struct sky2_port *sky2)
1338 {
1339 struct sky2_hw *hw = sky2->hw;
1340 unsigned rxq = rxqaddr[sky2->port];
1341 int i;
1342
1343 /* disable the RAM Buffer receive queue */
1344 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1345
1346 for (i = 0; i < 0xffff; i++)
1347 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1348 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1349 goto stopped;
1350
1351 netdev_warn(sky2->netdev, "receiver stop failed\n");
1352 stopped:
1353 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1354
1355 /* reset the Rx prefetch unit */
1356 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1357 mmiowb();
1358 }
1359
1360 /* Clean out receive buffer area, assumes receiver hardware stopped */
1361 static void sky2_rx_clean(struct sky2_port *sky2)
1362 {
1363 unsigned i;
1364
1365 if (sky2->rx_le)
1366 memset(sky2->rx_le, 0, RX_LE_BYTES);
1367
1368 for (i = 0; i < sky2->rx_pending; i++) {
1369 struct rx_ring_info *re = sky2->rx_ring + i;
1370
1371 if (re->skb) {
1372 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1373 kfree_skb(re->skb);
1374 re->skb = NULL;
1375 }
1376 }
1377 }
1378
1379 /* Basic MII support */
1380 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1381 {
1382 struct mii_ioctl_data *data = if_mii(ifr);
1383 struct sky2_port *sky2 = netdev_priv(dev);
1384 struct sky2_hw *hw = sky2->hw;
1385 int err = -EOPNOTSUPP;
1386
1387 if (!netif_running(dev))
1388 return -ENODEV; /* Phy still in reset */
1389
1390 switch (cmd) {
1391 case SIOCGMIIPHY:
1392 data->phy_id = PHY_ADDR_MARV;
1393
1394 /* fallthru */
1395 case SIOCGMIIREG: {
1396 u16 val = 0;
1397
1398 spin_lock_bh(&sky2->phy_lock);
1399 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1400 spin_unlock_bh(&sky2->phy_lock);
1401
1402 data->val_out = val;
1403 break;
1404 }
1405
1406 case SIOCSMIIREG:
1407 spin_lock_bh(&sky2->phy_lock);
1408 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1409 data->val_in);
1410 spin_unlock_bh(&sky2->phy_lock);
1411 break;
1412 }
1413 return err;
1414 }
1415
1416 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1417
1418 static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
1419 {
1420 struct sky2_port *sky2 = netdev_priv(dev);
1421 struct sky2_hw *hw = sky2->hw;
1422 u16 port = sky2->port;
1423
1424 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1425 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1426 RX_VLAN_STRIP_ON);
1427 else
1428 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1429 RX_VLAN_STRIP_OFF);
1430
1431 if (features & NETIF_F_HW_VLAN_CTAG_TX) {
1432 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1433 TX_VLAN_TAG_ON);
1434
1435 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1436 } else {
1437 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1438 TX_VLAN_TAG_OFF);
1439
1440 /* Can't do transmit offload of vlan without hw vlan */
1441 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1442 }
1443 }
1444
1445 /* Amount of required worst case padding in rx buffer */
1446 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1447 {
1448 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1449 }
1450
1451 /*
1452 * Allocate an skb for receiving. If the MTU is large enough
1453 * make the skb non-linear with a fragment list of pages.
1454 */
1455 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1456 {
1457 struct sk_buff *skb;
1458 int i;
1459
1460 skb = __netdev_alloc_skb(sky2->netdev,
1461 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1462 gfp);
1463 if (!skb)
1464 goto nomem;
1465
1466 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1467 unsigned char *start;
1468 /*
1469 * Workaround for a bug in FIFO that cause hang
1470 * if the FIFO if the receive buffer is not 64 byte aligned.
1471 * The buffer returned from netdev_alloc_skb is
1472 * aligned except if slab debugging is enabled.
1473 */
1474 start = PTR_ALIGN(skb->data, 8);
1475 skb_reserve(skb, start - skb->data);
1476 } else
1477 skb_reserve(skb, NET_IP_ALIGN);
1478
1479 for (i = 0; i < sky2->rx_nfrags; i++) {
1480 struct page *page = alloc_page(gfp);
1481
1482 if (!page)
1483 goto free_partial;
1484 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1485 }
1486
1487 return skb;
1488 free_partial:
1489 kfree_skb(skb);
1490 nomem:
1491 return NULL;
1492 }
1493
1494 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1495 {
1496 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1497 }
1498
1499 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1500 {
1501 struct sky2_hw *hw = sky2->hw;
1502 unsigned i;
1503
1504 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1505
1506 /* Fill Rx ring */
1507 for (i = 0; i < sky2->rx_pending; i++) {
1508 struct rx_ring_info *re = sky2->rx_ring + i;
1509
1510 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1511 if (!re->skb)
1512 return -ENOMEM;
1513
1514 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1515 dev_kfree_skb(re->skb);
1516 re->skb = NULL;
1517 return -ENOMEM;
1518 }
1519 }
1520 return 0;
1521 }
1522
1523 /*
1524 * Setup receiver buffer pool.
1525 * Normal case this ends up creating one list element for skb
1526 * in the receive ring. Worst case if using large MTU and each
1527 * allocation falls on a different 64 bit region, that results
1528 * in 6 list elements per ring entry.
1529 * One element is used for checksum enable/disable, and one
1530 * extra to avoid wrap.
1531 */
1532 static void sky2_rx_start(struct sky2_port *sky2)
1533 {
1534 struct sky2_hw *hw = sky2->hw;
1535 struct rx_ring_info *re;
1536 unsigned rxq = rxqaddr[sky2->port];
1537 unsigned i, thresh;
1538
1539 sky2->rx_put = sky2->rx_next = 0;
1540 sky2_qset(hw, rxq);
1541
1542 /* On PCI express lowering the watermark gives better performance */
1543 if (pci_is_pcie(hw->pdev))
1544 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1545
1546 /* These chips have no ram buffer?
1547 * MAC Rx RAM Read is controlled by hardware */
1548 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1549 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1550 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1551
1552 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1553
1554 if (!(hw->flags & SKY2_HW_NEW_LE))
1555 rx_set_checksum(sky2);
1556
1557 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1558 rx_set_rss(sky2->netdev, sky2->netdev->features);
1559
1560 /* submit Rx ring */
1561 for (i = 0; i < sky2->rx_pending; i++) {
1562 re = sky2->rx_ring + i;
1563 sky2_rx_submit(sky2, re);
1564 }
1565
1566 /*
1567 * The receiver hangs if it receives frames larger than the
1568 * packet buffer. As a workaround, truncate oversize frames, but
1569 * the register is limited to 9 bits, so if you do frames > 2052
1570 * you better get the MTU right!
1571 */
1572 thresh = sky2_get_rx_threshold(sky2);
1573 if (thresh > 0x1ff)
1574 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1575 else {
1576 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1577 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1578 }
1579
1580 /* Tell chip about available buffers */
1581 sky2_rx_update(sky2, rxq);
1582
1583 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1584 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1585 /*
1586 * Disable flushing of non ASF packets;
1587 * must be done after initializing the BMUs;
1588 * drivers without ASF support should do this too, otherwise
1589 * it may happen that they cannot run on ASF devices;
1590 * remember that the MAC FIFO isn't reset during initialization.
1591 */
1592 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1593 }
1594
1595 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1596 /* Enable RX Home Address & Routing Header checksum fix */
1597 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1598 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1599
1600 /* Enable TX Home Address & Routing Header checksum fix */
1601 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1602 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1603 }
1604 }
1605
1606 static int sky2_alloc_buffers(struct sky2_port *sky2)
1607 {
1608 struct sky2_hw *hw = sky2->hw;
1609
1610 /* must be power of 2 */
1611 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1612 sky2->tx_ring_size *
1613 sizeof(struct sky2_tx_le),
1614 &sky2->tx_le_map);
1615 if (!sky2->tx_le)
1616 goto nomem;
1617
1618 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1619 GFP_KERNEL);
1620 if (!sky2->tx_ring)
1621 goto nomem;
1622
1623 sky2->rx_le = pci_zalloc_consistent(hw->pdev, RX_LE_BYTES,
1624 &sky2->rx_le_map);
1625 if (!sky2->rx_le)
1626 goto nomem;
1627
1628 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1629 GFP_KERNEL);
1630 if (!sky2->rx_ring)
1631 goto nomem;
1632
1633 return sky2_alloc_rx_skbs(sky2);
1634 nomem:
1635 return -ENOMEM;
1636 }
1637
1638 static void sky2_free_buffers(struct sky2_port *sky2)
1639 {
1640 struct sky2_hw *hw = sky2->hw;
1641
1642 sky2_rx_clean(sky2);
1643
1644 if (sky2->rx_le) {
1645 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1646 sky2->rx_le, sky2->rx_le_map);
1647 sky2->rx_le = NULL;
1648 }
1649 if (sky2->tx_le) {
1650 pci_free_consistent(hw->pdev,
1651 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1652 sky2->tx_le, sky2->tx_le_map);
1653 sky2->tx_le = NULL;
1654 }
1655 kfree(sky2->tx_ring);
1656 kfree(sky2->rx_ring);
1657
1658 sky2->tx_ring = NULL;
1659 sky2->rx_ring = NULL;
1660 }
1661
1662 static void sky2_hw_up(struct sky2_port *sky2)
1663 {
1664 struct sky2_hw *hw = sky2->hw;
1665 unsigned port = sky2->port;
1666 u32 ramsize;
1667 int cap;
1668 struct net_device *otherdev = hw->dev[sky2->port^1];
1669
1670 tx_init(sky2);
1671
1672 /*
1673 * On dual port PCI-X card, there is an problem where status
1674 * can be received out of order due to split transactions
1675 */
1676 if (otherdev && netif_running(otherdev) &&
1677 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1678 u16 cmd;
1679
1680 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1681 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1682 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1683 }
1684
1685 sky2_mac_init(hw, port);
1686
1687 /* Register is number of 4K blocks on internal RAM buffer. */
1688 ramsize = sky2_read8(hw, B2_E_0) * 4;
1689 if (ramsize > 0) {
1690 u32 rxspace;
1691
1692 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1693 if (ramsize < 16)
1694 rxspace = ramsize / 2;
1695 else
1696 rxspace = 8 + (2*(ramsize - 16))/3;
1697
1698 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1699 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1700
1701 /* Make sure SyncQ is disabled */
1702 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1703 RB_RST_SET);
1704 }
1705
1706 sky2_qset(hw, txqaddr[port]);
1707
1708 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1709 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1710 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1711
1712 /* Set almost empty threshold */
1713 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1714 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1715 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1716
1717 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1718 sky2->tx_ring_size - 1);
1719
1720 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1721 netdev_update_features(sky2->netdev);
1722
1723 sky2_rx_start(sky2);
1724 }
1725
1726 /* Setup device IRQ and enable napi to process */
1727 static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1728 {
1729 struct pci_dev *pdev = hw->pdev;
1730 int err;
1731
1732 err = request_irq(pdev->irq, sky2_intr,
1733 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1734 name, hw);
1735 if (err)
1736 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1737 else {
1738 hw->flags |= SKY2_HW_IRQ_SETUP;
1739
1740 napi_enable(&hw->napi);
1741 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1742 sky2_read32(hw, B0_IMSK);
1743 }
1744
1745 return err;
1746 }
1747
1748
1749 /* Bring up network interface. */
1750 static int sky2_open(struct net_device *dev)
1751 {
1752 struct sky2_port *sky2 = netdev_priv(dev);
1753 struct sky2_hw *hw = sky2->hw;
1754 unsigned port = sky2->port;
1755 u32 imask;
1756 int err;
1757
1758 netif_carrier_off(dev);
1759
1760 err = sky2_alloc_buffers(sky2);
1761 if (err)
1762 goto err_out;
1763
1764 /* With single port, IRQ is setup when device is brought up */
1765 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1766 goto err_out;
1767
1768 sky2_hw_up(sky2);
1769
1770 /* Enable interrupts from phy/mac for port */
1771 imask = sky2_read32(hw, B0_IMSK);
1772
1773 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1774 hw->chip_id == CHIP_ID_YUKON_PRM ||
1775 hw->chip_id == CHIP_ID_YUKON_OP_2)
1776 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
1777
1778 imask |= portirq_msk[port];
1779 sky2_write32(hw, B0_IMSK, imask);
1780 sky2_read32(hw, B0_IMSK);
1781
1782 netif_info(sky2, ifup, dev, "enabling interface\n");
1783
1784 return 0;
1785
1786 err_out:
1787 sky2_free_buffers(sky2);
1788 return err;
1789 }
1790
1791 /* Modular subtraction in ring */
1792 static inline int tx_inuse(const struct sky2_port *sky2)
1793 {
1794 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1795 }
1796
1797 /* Number of list elements available for next tx */
1798 static inline int tx_avail(const struct sky2_port *sky2)
1799 {
1800 return sky2->tx_pending - tx_inuse(sky2);
1801 }
1802
1803 /* Estimate of number of transmit list elements required */
1804 static unsigned tx_le_req(const struct sk_buff *skb)
1805 {
1806 unsigned count;
1807
1808 count = (skb_shinfo(skb)->nr_frags + 1)
1809 * (sizeof(dma_addr_t) / sizeof(u32));
1810
1811 if (skb_is_gso(skb))
1812 ++count;
1813 else if (sizeof(dma_addr_t) == sizeof(u32))
1814 ++count; /* possible vlan */
1815
1816 if (skb->ip_summed == CHECKSUM_PARTIAL)
1817 ++count;
1818
1819 return count;
1820 }
1821
1822 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1823 {
1824 if (re->flags & TX_MAP_SINGLE)
1825 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1826 dma_unmap_len(re, maplen),
1827 PCI_DMA_TODEVICE);
1828 else if (re->flags & TX_MAP_PAGE)
1829 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1830 dma_unmap_len(re, maplen),
1831 PCI_DMA_TODEVICE);
1832 re->flags = 0;
1833 }
1834
1835 /*
1836 * Put one packet in ring for transmit.
1837 * A single packet can generate multiple list elements, and
1838 * the number of ring elements will probably be less than the number
1839 * of list elements used.
1840 */
1841 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1842 struct net_device *dev)
1843 {
1844 struct sky2_port *sky2 = netdev_priv(dev);
1845 struct sky2_hw *hw = sky2->hw;
1846 struct sky2_tx_le *le = NULL;
1847 struct tx_ring_info *re;
1848 unsigned i, len;
1849 dma_addr_t mapping;
1850 u32 upper;
1851 u16 slot;
1852 u16 mss;
1853 u8 ctrl;
1854
1855 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1856 return NETDEV_TX_BUSY;
1857
1858 len = skb_headlen(skb);
1859 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1860
1861 if (pci_dma_mapping_error(hw->pdev, mapping))
1862 goto mapping_error;
1863
1864 slot = sky2->tx_prod;
1865 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1866 "tx queued, slot %u, len %d\n", slot, skb->len);
1867
1868 /* Send high bits if needed */
1869 upper = upper_32_bits(mapping);
1870 if (upper != sky2->tx_last_upper) {
1871 le = get_tx_le(sky2, &slot);
1872 le->addr = cpu_to_le32(upper);
1873 sky2->tx_last_upper = upper;
1874 le->opcode = OP_ADDR64 | HW_OWNER;
1875 }
1876
1877 /* Check for TCP Segmentation Offload */
1878 mss = skb_shinfo(skb)->gso_size;
1879 if (mss != 0) {
1880
1881 if (!(hw->flags & SKY2_HW_NEW_LE))
1882 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1883
1884 if (mss != sky2->tx_last_mss) {
1885 le = get_tx_le(sky2, &slot);
1886 le->addr = cpu_to_le32(mss);
1887
1888 if (hw->flags & SKY2_HW_NEW_LE)
1889 le->opcode = OP_MSS | HW_OWNER;
1890 else
1891 le->opcode = OP_LRGLEN | HW_OWNER;
1892 sky2->tx_last_mss = mss;
1893 }
1894 }
1895
1896 ctrl = 0;
1897
1898 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1899 if (skb_vlan_tag_present(skb)) {
1900 if (!le) {
1901 le = get_tx_le(sky2, &slot);
1902 le->addr = 0;
1903 le->opcode = OP_VLAN|HW_OWNER;
1904 } else
1905 le->opcode |= OP_VLAN;
1906 le->length = cpu_to_be16(skb_vlan_tag_get(skb));
1907 ctrl |= INS_VLAN;
1908 }
1909
1910 /* Handle TCP checksum offload */
1911 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1912 /* On Yukon EX (some versions) encoding change. */
1913 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1914 ctrl |= CALSUM; /* auto checksum */
1915 else {
1916 const unsigned offset = skb_transport_offset(skb);
1917 u32 tcpsum;
1918
1919 tcpsum = offset << 16; /* sum start */
1920 tcpsum |= offset + skb->csum_offset; /* sum write */
1921
1922 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1923 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1924 ctrl |= UDPTCP;
1925
1926 if (tcpsum != sky2->tx_tcpsum) {
1927 sky2->tx_tcpsum = tcpsum;
1928
1929 le = get_tx_le(sky2, &slot);
1930 le->addr = cpu_to_le32(tcpsum);
1931 le->length = 0; /* initial checksum value */
1932 le->ctrl = 1; /* one packet */
1933 le->opcode = OP_TCPLISW | HW_OWNER;
1934 }
1935 }
1936 }
1937
1938 re = sky2->tx_ring + slot;
1939 re->flags = TX_MAP_SINGLE;
1940 dma_unmap_addr_set(re, mapaddr, mapping);
1941 dma_unmap_len_set(re, maplen, len);
1942
1943 le = get_tx_le(sky2, &slot);
1944 le->addr = cpu_to_le32(lower_32_bits(mapping));
1945 le->length = cpu_to_le16(len);
1946 le->ctrl = ctrl;
1947 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1948
1949
1950 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1951 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1952
1953 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1954 skb_frag_size(frag), DMA_TO_DEVICE);
1955
1956 if (dma_mapping_error(&hw->pdev->dev, mapping))
1957 goto mapping_unwind;
1958
1959 upper = upper_32_bits(mapping);
1960 if (upper != sky2->tx_last_upper) {
1961 le = get_tx_le(sky2, &slot);
1962 le->addr = cpu_to_le32(upper);
1963 sky2->tx_last_upper = upper;
1964 le->opcode = OP_ADDR64 | HW_OWNER;
1965 }
1966
1967 re = sky2->tx_ring + slot;
1968 re->flags = TX_MAP_PAGE;
1969 dma_unmap_addr_set(re, mapaddr, mapping);
1970 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1971
1972 le = get_tx_le(sky2, &slot);
1973 le->addr = cpu_to_le32(lower_32_bits(mapping));
1974 le->length = cpu_to_le16(skb_frag_size(frag));
1975 le->ctrl = ctrl;
1976 le->opcode = OP_BUFFER | HW_OWNER;
1977 }
1978
1979 re->skb = skb;
1980 le->ctrl |= EOP;
1981
1982 sky2->tx_prod = slot;
1983
1984 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1985 netif_stop_queue(dev);
1986
1987 netdev_sent_queue(dev, skb->len);
1988 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1989
1990 return NETDEV_TX_OK;
1991
1992 mapping_unwind:
1993 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1994 re = sky2->tx_ring + i;
1995
1996 sky2_tx_unmap(hw->pdev, re);
1997 }
1998
1999 mapping_error:
2000 if (net_ratelimit())
2001 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2002 dev_kfree_skb_any(skb);
2003 return NETDEV_TX_OK;
2004 }
2005
2006 /*
2007 * Free ring elements from starting at tx_cons until "done"
2008 *
2009 * NB:
2010 * 1. The hardware will tell us about partial completion of multi-part
2011 * buffers so make sure not to free skb to early.
2012 * 2. This may run in parallel start_xmit because the it only
2013 * looks at the tail of the queue of FIFO (tx_cons), not
2014 * the head (tx_prod)
2015 */
2016 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
2017 {
2018 struct net_device *dev = sky2->netdev;
2019 u16 idx;
2020 unsigned int bytes_compl = 0, pkts_compl = 0;
2021
2022 BUG_ON(done >= sky2->tx_ring_size);
2023
2024 for (idx = sky2->tx_cons; idx != done;
2025 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2026 struct tx_ring_info *re = sky2->tx_ring + idx;
2027 struct sk_buff *skb = re->skb;
2028
2029 sky2_tx_unmap(sky2->hw->pdev, re);
2030
2031 if (skb) {
2032 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2033 "tx done %u\n", idx);
2034
2035 pkts_compl++;
2036 bytes_compl += skb->len;
2037
2038 re->skb = NULL;
2039 dev_kfree_skb_any(skb);
2040
2041 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2042 }
2043 }
2044
2045 sky2->tx_cons = idx;
2046 smp_mb();
2047
2048 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2049
2050 u64_stats_update_begin(&sky2->tx_stats.syncp);
2051 sky2->tx_stats.packets += pkts_compl;
2052 sky2->tx_stats.bytes += bytes_compl;
2053 u64_stats_update_end(&sky2->tx_stats.syncp);
2054 }
2055
2056 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2057 {
2058 /* Disable Force Sync bit and Enable Alloc bit */
2059 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2060 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2061
2062 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2063 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2064 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2065
2066 /* Reset the PCI FIFO of the async Tx queue */
2067 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2068 BMU_RST_SET | BMU_FIFO_RST);
2069
2070 /* Reset the Tx prefetch units */
2071 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2072 PREF_UNIT_RST_SET);
2073
2074 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2075 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2076
2077 sky2_read32(hw, B0_CTST);
2078 }
2079
2080 static void sky2_hw_down(struct sky2_port *sky2)
2081 {
2082 struct sky2_hw *hw = sky2->hw;
2083 unsigned port = sky2->port;
2084 u16 ctrl;
2085
2086 /* Force flow control off */
2087 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2088
2089 /* Stop transmitter */
2090 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2091 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2092
2093 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2094 RB_RST_SET | RB_DIS_OP_MD);
2095
2096 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2097 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2098 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2099
2100 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2101
2102 /* Workaround shared GMAC reset */
2103 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2104 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2105 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2106
2107 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2108
2109 /* Force any delayed status interrupt and NAPI */
2110 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2111 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2112 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2113 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2114
2115 sky2_rx_stop(sky2);
2116
2117 spin_lock_bh(&sky2->phy_lock);
2118 sky2_phy_power_down(hw, port);
2119 spin_unlock_bh(&sky2->phy_lock);
2120
2121 sky2_tx_reset(hw, port);
2122
2123 /* Free any pending frames stuck in HW queue */
2124 sky2_tx_complete(sky2, sky2->tx_prod);
2125 }
2126
2127 /* Network shutdown */
2128 static int sky2_close(struct net_device *dev)
2129 {
2130 struct sky2_port *sky2 = netdev_priv(dev);
2131 struct sky2_hw *hw = sky2->hw;
2132
2133 /* Never really got started! */
2134 if (!sky2->tx_le)
2135 return 0;
2136
2137 netif_info(sky2, ifdown, dev, "disabling interface\n");
2138
2139 if (hw->ports == 1) {
2140 sky2_write32(hw, B0_IMSK, 0);
2141 sky2_read32(hw, B0_IMSK);
2142
2143 napi_disable(&hw->napi);
2144 free_irq(hw->pdev->irq, hw);
2145 hw->flags &= ~SKY2_HW_IRQ_SETUP;
2146 } else {
2147 u32 imask;
2148
2149 /* Disable port IRQ */
2150 imask = sky2_read32(hw, B0_IMSK);
2151 imask &= ~portirq_msk[sky2->port];
2152 sky2_write32(hw, B0_IMSK, imask);
2153 sky2_read32(hw, B0_IMSK);
2154
2155 synchronize_irq(hw->pdev->irq);
2156 napi_synchronize(&hw->napi);
2157 }
2158
2159 sky2_hw_down(sky2);
2160
2161 sky2_free_buffers(sky2);
2162
2163 return 0;
2164 }
2165
2166 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2167 {
2168 if (hw->flags & SKY2_HW_FIBRE_PHY)
2169 return SPEED_1000;
2170
2171 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2172 if (aux & PHY_M_PS_SPEED_100)
2173 return SPEED_100;
2174 else
2175 return SPEED_10;
2176 }
2177
2178 switch (aux & PHY_M_PS_SPEED_MSK) {
2179 case PHY_M_PS_SPEED_1000:
2180 return SPEED_1000;
2181 case PHY_M_PS_SPEED_100:
2182 return SPEED_100;
2183 default:
2184 return SPEED_10;
2185 }
2186 }
2187
2188 static void sky2_link_up(struct sky2_port *sky2)
2189 {
2190 struct sky2_hw *hw = sky2->hw;
2191 unsigned port = sky2->port;
2192 static const char *fc_name[] = {
2193 [FC_NONE] = "none",
2194 [FC_TX] = "tx",
2195 [FC_RX] = "rx",
2196 [FC_BOTH] = "both",
2197 };
2198
2199 sky2_set_ipg(sky2);
2200
2201 sky2_enable_rx_tx(sky2);
2202
2203 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2204
2205 netif_carrier_on(sky2->netdev);
2206
2207 mod_timer(&hw->watchdog_timer, jiffies + 1);
2208
2209 /* Turn on link LED */
2210 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2211 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2212
2213 netif_info(sky2, link, sky2->netdev,
2214 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2215 sky2->speed,
2216 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2217 fc_name[sky2->flow_status]);
2218 }
2219
2220 static void sky2_link_down(struct sky2_port *sky2)
2221 {
2222 struct sky2_hw *hw = sky2->hw;
2223 unsigned port = sky2->port;
2224 u16 reg;
2225
2226 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2227
2228 reg = gma_read16(hw, port, GM_GP_CTRL);
2229 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2230 gma_write16(hw, port, GM_GP_CTRL, reg);
2231
2232 netif_carrier_off(sky2->netdev);
2233
2234 /* Turn off link LED */
2235 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2236
2237 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2238
2239 sky2_phy_init(hw, port);
2240 }
2241
2242 static enum flow_control sky2_flow(int rx, int tx)
2243 {
2244 if (rx)
2245 return tx ? FC_BOTH : FC_RX;
2246 else
2247 return tx ? FC_TX : FC_NONE;
2248 }
2249
2250 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2251 {
2252 struct sky2_hw *hw = sky2->hw;
2253 unsigned port = sky2->port;
2254 u16 advert, lpa;
2255
2256 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2257 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2258 if (lpa & PHY_M_AN_RF) {
2259 netdev_err(sky2->netdev, "remote fault\n");
2260 return -1;
2261 }
2262
2263 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2264 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2265 return -1;
2266 }
2267
2268 sky2->speed = sky2_phy_speed(hw, aux);
2269 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2270
2271 /* Since the pause result bits seem to in different positions on
2272 * different chips. look at registers.
2273 */
2274 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2275 /* Shift for bits in fiber PHY */
2276 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2277 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2278
2279 if (advert & ADVERTISE_1000XPAUSE)
2280 advert |= ADVERTISE_PAUSE_CAP;
2281 if (advert & ADVERTISE_1000XPSE_ASYM)
2282 advert |= ADVERTISE_PAUSE_ASYM;
2283 if (lpa & LPA_1000XPAUSE)
2284 lpa |= LPA_PAUSE_CAP;
2285 if (lpa & LPA_1000XPAUSE_ASYM)
2286 lpa |= LPA_PAUSE_ASYM;
2287 }
2288
2289 sky2->flow_status = FC_NONE;
2290 if (advert & ADVERTISE_PAUSE_CAP) {
2291 if (lpa & LPA_PAUSE_CAP)
2292 sky2->flow_status = FC_BOTH;
2293 else if (advert & ADVERTISE_PAUSE_ASYM)
2294 sky2->flow_status = FC_RX;
2295 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2296 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2297 sky2->flow_status = FC_TX;
2298 }
2299
2300 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2301 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2302 sky2->flow_status = FC_NONE;
2303
2304 if (sky2->flow_status & FC_TX)
2305 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2306 else
2307 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2308
2309 return 0;
2310 }
2311
2312 /* Interrupt from PHY */
2313 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2314 {
2315 struct net_device *dev = hw->dev[port];
2316 struct sky2_port *sky2 = netdev_priv(dev);
2317 u16 istatus, phystat;
2318
2319 if (!netif_running(dev))
2320 return;
2321
2322 spin_lock(&sky2->phy_lock);
2323 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2324 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2325
2326 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2327 istatus, phystat);
2328
2329 if (istatus & PHY_M_IS_AN_COMPL) {
2330 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2331 !netif_carrier_ok(dev))
2332 sky2_link_up(sky2);
2333 goto out;
2334 }
2335
2336 if (istatus & PHY_M_IS_LSP_CHANGE)
2337 sky2->speed = sky2_phy_speed(hw, phystat);
2338
2339 if (istatus & PHY_M_IS_DUP_CHANGE)
2340 sky2->duplex =
2341 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2342
2343 if (istatus & PHY_M_IS_LST_CHANGE) {
2344 if (phystat & PHY_M_PS_LINK_UP)
2345 sky2_link_up(sky2);
2346 else
2347 sky2_link_down(sky2);
2348 }
2349 out:
2350 spin_unlock(&sky2->phy_lock);
2351 }
2352
2353 /* Special quick link interrupt (Yukon-2 Optima only) */
2354 static void sky2_qlink_intr(struct sky2_hw *hw)
2355 {
2356 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2357 u32 imask;
2358 u16 phy;
2359
2360 /* disable irq */
2361 imask = sky2_read32(hw, B0_IMSK);
2362 imask &= ~Y2_IS_PHY_QLNK;
2363 sky2_write32(hw, B0_IMSK, imask);
2364
2365 /* reset PHY Link Detect */
2366 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2367 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2368 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2369 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2370
2371 sky2_link_up(sky2);
2372 }
2373
2374 /* Transmit timeout is only called if we are running, carrier is up
2375 * and tx queue is full (stopped).
2376 */
2377 static void sky2_tx_timeout(struct net_device *dev)
2378 {
2379 struct sky2_port *sky2 = netdev_priv(dev);
2380 struct sky2_hw *hw = sky2->hw;
2381
2382 netif_err(sky2, timer, dev, "tx timeout\n");
2383
2384 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2385 sky2->tx_cons, sky2->tx_prod,
2386 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2387 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2388
2389 /* can't restart safely under softirq */
2390 schedule_work(&hw->restart_work);
2391 }
2392
2393 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2394 {
2395 struct sky2_port *sky2 = netdev_priv(dev);
2396 struct sky2_hw *hw = sky2->hw;
2397 unsigned port = sky2->port;
2398 int err;
2399 u16 ctl, mode;
2400 u32 imask;
2401
2402 if (!netif_running(dev)) {
2403 dev->mtu = new_mtu;
2404 netdev_update_features(dev);
2405 return 0;
2406 }
2407
2408 imask = sky2_read32(hw, B0_IMSK);
2409 sky2_write32(hw, B0_IMSK, 0);
2410 sky2_read32(hw, B0_IMSK);
2411
2412 netif_trans_update(dev); /* prevent tx timeout */
2413 napi_disable(&hw->napi);
2414 netif_tx_disable(dev);
2415
2416 synchronize_irq(hw->pdev->irq);
2417
2418 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2419 sky2_set_tx_stfwd(hw, port);
2420
2421 ctl = gma_read16(hw, port, GM_GP_CTRL);
2422 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2423 sky2_rx_stop(sky2);
2424 sky2_rx_clean(sky2);
2425
2426 dev->mtu = new_mtu;
2427 netdev_update_features(dev);
2428
2429 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2430 if (sky2->speed > SPEED_100)
2431 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2432 else
2433 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2434
2435 if (dev->mtu > ETH_DATA_LEN)
2436 mode |= GM_SMOD_JUMBO_ENA;
2437
2438 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2439
2440 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2441
2442 err = sky2_alloc_rx_skbs(sky2);
2443 if (!err)
2444 sky2_rx_start(sky2);
2445 else
2446 sky2_rx_clean(sky2);
2447 sky2_write32(hw, B0_IMSK, imask);
2448
2449 sky2_read32(hw, B0_Y2_SP_LISR);
2450 napi_enable(&hw->napi);
2451
2452 if (err)
2453 dev_close(dev);
2454 else {
2455 gma_write16(hw, port, GM_GP_CTRL, ctl);
2456
2457 netif_wake_queue(dev);
2458 }
2459
2460 return err;
2461 }
2462
2463 static inline bool needs_copy(const struct rx_ring_info *re,
2464 unsigned length)
2465 {
2466 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2467 /* Some architectures need the IP header to be aligned */
2468 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32)))
2469 return true;
2470 #endif
2471 return length < copybreak;
2472 }
2473
2474 /* For small just reuse existing skb for next receive */
2475 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2476 const struct rx_ring_info *re,
2477 unsigned length)
2478 {
2479 struct sk_buff *skb;
2480
2481 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2482 if (likely(skb)) {
2483 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2484 length, PCI_DMA_FROMDEVICE);
2485 skb_copy_from_linear_data(re->skb, skb->data, length);
2486 skb->ip_summed = re->skb->ip_summed;
2487 skb->csum = re->skb->csum;
2488 skb_copy_hash(skb, re->skb);
2489 skb->vlan_proto = re->skb->vlan_proto;
2490 skb->vlan_tci = re->skb->vlan_tci;
2491
2492 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2493 length, PCI_DMA_FROMDEVICE);
2494 re->skb->vlan_proto = 0;
2495 re->skb->vlan_tci = 0;
2496 skb_clear_hash(re->skb);
2497 re->skb->ip_summed = CHECKSUM_NONE;
2498 skb_put(skb, length);
2499 }
2500 return skb;
2501 }
2502
2503 /* Adjust length of skb with fragments to match received data */
2504 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2505 unsigned int length)
2506 {
2507 int i, num_frags;
2508 unsigned int size;
2509
2510 /* put header into skb */
2511 size = min(length, hdr_space);
2512 skb->tail += size;
2513 skb->len += size;
2514 length -= size;
2515
2516 num_frags = skb_shinfo(skb)->nr_frags;
2517 for (i = 0; i < num_frags; i++) {
2518 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2519
2520 if (length == 0) {
2521 /* don't need this page */
2522 __skb_frag_unref(frag);
2523 --skb_shinfo(skb)->nr_frags;
2524 } else {
2525 size = min(length, (unsigned) PAGE_SIZE);
2526
2527 skb_frag_size_set(frag, size);
2528 skb->data_len += size;
2529 skb->truesize += PAGE_SIZE;
2530 skb->len += size;
2531 length -= size;
2532 }
2533 }
2534 }
2535
2536 /* Normal packet - take skb from ring element and put in a new one */
2537 static struct sk_buff *receive_new(struct sky2_port *sky2,
2538 struct rx_ring_info *re,
2539 unsigned int length)
2540 {
2541 struct sk_buff *skb;
2542 struct rx_ring_info nre;
2543 unsigned hdr_space = sky2->rx_data_size;
2544
2545 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2546 if (unlikely(!nre.skb))
2547 goto nobuf;
2548
2549 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2550 goto nomap;
2551
2552 skb = re->skb;
2553 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2554 prefetch(skb->data);
2555 *re = nre;
2556
2557 if (skb_shinfo(skb)->nr_frags)
2558 skb_put_frags(skb, hdr_space, length);
2559 else
2560 skb_put(skb, length);
2561 return skb;
2562
2563 nomap:
2564 dev_kfree_skb(nre.skb);
2565 nobuf:
2566 return NULL;
2567 }
2568
2569 /*
2570 * Receive one packet.
2571 * For larger packets, get new buffer.
2572 */
2573 static struct sk_buff *sky2_receive(struct net_device *dev,
2574 u16 length, u32 status)
2575 {
2576 struct sky2_port *sky2 = netdev_priv(dev);
2577 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2578 struct sk_buff *skb = NULL;
2579 u16 count = (status & GMR_FS_LEN) >> 16;
2580
2581 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2582 "rx slot %u status 0x%x len %d\n",
2583 sky2->rx_next, status, length);
2584
2585 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2586 prefetch(sky2->rx_ring + sky2->rx_next);
2587
2588 if (skb_vlan_tag_present(re->skb))
2589 count -= VLAN_HLEN; /* Account for vlan tag */
2590
2591 /* This chip has hardware problems that generates bogus status.
2592 * So do only marginal checking and expect higher level protocols
2593 * to handle crap frames.
2594 */
2595 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2596 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2597 length != count)
2598 goto okay;
2599
2600 if (status & GMR_FS_ANY_ERR)
2601 goto error;
2602
2603 if (!(status & GMR_FS_RX_OK))
2604 goto resubmit;
2605
2606 /* if length reported by DMA does not match PHY, packet was truncated */
2607 if (length != count)
2608 goto error;
2609
2610 okay:
2611 if (needs_copy(re, length))
2612 skb = receive_copy(sky2, re, length);
2613 else
2614 skb = receive_new(sky2, re, length);
2615
2616 dev->stats.rx_dropped += (skb == NULL);
2617
2618 resubmit:
2619 sky2_rx_submit(sky2, re);
2620
2621 return skb;
2622
2623 error:
2624 ++dev->stats.rx_errors;
2625
2626 if (net_ratelimit())
2627 netif_info(sky2, rx_err, dev,
2628 "rx error, status 0x%x length %d\n", status, length);
2629
2630 goto resubmit;
2631 }
2632
2633 /* Transmit complete */
2634 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2635 {
2636 struct sky2_port *sky2 = netdev_priv(dev);
2637
2638 if (netif_running(dev)) {
2639 sky2_tx_complete(sky2, last);
2640
2641 /* Wake unless it's detached, and called e.g. from sky2_close() */
2642 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2643 netif_wake_queue(dev);
2644 }
2645 }
2646
2647 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2648 struct sk_buff *skb)
2649 {
2650 if (skb->ip_summed == CHECKSUM_NONE)
2651 netif_receive_skb(skb);
2652 else
2653 napi_gro_receive(&sky2->hw->napi, skb);
2654 }
2655
2656 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2657 unsigned packets, unsigned bytes)
2658 {
2659 struct net_device *dev = hw->dev[port];
2660 struct sky2_port *sky2 = netdev_priv(dev);
2661
2662 if (packets == 0)
2663 return;
2664
2665 u64_stats_update_begin(&sky2->rx_stats.syncp);
2666 sky2->rx_stats.packets += packets;
2667 sky2->rx_stats.bytes += bytes;
2668 u64_stats_update_end(&sky2->rx_stats.syncp);
2669
2670 sky2->last_rx = jiffies;
2671 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2672 }
2673
2674 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2675 {
2676 /* If this happens then driver assuming wrong format for chip type */
2677 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2678
2679 /* Both checksum counters are programmed to start at
2680 * the same offset, so unless there is a problem they
2681 * should match. This failure is an early indication that
2682 * hardware receive checksumming won't work.
2683 */
2684 if (likely((u16)(status >> 16) == (u16)status)) {
2685 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2686 skb->ip_summed = CHECKSUM_COMPLETE;
2687 skb->csum = le16_to_cpu(status);
2688 } else {
2689 dev_notice(&sky2->hw->pdev->dev,
2690 "%s: receive checksum problem (status = %#x)\n",
2691 sky2->netdev->name, status);
2692
2693 /* Disable checksum offload
2694 * It will be reenabled on next ndo_set_features, but if it's
2695 * really broken, will get disabled again
2696 */
2697 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2698 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2699 BMU_DIS_RX_CHKSUM);
2700 }
2701 }
2702
2703 static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
2704 {
2705 struct sk_buff *skb;
2706
2707 skb = sky2->rx_ring[sky2->rx_next].skb;
2708 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length));
2709 }
2710
2711 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2712 {
2713 struct sk_buff *skb;
2714
2715 skb = sky2->rx_ring[sky2->rx_next].skb;
2716 skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3);
2717 }
2718
2719 /* Process status response ring */
2720 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2721 {
2722 int work_done = 0;
2723 unsigned int total_bytes[2] = { 0 };
2724 unsigned int total_packets[2] = { 0 };
2725
2726 if (to_do <= 0)
2727 return work_done;
2728
2729 rmb();
2730 do {
2731 struct sky2_port *sky2;
2732 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2733 unsigned port;
2734 struct net_device *dev;
2735 struct sk_buff *skb;
2736 u32 status;
2737 u16 length;
2738 u8 opcode = le->opcode;
2739
2740 if (!(opcode & HW_OWNER))
2741 break;
2742
2743 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2744
2745 port = le->css & CSS_LINK_BIT;
2746 dev = hw->dev[port];
2747 sky2 = netdev_priv(dev);
2748 length = le16_to_cpu(le->length);
2749 status = le32_to_cpu(le->status);
2750
2751 le->opcode = 0;
2752 switch (opcode & ~HW_OWNER) {
2753 case OP_RXSTAT:
2754 total_packets[port]++;
2755 total_bytes[port] += length;
2756
2757 skb = sky2_receive(dev, length, status);
2758 if (!skb)
2759 break;
2760
2761 /* This chip reports checksum status differently */
2762 if (hw->flags & SKY2_HW_NEW_LE) {
2763 if ((dev->features & NETIF_F_RXCSUM) &&
2764 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2765 (le->css & CSS_TCPUDPCSOK))
2766 skb->ip_summed = CHECKSUM_UNNECESSARY;
2767 else
2768 skb->ip_summed = CHECKSUM_NONE;
2769 }
2770
2771 skb->protocol = eth_type_trans(skb, dev);
2772 sky2_skb_rx(sky2, skb);
2773
2774 /* Stop after net poll weight */
2775 if (++work_done >= to_do)
2776 goto exit_loop;
2777 break;
2778
2779 case OP_RXVLAN:
2780 sky2_rx_tag(sky2, length);
2781 break;
2782
2783 case OP_RXCHKSVLAN:
2784 sky2_rx_tag(sky2, length);
2785 /* fall through */
2786 case OP_RXCHKS:
2787 if (likely(dev->features & NETIF_F_RXCSUM))
2788 sky2_rx_checksum(sky2, status);
2789 break;
2790
2791 case OP_RSS_HASH:
2792 sky2_rx_hash(sky2, status);
2793 break;
2794
2795 case OP_TXINDEXLE:
2796 /* TX index reports status for both ports */
2797 sky2_tx_done(hw->dev[0], status & 0xfff);
2798 if (hw->dev[1])
2799 sky2_tx_done(hw->dev[1],
2800 ((status >> 24) & 0xff)
2801 | (u16)(length & 0xf) << 8);
2802 break;
2803
2804 default:
2805 if (net_ratelimit())
2806 pr_warn("unknown status opcode 0x%x\n", opcode);
2807 }
2808 } while (hw->st_idx != idx);
2809
2810 /* Fully processed status ring so clear irq */
2811 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2812
2813 exit_loop:
2814 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2815 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2816
2817 return work_done;
2818 }
2819
2820 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2821 {
2822 struct net_device *dev = hw->dev[port];
2823
2824 if (net_ratelimit())
2825 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2826
2827 if (status & Y2_IS_PAR_RD1) {
2828 if (net_ratelimit())
2829 netdev_err(dev, "ram data read parity error\n");
2830 /* Clear IRQ */
2831 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2832 }
2833
2834 if (status & Y2_IS_PAR_WR1) {
2835 if (net_ratelimit())
2836 netdev_err(dev, "ram data write parity error\n");
2837
2838 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2839 }
2840
2841 if (status & Y2_IS_PAR_MAC1) {
2842 if (net_ratelimit())
2843 netdev_err(dev, "MAC parity error\n");
2844 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2845 }
2846
2847 if (status & Y2_IS_PAR_RX1) {
2848 if (net_ratelimit())
2849 netdev_err(dev, "RX parity error\n");
2850 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2851 }
2852
2853 if (status & Y2_IS_TCP_TXA1) {
2854 if (net_ratelimit())
2855 netdev_err(dev, "TCP segmentation error\n");
2856 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2857 }
2858 }
2859
2860 static void sky2_hw_intr(struct sky2_hw *hw)
2861 {
2862 struct pci_dev *pdev = hw->pdev;
2863 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2864 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2865
2866 status &= hwmsk;
2867
2868 if (status & Y2_IS_TIST_OV)
2869 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2870
2871 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2872 u16 pci_err;
2873
2874 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2875 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2876 if (net_ratelimit())
2877 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2878 pci_err);
2879
2880 sky2_pci_write16(hw, PCI_STATUS,
2881 pci_err | PCI_STATUS_ERROR_BITS);
2882 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2883 }
2884
2885 if (status & Y2_IS_PCI_EXP) {
2886 /* PCI-Express uncorrectable Error occurred */
2887 u32 err;
2888
2889 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2890 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2891 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2892 0xfffffffful);
2893 if (net_ratelimit())
2894 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2895
2896 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2897 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2898 }
2899
2900 if (status & Y2_HWE_L1_MASK)
2901 sky2_hw_error(hw, 0, status);
2902 status >>= 8;
2903 if (status & Y2_HWE_L1_MASK)
2904 sky2_hw_error(hw, 1, status);
2905 }
2906
2907 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2908 {
2909 struct net_device *dev = hw->dev[port];
2910 struct sky2_port *sky2 = netdev_priv(dev);
2911 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2912
2913 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2914
2915 if (status & GM_IS_RX_CO_OV)
2916 gma_read16(hw, port, GM_RX_IRQ_SRC);
2917
2918 if (status & GM_IS_TX_CO_OV)
2919 gma_read16(hw, port, GM_TX_IRQ_SRC);
2920
2921 if (status & GM_IS_RX_FF_OR) {
2922 ++dev->stats.rx_fifo_errors;
2923 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2924 }
2925
2926 if (status & GM_IS_TX_FF_UR) {
2927 ++dev->stats.tx_fifo_errors;
2928 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2929 }
2930 }
2931
2932 /* This should never happen it is a bug. */
2933 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2934 {
2935 struct net_device *dev = hw->dev[port];
2936 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2937
2938 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2939 dev->name, (unsigned) q, (unsigned) idx,
2940 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2941
2942 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2943 }
2944
2945 static int sky2_rx_hung(struct net_device *dev)
2946 {
2947 struct sky2_port *sky2 = netdev_priv(dev);
2948 struct sky2_hw *hw = sky2->hw;
2949 unsigned port = sky2->port;
2950 unsigned rxq = rxqaddr[port];
2951 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2952 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2953 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2954 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2955
2956 /* If idle and MAC or PCI is stuck */
2957 if (sky2->check.last == sky2->last_rx &&
2958 ((mac_rp == sky2->check.mac_rp &&
2959 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2960 /* Check if the PCI RX hang */
2961 (fifo_rp == sky2->check.fifo_rp &&
2962 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2963 netdev_printk(KERN_DEBUG, dev,
2964 "hung mac %d:%d fifo %d (%d:%d)\n",
2965 mac_lev, mac_rp, fifo_lev,
2966 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2967 return 1;
2968 } else {
2969 sky2->check.last = sky2->last_rx;
2970 sky2->check.mac_rp = mac_rp;
2971 sky2->check.mac_lev = mac_lev;
2972 sky2->check.fifo_rp = fifo_rp;
2973 sky2->check.fifo_lev = fifo_lev;
2974 return 0;
2975 }
2976 }
2977
2978 static void sky2_watchdog(struct timer_list *t)
2979 {
2980 struct sky2_hw *hw = from_timer(hw, t, watchdog_timer);
2981
2982 /* Check for lost IRQ once a second */
2983 if (sky2_read32(hw, B0_ISRC)) {
2984 napi_schedule(&hw->napi);
2985 } else {
2986 int i, active = 0;
2987
2988 for (i = 0; i < hw->ports; i++) {
2989 struct net_device *dev = hw->dev[i];
2990 if (!netif_running(dev))
2991 continue;
2992 ++active;
2993
2994 /* For chips with Rx FIFO, check if stuck */
2995 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2996 sky2_rx_hung(dev)) {
2997 netdev_info(dev, "receiver hang detected\n");
2998 schedule_work(&hw->restart_work);
2999 return;
3000 }
3001 }
3002
3003 if (active == 0)
3004 return;
3005 }
3006
3007 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
3008 }
3009
3010 /* Hardware/software error handling */
3011 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
3012 {
3013 if (net_ratelimit())
3014 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
3015
3016 if (status & Y2_IS_HW_ERR)
3017 sky2_hw_intr(hw);
3018
3019 if (status & Y2_IS_IRQ_MAC1)
3020 sky2_mac_intr(hw, 0);
3021
3022 if (status & Y2_IS_IRQ_MAC2)
3023 sky2_mac_intr(hw, 1);
3024
3025 if (status & Y2_IS_CHK_RX1)
3026 sky2_le_error(hw, 0, Q_R1);
3027
3028 if (status & Y2_IS_CHK_RX2)
3029 sky2_le_error(hw, 1, Q_R2);
3030
3031 if (status & Y2_IS_CHK_TXA1)
3032 sky2_le_error(hw, 0, Q_XA1);
3033
3034 if (status & Y2_IS_CHK_TXA2)
3035 sky2_le_error(hw, 1, Q_XA2);
3036 }
3037
3038 static int sky2_poll(struct napi_struct *napi, int work_limit)
3039 {
3040 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3041 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
3042 int work_done = 0;
3043 u16 idx;
3044
3045 if (unlikely(status & Y2_IS_ERROR))
3046 sky2_err_intr(hw, status);
3047
3048 if (status & Y2_IS_IRQ_PHY1)
3049 sky2_phy_intr(hw, 0);
3050
3051 if (status & Y2_IS_IRQ_PHY2)
3052 sky2_phy_intr(hw, 1);
3053
3054 if (status & Y2_IS_PHY_QLNK)
3055 sky2_qlink_intr(hw);
3056
3057 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3058 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3059
3060 if (work_done >= work_limit)
3061 goto done;
3062 }
3063
3064 napi_complete_done(napi, work_done);
3065 sky2_read32(hw, B0_Y2_SP_LISR);
3066 done:
3067
3068 return work_done;
3069 }
3070
3071 static irqreturn_t sky2_intr(int irq, void *dev_id)
3072 {
3073 struct sky2_hw *hw = dev_id;
3074 u32 status;
3075
3076 /* Reading this mask interrupts as side effect */
3077 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3078 if (status == 0 || status == ~0) {
3079 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3080 return IRQ_NONE;
3081 }
3082
3083 prefetch(&hw->st_le[hw->st_idx]);
3084
3085 napi_schedule(&hw->napi);
3086
3087 return IRQ_HANDLED;
3088 }
3089
3090 #ifdef CONFIG_NET_POLL_CONTROLLER
3091 static void sky2_netpoll(struct net_device *dev)
3092 {
3093 struct sky2_port *sky2 = netdev_priv(dev);
3094
3095 napi_schedule(&sky2->hw->napi);
3096 }
3097 #endif
3098
3099 /* Chip internal frequency for clock calculations */
3100 static u32 sky2_mhz(const struct sky2_hw *hw)
3101 {
3102 switch (hw->chip_id) {
3103 case CHIP_ID_YUKON_EC:
3104 case CHIP_ID_YUKON_EC_U:
3105 case CHIP_ID_YUKON_EX:
3106 case CHIP_ID_YUKON_SUPR:
3107 case CHIP_ID_YUKON_UL_2:
3108 case CHIP_ID_YUKON_OPT:
3109 case CHIP_ID_YUKON_PRM:
3110 case CHIP_ID_YUKON_OP_2:
3111 return 125;
3112
3113 case CHIP_ID_YUKON_FE:
3114 return 100;
3115
3116 case CHIP_ID_YUKON_FE_P:
3117 return 50;
3118
3119 case CHIP_ID_YUKON_XL:
3120 return 156;
3121
3122 default:
3123 BUG();
3124 }
3125 }
3126
3127 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3128 {
3129 return sky2_mhz(hw) * us;
3130 }
3131
3132 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3133 {
3134 return clk / sky2_mhz(hw);
3135 }
3136
3137
3138 static int sky2_init(struct sky2_hw *hw)
3139 {
3140 u8 t8;
3141
3142 /* Enable all clocks and check for bad PCI access */
3143 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3144
3145 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3146
3147 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3148 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3149
3150 switch (hw->chip_id) {
3151 case CHIP_ID_YUKON_XL:
3152 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3153 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3154 hw->flags |= SKY2_HW_RSS_BROKEN;
3155 break;
3156
3157 case CHIP_ID_YUKON_EC_U:
3158 hw->flags = SKY2_HW_GIGABIT
3159 | SKY2_HW_NEWER_PHY
3160 | SKY2_HW_ADV_POWER_CTL;
3161 break;
3162
3163 case CHIP_ID_YUKON_EX:
3164 hw->flags = SKY2_HW_GIGABIT
3165 | SKY2_HW_NEWER_PHY
3166 | SKY2_HW_NEW_LE
3167 | SKY2_HW_ADV_POWER_CTL
3168 | SKY2_HW_RSS_CHKSUM;
3169
3170 /* New transmit checksum */
3171 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3172 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3173 break;
3174
3175 case CHIP_ID_YUKON_EC:
3176 /* This rev is really old, and requires untested workarounds */
3177 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3178 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3179 return -EOPNOTSUPP;
3180 }
3181 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3182 break;
3183
3184 case CHIP_ID_YUKON_FE:
3185 hw->flags = SKY2_HW_RSS_BROKEN;
3186 break;
3187
3188 case CHIP_ID_YUKON_FE_P:
3189 hw->flags = SKY2_HW_NEWER_PHY
3190 | SKY2_HW_NEW_LE
3191 | SKY2_HW_AUTO_TX_SUM
3192 | SKY2_HW_ADV_POWER_CTL;
3193
3194 /* The workaround for status conflicts VLAN tag detection. */
3195 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3196 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3197 break;
3198
3199 case CHIP_ID_YUKON_SUPR:
3200 hw->flags = SKY2_HW_GIGABIT
3201 | SKY2_HW_NEWER_PHY
3202 | SKY2_HW_NEW_LE
3203 | SKY2_HW_AUTO_TX_SUM
3204 | SKY2_HW_ADV_POWER_CTL;
3205
3206 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3207 hw->flags |= SKY2_HW_RSS_CHKSUM;
3208 break;
3209
3210 case CHIP_ID_YUKON_UL_2:
3211 hw->flags = SKY2_HW_GIGABIT
3212 | SKY2_HW_ADV_POWER_CTL;
3213 break;
3214
3215 case CHIP_ID_YUKON_OPT:
3216 case CHIP_ID_YUKON_PRM:
3217 case CHIP_ID_YUKON_OP_2:
3218 hw->flags = SKY2_HW_GIGABIT
3219 | SKY2_HW_NEW_LE
3220 | SKY2_HW_ADV_POWER_CTL;
3221 break;
3222
3223 default:
3224 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3225 hw->chip_id);
3226 return -EOPNOTSUPP;
3227 }
3228
3229 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3230 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3231 hw->flags |= SKY2_HW_FIBRE_PHY;
3232
3233 hw->ports = 1;
3234 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3235 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3236 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3237 ++hw->ports;
3238 }
3239
3240 if (sky2_read8(hw, B2_E_0))
3241 hw->flags |= SKY2_HW_RAM_BUFFER;
3242
3243 return 0;
3244 }
3245
3246 static void sky2_reset(struct sky2_hw *hw)
3247 {
3248 struct pci_dev *pdev = hw->pdev;
3249 u16 status;
3250 int i;
3251 u32 hwe_mask = Y2_HWE_ALL_MASK;
3252
3253 /* disable ASF */
3254 if (hw->chip_id == CHIP_ID_YUKON_EX
3255 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3256 sky2_write32(hw, CPU_WDOG, 0);
3257 status = sky2_read16(hw, HCU_CCSR);
3258 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3259 HCU_CCSR_UC_STATE_MSK);
3260 /*
3261 * CPU clock divider shouldn't be used because
3262 * - ASF firmware may malfunction
3263 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3264 */
3265 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3266 sky2_write16(hw, HCU_CCSR, status);
3267 sky2_write32(hw, CPU_WDOG, 0);
3268 } else
3269 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3270 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3271
3272 /* do a SW reset */
3273 sky2_write8(hw, B0_CTST, CS_RST_SET);
3274 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3275
3276 /* allow writes to PCI config */
3277 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3278
3279 /* clear PCI errors, if any */
3280 status = sky2_pci_read16(hw, PCI_STATUS);
3281 status |= PCI_STATUS_ERROR_BITS;
3282 sky2_pci_write16(hw, PCI_STATUS, status);
3283
3284 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3285
3286 if (pci_is_pcie(pdev)) {
3287 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3288 0xfffffffful);
3289
3290 /* If error bit is stuck on ignore it */
3291 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3292 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3293 else
3294 hwe_mask |= Y2_IS_PCI_EXP;
3295 }
3296
3297 sky2_power_on(hw);
3298 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3299
3300 for (i = 0; i < hw->ports; i++) {
3301 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3302 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3303
3304 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3305 hw->chip_id == CHIP_ID_YUKON_SUPR)
3306 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3307 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3308 | GMC_BYP_RETR_ON);
3309
3310 }
3311
3312 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3313 /* enable MACSec clock gating */
3314 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3315 }
3316
3317 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3318 hw->chip_id == CHIP_ID_YUKON_PRM ||
3319 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3320 u16 reg;
3321
3322 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3323 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3324 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3325
3326 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3327 reg = 10;
3328
3329 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3330 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3331 } else {
3332 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3333 reg = 3;
3334 }
3335
3336 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3337 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3338
3339 /* reset PHY Link Detect */
3340 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3341 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3342
3343 /* check if PSMv2 was running before */
3344 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3345 if (reg & PCI_EXP_LNKCTL_ASPMC)
3346 /* restore the PCIe Link Control register */
3347 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3348 reg);
3349
3350 if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3351 hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3352 /* change PHY Interrupt polarity to low active */
3353 reg = sky2_read16(hw, GPHY_CTRL);
3354 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
3355
3356 /* adapt HW for low active PHY Interrupt */
3357 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
3358 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
3359 }
3360
3361 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3362
3363 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3364 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3365 }
3366
3367 /* Clear I2C IRQ noise */
3368 sky2_write32(hw, B2_I2C_IRQ, 1);
3369
3370 /* turn off hardware timer (unused) */
3371 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3372 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3373
3374 /* Turn off descriptor polling */
3375 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3376
3377 /* Turn off receive timestamp */
3378 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3379 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3380
3381 /* enable the Tx Arbiters */
3382 for (i = 0; i < hw->ports; i++)
3383 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3384
3385 /* Initialize ram interface */
3386 for (i = 0; i < hw->ports; i++) {
3387 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3388
3389 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3390 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3391 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3392 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3393 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3394 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3395 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3396 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3397 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3398 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3399 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3400 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3401 }
3402
3403 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3404
3405 for (i = 0; i < hw->ports; i++)
3406 sky2_gmac_reset(hw, i);
3407
3408 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3409 hw->st_idx = 0;
3410
3411 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3412 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3413
3414 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3415 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3416
3417 /* Set the list last index */
3418 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3419
3420 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3421 sky2_write8(hw, STAT_FIFO_WM, 16);
3422
3423 /* set Status-FIFO ISR watermark */
3424 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3425 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3426 else
3427 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3428
3429 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3430 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3431 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3432
3433 /* enable status unit */
3434 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3435
3436 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3437 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3438 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3439 }
3440
3441 /* Take device down (offline).
3442 * Equivalent to doing dev_stop() but this does not
3443 * inform upper layers of the transition.
3444 */
3445 static void sky2_detach(struct net_device *dev)
3446 {
3447 if (netif_running(dev)) {
3448 netif_tx_lock(dev);
3449 netif_device_detach(dev); /* stop txq */
3450 netif_tx_unlock(dev);
3451 sky2_close(dev);
3452 }
3453 }
3454
3455 /* Bring device back after doing sky2_detach */
3456 static int sky2_reattach(struct net_device *dev)
3457 {
3458 int err = 0;
3459
3460 if (netif_running(dev)) {
3461 err = sky2_open(dev);
3462 if (err) {
3463 netdev_info(dev, "could not restart %d\n", err);
3464 dev_close(dev);
3465 } else {
3466 netif_device_attach(dev);
3467 sky2_set_multicast(dev);
3468 }
3469 }
3470
3471 return err;
3472 }
3473
3474 static void sky2_all_down(struct sky2_hw *hw)
3475 {
3476 int i;
3477
3478 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3479 sky2_write32(hw, B0_IMSK, 0);
3480 sky2_read32(hw, B0_IMSK);
3481
3482 synchronize_irq(hw->pdev->irq);
3483 napi_disable(&hw->napi);
3484 }
3485
3486 for (i = 0; i < hw->ports; i++) {
3487 struct net_device *dev = hw->dev[i];
3488 struct sky2_port *sky2 = netdev_priv(dev);
3489
3490 if (!netif_running(dev))
3491 continue;
3492
3493 netif_carrier_off(dev);
3494 netif_tx_disable(dev);
3495 sky2_hw_down(sky2);
3496 }
3497 }
3498
3499 static void sky2_all_up(struct sky2_hw *hw)
3500 {
3501 u32 imask = Y2_IS_BASE;
3502 int i;
3503
3504 for (i = 0; i < hw->ports; i++) {
3505 struct net_device *dev = hw->dev[i];
3506 struct sky2_port *sky2 = netdev_priv(dev);
3507
3508 if (!netif_running(dev))
3509 continue;
3510
3511 sky2_hw_up(sky2);
3512 sky2_set_multicast(dev);
3513 imask |= portirq_msk[i];
3514 netif_wake_queue(dev);
3515 }
3516
3517 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3518 sky2_write32(hw, B0_IMSK, imask);
3519 sky2_read32(hw, B0_IMSK);
3520 sky2_read32(hw, B0_Y2_SP_LISR);
3521 napi_enable(&hw->napi);
3522 }
3523 }
3524
3525 static void sky2_restart(struct work_struct *work)
3526 {
3527 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3528
3529 rtnl_lock();
3530
3531 sky2_all_down(hw);
3532 sky2_reset(hw);
3533 sky2_all_up(hw);
3534
3535 rtnl_unlock();
3536 }
3537
3538 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3539 {
3540 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3541 }
3542
3543 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3544 {
3545 const struct sky2_port *sky2 = netdev_priv(dev);
3546
3547 wol->supported = sky2_wol_supported(sky2->hw);
3548 wol->wolopts = sky2->wol;
3549 }
3550
3551 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3552 {
3553 struct sky2_port *sky2 = netdev_priv(dev);
3554 struct sky2_hw *hw = sky2->hw;
3555 bool enable_wakeup = false;
3556 int i;
3557
3558 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3559 !device_can_wakeup(&hw->pdev->dev))
3560 return -EOPNOTSUPP;
3561
3562 sky2->wol = wol->wolopts;
3563
3564 for (i = 0; i < hw->ports; i++) {
3565 struct net_device *dev = hw->dev[i];
3566 struct sky2_port *sky2 = netdev_priv(dev);
3567
3568 if (sky2->wol)
3569 enable_wakeup = true;
3570 }
3571 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3572
3573 return 0;
3574 }
3575
3576 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3577 {
3578 if (sky2_is_copper(hw)) {
3579 u32 modes = SUPPORTED_10baseT_Half
3580 | SUPPORTED_10baseT_Full
3581 | SUPPORTED_100baseT_Half
3582 | SUPPORTED_100baseT_Full;
3583
3584 if (hw->flags & SKY2_HW_GIGABIT)
3585 modes |= SUPPORTED_1000baseT_Half
3586 | SUPPORTED_1000baseT_Full;
3587 return modes;
3588 } else
3589 return SUPPORTED_1000baseT_Half
3590 | SUPPORTED_1000baseT_Full;
3591 }
3592
3593 static int sky2_get_link_ksettings(struct net_device *dev,
3594 struct ethtool_link_ksettings *cmd)
3595 {
3596 struct sky2_port *sky2 = netdev_priv(dev);
3597 struct sky2_hw *hw = sky2->hw;
3598 u32 supported, advertising;
3599
3600 supported = sky2_supported_modes(hw);
3601 cmd->base.phy_address = PHY_ADDR_MARV;
3602 if (sky2_is_copper(hw)) {
3603 cmd->base.port = PORT_TP;
3604 cmd->base.speed = sky2->speed;
3605 supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3606 } else {
3607 cmd->base.speed = SPEED_1000;
3608 cmd->base.port = PORT_FIBRE;
3609 supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3610 }
3611
3612 advertising = sky2->advertising;
3613 cmd->base.autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3614 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3615 cmd->base.duplex = sky2->duplex;
3616
3617 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3618 supported);
3619 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3620 advertising);
3621
3622 return 0;
3623 }
3624
3625 static int sky2_set_link_ksettings(struct net_device *dev,
3626 const struct ethtool_link_ksettings *cmd)
3627 {
3628 struct sky2_port *sky2 = netdev_priv(dev);
3629 const struct sky2_hw *hw = sky2->hw;
3630 u32 supported = sky2_supported_modes(hw);
3631 u32 new_advertising;
3632
3633 ethtool_convert_link_mode_to_legacy_u32(&new_advertising,
3634 cmd->link_modes.advertising);
3635
3636 if (cmd->base.autoneg == AUTONEG_ENABLE) {
3637 if (new_advertising & ~supported)
3638 return -EINVAL;
3639
3640 if (sky2_is_copper(hw))
3641 sky2->advertising = new_advertising |
3642 ADVERTISED_TP |
3643 ADVERTISED_Autoneg;
3644 else
3645 sky2->advertising = new_advertising |
3646 ADVERTISED_FIBRE |
3647 ADVERTISED_Autoneg;
3648
3649 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3650 sky2->duplex = -1;
3651 sky2->speed = -1;
3652 } else {
3653 u32 setting;
3654 u32 speed = cmd->base.speed;
3655
3656 switch (speed) {
3657 case SPEED_1000:
3658 if (cmd->base.duplex == DUPLEX_FULL)
3659 setting = SUPPORTED_1000baseT_Full;
3660 else if (cmd->base.duplex == DUPLEX_HALF)
3661 setting = SUPPORTED_1000baseT_Half;
3662 else
3663 return -EINVAL;
3664 break;
3665 case SPEED_100:
3666 if (cmd->base.duplex == DUPLEX_FULL)
3667 setting = SUPPORTED_100baseT_Full;
3668 else if (cmd->base.duplex == DUPLEX_HALF)
3669 setting = SUPPORTED_100baseT_Half;
3670 else
3671 return -EINVAL;
3672 break;
3673
3674 case SPEED_10:
3675 if (cmd->base.duplex == DUPLEX_FULL)
3676 setting = SUPPORTED_10baseT_Full;
3677 else if (cmd->base.duplex == DUPLEX_HALF)
3678 setting = SUPPORTED_10baseT_Half;
3679 else
3680 return -EINVAL;
3681 break;
3682 default:
3683 return -EINVAL;
3684 }
3685
3686 if ((setting & supported) == 0)
3687 return -EINVAL;
3688
3689 sky2->speed = speed;
3690 sky2->duplex = cmd->base.duplex;
3691 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3692 }
3693
3694 if (netif_running(dev)) {
3695 sky2_phy_reinit(sky2);
3696 sky2_set_multicast(dev);
3697 }
3698
3699 return 0;
3700 }
3701
3702 static void sky2_get_drvinfo(struct net_device *dev,
3703 struct ethtool_drvinfo *info)
3704 {
3705 struct sky2_port *sky2 = netdev_priv(dev);
3706
3707 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
3708 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3709 strlcpy(info->bus_info, pci_name(sky2->hw->pdev),
3710 sizeof(info->bus_info));
3711 }
3712
3713 static const struct sky2_stat {
3714 char name[ETH_GSTRING_LEN];
3715 u16 offset;
3716 } sky2_stats[] = {
3717 { "tx_bytes", GM_TXO_OK_HI },
3718 { "rx_bytes", GM_RXO_OK_HI },
3719 { "tx_broadcast", GM_TXF_BC_OK },
3720 { "rx_broadcast", GM_RXF_BC_OK },
3721 { "tx_multicast", GM_TXF_MC_OK },
3722 { "rx_multicast", GM_RXF_MC_OK },
3723 { "tx_unicast", GM_TXF_UC_OK },
3724 { "rx_unicast", GM_RXF_UC_OK },
3725 { "tx_mac_pause", GM_TXF_MPAUSE },
3726 { "rx_mac_pause", GM_RXF_MPAUSE },
3727 { "collisions", GM_TXF_COL },
3728 { "late_collision",GM_TXF_LAT_COL },
3729 { "aborted", GM_TXF_ABO_COL },
3730 { "single_collisions", GM_TXF_SNG_COL },
3731 { "multi_collisions", GM_TXF_MUL_COL },
3732
3733 { "rx_short", GM_RXF_SHT },
3734 { "rx_runt", GM_RXE_FRAG },
3735 { "rx_64_byte_packets", GM_RXF_64B },
3736 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3737 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3738 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3739 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3740 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3741 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3742 { "rx_too_long", GM_RXF_LNG_ERR },
3743 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3744 { "rx_jabber", GM_RXF_JAB_PKT },
3745 { "rx_fcs_error", GM_RXF_FCS_ERR },
3746
3747 { "tx_64_byte_packets", GM_TXF_64B },
3748 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3749 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3750 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3751 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3752 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3753 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3754 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3755 };
3756
3757 static u32 sky2_get_msglevel(struct net_device *netdev)
3758 {
3759 struct sky2_port *sky2 = netdev_priv(netdev);
3760 return sky2->msg_enable;
3761 }
3762
3763 static int sky2_nway_reset(struct net_device *dev)
3764 {
3765 struct sky2_port *sky2 = netdev_priv(dev);
3766
3767 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3768 return -EINVAL;
3769
3770 sky2_phy_reinit(sky2);
3771 sky2_set_multicast(dev);
3772
3773 return 0;
3774 }
3775
3776 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3777 {
3778 struct sky2_hw *hw = sky2->hw;
3779 unsigned port = sky2->port;
3780 int i;
3781
3782 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3783 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3784
3785 for (i = 2; i < count; i++)
3786 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3787 }
3788
3789 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3790 {
3791 struct sky2_port *sky2 = netdev_priv(netdev);
3792 sky2->msg_enable = value;
3793 }
3794
3795 static int sky2_get_sset_count(struct net_device *dev, int sset)
3796 {
3797 switch (sset) {
3798 case ETH_SS_STATS:
3799 return ARRAY_SIZE(sky2_stats);
3800 default:
3801 return -EOPNOTSUPP;
3802 }
3803 }
3804
3805 static void sky2_get_ethtool_stats(struct net_device *dev,
3806 struct ethtool_stats *stats, u64 * data)
3807 {
3808 struct sky2_port *sky2 = netdev_priv(dev);
3809
3810 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3811 }
3812
3813 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3814 {
3815 int i;
3816
3817 switch (stringset) {
3818 case ETH_SS_STATS:
3819 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3820 memcpy(data + i * ETH_GSTRING_LEN,
3821 sky2_stats[i].name, ETH_GSTRING_LEN);
3822 break;
3823 }
3824 }
3825
3826 static int sky2_set_mac_address(struct net_device *dev, void *p)
3827 {
3828 struct sky2_port *sky2 = netdev_priv(dev);
3829 struct sky2_hw *hw = sky2->hw;
3830 unsigned port = sky2->port;
3831 const struct sockaddr *addr = p;
3832
3833 if (!is_valid_ether_addr(addr->sa_data))
3834 return -EADDRNOTAVAIL;
3835
3836 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3837 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3838 dev->dev_addr, ETH_ALEN);
3839 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3840 dev->dev_addr, ETH_ALEN);
3841
3842 /* virtual address for data */
3843 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3844
3845 /* physical address: used for pause frames */
3846 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3847
3848 return 0;
3849 }
3850
3851 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3852 {
3853 u32 bit;
3854
3855 bit = ether_crc(ETH_ALEN, addr) & 63;
3856 filter[bit >> 3] |= 1 << (bit & 7);
3857 }
3858
3859 static void sky2_set_multicast(struct net_device *dev)
3860 {
3861 struct sky2_port *sky2 = netdev_priv(dev);
3862 struct sky2_hw *hw = sky2->hw;
3863 unsigned port = sky2->port;
3864 struct netdev_hw_addr *ha;
3865 u16 reg;
3866 u8 filter[8];
3867 int rx_pause;
3868 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3869
3870 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3871 memset(filter, 0, sizeof(filter));
3872
3873 reg = gma_read16(hw, port, GM_RX_CTRL);
3874 reg |= GM_RXCR_UCF_ENA;
3875
3876 if (dev->flags & IFF_PROMISC) /* promiscuous */
3877 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3878 else if (dev->flags & IFF_ALLMULTI)
3879 memset(filter, 0xff, sizeof(filter));
3880 else if (netdev_mc_empty(dev) && !rx_pause)
3881 reg &= ~GM_RXCR_MCF_ENA;
3882 else {
3883 reg |= GM_RXCR_MCF_ENA;
3884
3885 if (rx_pause)
3886 sky2_add_filter(filter, pause_mc_addr);
3887
3888 netdev_for_each_mc_addr(ha, dev)
3889 sky2_add_filter(filter, ha->addr);
3890 }
3891
3892 gma_write16(hw, port, GM_MC_ADDR_H1,
3893 (u16) filter[0] | ((u16) filter[1] << 8));
3894 gma_write16(hw, port, GM_MC_ADDR_H2,
3895 (u16) filter[2] | ((u16) filter[3] << 8));
3896 gma_write16(hw, port, GM_MC_ADDR_H3,
3897 (u16) filter[4] | ((u16) filter[5] << 8));
3898 gma_write16(hw, port, GM_MC_ADDR_H4,
3899 (u16) filter[6] | ((u16) filter[7] << 8));
3900
3901 gma_write16(hw, port, GM_RX_CTRL, reg);
3902 }
3903
3904 static void sky2_get_stats(struct net_device *dev,
3905 struct rtnl_link_stats64 *stats)
3906 {
3907 struct sky2_port *sky2 = netdev_priv(dev);
3908 struct sky2_hw *hw = sky2->hw;
3909 unsigned port = sky2->port;
3910 unsigned int start;
3911 u64 _bytes, _packets;
3912
3913 do {
3914 start = u64_stats_fetch_begin_irq(&sky2->rx_stats.syncp);
3915 _bytes = sky2->rx_stats.bytes;
3916 _packets = sky2->rx_stats.packets;
3917 } while (u64_stats_fetch_retry_irq(&sky2->rx_stats.syncp, start));
3918
3919 stats->rx_packets = _packets;
3920 stats->rx_bytes = _bytes;
3921
3922 do {
3923 start = u64_stats_fetch_begin_irq(&sky2->tx_stats.syncp);
3924 _bytes = sky2->tx_stats.bytes;
3925 _packets = sky2->tx_stats.packets;
3926 } while (u64_stats_fetch_retry_irq(&sky2->tx_stats.syncp, start));
3927
3928 stats->tx_packets = _packets;
3929 stats->tx_bytes = _bytes;
3930
3931 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3932 + get_stats32(hw, port, GM_RXF_BC_OK);
3933
3934 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3935
3936 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3937 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3938 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3939 + get_stats32(hw, port, GM_RXE_FRAG);
3940 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3941
3942 stats->rx_dropped = dev->stats.rx_dropped;
3943 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3944 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3945 }
3946
3947 /* Can have one global because blinking is controlled by
3948 * ethtool and that is always under RTNL mutex
3949 */
3950 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3951 {
3952 struct sky2_hw *hw = sky2->hw;
3953 unsigned port = sky2->port;
3954
3955 spin_lock_bh(&sky2->phy_lock);
3956 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3957 hw->chip_id == CHIP_ID_YUKON_EX ||
3958 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3959 u16 pg;
3960 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3961 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3962
3963 switch (mode) {
3964 case MO_LED_OFF:
3965 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3966 PHY_M_LEDC_LOS_CTRL(8) |
3967 PHY_M_LEDC_INIT_CTRL(8) |
3968 PHY_M_LEDC_STA1_CTRL(8) |
3969 PHY_M_LEDC_STA0_CTRL(8));
3970 break;
3971 case MO_LED_ON:
3972 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3973 PHY_M_LEDC_LOS_CTRL(9) |
3974 PHY_M_LEDC_INIT_CTRL(9) |
3975 PHY_M_LEDC_STA1_CTRL(9) |
3976 PHY_M_LEDC_STA0_CTRL(9));
3977 break;
3978 case MO_LED_BLINK:
3979 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3980 PHY_M_LEDC_LOS_CTRL(0xa) |
3981 PHY_M_LEDC_INIT_CTRL(0xa) |
3982 PHY_M_LEDC_STA1_CTRL(0xa) |
3983 PHY_M_LEDC_STA0_CTRL(0xa));
3984 break;
3985 case MO_LED_NORM:
3986 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3987 PHY_M_LEDC_LOS_CTRL(1) |
3988 PHY_M_LEDC_INIT_CTRL(8) |
3989 PHY_M_LEDC_STA1_CTRL(7) |
3990 PHY_M_LEDC_STA0_CTRL(7));
3991 }
3992
3993 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3994 } else
3995 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3996 PHY_M_LED_MO_DUP(mode) |
3997 PHY_M_LED_MO_10(mode) |
3998 PHY_M_LED_MO_100(mode) |
3999 PHY_M_LED_MO_1000(mode) |
4000 PHY_M_LED_MO_RX(mode) |
4001 PHY_M_LED_MO_TX(mode));
4002
4003 spin_unlock_bh(&sky2->phy_lock);
4004 }
4005
4006 /* blink LED's for finding board */
4007 static int sky2_set_phys_id(struct net_device *dev,
4008 enum ethtool_phys_id_state state)
4009 {
4010 struct sky2_port *sky2 = netdev_priv(dev);
4011
4012 switch (state) {
4013 case ETHTOOL_ID_ACTIVE:
4014 return 1; /* cycle on/off once per second */
4015 case ETHTOOL_ID_INACTIVE:
4016 sky2_led(sky2, MO_LED_NORM);
4017 break;
4018 case ETHTOOL_ID_ON:
4019 sky2_led(sky2, MO_LED_ON);
4020 break;
4021 case ETHTOOL_ID_OFF:
4022 sky2_led(sky2, MO_LED_OFF);
4023 break;
4024 }
4025
4026 return 0;
4027 }
4028
4029 static void sky2_get_pauseparam(struct net_device *dev,
4030 struct ethtool_pauseparam *ecmd)
4031 {
4032 struct sky2_port *sky2 = netdev_priv(dev);
4033
4034 switch (sky2->flow_mode) {
4035 case FC_NONE:
4036 ecmd->tx_pause = ecmd->rx_pause = 0;
4037 break;
4038 case FC_TX:
4039 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
4040 break;
4041 case FC_RX:
4042 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
4043 break;
4044 case FC_BOTH:
4045 ecmd->tx_pause = ecmd->rx_pause = 1;
4046 }
4047
4048 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
4049 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
4050 }
4051
4052 static int sky2_set_pauseparam(struct net_device *dev,
4053 struct ethtool_pauseparam *ecmd)
4054 {
4055 struct sky2_port *sky2 = netdev_priv(dev);
4056
4057 if (ecmd->autoneg == AUTONEG_ENABLE)
4058 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
4059 else
4060 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
4061
4062 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
4063
4064 if (netif_running(dev))
4065 sky2_phy_reinit(sky2);
4066
4067 return 0;
4068 }
4069
4070 static int sky2_get_coalesce(struct net_device *dev,
4071 struct ethtool_coalesce *ecmd)
4072 {
4073 struct sky2_port *sky2 = netdev_priv(dev);
4074 struct sky2_hw *hw = sky2->hw;
4075
4076 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4077 ecmd->tx_coalesce_usecs = 0;
4078 else {
4079 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4080 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4081 }
4082 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4083
4084 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4085 ecmd->rx_coalesce_usecs = 0;
4086 else {
4087 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4088 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4089 }
4090 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4091
4092 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4093 ecmd->rx_coalesce_usecs_irq = 0;
4094 else {
4095 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4096 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4097 }
4098
4099 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4100
4101 return 0;
4102 }
4103
4104 /* Note: this affect both ports */
4105 static int sky2_set_coalesce(struct net_device *dev,
4106 struct ethtool_coalesce *ecmd)
4107 {
4108 struct sky2_port *sky2 = netdev_priv(dev);
4109 struct sky2_hw *hw = sky2->hw;
4110 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4111
4112 if (ecmd->tx_coalesce_usecs > tmax ||
4113 ecmd->rx_coalesce_usecs > tmax ||
4114 ecmd->rx_coalesce_usecs_irq > tmax)
4115 return -EINVAL;
4116
4117 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4118 return -EINVAL;
4119 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4120 return -EINVAL;
4121 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4122 return -EINVAL;
4123
4124 if (ecmd->tx_coalesce_usecs == 0)
4125 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4126 else {
4127 sky2_write32(hw, STAT_TX_TIMER_INI,
4128 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4129 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4130 }
4131 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4132
4133 if (ecmd->rx_coalesce_usecs == 0)
4134 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4135 else {
4136 sky2_write32(hw, STAT_LEV_TIMER_INI,
4137 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4138 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4139 }
4140 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4141
4142 if (ecmd->rx_coalesce_usecs_irq == 0)
4143 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4144 else {
4145 sky2_write32(hw, STAT_ISR_TIMER_INI,
4146 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4147 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4148 }
4149 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4150 return 0;
4151 }
4152
4153 /*
4154 * Hardware is limited to min of 128 and max of 2048 for ring size
4155 * and rounded up to next power of two
4156 * to avoid division in modulus calclation
4157 */
4158 static unsigned long roundup_ring_size(unsigned long pending)
4159 {
4160 return max(128ul, roundup_pow_of_two(pending+1));
4161 }
4162
4163 static void sky2_get_ringparam(struct net_device *dev,
4164 struct ethtool_ringparam *ering)
4165 {
4166 struct sky2_port *sky2 = netdev_priv(dev);
4167
4168 ering->rx_max_pending = RX_MAX_PENDING;
4169 ering->tx_max_pending = TX_MAX_PENDING;
4170
4171 ering->rx_pending = sky2->rx_pending;
4172 ering->tx_pending = sky2->tx_pending;
4173 }
4174
4175 static int sky2_set_ringparam(struct net_device *dev,
4176 struct ethtool_ringparam *ering)
4177 {
4178 struct sky2_port *sky2 = netdev_priv(dev);
4179
4180 if (ering->rx_pending > RX_MAX_PENDING ||
4181 ering->rx_pending < 8 ||
4182 ering->tx_pending < TX_MIN_PENDING ||
4183 ering->tx_pending > TX_MAX_PENDING)
4184 return -EINVAL;
4185
4186 sky2_detach(dev);
4187
4188 sky2->rx_pending = ering->rx_pending;
4189 sky2->tx_pending = ering->tx_pending;
4190 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending);
4191
4192 return sky2_reattach(dev);
4193 }
4194
4195 static int sky2_get_regs_len(struct net_device *dev)
4196 {
4197 return 0x4000;
4198 }
4199
4200 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4201 {
4202 /* This complicated switch statement is to make sure and
4203 * only access regions that are unreserved.
4204 * Some blocks are only valid on dual port cards.
4205 */
4206 switch (b) {
4207 /* second port */
4208 case 5: /* Tx Arbiter 2 */
4209 case 9: /* RX2 */
4210 case 14 ... 15: /* TX2 */
4211 case 17: case 19: /* Ram Buffer 2 */
4212 case 22 ... 23: /* Tx Ram Buffer 2 */
4213 case 25: /* Rx MAC Fifo 1 */
4214 case 27: /* Tx MAC Fifo 2 */
4215 case 31: /* GPHY 2 */
4216 case 40 ... 47: /* Pattern Ram 2 */
4217 case 52: case 54: /* TCP Segmentation 2 */
4218 case 112 ... 116: /* GMAC 2 */
4219 return hw->ports > 1;
4220
4221 case 0: /* Control */
4222 case 2: /* Mac address */
4223 case 4: /* Tx Arbiter 1 */
4224 case 7: /* PCI express reg */
4225 case 8: /* RX1 */
4226 case 12 ... 13: /* TX1 */
4227 case 16: case 18:/* Rx Ram Buffer 1 */
4228 case 20 ... 21: /* Tx Ram Buffer 1 */
4229 case 24: /* Rx MAC Fifo 1 */
4230 case 26: /* Tx MAC Fifo 1 */
4231 case 28 ... 29: /* Descriptor and status unit */
4232 case 30: /* GPHY 1*/
4233 case 32 ... 39: /* Pattern Ram 1 */
4234 case 48: case 50: /* TCP Segmentation 1 */
4235 case 56 ... 60: /* PCI space */
4236 case 80 ... 84: /* GMAC 1 */
4237 return 1;
4238
4239 default:
4240 return 0;
4241 }
4242 }
4243
4244 /*
4245 * Returns copy of control register region
4246 * Note: ethtool_get_regs always provides full size (16k) buffer
4247 */
4248 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4249 void *p)
4250 {
4251 const struct sky2_port *sky2 = netdev_priv(dev);
4252 const void __iomem *io = sky2->hw->regs;
4253 unsigned int b;
4254
4255 regs->version = 1;
4256
4257 for (b = 0; b < 128; b++) {
4258 /* skip poisonous diagnostic ram region in block 3 */
4259 if (b == 3)
4260 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4261 else if (sky2_reg_access_ok(sky2->hw, b))
4262 memcpy_fromio(p, io, 128);
4263 else
4264 memset(p, 0, 128);
4265
4266 p += 128;
4267 io += 128;
4268 }
4269 }
4270
4271 static int sky2_get_eeprom_len(struct net_device *dev)
4272 {
4273 struct sky2_port *sky2 = netdev_priv(dev);
4274 struct sky2_hw *hw = sky2->hw;
4275 u16 reg2;
4276
4277 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4278 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4279 }
4280
4281 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4282 {
4283 unsigned long start = jiffies;
4284
4285 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4286 /* Can take up to 10.6 ms for write */
4287 if (time_after(jiffies, start + HZ/4)) {
4288 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4289 return -ETIMEDOUT;
4290 }
4291 msleep(1);
4292 }
4293
4294 return 0;
4295 }
4296
4297 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4298 u16 offset, size_t length)
4299 {
4300 int rc = 0;
4301
4302 while (length > 0) {
4303 u32 val;
4304
4305 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4306 rc = sky2_vpd_wait(hw, cap, 0);
4307 if (rc)
4308 break;
4309
4310 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4311
4312 memcpy(data, &val, min(sizeof(val), length));
4313 offset += sizeof(u32);
4314 data += sizeof(u32);
4315 length -= sizeof(u32);
4316 }
4317
4318 return rc;
4319 }
4320
4321 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4322 u16 offset, unsigned int length)
4323 {
4324 unsigned int i;
4325 int rc = 0;
4326
4327 for (i = 0; i < length; i += sizeof(u32)) {
4328 u32 val = *(u32 *)(data + i);
4329
4330 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4331 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4332
4333 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4334 if (rc)
4335 break;
4336 }
4337 return rc;
4338 }
4339
4340 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4341 u8 *data)
4342 {
4343 struct sky2_port *sky2 = netdev_priv(dev);
4344 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4345
4346 if (!cap)
4347 return -EINVAL;
4348
4349 eeprom->magic = SKY2_EEPROM_MAGIC;
4350
4351 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4352 }
4353
4354 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4355 u8 *data)
4356 {
4357 struct sky2_port *sky2 = netdev_priv(dev);
4358 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4359
4360 if (!cap)
4361 return -EINVAL;
4362
4363 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4364 return -EINVAL;
4365
4366 /* Partial writes not supported */
4367 if ((eeprom->offset & 3) || (eeprom->len & 3))
4368 return -EINVAL;
4369
4370 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4371 }
4372
4373 static netdev_features_t sky2_fix_features(struct net_device *dev,
4374 netdev_features_t features)
4375 {
4376 const struct sky2_port *sky2 = netdev_priv(dev);
4377 const struct sky2_hw *hw = sky2->hw;
4378
4379 /* In order to do Jumbo packets on these chips, need to turn off the
4380 * transmit store/forward. Therefore checksum offload won't work.
4381 */
4382 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4383 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4384 features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_CSUM_MASK);
4385 }
4386
4387 /* Some hardware requires receive checksum for RSS to work. */
4388 if ( (features & NETIF_F_RXHASH) &&
4389 !(features & NETIF_F_RXCSUM) &&
4390 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4391 netdev_info(dev, "receive hashing forces receive checksum\n");
4392 features |= NETIF_F_RXCSUM;
4393 }
4394
4395 return features;
4396 }
4397
4398 static int sky2_set_features(struct net_device *dev, netdev_features_t features)
4399 {
4400 struct sky2_port *sky2 = netdev_priv(dev);
4401 netdev_features_t changed = dev->features ^ features;
4402
4403 if ((changed & NETIF_F_RXCSUM) &&
4404 !(sky2->hw->flags & SKY2_HW_NEW_LE)) {
4405 sky2_write32(sky2->hw,
4406 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4407 (features & NETIF_F_RXCSUM)
4408 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4409 }
4410
4411 if (changed & NETIF_F_RXHASH)
4412 rx_set_rss(dev, features);
4413
4414 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4415 sky2_vlan_mode(dev, features);
4416
4417 return 0;
4418 }
4419
4420 static const struct ethtool_ops sky2_ethtool_ops = {
4421 .get_drvinfo = sky2_get_drvinfo,
4422 .get_wol = sky2_get_wol,
4423 .set_wol = sky2_set_wol,
4424 .get_msglevel = sky2_get_msglevel,
4425 .set_msglevel = sky2_set_msglevel,
4426 .nway_reset = sky2_nway_reset,
4427 .get_regs_len = sky2_get_regs_len,
4428 .get_regs = sky2_get_regs,
4429 .get_link = ethtool_op_get_link,
4430 .get_eeprom_len = sky2_get_eeprom_len,
4431 .get_eeprom = sky2_get_eeprom,
4432 .set_eeprom = sky2_set_eeprom,
4433 .get_strings = sky2_get_strings,
4434 .get_coalesce = sky2_get_coalesce,
4435 .set_coalesce = sky2_set_coalesce,
4436 .get_ringparam = sky2_get_ringparam,
4437 .set_ringparam = sky2_set_ringparam,
4438 .get_pauseparam = sky2_get_pauseparam,
4439 .set_pauseparam = sky2_set_pauseparam,
4440 .set_phys_id = sky2_set_phys_id,
4441 .get_sset_count = sky2_get_sset_count,
4442 .get_ethtool_stats = sky2_get_ethtool_stats,
4443 .get_link_ksettings = sky2_get_link_ksettings,
4444 .set_link_ksettings = sky2_set_link_ksettings,
4445 };
4446
4447 #ifdef CONFIG_SKY2_DEBUG
4448
4449 static struct dentry *sky2_debug;
4450
4451
4452 /*
4453 * Read and parse the first part of Vital Product Data
4454 */
4455 #define VPD_SIZE 128
4456 #define VPD_MAGIC 0x82
4457
4458 static const struct vpd_tag {
4459 char tag[2];
4460 char *label;
4461 } vpd_tags[] = {
4462 { "PN", "Part Number" },
4463 { "EC", "Engineering Level" },
4464 { "MN", "Manufacturer" },
4465 { "SN", "Serial Number" },
4466 { "YA", "Asset Tag" },
4467 { "VL", "First Error Log Message" },
4468 { "VF", "Second Error Log Message" },
4469 { "VB", "Boot Agent ROM Configuration" },
4470 { "VE", "EFI UNDI Configuration" },
4471 };
4472
4473 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4474 {
4475 size_t vpd_size;
4476 loff_t offs;
4477 u8 len;
4478 unsigned char *buf;
4479 u16 reg2;
4480
4481 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4482 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4483
4484 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4485 buf = kmalloc(vpd_size, GFP_KERNEL);
4486 if (!buf) {
4487 seq_puts(seq, "no memory!\n");
4488 return;
4489 }
4490
4491 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4492 seq_puts(seq, "VPD read failed\n");
4493 goto out;
4494 }
4495
4496 if (buf[0] != VPD_MAGIC) {
4497 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4498 goto out;
4499 }
4500 len = buf[1];
4501 if (len == 0 || len > vpd_size - 4) {
4502 seq_printf(seq, "Invalid id length: %d\n", len);
4503 goto out;
4504 }
4505
4506 seq_printf(seq, "%.*s\n", len, buf + 3);
4507 offs = len + 3;
4508
4509 while (offs < vpd_size - 4) {
4510 int i;
4511
4512 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4513 break;
4514 len = buf[offs + 2];
4515 if (offs + len + 3 >= vpd_size)
4516 break;
4517
4518 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4519 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4520 seq_printf(seq, " %s: %.*s\n",
4521 vpd_tags[i].label, len, buf + offs + 3);
4522 break;
4523 }
4524 }
4525 offs += len + 3;
4526 }
4527 out:
4528 kfree(buf);
4529 }
4530
4531 static int sky2_debug_show(struct seq_file *seq, void *v)
4532 {
4533 struct net_device *dev = seq->private;
4534 const struct sky2_port *sky2 = netdev_priv(dev);
4535 struct sky2_hw *hw = sky2->hw;
4536 unsigned port = sky2->port;
4537 unsigned idx, last;
4538 int sop;
4539
4540 sky2_show_vpd(seq, hw);
4541
4542 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4543 sky2_read32(hw, B0_ISRC),
4544 sky2_read32(hw, B0_IMSK),
4545 sky2_read32(hw, B0_Y2_SP_ICR));
4546
4547 if (!netif_running(dev)) {
4548 seq_puts(seq, "network not running\n");
4549 return 0;
4550 }
4551
4552 napi_disable(&hw->napi);
4553 last = sky2_read16(hw, STAT_PUT_IDX);
4554
4555 seq_printf(seq, "Status ring %u\n", hw->st_size);
4556 if (hw->st_idx == last)
4557 seq_puts(seq, "Status ring (empty)\n");
4558 else {
4559 seq_puts(seq, "Status ring\n");
4560 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4561 idx = RING_NEXT(idx, hw->st_size)) {
4562 const struct sky2_status_le *le = hw->st_le + idx;
4563 seq_printf(seq, "[%d] %#x %d %#x\n",
4564 idx, le->opcode, le->length, le->status);
4565 }
4566 seq_puts(seq, "\n");
4567 }
4568
4569 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4570 sky2->tx_cons, sky2->tx_prod,
4571 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4572 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4573
4574 /* Dump contents of tx ring */
4575 sop = 1;
4576 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4577 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4578 const struct sky2_tx_le *le = sky2->tx_le + idx;
4579 u32 a = le32_to_cpu(le->addr);
4580
4581 if (sop)
4582 seq_printf(seq, "%u:", idx);
4583 sop = 0;
4584
4585 switch (le->opcode & ~HW_OWNER) {
4586 case OP_ADDR64:
4587 seq_printf(seq, " %#x:", a);
4588 break;
4589 case OP_LRGLEN:
4590 seq_printf(seq, " mtu=%d", a);
4591 break;
4592 case OP_VLAN:
4593 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4594 break;
4595 case OP_TCPLISW:
4596 seq_printf(seq, " csum=%#x", a);
4597 break;
4598 case OP_LARGESEND:
4599 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4600 break;
4601 case OP_PACKET:
4602 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4603 break;
4604 case OP_BUFFER:
4605 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4606 break;
4607 default:
4608 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4609 a, le16_to_cpu(le->length));
4610 }
4611
4612 if (le->ctrl & EOP) {
4613 seq_putc(seq, '\n');
4614 sop = 1;
4615 }
4616 }
4617
4618 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4619 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4620 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4621 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4622
4623 sky2_read32(hw, B0_Y2_SP_LISR);
4624 napi_enable(&hw->napi);
4625 return 0;
4626 }
4627
4628 static int sky2_debug_open(struct inode *inode, struct file *file)
4629 {
4630 return single_open(file, sky2_debug_show, inode->i_private);
4631 }
4632
4633 static const struct file_operations sky2_debug_fops = {
4634 .owner = THIS_MODULE,
4635 .open = sky2_debug_open,
4636 .read = seq_read,
4637 .llseek = seq_lseek,
4638 .release = single_release,
4639 };
4640
4641 /*
4642 * Use network device events to create/remove/rename
4643 * debugfs file entries
4644 */
4645 static int sky2_device_event(struct notifier_block *unused,
4646 unsigned long event, void *ptr)
4647 {
4648 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4649 struct sky2_port *sky2 = netdev_priv(dev);
4650
4651 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4652 return NOTIFY_DONE;
4653
4654 switch (event) {
4655 case NETDEV_CHANGENAME:
4656 if (sky2->debugfs) {
4657 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4658 sky2_debug, dev->name);
4659 }
4660 break;
4661
4662 case NETDEV_GOING_DOWN:
4663 if (sky2->debugfs) {
4664 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4665 debugfs_remove(sky2->debugfs);
4666 sky2->debugfs = NULL;
4667 }
4668 break;
4669
4670 case NETDEV_UP:
4671 sky2->debugfs = debugfs_create_file(dev->name, 0444,
4672 sky2_debug, dev,
4673 &sky2_debug_fops);
4674 if (IS_ERR(sky2->debugfs))
4675 sky2->debugfs = NULL;
4676 }
4677
4678 return NOTIFY_DONE;
4679 }
4680
4681 static struct notifier_block sky2_notifier = {
4682 .notifier_call = sky2_device_event,
4683 };
4684
4685
4686 static __init void sky2_debug_init(void)
4687 {
4688 struct dentry *ent;
4689
4690 ent = debugfs_create_dir("sky2", NULL);
4691 if (!ent || IS_ERR(ent))
4692 return;
4693
4694 sky2_debug = ent;
4695 register_netdevice_notifier(&sky2_notifier);
4696 }
4697
4698 static __exit void sky2_debug_cleanup(void)
4699 {
4700 if (sky2_debug) {
4701 unregister_netdevice_notifier(&sky2_notifier);
4702 debugfs_remove(sky2_debug);
4703 sky2_debug = NULL;
4704 }
4705 }
4706
4707 #else
4708 #define sky2_debug_init()
4709 #define sky2_debug_cleanup()
4710 #endif
4711
4712 /* Two copies of network device operations to handle special case of
4713 not allowing netpoll on second port */
4714 static const struct net_device_ops sky2_netdev_ops[2] = {
4715 {
4716 .ndo_open = sky2_open,
4717 .ndo_stop = sky2_close,
4718 .ndo_start_xmit = sky2_xmit_frame,
4719 .ndo_do_ioctl = sky2_ioctl,
4720 .ndo_validate_addr = eth_validate_addr,
4721 .ndo_set_mac_address = sky2_set_mac_address,
4722 .ndo_set_rx_mode = sky2_set_multicast,
4723 .ndo_change_mtu = sky2_change_mtu,
4724 .ndo_fix_features = sky2_fix_features,
4725 .ndo_set_features = sky2_set_features,
4726 .ndo_tx_timeout = sky2_tx_timeout,
4727 .ndo_get_stats64 = sky2_get_stats,
4728 #ifdef CONFIG_NET_POLL_CONTROLLER
4729 .ndo_poll_controller = sky2_netpoll,
4730 #endif
4731 },
4732 {
4733 .ndo_open = sky2_open,
4734 .ndo_stop = sky2_close,
4735 .ndo_start_xmit = sky2_xmit_frame,
4736 .ndo_do_ioctl = sky2_ioctl,
4737 .ndo_validate_addr = eth_validate_addr,
4738 .ndo_set_mac_address = sky2_set_mac_address,
4739 .ndo_set_rx_mode = sky2_set_multicast,
4740 .ndo_change_mtu = sky2_change_mtu,
4741 .ndo_fix_features = sky2_fix_features,
4742 .ndo_set_features = sky2_set_features,
4743 .ndo_tx_timeout = sky2_tx_timeout,
4744 .ndo_get_stats64 = sky2_get_stats,
4745 },
4746 };
4747
4748 /* Initialize network device */
4749 static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
4750 int highmem, int wol)
4751 {
4752 struct sky2_port *sky2;
4753 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4754 const void *iap;
4755
4756 if (!dev)
4757 return NULL;
4758
4759 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4760 dev->irq = hw->pdev->irq;
4761 dev->ethtool_ops = &sky2_ethtool_ops;
4762 dev->watchdog_timeo = TX_WATCHDOG;
4763 dev->netdev_ops = &sky2_netdev_ops[port];
4764
4765 sky2 = netdev_priv(dev);
4766 sky2->netdev = dev;
4767 sky2->hw = hw;
4768 sky2->msg_enable = netif_msg_init(debug, default_msg);
4769
4770 u64_stats_init(&sky2->tx_stats.syncp);
4771 u64_stats_init(&sky2->rx_stats.syncp);
4772
4773 /* Auto speed and flow control */
4774 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4775 if (hw->chip_id != CHIP_ID_YUKON_XL)
4776 dev->hw_features |= NETIF_F_RXCSUM;
4777
4778 sky2->flow_mode = FC_BOTH;
4779
4780 sky2->duplex = -1;
4781 sky2->speed = -1;
4782 sky2->advertising = sky2_supported_modes(hw);
4783 sky2->wol = wol;
4784
4785 spin_lock_init(&sky2->phy_lock);
4786
4787 sky2->tx_pending = TX_DEF_PENDING;
4788 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING);
4789 sky2->rx_pending = RX_DEF_PENDING;
4790
4791 hw->dev[port] = dev;
4792
4793 sky2->port = port;
4794
4795 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4796
4797 if (highmem)
4798 dev->features |= NETIF_F_HIGHDMA;
4799
4800 /* Enable receive hashing unless hardware is known broken */
4801 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4802 dev->hw_features |= NETIF_F_RXHASH;
4803
4804 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4805 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
4806 NETIF_F_HW_VLAN_CTAG_RX;
4807 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4808 }
4809
4810 dev->features |= dev->hw_features;
4811
4812 /* MTU range: 60 - 1500 or 9000 */
4813 dev->min_mtu = ETH_ZLEN;
4814 if (hw->chip_id == CHIP_ID_YUKON_FE ||
4815 hw->chip_id == CHIP_ID_YUKON_FE_P)
4816 dev->max_mtu = ETH_DATA_LEN;
4817 else
4818 dev->max_mtu = ETH_JUMBO_MTU;
4819
4820 /* try to get mac address in the following order:
4821 * 1) from device tree data
4822 * 2) from internal registers set by bootloader
4823 */
4824 iap = of_get_mac_address(hw->pdev->dev.of_node);
4825 if (iap)
4826 memcpy(dev->dev_addr, iap, ETH_ALEN);
4827 else
4828 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8,
4829 ETH_ALEN);
4830
4831 /* if the address is invalid, use a random value */
4832 if (!is_valid_ether_addr(dev->dev_addr)) {
4833 struct sockaddr sa = { AF_UNSPEC };
4834
4835 netdev_warn(dev,
4836 "Invalid MAC address, defaulting to random\n");
4837 eth_hw_addr_random(dev);
4838 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
4839 if (sky2_set_mac_address(dev, &sa))
4840 netdev_warn(dev, "Failed to set MAC address.\n");
4841 }
4842
4843 return dev;
4844 }
4845
4846 static void sky2_show_addr(struct net_device *dev)
4847 {
4848 const struct sky2_port *sky2 = netdev_priv(dev);
4849
4850 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4851 }
4852
4853 /* Handle software interrupt used during MSI test */
4854 static irqreturn_t sky2_test_intr(int irq, void *dev_id)
4855 {
4856 struct sky2_hw *hw = dev_id;
4857 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4858
4859 if (status == 0)
4860 return IRQ_NONE;
4861
4862 if (status & Y2_IS_IRQ_SW) {
4863 hw->flags |= SKY2_HW_USE_MSI;
4864 wake_up(&hw->msi_wait);
4865 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4866 }
4867 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4868
4869 return IRQ_HANDLED;
4870 }
4871
4872 /* Test interrupt path by forcing a a software IRQ */
4873 static int sky2_test_msi(struct sky2_hw *hw)
4874 {
4875 struct pci_dev *pdev = hw->pdev;
4876 int err;
4877
4878 init_waitqueue_head(&hw->msi_wait);
4879
4880 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4881 if (err) {
4882 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4883 return err;
4884 }
4885
4886 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4887
4888 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4889 sky2_read8(hw, B0_CTST);
4890
4891 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4892
4893 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4894 /* MSI test failed, go back to INTx mode */
4895 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4896 "switching to INTx mode.\n");
4897
4898 err = -EOPNOTSUPP;
4899 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4900 }
4901
4902 sky2_write32(hw, B0_IMSK, 0);
4903 sky2_read32(hw, B0_IMSK);
4904
4905 free_irq(pdev->irq, hw);
4906
4907 return err;
4908 }
4909
4910 /* This driver supports yukon2 chipset only */
4911 static const char *sky2_name(u8 chipid, char *buf, int sz)
4912 {
4913 const char *name[] = {
4914 "XL", /* 0xb3 */
4915 "EC Ultra", /* 0xb4 */
4916 "Extreme", /* 0xb5 */
4917 "EC", /* 0xb6 */
4918 "FE", /* 0xb7 */
4919 "FE+", /* 0xb8 */
4920 "Supreme", /* 0xb9 */
4921 "UL 2", /* 0xba */
4922 "Unknown", /* 0xbb */
4923 "Optima", /* 0xbc */
4924 "OptimaEEE", /* 0xbd */
4925 "Optima 2", /* 0xbe */
4926 };
4927
4928 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4929 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4930 else
4931 snprintf(buf, sz, "(chip %#x)", chipid);
4932 return buf;
4933 }
4934
4935 static const struct dmi_system_id msi_blacklist[] = {
4936 {
4937 .ident = "Dell Inspiron 1545",
4938 .matches = {
4939 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
4940 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 1545"),
4941 },
4942 },
4943 {
4944 .ident = "Gateway P-79",
4945 .matches = {
4946 DMI_MATCH(DMI_SYS_VENDOR, "Gateway"),
4947 DMI_MATCH(DMI_PRODUCT_NAME, "P-79"),
4948 },
4949 },
4950 {
4951 .ident = "ASUS P6T",
4952 .matches = {
4953 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4954 DMI_MATCH(DMI_BOARD_NAME, "P6T"),
4955 },
4956 },
4957 {
4958 .ident = "ASUS P6X",
4959 .matches = {
4960 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4961 DMI_MATCH(DMI_BOARD_NAME, "P6X"),
4962 },
4963 },
4964 {}
4965 };
4966
4967 static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4968 {
4969 struct net_device *dev, *dev1;
4970 struct sky2_hw *hw;
4971 int err, using_dac = 0, wol_default;
4972 u32 reg;
4973 char buf1[16];
4974
4975 err = pci_enable_device(pdev);
4976 if (err) {
4977 dev_err(&pdev->dev, "cannot enable PCI device\n");
4978 goto err_out;
4979 }
4980
4981 /* Get configuration information
4982 * Note: only regular PCI config access once to test for HW issues
4983 * other PCI access through shared memory for speed and to
4984 * avoid MMCONFIG problems.
4985 */
4986 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4987 if (err) {
4988 dev_err(&pdev->dev, "PCI read config failed\n");
4989 goto err_out_disable;
4990 }
4991
4992 if (~reg == 0) {
4993 dev_err(&pdev->dev, "PCI configuration read error\n");
4994 err = -EIO;
4995 goto err_out_disable;
4996 }
4997
4998 err = pci_request_regions(pdev, DRV_NAME);
4999 if (err) {
5000 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
5001 goto err_out_disable;
5002 }
5003
5004 pci_set_master(pdev);
5005
5006 if (sizeof(dma_addr_t) > sizeof(u32) &&
5007 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
5008 using_dac = 1;
5009 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
5010 if (err < 0) {
5011 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
5012 "for consistent allocations\n");
5013 goto err_out_free_regions;
5014 }
5015 } else {
5016 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5017 if (err) {
5018 dev_err(&pdev->dev, "no usable DMA configuration\n");
5019 goto err_out_free_regions;
5020 }
5021 }
5022
5023
5024 #ifdef __BIG_ENDIAN
5025 /* The sk98lin vendor driver uses hardware byte swapping but
5026 * this driver uses software swapping.
5027 */
5028 reg &= ~PCI_REV_DESC;
5029 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
5030 if (err) {
5031 dev_err(&pdev->dev, "PCI write config failed\n");
5032 goto err_out_free_regions;
5033 }
5034 #endif
5035
5036 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
5037
5038 err = -ENOMEM;
5039
5040 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
5041 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
5042 if (!hw)
5043 goto err_out_free_regions;
5044
5045 hw->pdev = pdev;
5046 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
5047
5048 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
5049 if (!hw->regs) {
5050 dev_err(&pdev->dev, "cannot map device registers\n");
5051 goto err_out_free_hw;
5052 }
5053
5054 err = sky2_init(hw);
5055 if (err)
5056 goto err_out_iounmap;
5057
5058 /* ring for status responses */
5059 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
5060 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5061 &hw->st_dma);
5062 if (!hw->st_le) {
5063 err = -ENOMEM;
5064 goto err_out_reset;
5065 }
5066
5067 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
5068 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
5069
5070 sky2_reset(hw);
5071
5072 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
5073 if (!dev) {
5074 err = -ENOMEM;
5075 goto err_out_free_pci;
5076 }
5077
5078 if (disable_msi == -1)
5079 disable_msi = !!dmi_check_system(msi_blacklist);
5080
5081 if (!disable_msi && pci_enable_msi(pdev) == 0) {
5082 err = sky2_test_msi(hw);
5083 if (err) {
5084 pci_disable_msi(pdev);
5085 if (err != -EOPNOTSUPP)
5086 goto err_out_free_netdev;
5087 }
5088 }
5089
5090 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
5091
5092 err = register_netdev(dev);
5093 if (err) {
5094 dev_err(&pdev->dev, "cannot register net device\n");
5095 goto err_out_free_netdev;
5096 }
5097
5098 netif_carrier_off(dev);
5099
5100 sky2_show_addr(dev);
5101
5102 if (hw->ports > 1) {
5103 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
5104 if (!dev1) {
5105 err = -ENOMEM;
5106 goto err_out_unregister;
5107 }
5108
5109 err = register_netdev(dev1);
5110 if (err) {
5111 dev_err(&pdev->dev, "cannot register second net device\n");
5112 goto err_out_free_dev1;
5113 }
5114
5115 err = sky2_setup_irq(hw, hw->irq_name);
5116 if (err)
5117 goto err_out_unregister_dev1;
5118
5119 sky2_show_addr(dev1);
5120 }
5121
5122 timer_setup(&hw->watchdog_timer, sky2_watchdog, 0);
5123 INIT_WORK(&hw->restart_work, sky2_restart);
5124
5125 pci_set_drvdata(pdev, hw);
5126 pdev->d3_delay = 300;
5127
5128 return 0;
5129
5130 err_out_unregister_dev1:
5131 unregister_netdev(dev1);
5132 err_out_free_dev1:
5133 free_netdev(dev1);
5134 err_out_unregister:
5135 unregister_netdev(dev);
5136 err_out_free_netdev:
5137 if (hw->flags & SKY2_HW_USE_MSI)
5138 pci_disable_msi(pdev);
5139 free_netdev(dev);
5140 err_out_free_pci:
5141 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5142 hw->st_le, hw->st_dma);
5143 err_out_reset:
5144 sky2_write8(hw, B0_CTST, CS_RST_SET);
5145 err_out_iounmap:
5146 iounmap(hw->regs);
5147 err_out_free_hw:
5148 kfree(hw);
5149 err_out_free_regions:
5150 pci_release_regions(pdev);
5151 err_out_disable:
5152 pci_disable_device(pdev);
5153 err_out:
5154 return err;
5155 }
5156
5157 static void sky2_remove(struct pci_dev *pdev)
5158 {
5159 struct sky2_hw *hw = pci_get_drvdata(pdev);
5160 int i;
5161
5162 if (!hw)
5163 return;
5164
5165 del_timer_sync(&hw->watchdog_timer);
5166 cancel_work_sync(&hw->restart_work);
5167
5168 for (i = hw->ports-1; i >= 0; --i)
5169 unregister_netdev(hw->dev[i]);
5170
5171 sky2_write32(hw, B0_IMSK, 0);
5172 sky2_read32(hw, B0_IMSK);
5173
5174 sky2_power_aux(hw);
5175
5176 sky2_write8(hw, B0_CTST, CS_RST_SET);
5177 sky2_read8(hw, B0_CTST);
5178
5179 if (hw->ports > 1) {
5180 napi_disable(&hw->napi);
5181 free_irq(pdev->irq, hw);
5182 }
5183
5184 if (hw->flags & SKY2_HW_USE_MSI)
5185 pci_disable_msi(pdev);
5186 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5187 hw->st_le, hw->st_dma);
5188 pci_release_regions(pdev);
5189 pci_disable_device(pdev);
5190
5191 for (i = hw->ports-1; i >= 0; --i)
5192 free_netdev(hw->dev[i]);
5193
5194 iounmap(hw->regs);
5195 kfree(hw);
5196 }
5197
5198 static int sky2_suspend(struct device *dev)
5199 {
5200 struct pci_dev *pdev = to_pci_dev(dev);
5201 struct sky2_hw *hw = pci_get_drvdata(pdev);
5202 int i;
5203
5204 if (!hw)
5205 return 0;
5206
5207 del_timer_sync(&hw->watchdog_timer);
5208 cancel_work_sync(&hw->restart_work);
5209
5210 rtnl_lock();
5211
5212 sky2_all_down(hw);
5213 for (i = 0; i < hw->ports; i++) {
5214 struct net_device *dev = hw->dev[i];
5215 struct sky2_port *sky2 = netdev_priv(dev);
5216
5217 if (sky2->wol)
5218 sky2_wol_init(sky2);
5219 }
5220
5221 sky2_power_aux(hw);
5222 rtnl_unlock();
5223
5224 return 0;
5225 }
5226
5227 #ifdef CONFIG_PM_SLEEP
5228 static int sky2_resume(struct device *dev)
5229 {
5230 struct pci_dev *pdev = to_pci_dev(dev);
5231 struct sky2_hw *hw = pci_get_drvdata(pdev);
5232 int err;
5233
5234 if (!hw)
5235 return 0;
5236
5237 /* Re-enable all clocks */
5238 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5239 if (err) {
5240 dev_err(&pdev->dev, "PCI write config failed\n");
5241 goto out;
5242 }
5243
5244 rtnl_lock();
5245 sky2_reset(hw);
5246 sky2_all_up(hw);
5247 rtnl_unlock();
5248
5249 return 0;
5250 out:
5251
5252 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5253 pci_disable_device(pdev);
5254 return err;
5255 }
5256
5257 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5258 #define SKY2_PM_OPS (&sky2_pm_ops)
5259
5260 #else
5261
5262 #define SKY2_PM_OPS NULL
5263 #endif
5264
5265 static void sky2_shutdown(struct pci_dev *pdev)
5266 {
5267 struct sky2_hw *hw = pci_get_drvdata(pdev);
5268 int port;
5269
5270 for (port = 0; port < hw->ports; port++) {
5271 struct net_device *ndev = hw->dev[port];
5272
5273 rtnl_lock();
5274 if (netif_running(ndev)) {
5275 dev_close(ndev);
5276 netif_device_detach(ndev);
5277 }
5278 rtnl_unlock();
5279 }
5280 sky2_suspend(&pdev->dev);
5281 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5282 pci_set_power_state(pdev, PCI_D3hot);
5283 }
5284
5285 static struct pci_driver sky2_driver = {
5286 .name = DRV_NAME,
5287 .id_table = sky2_id_table,
5288 .probe = sky2_probe,
5289 .remove = sky2_remove,
5290 .shutdown = sky2_shutdown,
5291 .driver.pm = SKY2_PM_OPS,
5292 };
5293
5294 static int __init sky2_init_module(void)
5295 {
5296 pr_info("driver version " DRV_VERSION "\n");
5297
5298 sky2_debug_init();
5299 return pci_register_driver(&sky2_driver);
5300 }
5301
5302 static void __exit sky2_cleanup_module(void)
5303 {
5304 pci_unregister_driver(&sky2_driver);
5305 sky2_debug_cleanup();
5306 }
5307
5308 module_init(sky2_init_module);
5309 module_exit(sky2_cleanup_module);
5310
5311 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5312 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5313 MODULE_LICENSE("GPL");
5314 MODULE_VERSION(DRV_VERSION);
Linux with added FPC-III support