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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
blob1d55f014725efd75bd94dfbe2484dfae0792f857
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/if_vlan.h>
23 #include <linux/reset.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/pinctrl/devinfo.h>
27
28 #include "mtk_eth_soc.h"
29
30 static int mtk_msg_level = -1;
31 module_param_named(msg_level, mtk_msg_level, int, 0);
32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
33
34 #define MTK_ETHTOOL_STAT(x) { #x, \
35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
36
37 /* strings used by ethtool */
38 static const struct mtk_ethtool_stats {
39 char str[ETH_GSTRING_LEN];
40 u32 offset;
41 } mtk_ethtool_stats[] = {
42 MTK_ETHTOOL_STAT(tx_bytes),
43 MTK_ETHTOOL_STAT(tx_packets),
44 MTK_ETHTOOL_STAT(tx_skip),
45 MTK_ETHTOOL_STAT(tx_collisions),
46 MTK_ETHTOOL_STAT(rx_bytes),
47 MTK_ETHTOOL_STAT(rx_packets),
48 MTK_ETHTOOL_STAT(rx_overflow),
49 MTK_ETHTOOL_STAT(rx_fcs_errors),
50 MTK_ETHTOOL_STAT(rx_short_errors),
51 MTK_ETHTOOL_STAT(rx_long_errors),
52 MTK_ETHTOOL_STAT(rx_checksum_errors),
53 MTK_ETHTOOL_STAT(rx_flow_control_packets),
54 };
55
56 static const char * const mtk_clks_source_name[] = {
57 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m",
58 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll"
59 };
60
61 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
62 {
63 __raw_writel(val, eth->base + reg);
64 }
65
66 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
67 {
68 return __raw_readl(eth->base + reg);
69 }
70
71 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
72 {
73 unsigned long t_start = jiffies;
74
75 while (1) {
76 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
77 return 0;
78 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
79 break;
80 usleep_range(10, 20);
81 }
82
83 dev_err(eth->dev, "mdio: MDIO timeout\n");
84 return -1;
85 }
86
87 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
88 u32 phy_register, u32 write_data)
89 {
90 if (mtk_mdio_busy_wait(eth))
91 return -1;
92
93 write_data &= 0xffff;
94
95 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
96 (phy_register << PHY_IAC_REG_SHIFT) |
97 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
98 MTK_PHY_IAC);
99
100 if (mtk_mdio_busy_wait(eth))
101 return -1;
102
103 return 0;
104 }
105
106 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
107 {
108 u32 d;
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
114 (phy_reg << PHY_IAC_REG_SHIFT) |
115 (phy_addr << PHY_IAC_ADDR_SHIFT),
116 MTK_PHY_IAC);
117
118 if (mtk_mdio_busy_wait(eth))
119 return 0xffff;
120
121 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
122
123 return d;
124 }
125
126 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
127 int phy_reg, u16 val)
128 {
129 struct mtk_eth *eth = bus->priv;
130
131 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
132 }
133
134 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
135 {
136 struct mtk_eth *eth = bus->priv;
137
138 return _mtk_mdio_read(eth, phy_addr, phy_reg);
139 }
140
141 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
142 {
143 u32 val;
144 int ret;
145
146 val = (speed == SPEED_1000) ?
147 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
148 mtk_w32(eth, val, INTF_MODE);
149
150 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
151 ETHSYS_TRGMII_CLK_SEL362_5,
152 ETHSYS_TRGMII_CLK_SEL362_5);
153
154 val = (speed == SPEED_1000) ? 250000000 : 500000000;
155 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
156 if (ret)
157 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
158
159 val = (speed == SPEED_1000) ?
160 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
161 mtk_w32(eth, val, TRGMII_RCK_CTRL);
162
163 val = (speed == SPEED_1000) ?
164 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
165 mtk_w32(eth, val, TRGMII_TCK_CTRL);
166 }
167
168 static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id)
169 {
170 u32 val;
171
172 /* Setup the link timer and QPHY power up inside SGMIISYS */
173 regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER,
174 SGMII_LINK_TIMER_DEFAULT);
175
176 regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val);
177 val |= SGMII_REMOTE_FAULT_DIS;
178 regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val);
179
180 regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val);
181 val |= SGMII_AN_RESTART;
182 regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val);
183
184 regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
185 val &= ~SGMII_PHYA_PWD;
186 regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val);
187
188 /* Determine MUX for which GMAC uses the SGMII interface */
189 if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) {
190 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
191 val &= ~SYSCFG0_SGMII_MASK;
192 val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2;
193 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
194
195 dev_info(eth->dev, "setup shared sgmii for gmac=%d\n",
196 mac_id);
197 }
198
199 /* Setup the GMAC1 going through SGMII path when SoC also support
200 * ESW on GMAC1
201 */
202 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) &&
203 !mac_id) {
204 mtk_w32(eth, 0, MTK_MAC_MISC);
205 dev_info(eth->dev, "setup gmac1 going through sgmii");
206 }
207 }
208
209 static void mtk_phy_link_adjust(struct net_device *dev)
210 {
211 struct mtk_mac *mac = netdev_priv(dev);
212 u16 lcl_adv = 0, rmt_adv = 0;
213 u8 flowctrl;
214 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
215 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
216 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
217 MAC_MCR_BACKPR_EN;
218
219 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
220 return;
221
222 switch (dev->phydev->speed) {
223 case SPEED_1000:
224 mcr |= MAC_MCR_SPEED_1000;
225 break;
226 case SPEED_100:
227 mcr |= MAC_MCR_SPEED_100;
228 break;
229 };
230
231 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
232 !mac->id && !mac->trgmii)
233 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);
234
235 if (dev->phydev->link)
236 mcr |= MAC_MCR_FORCE_LINK;
237
238 if (dev->phydev->duplex) {
239 mcr |= MAC_MCR_FORCE_DPX;
240
241 if (dev->phydev->pause)
242 rmt_adv = LPA_PAUSE_CAP;
243 if (dev->phydev->asym_pause)
244 rmt_adv |= LPA_PAUSE_ASYM;
245
246 if (dev->phydev->advertising & ADVERTISED_Pause)
247 lcl_adv |= ADVERTISE_PAUSE_CAP;
248 if (dev->phydev->advertising & ADVERTISED_Asym_Pause)
249 lcl_adv |= ADVERTISE_PAUSE_ASYM;
250
251 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
252
253 if (flowctrl & FLOW_CTRL_TX)
254 mcr |= MAC_MCR_FORCE_TX_FC;
255 if (flowctrl & FLOW_CTRL_RX)
256 mcr |= MAC_MCR_FORCE_RX_FC;
257
258 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
259 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
260 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
261 }
262
263 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
264
265 if (dev->phydev->link)
266 netif_carrier_on(dev);
267 else
268 netif_carrier_off(dev);
269
270 if (!of_phy_is_fixed_link(mac->of_node))
271 phy_print_status(dev->phydev);
272 }
273
274 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
275 struct device_node *phy_node)
276 {
277 struct phy_device *phydev;
278 int phy_mode;
279
280 phy_mode = of_get_phy_mode(phy_node);
281 if (phy_mode < 0) {
282 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
283 return -EINVAL;
284 }
285
286 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
287 mtk_phy_link_adjust, 0, phy_mode);
288 if (!phydev) {
289 dev_err(eth->dev, "could not connect to PHY\n");
290 return -ENODEV;
291 }
292
293 dev_info(eth->dev,
294 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
295 mac->id, phydev_name(phydev), phydev->phy_id,
296 phydev->drv->name);
297
298 return 0;
299 }
300
301 static int mtk_phy_connect(struct net_device *dev)
302 {
303 struct mtk_mac *mac = netdev_priv(dev);
304 struct mtk_eth *eth;
305 struct device_node *np;
306 u32 val;
307
308 eth = mac->hw;
309 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
310 if (!np && of_phy_is_fixed_link(mac->of_node))
311 if (!of_phy_register_fixed_link(mac->of_node))
312 np = of_node_get(mac->of_node);
313 if (!np)
314 return -ENODEV;
315
316 mac->ge_mode = 0;
317 switch (of_get_phy_mode(np)) {
318 case PHY_INTERFACE_MODE_TRGMII:
319 mac->trgmii = true;
320 case PHY_INTERFACE_MODE_RGMII_TXID:
321 case PHY_INTERFACE_MODE_RGMII_RXID:
322 case PHY_INTERFACE_MODE_RGMII_ID:
323 case PHY_INTERFACE_MODE_RGMII:
324 break;
325 case PHY_INTERFACE_MODE_SGMII:
326 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII))
327 mtk_gmac_sgmii_hw_setup(eth, mac->id);
328 break;
329 case PHY_INTERFACE_MODE_MII:
330 mac->ge_mode = 1;
331 break;
332 case PHY_INTERFACE_MODE_REVMII:
333 mac->ge_mode = 2;
334 break;
335 case PHY_INTERFACE_MODE_RMII:
336 if (!mac->id)
337 goto err_phy;
338 mac->ge_mode = 3;
339 break;
340 default:
341 goto err_phy;
342 }
343
344 /* put the gmac into the right mode */
345 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
346 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
347 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
348 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
349
350 /* couple phydev to net_device */
351 if (mtk_phy_connect_node(eth, mac, np))
352 goto err_phy;
353
354 dev->phydev->autoneg = AUTONEG_ENABLE;
355 dev->phydev->speed = 0;
356 dev->phydev->duplex = 0;
357
358 if (of_phy_is_fixed_link(mac->of_node))
359 dev->phydev->supported |=
360 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
361
362 dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
363 SUPPORTED_Asym_Pause;
364 dev->phydev->advertising = dev->phydev->supported |
365 ADVERTISED_Autoneg;
366 phy_start_aneg(dev->phydev);
367
368 of_node_put(np);
369
370 return 0;
371
372 err_phy:
373 if (of_phy_is_fixed_link(mac->of_node))
374 of_phy_deregister_fixed_link(mac->of_node);
375 of_node_put(np);
376 dev_err(eth->dev, "%s: invalid phy\n", __func__);
377 return -EINVAL;
378 }
379
380 static int mtk_mdio_init(struct mtk_eth *eth)
381 {
382 struct device_node *mii_np;
383 int ret;
384
385 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
386 if (!mii_np) {
387 dev_err(eth->dev, "no %s child node found", "mdio-bus");
388 return -ENODEV;
389 }
390
391 if (!of_device_is_available(mii_np)) {
392 ret = -ENODEV;
393 goto err_put_node;
394 }
395
396 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
397 if (!eth->mii_bus) {
398 ret = -ENOMEM;
399 goto err_put_node;
400 }
401
402 eth->mii_bus->name = "mdio";
403 eth->mii_bus->read = mtk_mdio_read;
404 eth->mii_bus->write = mtk_mdio_write;
405 eth->mii_bus->priv = eth;
406 eth->mii_bus->parent = eth->dev;
407
408 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
409 ret = of_mdiobus_register(eth->mii_bus, mii_np);
410
411 err_put_node:
412 of_node_put(mii_np);
413 return ret;
414 }
415
416 static void mtk_mdio_cleanup(struct mtk_eth *eth)
417 {
418 if (!eth->mii_bus)
419 return;
420
421 mdiobus_unregister(eth->mii_bus);
422 }
423
424 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
425 {
426 unsigned long flags;
427 u32 val;
428
429 spin_lock_irqsave(&eth->tx_irq_lock, flags);
430 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
431 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
432 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
433 }
434
435 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
436 {
437 unsigned long flags;
438 u32 val;
439
440 spin_lock_irqsave(&eth->tx_irq_lock, flags);
441 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
442 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
443 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
444 }
445
446 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
447 {
448 unsigned long flags;
449 u32 val;
450
451 spin_lock_irqsave(&eth->rx_irq_lock, flags);
452 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
453 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
454 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
455 }
456
457 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
458 {
459 unsigned long flags;
460 u32 val;
461
462 spin_lock_irqsave(&eth->rx_irq_lock, flags);
463 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
464 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
465 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
466 }
467
468 static int mtk_set_mac_address(struct net_device *dev, void *p)
469 {
470 int ret = eth_mac_addr(dev, p);
471 struct mtk_mac *mac = netdev_priv(dev);
472 const char *macaddr = dev->dev_addr;
473
474 if (ret)
475 return ret;
476
477 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
478 return -EBUSY;
479
480 spin_lock_bh(&mac->hw->page_lock);
481 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
482 MTK_GDMA_MAC_ADRH(mac->id));
483 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
484 (macaddr[4] << 8) | macaddr[5],
485 MTK_GDMA_MAC_ADRL(mac->id));
486 spin_unlock_bh(&mac->hw->page_lock);
487
488 return 0;
489 }
490
491 void mtk_stats_update_mac(struct mtk_mac *mac)
492 {
493 struct mtk_hw_stats *hw_stats = mac->hw_stats;
494 unsigned int base = MTK_GDM1_TX_GBCNT;
495 u64 stats;
496
497 base += hw_stats->reg_offset;
498
499 u64_stats_update_begin(&hw_stats->syncp);
500
501 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
502 stats = mtk_r32(mac->hw, base + 0x04);
503 if (stats)
504 hw_stats->rx_bytes += (stats << 32);
505 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
506 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
507 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
508 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
509 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
510 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
511 hw_stats->rx_flow_control_packets +=
512 mtk_r32(mac->hw, base + 0x24);
513 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
514 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
515 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
516 stats = mtk_r32(mac->hw, base + 0x34);
517 if (stats)
518 hw_stats->tx_bytes += (stats << 32);
519 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
520 u64_stats_update_end(&hw_stats->syncp);
521 }
522
523 static void mtk_stats_update(struct mtk_eth *eth)
524 {
525 int i;
526
527 for (i = 0; i < MTK_MAC_COUNT; i++) {
528 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
529 continue;
530 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
531 mtk_stats_update_mac(eth->mac[i]);
532 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
533 }
534 }
535 }
536
537 static void mtk_get_stats64(struct net_device *dev,
538 struct rtnl_link_stats64 *storage)
539 {
540 struct mtk_mac *mac = netdev_priv(dev);
541 struct mtk_hw_stats *hw_stats = mac->hw_stats;
542 unsigned int start;
543
544 if (netif_running(dev) && netif_device_present(dev)) {
545 if (spin_trylock_bh(&hw_stats->stats_lock)) {
546 mtk_stats_update_mac(mac);
547 spin_unlock_bh(&hw_stats->stats_lock);
548 }
549 }
550
551 do {
552 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
553 storage->rx_packets = hw_stats->rx_packets;
554 storage->tx_packets = hw_stats->tx_packets;
555 storage->rx_bytes = hw_stats->rx_bytes;
556 storage->tx_bytes = hw_stats->tx_bytes;
557 storage->collisions = hw_stats->tx_collisions;
558 storage->rx_length_errors = hw_stats->rx_short_errors +
559 hw_stats->rx_long_errors;
560 storage->rx_over_errors = hw_stats->rx_overflow;
561 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
562 storage->rx_errors = hw_stats->rx_checksum_errors;
563 storage->tx_aborted_errors = hw_stats->tx_skip;
564 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
565
566 storage->tx_errors = dev->stats.tx_errors;
567 storage->rx_dropped = dev->stats.rx_dropped;
568 storage->tx_dropped = dev->stats.tx_dropped;
569 }
570
571 static inline int mtk_max_frag_size(int mtu)
572 {
573 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
574 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
575 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
576
577 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
578 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
579 }
580
581 static inline int mtk_max_buf_size(int frag_size)
582 {
583 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
584 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
585
586 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
587
588 return buf_size;
589 }
590
591 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
592 struct mtk_rx_dma *dma_rxd)
593 {
594 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
595 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
596 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
597 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
598 }
599
600 /* the qdma core needs scratch memory to be setup */
601 static int mtk_init_fq_dma(struct mtk_eth *eth)
602 {
603 dma_addr_t phy_ring_tail;
604 int cnt = MTK_DMA_SIZE;
605 dma_addr_t dma_addr;
606 int i;
607
608 eth->scratch_ring = dma_zalloc_coherent(eth->dev,
609 cnt * sizeof(struct mtk_tx_dma),
610 &eth->phy_scratch_ring,
611 GFP_ATOMIC);
612 if (unlikely(!eth->scratch_ring))
613 return -ENOMEM;
614
615 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
616 GFP_KERNEL);
617 if (unlikely(!eth->scratch_head))
618 return -ENOMEM;
619
620 dma_addr = dma_map_single(eth->dev,
621 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
622 DMA_FROM_DEVICE);
623 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
624 return -ENOMEM;
625
626 phy_ring_tail = eth->phy_scratch_ring +
627 (sizeof(struct mtk_tx_dma) * (cnt - 1));
628
629 for (i = 0; i < cnt; i++) {
630 eth->scratch_ring[i].txd1 =
631 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
632 if (i < cnt - 1)
633 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
634 ((i + 1) * sizeof(struct mtk_tx_dma)));
635 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
636 }
637
638 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
639 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
640 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
641 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
642
643 return 0;
644 }
645
646 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
647 {
648 void *ret = ring->dma;
649
650 return ret + (desc - ring->phys);
651 }
652
653 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
654 struct mtk_tx_dma *txd)
655 {
656 int idx = txd - ring->dma;
657
658 return &ring->buf[idx];
659 }
660
661 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
662 {
663 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
664 dma_unmap_single(eth->dev,
665 dma_unmap_addr(tx_buf, dma_addr0),
666 dma_unmap_len(tx_buf, dma_len0),
667 DMA_TO_DEVICE);
668 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
669 dma_unmap_page(eth->dev,
670 dma_unmap_addr(tx_buf, dma_addr0),
671 dma_unmap_len(tx_buf, dma_len0),
672 DMA_TO_DEVICE);
673 }
674 tx_buf->flags = 0;
675 if (tx_buf->skb &&
676 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
677 dev_kfree_skb_any(tx_buf->skb);
678 tx_buf->skb = NULL;
679 }
680
681 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
682 int tx_num, struct mtk_tx_ring *ring, bool gso)
683 {
684 struct mtk_mac *mac = netdev_priv(dev);
685 struct mtk_eth *eth = mac->hw;
686 struct mtk_tx_dma *itxd, *txd;
687 struct mtk_tx_buf *itx_buf, *tx_buf;
688 dma_addr_t mapped_addr;
689 unsigned int nr_frags;
690 int i, n_desc = 1;
691 u32 txd4 = 0, fport;
692
693 itxd = ring->next_free;
694 if (itxd == ring->last_free)
695 return -ENOMEM;
696
697 /* set the forward port */
698 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
699 txd4 |= fport;
700
701 itx_buf = mtk_desc_to_tx_buf(ring, itxd);
702 memset(itx_buf, 0, sizeof(*itx_buf));
703
704 if (gso)
705 txd4 |= TX_DMA_TSO;
706
707 /* TX Checksum offload */
708 if (skb->ip_summed == CHECKSUM_PARTIAL)
709 txd4 |= TX_DMA_CHKSUM;
710
711 /* VLAN header offload */
712 if (skb_vlan_tag_present(skb))
713 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
714
715 mapped_addr = dma_map_single(eth->dev, skb->data,
716 skb_headlen(skb), DMA_TO_DEVICE);
717 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
718 return -ENOMEM;
719
720 WRITE_ONCE(itxd->txd1, mapped_addr);
721 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
722 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
723 MTK_TX_FLAGS_FPORT1;
724 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr);
725 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb));
726
727 /* TX SG offload */
728 txd = itxd;
729 nr_frags = skb_shinfo(skb)->nr_frags;
730 for (i = 0; i < nr_frags; i++) {
731 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
732 unsigned int offset = 0;
733 int frag_size = skb_frag_size(frag);
734
735 while (frag_size) {
736 bool last_frag = false;
737 unsigned int frag_map_size;
738
739 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
740 if (txd == ring->last_free)
741 goto err_dma;
742
743 n_desc++;
744 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
745 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
746 frag_map_size,
747 DMA_TO_DEVICE);
748 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
749 goto err_dma;
750
751 if (i == nr_frags - 1 &&
752 (frag_size - frag_map_size) == 0)
753 last_frag = true;
754
755 WRITE_ONCE(txd->txd1, mapped_addr);
756 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
757 TX_DMA_PLEN0(frag_map_size) |
758 last_frag * TX_DMA_LS0));
759 WRITE_ONCE(txd->txd4, fport);
760
761 tx_buf = mtk_desc_to_tx_buf(ring, txd);
762 memset(tx_buf, 0, sizeof(*tx_buf));
763 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
764 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
765 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
766 MTK_TX_FLAGS_FPORT1;
767
768 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
769 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
770 frag_size -= frag_map_size;
771 offset += frag_map_size;
772 }
773 }
774
775 /* store skb to cleanup */
776 itx_buf->skb = skb;
777
778 WRITE_ONCE(itxd->txd4, txd4);
779 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
780 (!nr_frags * TX_DMA_LS0)));
781
782 netdev_sent_queue(dev, skb->len);
783 skb_tx_timestamp(skb);
784
785 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
786 atomic_sub(n_desc, &ring->free_count);
787
788 /* make sure that all changes to the dma ring are flushed before we
789 * continue
790 */
791 wmb();
792
793 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
794 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
795
796 return 0;
797
798 err_dma:
799 do {
800 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
801
802 /* unmap dma */
803 mtk_tx_unmap(eth, tx_buf);
804
805 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
806 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
807 } while (itxd != txd);
808
809 return -ENOMEM;
810 }
811
812 static inline int mtk_cal_txd_req(struct sk_buff *skb)
813 {
814 int i, nfrags;
815 struct skb_frag_struct *frag;
816
817 nfrags = 1;
818 if (skb_is_gso(skb)) {
819 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
820 frag = &skb_shinfo(skb)->frags[i];
821 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
822 }
823 } else {
824 nfrags += skb_shinfo(skb)->nr_frags;
825 }
826
827 return nfrags;
828 }
829
830 static int mtk_queue_stopped(struct mtk_eth *eth)
831 {
832 int i;
833
834 for (i = 0; i < MTK_MAC_COUNT; i++) {
835 if (!eth->netdev[i])
836 continue;
837 if (netif_queue_stopped(eth->netdev[i]))
838 return 1;
839 }
840
841 return 0;
842 }
843
844 static void mtk_wake_queue(struct mtk_eth *eth)
845 {
846 int i;
847
848 for (i = 0; i < MTK_MAC_COUNT; i++) {
849 if (!eth->netdev[i])
850 continue;
851 netif_wake_queue(eth->netdev[i]);
852 }
853 }
854
855 static void mtk_stop_queue(struct mtk_eth *eth)
856 {
857 int i;
858
859 for (i = 0; i < MTK_MAC_COUNT; i++) {
860 if (!eth->netdev[i])
861 continue;
862 netif_stop_queue(eth->netdev[i]);
863 }
864 }
865
866 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
867 {
868 struct mtk_mac *mac = netdev_priv(dev);
869 struct mtk_eth *eth = mac->hw;
870 struct mtk_tx_ring *ring = &eth->tx_ring;
871 struct net_device_stats *stats = &dev->stats;
872 bool gso = false;
873 int tx_num;
874
875 /* normally we can rely on the stack not calling this more than once,
876 * however we have 2 queues running on the same ring so we need to lock
877 * the ring access
878 */
879 spin_lock(&eth->page_lock);
880
881 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
882 goto drop;
883
884 tx_num = mtk_cal_txd_req(skb);
885 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
886 mtk_stop_queue(eth);
887 netif_err(eth, tx_queued, dev,
888 "Tx Ring full when queue awake!\n");
889 spin_unlock(&eth->page_lock);
890 return NETDEV_TX_BUSY;
891 }
892
893 /* TSO: fill MSS info in tcp checksum field */
894 if (skb_is_gso(skb)) {
895 if (skb_cow_head(skb, 0)) {
896 netif_warn(eth, tx_err, dev,
897 "GSO expand head fail.\n");
898 goto drop;
899 }
900
901 if (skb_shinfo(skb)->gso_type &
902 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
903 gso = true;
904 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
905 }
906 }
907
908 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
909 goto drop;
910
911 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
912 mtk_stop_queue(eth);
913
914 spin_unlock(&eth->page_lock);
915
916 return NETDEV_TX_OK;
917
918 drop:
919 spin_unlock(&eth->page_lock);
920 stats->tx_dropped++;
921 dev_kfree_skb_any(skb);
922 return NETDEV_TX_OK;
923 }
924
925 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
926 {
927 int i;
928 struct mtk_rx_ring *ring;
929 int idx;
930
931 if (!eth->hwlro)
932 return &eth->rx_ring[0];
933
934 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
935 ring = &eth->rx_ring[i];
936 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
937 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
938 ring->calc_idx_update = true;
939 return ring;
940 }
941 }
942
943 return NULL;
944 }
945
946 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
947 {
948 struct mtk_rx_ring *ring;
949 int i;
950
951 if (!eth->hwlro) {
952 ring = &eth->rx_ring[0];
953 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
954 } else {
955 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
956 ring = &eth->rx_ring[i];
957 if (ring->calc_idx_update) {
958 ring->calc_idx_update = false;
959 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
960 }
961 }
962 }
963 }
964
965 static int mtk_poll_rx(struct napi_struct *napi, int budget,
966 struct mtk_eth *eth)
967 {
968 struct mtk_rx_ring *ring;
969 int idx;
970 struct sk_buff *skb;
971 u8 *data, *new_data;
972 struct mtk_rx_dma *rxd, trxd;
973 int done = 0;
974
975 while (done < budget) {
976 struct net_device *netdev;
977 unsigned int pktlen;
978 dma_addr_t dma_addr;
979 int mac = 0;
980
981 ring = mtk_get_rx_ring(eth);
982 if (unlikely(!ring))
983 goto rx_done;
984
985 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
986 rxd = &ring->dma[idx];
987 data = ring->data[idx];
988
989 mtk_rx_get_desc(&trxd, rxd);
990 if (!(trxd.rxd2 & RX_DMA_DONE))
991 break;
992
993 /* find out which mac the packet come from. values start at 1 */
994 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
995 RX_DMA_FPORT_MASK;
996 mac--;
997
998 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
999 !eth->netdev[mac]))
1000 goto release_desc;
1001
1002 netdev = eth->netdev[mac];
1003
1004 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
1005 goto release_desc;
1006
1007 /* alloc new buffer */
1008 new_data = napi_alloc_frag(ring->frag_size);
1009 if (unlikely(!new_data)) {
1010 netdev->stats.rx_dropped++;
1011 goto release_desc;
1012 }
1013 dma_addr = dma_map_single(eth->dev,
1014 new_data + NET_SKB_PAD,
1015 ring->buf_size,
1016 DMA_FROM_DEVICE);
1017 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
1018 skb_free_frag(new_data);
1019 netdev->stats.rx_dropped++;
1020 goto release_desc;
1021 }
1022
1023 /* receive data */
1024 skb = build_skb(data, ring->frag_size);
1025 if (unlikely(!skb)) {
1026 skb_free_frag(new_data);
1027 netdev->stats.rx_dropped++;
1028 goto release_desc;
1029 }
1030 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1031
1032 dma_unmap_single(eth->dev, trxd.rxd1,
1033 ring->buf_size, DMA_FROM_DEVICE);
1034 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1035 skb->dev = netdev;
1036 skb_put(skb, pktlen);
1037 if (trxd.rxd4 & RX_DMA_L4_VALID)
1038 skb->ip_summed = CHECKSUM_UNNECESSARY;
1039 else
1040 skb_checksum_none_assert(skb);
1041 skb->protocol = eth_type_trans(skb, netdev);
1042
1043 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1044 RX_DMA_VID(trxd.rxd3))
1045 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1046 RX_DMA_VID(trxd.rxd3));
1047 skb_record_rx_queue(skb, 0);
1048 napi_gro_receive(napi, skb);
1049
1050 ring->data[idx] = new_data;
1051 rxd->rxd1 = (unsigned int)dma_addr;
1052
1053 release_desc:
1054 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
1055
1056 ring->calc_idx = idx;
1057
1058 done++;
1059 }
1060
1061 rx_done:
1062 if (done) {
1063 /* make sure that all changes to the dma ring are flushed before
1064 * we continue
1065 */
1066 wmb();
1067 mtk_update_rx_cpu_idx(eth);
1068 }
1069
1070 return done;
1071 }
1072
1073 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
1074 {
1075 struct mtk_tx_ring *ring = &eth->tx_ring;
1076 struct mtk_tx_dma *desc;
1077 struct sk_buff *skb;
1078 struct mtk_tx_buf *tx_buf;
1079 unsigned int done[MTK_MAX_DEVS];
1080 unsigned int bytes[MTK_MAX_DEVS];
1081 u32 cpu, dma;
1082 int total = 0, i;
1083
1084 memset(done, 0, sizeof(done));
1085 memset(bytes, 0, sizeof(bytes));
1086
1087 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1088 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1089
1090 desc = mtk_qdma_phys_to_virt(ring, cpu);
1091
1092 while ((cpu != dma) && budget) {
1093 u32 next_cpu = desc->txd2;
1094 int mac = 0;
1095
1096 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1097 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1098 break;
1099
1100 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1101 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1102 mac = 1;
1103
1104 skb = tx_buf->skb;
1105 if (!skb)
1106 break;
1107
1108 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1109 bytes[mac] += skb->len;
1110 done[mac]++;
1111 budget--;
1112 }
1113 mtk_tx_unmap(eth, tx_buf);
1114
1115 ring->last_free = desc;
1116 atomic_inc(&ring->free_count);
1117
1118 cpu = next_cpu;
1119 }
1120
1121 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1122
1123 for (i = 0; i < MTK_MAC_COUNT; i++) {
1124 if (!eth->netdev[i] || !done[i])
1125 continue;
1126 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1127 total += done[i];
1128 }
1129
1130 if (mtk_queue_stopped(eth) &&
1131 (atomic_read(&ring->free_count) > ring->thresh))
1132 mtk_wake_queue(eth);
1133
1134 return total;
1135 }
1136
1137 static void mtk_handle_status_irq(struct mtk_eth *eth)
1138 {
1139 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1140
1141 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1142 mtk_stats_update(eth);
1143 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1144 MTK_INT_STATUS2);
1145 }
1146 }
1147
1148 static int mtk_napi_tx(struct napi_struct *napi, int budget)
1149 {
1150 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1151 u32 status, mask;
1152 int tx_done = 0;
1153
1154 mtk_handle_status_irq(eth);
1155 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1156 tx_done = mtk_poll_tx(eth, budget);
1157
1158 if (unlikely(netif_msg_intr(eth))) {
1159 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1160 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1161 dev_info(eth->dev,
1162 "done tx %d, intr 0x%08x/0x%x\n",
1163 tx_done, status, mask);
1164 }
1165
1166 if (tx_done == budget)
1167 return budget;
1168
1169 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1170 if (status & MTK_TX_DONE_INT)
1171 return budget;
1172
1173 napi_complete(napi);
1174 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1175
1176 return tx_done;
1177 }
1178
1179 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1180 {
1181 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1182 u32 status, mask;
1183 int rx_done = 0;
1184 int remain_budget = budget;
1185
1186 mtk_handle_status_irq(eth);
1187
1188 poll_again:
1189 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1190 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1191
1192 if (unlikely(netif_msg_intr(eth))) {
1193 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1194 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1195 dev_info(eth->dev,
1196 "done rx %d, intr 0x%08x/0x%x\n",
1197 rx_done, status, mask);
1198 }
1199 if (rx_done == remain_budget)
1200 return budget;
1201
1202 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1203 if (status & MTK_RX_DONE_INT) {
1204 remain_budget -= rx_done;
1205 goto poll_again;
1206 }
1207 napi_complete(napi);
1208 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1209
1210 return rx_done + budget - remain_budget;
1211 }
1212
1213 static int mtk_tx_alloc(struct mtk_eth *eth)
1214 {
1215 struct mtk_tx_ring *ring = &eth->tx_ring;
1216 int i, sz = sizeof(*ring->dma);
1217
1218 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1219 GFP_KERNEL);
1220 if (!ring->buf)
1221 goto no_tx_mem;
1222
1223 ring->dma = dma_zalloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1224 &ring->phys, GFP_ATOMIC);
1225 if (!ring->dma)
1226 goto no_tx_mem;
1227
1228 for (i = 0; i < MTK_DMA_SIZE; i++) {
1229 int next = (i + 1) % MTK_DMA_SIZE;
1230 u32 next_ptr = ring->phys + next * sz;
1231
1232 ring->dma[i].txd2 = next_ptr;
1233 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1234 }
1235
1236 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1237 ring->next_free = &ring->dma[0];
1238 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1239 ring->thresh = MAX_SKB_FRAGS;
1240
1241 /* make sure that all changes to the dma ring are flushed before we
1242 * continue
1243 */
1244 wmb();
1245
1246 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1247 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1248 mtk_w32(eth,
1249 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1250 MTK_QTX_CRX_PTR);
1251 mtk_w32(eth,
1252 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1253 MTK_QTX_DRX_PTR);
1254 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1255
1256 return 0;
1257
1258 no_tx_mem:
1259 return -ENOMEM;
1260 }
1261
1262 static void mtk_tx_clean(struct mtk_eth *eth)
1263 {
1264 struct mtk_tx_ring *ring = &eth->tx_ring;
1265 int i;
1266
1267 if (ring->buf) {
1268 for (i = 0; i < MTK_DMA_SIZE; i++)
1269 mtk_tx_unmap(eth, &ring->buf[i]);
1270 kfree(ring->buf);
1271 ring->buf = NULL;
1272 }
1273
1274 if (ring->dma) {
1275 dma_free_coherent(eth->dev,
1276 MTK_DMA_SIZE * sizeof(*ring->dma),
1277 ring->dma,
1278 ring->phys);
1279 ring->dma = NULL;
1280 }
1281 }
1282
1283 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1284 {
1285 struct mtk_rx_ring *ring;
1286 int rx_data_len, rx_dma_size;
1287 int i;
1288 u32 offset = 0;
1289
1290 if (rx_flag == MTK_RX_FLAGS_QDMA) {
1291 if (ring_no)
1292 return -EINVAL;
1293 ring = &eth->rx_ring_qdma;
1294 offset = 0x1000;
1295 } else {
1296 ring = &eth->rx_ring[ring_no];
1297 }
1298
1299 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1300 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1301 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1302 } else {
1303 rx_data_len = ETH_DATA_LEN;
1304 rx_dma_size = MTK_DMA_SIZE;
1305 }
1306
1307 ring->frag_size = mtk_max_frag_size(rx_data_len);
1308 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1309 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1310 GFP_KERNEL);
1311 if (!ring->data)
1312 return -ENOMEM;
1313
1314 for (i = 0; i < rx_dma_size; i++) {
1315 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1316 if (!ring->data[i])
1317 return -ENOMEM;
1318 }
1319
1320 ring->dma = dma_zalloc_coherent(eth->dev,
1321 rx_dma_size * sizeof(*ring->dma),
1322 &ring->phys, GFP_ATOMIC);
1323 if (!ring->dma)
1324 return -ENOMEM;
1325
1326 for (i = 0; i < rx_dma_size; i++) {
1327 dma_addr_t dma_addr = dma_map_single(eth->dev,
1328 ring->data[i] + NET_SKB_PAD,
1329 ring->buf_size,
1330 DMA_FROM_DEVICE);
1331 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1332 return -ENOMEM;
1333 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1334
1335 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1336 }
1337 ring->dma_size = rx_dma_size;
1338 ring->calc_idx_update = false;
1339 ring->calc_idx = rx_dma_size - 1;
1340 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1341 /* make sure that all changes to the dma ring are flushed before we
1342 * continue
1343 */
1344 wmb();
1345
1346 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
1347 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
1348 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
1349 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
1350
1351 return 0;
1352 }
1353
1354 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
1355 {
1356 int i;
1357
1358 if (ring->data && ring->dma) {
1359 for (i = 0; i < ring->dma_size; i++) {
1360 if (!ring->data[i])
1361 continue;
1362 if (!ring->dma[i].rxd1)
1363 continue;
1364 dma_unmap_single(eth->dev,
1365 ring->dma[i].rxd1,
1366 ring->buf_size,
1367 DMA_FROM_DEVICE);
1368 skb_free_frag(ring->data[i]);
1369 }
1370 kfree(ring->data);
1371 ring->data = NULL;
1372 }
1373
1374 if (ring->dma) {
1375 dma_free_coherent(eth->dev,
1376 ring->dma_size * sizeof(*ring->dma),
1377 ring->dma,
1378 ring->phys);
1379 ring->dma = NULL;
1380 }
1381 }
1382
1383 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1384 {
1385 int i;
1386 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1387 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1388
1389 /* set LRO rings to auto-learn modes */
1390 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1391
1392 /* validate LRO ring */
1393 ring_ctrl_dw2 |= MTK_RING_VLD;
1394
1395 /* set AGE timer (unit: 20us) */
1396 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1397 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1398
1399 /* set max AGG timer (unit: 20us) */
1400 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1401
1402 /* set max LRO AGG count */
1403 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1404 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1405
1406 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1407 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1408 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1409 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1410 }
1411
1412 /* IPv4 checksum update enable */
1413 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1414
1415 /* switch priority comparison to packet count mode */
1416 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1417
1418 /* bandwidth threshold setting */
1419 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1420
1421 /* auto-learn score delta setting */
1422 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1423
1424 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1425 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1426 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1427
1428 /* set HW LRO mode & the max aggregation count for rx packets */
1429 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1430
1431 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1432 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1433
1434 /* enable HW LRO */
1435 lro_ctrl_dw0 |= MTK_LRO_EN;
1436
1437 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1438 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1439
1440 return 0;
1441 }
1442
1443 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1444 {
1445 int i;
1446 u32 val;
1447
1448 /* relinquish lro rings, flush aggregated packets */
1449 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1450
1451 /* wait for relinquishments done */
1452 for (i = 0; i < 10; i++) {
1453 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1454 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1455 msleep(20);
1456 continue;
1457 }
1458 break;
1459 }
1460
1461 /* invalidate lro rings */
1462 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1463 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1464
1465 /* disable HW LRO */
1466 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1467 }
1468
1469 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1470 {
1471 u32 reg_val;
1472
1473 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1474
1475 /* invalidate the IP setting */
1476 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1477
1478 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1479
1480 /* validate the IP setting */
1481 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1482 }
1483
1484 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1485 {
1486 u32 reg_val;
1487
1488 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1489
1490 /* invalidate the IP setting */
1491 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1492
1493 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1494 }
1495
1496 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1497 {
1498 int cnt = 0;
1499 int i;
1500
1501 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1502 if (mac->hwlro_ip[i])
1503 cnt++;
1504 }
1505
1506 return cnt;
1507 }
1508
1509 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1510 struct ethtool_rxnfc *cmd)
1511 {
1512 struct ethtool_rx_flow_spec *fsp =
1513 (struct ethtool_rx_flow_spec *)&cmd->fs;
1514 struct mtk_mac *mac = netdev_priv(dev);
1515 struct mtk_eth *eth = mac->hw;
1516 int hwlro_idx;
1517
1518 if ((fsp->flow_type != TCP_V4_FLOW) ||
1519 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1520 (fsp->location > 1))
1521 return -EINVAL;
1522
1523 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1524 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1525
1526 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1527
1528 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1529
1530 return 0;
1531 }
1532
1533 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1534 struct ethtool_rxnfc *cmd)
1535 {
1536 struct ethtool_rx_flow_spec *fsp =
1537 (struct ethtool_rx_flow_spec *)&cmd->fs;
1538 struct mtk_mac *mac = netdev_priv(dev);
1539 struct mtk_eth *eth = mac->hw;
1540 int hwlro_idx;
1541
1542 if (fsp->location > 1)
1543 return -EINVAL;
1544
1545 mac->hwlro_ip[fsp->location] = 0;
1546 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1547
1548 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1549
1550 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1551
1552 return 0;
1553 }
1554
1555 static void mtk_hwlro_netdev_disable(struct net_device *dev)
1556 {
1557 struct mtk_mac *mac = netdev_priv(dev);
1558 struct mtk_eth *eth = mac->hw;
1559 int i, hwlro_idx;
1560
1561 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1562 mac->hwlro_ip[i] = 0;
1563 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1564
1565 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1566 }
1567
1568 mac->hwlro_ip_cnt = 0;
1569 }
1570
1571 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1572 struct ethtool_rxnfc *cmd)
1573 {
1574 struct mtk_mac *mac = netdev_priv(dev);
1575 struct ethtool_rx_flow_spec *fsp =
1576 (struct ethtool_rx_flow_spec *)&cmd->fs;
1577
1578 /* only tcp dst ipv4 is meaningful, others are meaningless */
1579 fsp->flow_type = TCP_V4_FLOW;
1580 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1581 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1582
1583 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1584 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1585 fsp->h_u.tcp_ip4_spec.psrc = 0;
1586 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1587 fsp->h_u.tcp_ip4_spec.pdst = 0;
1588 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1589 fsp->h_u.tcp_ip4_spec.tos = 0;
1590 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1591
1592 return 0;
1593 }
1594
1595 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1596 struct ethtool_rxnfc *cmd,
1597 u32 *rule_locs)
1598 {
1599 struct mtk_mac *mac = netdev_priv(dev);
1600 int cnt = 0;
1601 int i;
1602
1603 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1604 if (mac->hwlro_ip[i]) {
1605 rule_locs[cnt] = i;
1606 cnt++;
1607 }
1608 }
1609
1610 cmd->rule_cnt = cnt;
1611
1612 return 0;
1613 }
1614
1615 static netdev_features_t mtk_fix_features(struct net_device *dev,
1616 netdev_features_t features)
1617 {
1618 if (!(features & NETIF_F_LRO)) {
1619 struct mtk_mac *mac = netdev_priv(dev);
1620 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1621
1622 if (ip_cnt) {
1623 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1624
1625 features |= NETIF_F_LRO;
1626 }
1627 }
1628
1629 return features;
1630 }
1631
1632 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1633 {
1634 int err = 0;
1635
1636 if (!((dev->features ^ features) & NETIF_F_LRO))
1637 return 0;
1638
1639 if (!(features & NETIF_F_LRO))
1640 mtk_hwlro_netdev_disable(dev);
1641
1642 return err;
1643 }
1644
1645 /* wait for DMA to finish whatever it is doing before we start using it again */
1646 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1647 {
1648 unsigned long t_start = jiffies;
1649
1650 while (1) {
1651 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1652 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1653 return 0;
1654 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1655 break;
1656 }
1657
1658 dev_err(eth->dev, "DMA init timeout\n");
1659 return -1;
1660 }
1661
1662 static int mtk_dma_init(struct mtk_eth *eth)
1663 {
1664 int err;
1665 u32 i;
1666
1667 if (mtk_dma_busy_wait(eth))
1668 return -EBUSY;
1669
1670 /* QDMA needs scratch memory for internal reordering of the
1671 * descriptors
1672 */
1673 err = mtk_init_fq_dma(eth);
1674 if (err)
1675 return err;
1676
1677 err = mtk_tx_alloc(eth);
1678 if (err)
1679 return err;
1680
1681 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
1682 if (err)
1683 return err;
1684
1685 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
1686 if (err)
1687 return err;
1688
1689 if (eth->hwlro) {
1690 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1691 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
1692 if (err)
1693 return err;
1694 }
1695 err = mtk_hwlro_rx_init(eth);
1696 if (err)
1697 return err;
1698 }
1699
1700 /* Enable random early drop and set drop threshold automatically */
1701 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1702 MTK_QDMA_FC_THRES);
1703 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1704
1705 return 0;
1706 }
1707
1708 static void mtk_dma_free(struct mtk_eth *eth)
1709 {
1710 int i;
1711
1712 for (i = 0; i < MTK_MAC_COUNT; i++)
1713 if (eth->netdev[i])
1714 netdev_reset_queue(eth->netdev[i]);
1715 if (eth->scratch_ring) {
1716 dma_free_coherent(eth->dev,
1717 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1718 eth->scratch_ring,
1719 eth->phy_scratch_ring);
1720 eth->scratch_ring = NULL;
1721 eth->phy_scratch_ring = 0;
1722 }
1723 mtk_tx_clean(eth);
1724 mtk_rx_clean(eth, &eth->rx_ring[0]);
1725 mtk_rx_clean(eth, &eth->rx_ring_qdma);
1726
1727 if (eth->hwlro) {
1728 mtk_hwlro_rx_uninit(eth);
1729 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1730 mtk_rx_clean(eth, &eth->rx_ring[i]);
1731 }
1732
1733 kfree(eth->scratch_head);
1734 }
1735
1736 static void mtk_tx_timeout(struct net_device *dev)
1737 {
1738 struct mtk_mac *mac = netdev_priv(dev);
1739 struct mtk_eth *eth = mac->hw;
1740
1741 eth->netdev[mac->id]->stats.tx_errors++;
1742 netif_err(eth, tx_err, dev,
1743 "transmit timed out\n");
1744 schedule_work(&eth->pending_work);
1745 }
1746
1747 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1748 {
1749 struct mtk_eth *eth = _eth;
1750
1751 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1752 __napi_schedule(&eth->rx_napi);
1753 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1754 }
1755
1756 return IRQ_HANDLED;
1757 }
1758
1759 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1760 {
1761 struct mtk_eth *eth = _eth;
1762
1763 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1764 __napi_schedule(&eth->tx_napi);
1765 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1766 }
1767
1768 return IRQ_HANDLED;
1769 }
1770
1771 #ifdef CONFIG_NET_POLL_CONTROLLER
1772 static void mtk_poll_controller(struct net_device *dev)
1773 {
1774 struct mtk_mac *mac = netdev_priv(dev);
1775 struct mtk_eth *eth = mac->hw;
1776
1777 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1778 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1779 mtk_handle_irq_rx(eth->irq[2], dev);
1780 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1781 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1782 }
1783 #endif
1784
1785 static int mtk_start_dma(struct mtk_eth *eth)
1786 {
1787 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
1788 int err;
1789
1790 err = mtk_dma_init(eth);
1791 if (err) {
1792 mtk_dma_free(eth);
1793 return err;
1794 }
1795
1796 mtk_w32(eth,
1797 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1798 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
1799 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1800 MTK_RX_BT_32DWORDS,
1801 MTK_QDMA_GLO_CFG);
1802
1803 mtk_w32(eth,
1804 MTK_RX_DMA_EN | rx_2b_offset |
1805 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1806 MTK_PDMA_GLO_CFG);
1807
1808 return 0;
1809 }
1810
1811 static int mtk_open(struct net_device *dev)
1812 {
1813 struct mtk_mac *mac = netdev_priv(dev);
1814 struct mtk_eth *eth = mac->hw;
1815
1816 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1817 if (!refcount_read(&eth->dma_refcnt)) {
1818 int err = mtk_start_dma(eth);
1819
1820 if (err)
1821 return err;
1822
1823 napi_enable(&eth->tx_napi);
1824 napi_enable(&eth->rx_napi);
1825 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1826 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1827 refcount_set(&eth->dma_refcnt, 1);
1828 }
1829 else
1830 refcount_inc(&eth->dma_refcnt);
1831
1832 phy_start(dev->phydev);
1833 netif_start_queue(dev);
1834
1835 return 0;
1836 }
1837
1838 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1839 {
1840 u32 val;
1841 int i;
1842
1843 /* stop the dma engine */
1844 spin_lock_bh(&eth->page_lock);
1845 val = mtk_r32(eth, glo_cfg);
1846 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1847 glo_cfg);
1848 spin_unlock_bh(&eth->page_lock);
1849
1850 /* wait for dma stop */
1851 for (i = 0; i < 10; i++) {
1852 val = mtk_r32(eth, glo_cfg);
1853 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1854 msleep(20);
1855 continue;
1856 }
1857 break;
1858 }
1859 }
1860
1861 static int mtk_stop(struct net_device *dev)
1862 {
1863 struct mtk_mac *mac = netdev_priv(dev);
1864 struct mtk_eth *eth = mac->hw;
1865
1866 netif_tx_disable(dev);
1867 phy_stop(dev->phydev);
1868
1869 /* only shutdown DMA if this is the last user */
1870 if (!refcount_dec_and_test(&eth->dma_refcnt))
1871 return 0;
1872
1873 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1874 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1875 napi_disable(&eth->tx_napi);
1876 napi_disable(&eth->rx_napi);
1877
1878 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1879 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
1880
1881 mtk_dma_free(eth);
1882
1883 return 0;
1884 }
1885
1886 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1887 {
1888 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1889 reset_bits,
1890 reset_bits);
1891
1892 usleep_range(1000, 1100);
1893 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1894 reset_bits,
1895 ~reset_bits);
1896 mdelay(10);
1897 }
1898
1899 static void mtk_clk_disable(struct mtk_eth *eth)
1900 {
1901 int clk;
1902
1903 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
1904 clk_disable_unprepare(eth->clks[clk]);
1905 }
1906
1907 static int mtk_clk_enable(struct mtk_eth *eth)
1908 {
1909 int clk, ret;
1910
1911 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
1912 ret = clk_prepare_enable(eth->clks[clk]);
1913 if (ret)
1914 goto err_disable_clks;
1915 }
1916
1917 return 0;
1918
1919 err_disable_clks:
1920 while (--clk >= 0)
1921 clk_disable_unprepare(eth->clks[clk]);
1922
1923 return ret;
1924 }
1925
1926 static int mtk_hw_init(struct mtk_eth *eth)
1927 {
1928 int i, val, ret;
1929
1930 if (test_and_set_bit(MTK_HW_INIT, &eth->state))
1931 return 0;
1932
1933 pm_runtime_enable(eth->dev);
1934 pm_runtime_get_sync(eth->dev);
1935
1936 ret = mtk_clk_enable(eth);
1937 if (ret)
1938 goto err_disable_pm;
1939
1940 ethsys_reset(eth, RSTCTRL_FE);
1941 ethsys_reset(eth, RSTCTRL_PPE);
1942
1943 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1944 for (i = 0; i < MTK_MAC_COUNT; i++) {
1945 if (!eth->mac[i])
1946 continue;
1947 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1948 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1949 }
1950 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1951
1952 if (eth->pctl) {
1953 /* Set GE2 driving and slew rate */
1954 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1955
1956 /* set GE2 TDSEL */
1957 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1958
1959 /* set GE2 TUNE */
1960 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1961 }
1962
1963 /* Set linkdown as the default for each GMAC. Its own MCR would be set
1964 * up with the more appropriate value when mtk_phy_link_adjust call is
1965 * being invoked.
1966 */
1967 for (i = 0; i < MTK_MAC_COUNT; i++)
1968 mtk_w32(eth, 0, MTK_MAC_MCR(i));
1969
1970 /* Indicates CDM to parse the MTK special tag from CPU
1971 * which also is working out for untag packets.
1972 */
1973 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
1974 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
1975
1976 /* Enable RX VLan Offloading */
1977 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1978
1979 /* enable interrupt delay for RX */
1980 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
1981
1982 /* disable delay and normal interrupt */
1983 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1984 mtk_tx_irq_disable(eth, ~0);
1985 mtk_rx_irq_disable(eth, ~0);
1986 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1987 mtk_w32(eth, 0, MTK_RST_GL);
1988
1989 /* FE int grouping */
1990 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1991 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1992 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1993 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1994 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1995
1996 for (i = 0; i < 2; i++) {
1997 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1998
1999 /* setup the forward port to send frame to PDMA */
2000 val &= ~0xffff;
2001
2002 /* Enable RX checksum */
2003 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
2004
2005 /* setup the mac dma */
2006 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2007 }
2008
2009 return 0;
2010
2011 err_disable_pm:
2012 pm_runtime_put_sync(eth->dev);
2013 pm_runtime_disable(eth->dev);
2014
2015 return ret;
2016 }
2017
2018 static int mtk_hw_deinit(struct mtk_eth *eth)
2019 {
2020 if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))
2021 return 0;
2022
2023 mtk_clk_disable(eth);
2024
2025 pm_runtime_put_sync(eth->dev);
2026 pm_runtime_disable(eth->dev);
2027
2028 return 0;
2029 }
2030
2031 static int __init mtk_init(struct net_device *dev)
2032 {
2033 struct mtk_mac *mac = netdev_priv(dev);
2034 struct mtk_eth *eth = mac->hw;
2035 const char *mac_addr;
2036
2037 mac_addr = of_get_mac_address(mac->of_node);
2038 if (mac_addr)
2039 ether_addr_copy(dev->dev_addr, mac_addr);
2040
2041 /* If the mac address is invalid, use random mac address */
2042 if (!is_valid_ether_addr(dev->dev_addr)) {
2043 eth_hw_addr_random(dev);
2044 dev_err(eth->dev, "generated random MAC address %pM\n",
2045 dev->dev_addr);
2046 }
2047
2048 return mtk_phy_connect(dev);
2049 }
2050
2051 static void mtk_uninit(struct net_device *dev)
2052 {
2053 struct mtk_mac *mac = netdev_priv(dev);
2054 struct mtk_eth *eth = mac->hw;
2055
2056 phy_disconnect(dev->phydev);
2057 if (of_phy_is_fixed_link(mac->of_node))
2058 of_phy_deregister_fixed_link(mac->of_node);
2059 mtk_tx_irq_disable(eth, ~0);
2060 mtk_rx_irq_disable(eth, ~0);
2061 }
2062
2063 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2064 {
2065 switch (cmd) {
2066 case SIOCGMIIPHY:
2067 case SIOCGMIIREG:
2068 case SIOCSMIIREG:
2069 return phy_mii_ioctl(dev->phydev, ifr, cmd);
2070 default:
2071 break;
2072 }
2073
2074 return -EOPNOTSUPP;
2075 }
2076
2077 static void mtk_pending_work(struct work_struct *work)
2078 {
2079 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
2080 int err, i;
2081 unsigned long restart = 0;
2082
2083 rtnl_lock();
2084
2085 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
2086
2087 while (test_and_set_bit_lock(MTK_RESETTING, &eth->state))
2088 cpu_relax();
2089
2090 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
2091 /* stop all devices to make sure that dma is properly shut down */
2092 for (i = 0; i < MTK_MAC_COUNT; i++) {
2093 if (!eth->netdev[i])
2094 continue;
2095 mtk_stop(eth->netdev[i]);
2096 __set_bit(i, &restart);
2097 }
2098 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
2099
2100 /* restart underlying hardware such as power, clock, pin mux
2101 * and the connected phy
2102 */
2103 mtk_hw_deinit(eth);
2104
2105 if (eth->dev->pins)
2106 pinctrl_select_state(eth->dev->pins->p,
2107 eth->dev->pins->default_state);
2108 mtk_hw_init(eth);
2109
2110 for (i = 0; i < MTK_MAC_COUNT; i++) {
2111 if (!eth->mac[i] ||
2112 of_phy_is_fixed_link(eth->mac[i]->of_node))
2113 continue;
2114 err = phy_init_hw(eth->netdev[i]->phydev);
2115 if (err)
2116 dev_err(eth->dev, "%s: PHY init failed.\n",
2117 eth->netdev[i]->name);
2118 }
2119
2120 /* restart DMA and enable IRQs */
2121 for (i = 0; i < MTK_MAC_COUNT; i++) {
2122 if (!test_bit(i, &restart))
2123 continue;
2124 err = mtk_open(eth->netdev[i]);
2125 if (err) {
2126 netif_alert(eth, ifup, eth->netdev[i],
2127 "Driver up/down cycle failed, closing device.\n");
2128 dev_close(eth->netdev[i]);
2129 }
2130 }
2131
2132 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2133
2134 clear_bit_unlock(MTK_RESETTING, &eth->state);
2135
2136 rtnl_unlock();
2137 }
2138
2139 static int mtk_free_dev(struct mtk_eth *eth)
2140 {
2141 int i;
2142
2143 for (i = 0; i < MTK_MAC_COUNT; i++) {
2144 if (!eth->netdev[i])
2145 continue;
2146 free_netdev(eth->netdev[i]);
2147 }
2148
2149 return 0;
2150 }
2151
2152 static int mtk_unreg_dev(struct mtk_eth *eth)
2153 {
2154 int i;
2155
2156 for (i = 0; i < MTK_MAC_COUNT; i++) {
2157 if (!eth->netdev[i])
2158 continue;
2159 unregister_netdev(eth->netdev[i]);
2160 }
2161
2162 return 0;
2163 }
2164
2165 static int mtk_cleanup(struct mtk_eth *eth)
2166 {
2167 mtk_unreg_dev(eth);
2168 mtk_free_dev(eth);
2169 cancel_work_sync(&eth->pending_work);
2170
2171 return 0;
2172 }
2173
2174 static int mtk_get_link_ksettings(struct net_device *ndev,
2175 struct ethtool_link_ksettings *cmd)
2176 {
2177 struct mtk_mac *mac = netdev_priv(ndev);
2178
2179 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2180 return -EBUSY;
2181
2182 phy_ethtool_ksettings_get(ndev->phydev, cmd);
2183
2184 return 0;
2185 }
2186
2187 static int mtk_set_link_ksettings(struct net_device *ndev,
2188 const struct ethtool_link_ksettings *cmd)
2189 {
2190 struct mtk_mac *mac = netdev_priv(ndev);
2191
2192 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2193 return -EBUSY;
2194
2195 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
2196 }
2197
2198 static void mtk_get_drvinfo(struct net_device *dev,
2199 struct ethtool_drvinfo *info)
2200 {
2201 struct mtk_mac *mac = netdev_priv(dev);
2202
2203 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2204 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2205 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2206 }
2207
2208 static u32 mtk_get_msglevel(struct net_device *dev)
2209 {
2210 struct mtk_mac *mac = netdev_priv(dev);
2211
2212 return mac->hw->msg_enable;
2213 }
2214
2215 static void mtk_set_msglevel(struct net_device *dev, u32 value)
2216 {
2217 struct mtk_mac *mac = netdev_priv(dev);
2218
2219 mac->hw->msg_enable = value;
2220 }
2221
2222 static int mtk_nway_reset(struct net_device *dev)
2223 {
2224 struct mtk_mac *mac = netdev_priv(dev);
2225
2226 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2227 return -EBUSY;
2228
2229 return genphy_restart_aneg(dev->phydev);
2230 }
2231
2232 static u32 mtk_get_link(struct net_device *dev)
2233 {
2234 struct mtk_mac *mac = netdev_priv(dev);
2235 int err;
2236
2237 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2238 return -EBUSY;
2239
2240 err = genphy_update_link(dev->phydev);
2241 if (err)
2242 return ethtool_op_get_link(dev);
2243
2244 return dev->phydev->link;
2245 }
2246
2247 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2248 {
2249 int i;
2250
2251 switch (stringset) {
2252 case ETH_SS_STATS:
2253 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2254 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2255 data += ETH_GSTRING_LEN;
2256 }
2257 break;
2258 }
2259 }
2260
2261 static int mtk_get_sset_count(struct net_device *dev, int sset)
2262 {
2263 switch (sset) {
2264 case ETH_SS_STATS:
2265 return ARRAY_SIZE(mtk_ethtool_stats);
2266 default:
2267 return -EOPNOTSUPP;
2268 }
2269 }
2270
2271 static void mtk_get_ethtool_stats(struct net_device *dev,
2272 struct ethtool_stats *stats, u64 *data)
2273 {
2274 struct mtk_mac *mac = netdev_priv(dev);
2275 struct mtk_hw_stats *hwstats = mac->hw_stats;
2276 u64 *data_src, *data_dst;
2277 unsigned int start;
2278 int i;
2279
2280 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2281 return;
2282
2283 if (netif_running(dev) && netif_device_present(dev)) {
2284 if (spin_trylock_bh(&hwstats->stats_lock)) {
2285 mtk_stats_update_mac(mac);
2286 spin_unlock_bh(&hwstats->stats_lock);
2287 }
2288 }
2289
2290 data_src = (u64 *)hwstats;
2291
2292 do {
2293 data_dst = data;
2294 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2295
2296 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2297 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2298 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2299 }
2300
2301 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2302 u32 *rule_locs)
2303 {
2304 int ret = -EOPNOTSUPP;
2305
2306 switch (cmd->cmd) {
2307 case ETHTOOL_GRXRINGS:
2308 if (dev->hw_features & NETIF_F_LRO) {
2309 cmd->data = MTK_MAX_RX_RING_NUM;
2310 ret = 0;
2311 }
2312 break;
2313 case ETHTOOL_GRXCLSRLCNT:
2314 if (dev->hw_features & NETIF_F_LRO) {
2315 struct mtk_mac *mac = netdev_priv(dev);
2316
2317 cmd->rule_cnt = mac->hwlro_ip_cnt;
2318 ret = 0;
2319 }
2320 break;
2321 case ETHTOOL_GRXCLSRULE:
2322 if (dev->hw_features & NETIF_F_LRO)
2323 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2324 break;
2325 case ETHTOOL_GRXCLSRLALL:
2326 if (dev->hw_features & NETIF_F_LRO)
2327 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2328 rule_locs);
2329 break;
2330 default:
2331 break;
2332 }
2333
2334 return ret;
2335 }
2336
2337 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2338 {
2339 int ret = -EOPNOTSUPP;
2340
2341 switch (cmd->cmd) {
2342 case ETHTOOL_SRXCLSRLINS:
2343 if (dev->hw_features & NETIF_F_LRO)
2344 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2345 break;
2346 case ETHTOOL_SRXCLSRLDEL:
2347 if (dev->hw_features & NETIF_F_LRO)
2348 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2349 break;
2350 default:
2351 break;
2352 }
2353
2354 return ret;
2355 }
2356
2357 static const struct ethtool_ops mtk_ethtool_ops = {
2358 .get_link_ksettings = mtk_get_link_ksettings,
2359 .set_link_ksettings = mtk_set_link_ksettings,
2360 .get_drvinfo = mtk_get_drvinfo,
2361 .get_msglevel = mtk_get_msglevel,
2362 .set_msglevel = mtk_set_msglevel,
2363 .nway_reset = mtk_nway_reset,
2364 .get_link = mtk_get_link,
2365 .get_strings = mtk_get_strings,
2366 .get_sset_count = mtk_get_sset_count,
2367 .get_ethtool_stats = mtk_get_ethtool_stats,
2368 .get_rxnfc = mtk_get_rxnfc,
2369 .set_rxnfc = mtk_set_rxnfc,
2370 };
2371
2372 static const struct net_device_ops mtk_netdev_ops = {
2373 .ndo_init = mtk_init,
2374 .ndo_uninit = mtk_uninit,
2375 .ndo_open = mtk_open,
2376 .ndo_stop = mtk_stop,
2377 .ndo_start_xmit = mtk_start_xmit,
2378 .ndo_set_mac_address = mtk_set_mac_address,
2379 .ndo_validate_addr = eth_validate_addr,
2380 .ndo_do_ioctl = mtk_do_ioctl,
2381 .ndo_tx_timeout = mtk_tx_timeout,
2382 .ndo_get_stats64 = mtk_get_stats64,
2383 .ndo_fix_features = mtk_fix_features,
2384 .ndo_set_features = mtk_set_features,
2385 #ifdef CONFIG_NET_POLL_CONTROLLER
2386 .ndo_poll_controller = mtk_poll_controller,
2387 #endif
2388 };
2389
2390 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2391 {
2392 struct mtk_mac *mac;
2393 const __be32 *_id = of_get_property(np, "reg", NULL);
2394 int id, err;
2395
2396 if (!_id) {
2397 dev_err(eth->dev, "missing mac id\n");
2398 return -EINVAL;
2399 }
2400
2401 id = be32_to_cpup(_id);
2402 if (id >= MTK_MAC_COUNT) {
2403 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2404 return -EINVAL;
2405 }
2406
2407 if (eth->netdev[id]) {
2408 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2409 return -EINVAL;
2410 }
2411
2412 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2413 if (!eth->netdev[id]) {
2414 dev_err(eth->dev, "alloc_etherdev failed\n");
2415 return -ENOMEM;
2416 }
2417 mac = netdev_priv(eth->netdev[id]);
2418 eth->mac[id] = mac;
2419 mac->id = id;
2420 mac->hw = eth;
2421 mac->of_node = np;
2422
2423 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2424 mac->hwlro_ip_cnt = 0;
2425
2426 mac->hw_stats = devm_kzalloc(eth->dev,
2427 sizeof(*mac->hw_stats),
2428 GFP_KERNEL);
2429 if (!mac->hw_stats) {
2430 dev_err(eth->dev, "failed to allocate counter memory\n");
2431 err = -ENOMEM;
2432 goto free_netdev;
2433 }
2434 spin_lock_init(&mac->hw_stats->stats_lock);
2435 u64_stats_init(&mac->hw_stats->syncp);
2436 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2437
2438 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2439 eth->netdev[id]->watchdog_timeo = 5 * HZ;
2440 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2441 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2442
2443 eth->netdev[id]->hw_features = MTK_HW_FEATURES;
2444 if (eth->hwlro)
2445 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2446
2447 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
2448 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2449 eth->netdev[id]->features |= MTK_HW_FEATURES;
2450 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2451
2452 eth->netdev[id]->irq = eth->irq[0];
2453 eth->netdev[id]->dev.of_node = np;
2454
2455 return 0;
2456
2457 free_netdev:
2458 free_netdev(eth->netdev[id]);
2459 return err;
2460 }
2461
2462 static int mtk_probe(struct platform_device *pdev)
2463 {
2464 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2465 struct device_node *mac_np;
2466 struct mtk_eth *eth;
2467 int err;
2468 int i;
2469
2470 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2471 if (!eth)
2472 return -ENOMEM;
2473
2474 eth->soc = of_device_get_match_data(&pdev->dev);
2475
2476 eth->dev = &pdev->dev;
2477 eth->base = devm_ioremap_resource(&pdev->dev, res);
2478 if (IS_ERR(eth->base))
2479 return PTR_ERR(eth->base);
2480
2481 spin_lock_init(&eth->page_lock);
2482 spin_lock_init(&eth->tx_irq_lock);
2483 spin_lock_init(&eth->rx_irq_lock);
2484
2485 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2486 "mediatek,ethsys");
2487 if (IS_ERR(eth->ethsys)) {
2488 dev_err(&pdev->dev, "no ethsys regmap found\n");
2489 return PTR_ERR(eth->ethsys);
2490 }
2491
2492 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
2493 eth->sgmiisys =
2494 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2495 "mediatek,sgmiisys");
2496 if (IS_ERR(eth->sgmiisys)) {
2497 dev_err(&pdev->dev, "no sgmiisys regmap found\n");
2498 return PTR_ERR(eth->sgmiisys);
2499 }
2500 }
2501
2502 if (eth->soc->required_pctl) {
2503 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2504 "mediatek,pctl");
2505 if (IS_ERR(eth->pctl)) {
2506 dev_err(&pdev->dev, "no pctl regmap found\n");
2507 return PTR_ERR(eth->pctl);
2508 }
2509 }
2510
2511 for (i = 0; i < 3; i++) {
2512 eth->irq[i] = platform_get_irq(pdev, i);
2513 if (eth->irq[i] < 0) {
2514 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2515 return -ENXIO;
2516 }
2517 }
2518 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2519 eth->clks[i] = devm_clk_get(eth->dev,
2520 mtk_clks_source_name[i]);
2521 if (IS_ERR(eth->clks[i])) {
2522 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2523 return -EPROBE_DEFER;
2524 if (eth->soc->required_clks & BIT(i)) {
2525 dev_err(&pdev->dev, "clock %s not found\n",
2526 mtk_clks_source_name[i]);
2527 return -EINVAL;
2528 }
2529 eth->clks[i] = NULL;
2530 }
2531 }
2532
2533 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2534 INIT_WORK(&eth->pending_work, mtk_pending_work);
2535
2536 err = mtk_hw_init(eth);
2537 if (err)
2538 return err;
2539
2540 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
2541
2542 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2543 if (!of_device_is_compatible(mac_np,
2544 "mediatek,eth-mac"))
2545 continue;
2546
2547 if (!of_device_is_available(mac_np))
2548 continue;
2549
2550 err = mtk_add_mac(eth, mac_np);
2551 if (err)
2552 goto err_deinit_hw;
2553 }
2554
2555 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
2556 dev_name(eth->dev), eth);
2557 if (err)
2558 goto err_free_dev;
2559
2560 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
2561 dev_name(eth->dev), eth);
2562 if (err)
2563 goto err_free_dev;
2564
2565 err = mtk_mdio_init(eth);
2566 if (err)
2567 goto err_free_dev;
2568
2569 for (i = 0; i < MTK_MAX_DEVS; i++) {
2570 if (!eth->netdev[i])
2571 continue;
2572
2573 err = register_netdev(eth->netdev[i]);
2574 if (err) {
2575 dev_err(eth->dev, "error bringing up device\n");
2576 goto err_deinit_mdio;
2577 } else
2578 netif_info(eth, probe, eth->netdev[i],
2579 "mediatek frame engine at 0x%08lx, irq %d\n",
2580 eth->netdev[i]->base_addr, eth->irq[0]);
2581 }
2582
2583 /* we run 2 devices on the same DMA ring so we need a dummy device
2584 * for NAPI to work
2585 */
2586 init_dummy_netdev(&eth->dummy_dev);
2587 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
2588 MTK_NAPI_WEIGHT);
2589 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
2590 MTK_NAPI_WEIGHT);
2591
2592 platform_set_drvdata(pdev, eth);
2593
2594 return 0;
2595
2596 err_deinit_mdio:
2597 mtk_mdio_cleanup(eth);
2598 err_free_dev:
2599 mtk_free_dev(eth);
2600 err_deinit_hw:
2601 mtk_hw_deinit(eth);
2602
2603 return err;
2604 }
2605
2606 static int mtk_remove(struct platform_device *pdev)
2607 {
2608 struct mtk_eth *eth = platform_get_drvdata(pdev);
2609 int i;
2610
2611 /* stop all devices to make sure that dma is properly shut down */
2612 for (i = 0; i < MTK_MAC_COUNT; i++) {
2613 if (!eth->netdev[i])
2614 continue;
2615 mtk_stop(eth->netdev[i]);
2616 }
2617
2618 mtk_hw_deinit(eth);
2619
2620 netif_napi_del(&eth->tx_napi);
2621 netif_napi_del(&eth->rx_napi);
2622 mtk_cleanup(eth);
2623 mtk_mdio_cleanup(eth);
2624
2625 return 0;
2626 }
2627
2628 static const struct mtk_soc_data mt2701_data = {
2629 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO,
2630 .required_clks = MT7623_CLKS_BITMAP,
2631 .required_pctl = true,
2632 };
2633
2634 static const struct mtk_soc_data mt7622_data = {
2635 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO,
2636 .required_clks = MT7622_CLKS_BITMAP,
2637 .required_pctl = false,
2638 };
2639
2640 static const struct mtk_soc_data mt7623_data = {
2641 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO,
2642 .required_clks = MT7623_CLKS_BITMAP,
2643 .required_pctl = true,
2644 };
2645
2646 const struct of_device_id of_mtk_match[] = {
2647 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
2648 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
2649 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
2650 {},
2651 };
2652 MODULE_DEVICE_TABLE(of, of_mtk_match);
2653
2654 static struct platform_driver mtk_driver = {
2655 .probe = mtk_probe,
2656 .remove = mtk_remove,
2657 .driver = {
2658 .name = "mtk_soc_eth",
2659 .of_match_table = of_mtk_match,
2660 },
2661 };
2662
2663 module_platform_driver(mtk_driver);
2664
2665 MODULE_LICENSE("GPL");
2666 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2667 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux with added FPC-III support