?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / qlogic / netxen / netxen_nic_ctx.c
blob7503aa222392f7f9634277ecb9a886a188bf7ea6
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 * The full GNU General Public License is included in this distribution
20 * in the file called "COPYING".
21 *
22 */
23
24 #include "netxen_nic_hw.h"
25 #include "netxen_nic.h"
26
27 #define NXHAL_VERSION 1
28
29 static u32
30 netxen_poll_rsp(struct netxen_adapter *adapter)
31 {
32 u32 rsp = NX_CDRP_RSP_OK;
33 int timeout = 0;
34
35 do {
36 /* give atleast 1ms for firmware to respond */
37 msleep(1);
38
39 if (++timeout > NX_OS_CRB_RETRY_COUNT)
40 return NX_CDRP_RSP_TIMEOUT;
41
42 rsp = NXRD32(adapter, NX_CDRP_CRB_OFFSET);
43 } while (!NX_CDRP_IS_RSP(rsp));
44
45 return rsp;
46 }
47
48 static u32
49 netxen_issue_cmd(struct netxen_adapter *adapter, struct netxen_cmd_args *cmd)
50 {
51 u32 rsp;
52 u32 signature = 0;
53 u32 rcode = NX_RCODE_SUCCESS;
54
55 signature = NX_CDRP_SIGNATURE_MAKE(adapter->ahw.pci_func,
56 NXHAL_VERSION);
57 /* Acquire semaphore before accessing CRB */
58 if (netxen_api_lock(adapter))
59 return NX_RCODE_TIMEOUT;
60
61 NXWR32(adapter, NX_SIGN_CRB_OFFSET, signature);
62
63 NXWR32(adapter, NX_ARG1_CRB_OFFSET, cmd->req.arg1);
64
65 NXWR32(adapter, NX_ARG2_CRB_OFFSET, cmd->req.arg2);
66
67 NXWR32(adapter, NX_ARG3_CRB_OFFSET, cmd->req.arg3);
68
69 NXWR32(adapter, NX_CDRP_CRB_OFFSET, NX_CDRP_FORM_CMD(cmd->req.cmd));
70
71 rsp = netxen_poll_rsp(adapter);
72
73 if (rsp == NX_CDRP_RSP_TIMEOUT) {
74 printk(KERN_ERR "%s: card response timeout.\n",
75 netxen_nic_driver_name);
76
77 rcode = NX_RCODE_TIMEOUT;
78 } else if (rsp == NX_CDRP_RSP_FAIL) {
79 rcode = NXRD32(adapter, NX_ARG1_CRB_OFFSET);
80
81 printk(KERN_ERR "%s: failed card response code:0x%x\n",
82 netxen_nic_driver_name, rcode);
83 } else if (rsp == NX_CDRP_RSP_OK) {
84 cmd->rsp.cmd = NX_RCODE_SUCCESS;
85 if (cmd->rsp.arg2)
86 cmd->rsp.arg2 = NXRD32(adapter, NX_ARG2_CRB_OFFSET);
87 if (cmd->rsp.arg3)
88 cmd->rsp.arg3 = NXRD32(adapter, NX_ARG3_CRB_OFFSET);
89 }
90
91 if (cmd->rsp.arg1)
92 cmd->rsp.arg1 = NXRD32(adapter, NX_ARG1_CRB_OFFSET);
93 /* Release semaphore */
94 netxen_api_unlock(adapter);
95
96 return rcode;
97 }
98
99 static int
100 netxen_get_minidump_template_size(struct netxen_adapter *adapter)
101 {
102 struct netxen_cmd_args cmd;
103 memset(&cmd, 0, sizeof(cmd));
104 cmd.req.cmd = NX_CDRP_CMD_TEMP_SIZE;
105 memset(&cmd.rsp, 1, sizeof(struct _cdrp_cmd));
106 netxen_issue_cmd(adapter, &cmd);
107 if (cmd.rsp.cmd != NX_RCODE_SUCCESS) {
108 dev_info(&adapter->pdev->dev,
109 "Can't get template size %d\n", cmd.rsp.cmd);
110 return -EIO;
111 }
112 adapter->mdump.md_template_size = cmd.rsp.arg2;
113 adapter->mdump.md_template_ver = cmd.rsp.arg3;
114 return 0;
115 }
116
117 static int
118 netxen_get_minidump_template(struct netxen_adapter *adapter)
119 {
120 dma_addr_t md_template_addr;
121 void *addr;
122 u32 size;
123 struct netxen_cmd_args cmd;
124 size = adapter->mdump.md_template_size;
125
126 if (size == 0) {
127 dev_err(&adapter->pdev->dev, "Can not capture Minidump "
128 "template. Invalid template size.\n");
129 return NX_RCODE_INVALID_ARGS;
130 }
131
132 addr = pci_zalloc_consistent(adapter->pdev, size, &md_template_addr);
133 if (!addr) {
134 dev_err(&adapter->pdev->dev, "Unable to allocate dmable memory for template.\n");
135 return -ENOMEM;
136 }
137
138 memset(&cmd, 0, sizeof(cmd));
139 memset(&cmd.rsp, 1, sizeof(struct _cdrp_cmd));
140 cmd.req.cmd = NX_CDRP_CMD_GET_TEMP_HDR;
141 cmd.req.arg1 = LSD(md_template_addr);
142 cmd.req.arg2 = MSD(md_template_addr);
143 cmd.req.arg3 |= size;
144 netxen_issue_cmd(adapter, &cmd);
145
146 if ((cmd.rsp.cmd == NX_RCODE_SUCCESS) && (size == cmd.rsp.arg2)) {
147 memcpy(adapter->mdump.md_template, addr, size);
148 } else {
149 dev_err(&adapter->pdev->dev, "Failed to get minidump template, err_code : %d, requested_size : %d, actual_size : %d\n",
150 cmd.rsp.cmd, size, cmd.rsp.arg2);
151 }
152 pci_free_consistent(adapter->pdev, size, addr, md_template_addr);
153 return 0;
154 }
155
156 static u32
157 netxen_check_template_checksum(struct netxen_adapter *adapter)
158 {
159 u64 sum = 0 ;
160 u32 *buff = adapter->mdump.md_template;
161 int count = adapter->mdump.md_template_size/sizeof(uint32_t) ;
162
163 while (count-- > 0)
164 sum += *buff++ ;
165 while (sum >> 32)
166 sum = (sum & 0xFFFFFFFF) + (sum >> 32) ;
167
168 return ~sum;
169 }
170
171 int
172 netxen_setup_minidump(struct netxen_adapter *adapter)
173 {
174 int err = 0, i;
175 u32 *template, *tmp_buf;
176 err = netxen_get_minidump_template_size(adapter);
177 if (err) {
178 adapter->mdump.fw_supports_md = 0;
179 if ((err == NX_RCODE_CMD_INVALID) ||
180 (err == NX_RCODE_CMD_NOT_IMPL)) {
181 dev_info(&adapter->pdev->dev,
182 "Flashed firmware version does not support minidump, minimum version required is [ %u.%u.%u ]\n",
183 NX_MD_SUPPORT_MAJOR, NX_MD_SUPPORT_MINOR,
184 NX_MD_SUPPORT_SUBVERSION);
185 }
186 return err;
187 }
188
189 if (!adapter->mdump.md_template_size) {
190 dev_err(&adapter->pdev->dev, "Error : Invalid template size "
191 ",should be non-zero.\n");
192 return -EIO;
193 }
194 adapter->mdump.md_template =
195 kmalloc(adapter->mdump.md_template_size, GFP_KERNEL);
196
197 if (!adapter->mdump.md_template)
198 return -ENOMEM;
199
200 err = netxen_get_minidump_template(adapter);
201 if (err) {
202 if (err == NX_RCODE_CMD_NOT_IMPL)
203 adapter->mdump.fw_supports_md = 0;
204 goto free_template;
205 }
206
207 if (netxen_check_template_checksum(adapter)) {
208 dev_err(&adapter->pdev->dev, "Minidump template checksum Error\n");
209 err = -EIO;
210 goto free_template;
211 }
212
213 adapter->mdump.md_capture_mask = NX_DUMP_MASK_DEF;
214 tmp_buf = (u32 *) adapter->mdump.md_template;
215 template = (u32 *) adapter->mdump.md_template;
216 for (i = 0; i < adapter->mdump.md_template_size/sizeof(u32); i++)
217 *template++ = __le32_to_cpu(*tmp_buf++);
218 adapter->mdump.md_capture_buff = NULL;
219 adapter->mdump.fw_supports_md = 1;
220 adapter->mdump.md_enabled = 0;
221
222 return err;
223
224 free_template:
225 kfree(adapter->mdump.md_template);
226 adapter->mdump.md_template = NULL;
227 return err;
228 }
229
230
231 int
232 nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu)
233 {
234 u32 rcode = NX_RCODE_SUCCESS;
235 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
236 struct netxen_cmd_args cmd;
237
238 memset(&cmd, 0, sizeof(cmd));
239 cmd.req.cmd = NX_CDRP_CMD_SET_MTU;
240 cmd.req.arg1 = recv_ctx->context_id;
241 cmd.req.arg2 = mtu;
242 cmd.req.arg3 = 0;
243
244 if (recv_ctx->state == NX_HOST_CTX_STATE_ACTIVE)
245 rcode = netxen_issue_cmd(adapter, &cmd);
246
247 if (rcode != NX_RCODE_SUCCESS)
248 return -EIO;
249
250 return 0;
251 }
252
253 int
254 nx_fw_cmd_set_gbe_port(struct netxen_adapter *adapter,
255 u32 speed, u32 duplex, u32 autoneg)
256 {
257 struct netxen_cmd_args cmd;
258
259 memset(&cmd, 0, sizeof(cmd));
260 cmd.req.cmd = NX_CDRP_CMD_CONFIG_GBE_PORT;
261 cmd.req.arg1 = speed;
262 cmd.req.arg2 = duplex;
263 cmd.req.arg3 = autoneg;
264 return netxen_issue_cmd(adapter, &cmd);
265 }
266
267 static int
268 nx_fw_cmd_create_rx_ctx(struct netxen_adapter *adapter)
269 {
270 void *addr;
271 nx_hostrq_rx_ctx_t *prq;
272 nx_cardrsp_rx_ctx_t *prsp;
273 nx_hostrq_rds_ring_t *prq_rds;
274 nx_hostrq_sds_ring_t *prq_sds;
275 nx_cardrsp_rds_ring_t *prsp_rds;
276 nx_cardrsp_sds_ring_t *prsp_sds;
277 struct nx_host_rds_ring *rds_ring;
278 struct nx_host_sds_ring *sds_ring;
279 struct netxen_cmd_args cmd;
280
281 dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
282 u64 phys_addr;
283
284 int i, nrds_rings, nsds_rings;
285 size_t rq_size, rsp_size;
286 u32 cap, reg, val;
287
288 int err;
289
290 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
291
292 nrds_rings = adapter->max_rds_rings;
293 nsds_rings = adapter->max_sds_rings;
294
295 rq_size =
296 SIZEOF_HOSTRQ_RX(nx_hostrq_rx_ctx_t, nrds_rings, nsds_rings);
297 rsp_size =
298 SIZEOF_CARDRSP_RX(nx_cardrsp_rx_ctx_t, nrds_rings, nsds_rings);
299
300 addr = pci_alloc_consistent(adapter->pdev,
301 rq_size, &hostrq_phys_addr);
302 if (addr == NULL)
303 return -ENOMEM;
304 prq = addr;
305
306 addr = pci_alloc_consistent(adapter->pdev,
307 rsp_size, &cardrsp_phys_addr);
308 if (addr == NULL) {
309 err = -ENOMEM;
310 goto out_free_rq;
311 }
312 prsp = addr;
313
314 prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
315
316 cap = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN);
317 cap |= (NX_CAP0_JUMBO_CONTIGUOUS | NX_CAP0_LRO_CONTIGUOUS);
318
319 if (adapter->flags & NETXEN_FW_MSS_CAP)
320 cap |= NX_CAP0_HW_LRO_MSS;
321
322 prq->capabilities[0] = cpu_to_le32(cap);
323 prq->host_int_crb_mode =
324 cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
325 prq->host_rds_crb_mode =
326 cpu_to_le32(NX_HOST_RDS_CRB_MODE_UNIQUE);
327
328 prq->num_rds_rings = cpu_to_le16(nrds_rings);
329 prq->num_sds_rings = cpu_to_le16(nsds_rings);
330 prq->rds_ring_offset = cpu_to_le32(0);
331
332 val = le32_to_cpu(prq->rds_ring_offset) +
333 (sizeof(nx_hostrq_rds_ring_t) * nrds_rings);
334 prq->sds_ring_offset = cpu_to_le32(val);
335
336 prq_rds = (nx_hostrq_rds_ring_t *)(prq->data +
337 le32_to_cpu(prq->rds_ring_offset));
338
339 for (i = 0; i < nrds_rings; i++) {
340
341 rds_ring = &recv_ctx->rds_rings[i];
342
343 prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
344 prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
345 prq_rds[i].ring_kind = cpu_to_le32(i);
346 prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
347 }
348
349 prq_sds = (nx_hostrq_sds_ring_t *)(prq->data +
350 le32_to_cpu(prq->sds_ring_offset));
351
352 for (i = 0; i < nsds_rings; i++) {
353
354 sds_ring = &recv_ctx->sds_rings[i];
355
356 prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
357 prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
358 prq_sds[i].msi_index = cpu_to_le16(i);
359 }
360
361 phys_addr = hostrq_phys_addr;
362 memset(&cmd, 0, sizeof(cmd));
363 cmd.req.arg1 = (u32)(phys_addr >> 32);
364 cmd.req.arg2 = (u32)(phys_addr & 0xffffffff);
365 cmd.req.arg3 = rq_size;
366 cmd.req.cmd = NX_CDRP_CMD_CREATE_RX_CTX;
367 err = netxen_issue_cmd(adapter, &cmd);
368 if (err) {
369 printk(KERN_WARNING
370 "Failed to create rx ctx in firmware%d\n", err);
371 goto out_free_rsp;
372 }
373
374
375 prsp_rds = ((nx_cardrsp_rds_ring_t *)
376 &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
377
378 for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
379 rds_ring = &recv_ctx->rds_rings[i];
380
381 reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
382 rds_ring->crb_rcv_producer = netxen_get_ioaddr(adapter,
383 NETXEN_NIC_REG(reg - 0x200));
384 }
385
386 prsp_sds = ((nx_cardrsp_sds_ring_t *)
387 &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
388
389 for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
390 sds_ring = &recv_ctx->sds_rings[i];
391
392 reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
393 sds_ring->crb_sts_consumer = netxen_get_ioaddr(adapter,
394 NETXEN_NIC_REG(reg - 0x200));
395
396 reg = le32_to_cpu(prsp_sds[i].interrupt_crb);
397 sds_ring->crb_intr_mask = netxen_get_ioaddr(adapter,
398 NETXEN_NIC_REG(reg - 0x200));
399 }
400
401 recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
402 recv_ctx->context_id = le16_to_cpu(prsp->context_id);
403 recv_ctx->virt_port = prsp->virt_port;
404
405 out_free_rsp:
406 pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr);
407 out_free_rq:
408 pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr);
409 return err;
410 }
411
412 static void
413 nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter)
414 {
415 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
416 struct netxen_cmd_args cmd;
417
418 memset(&cmd, 0, sizeof(cmd));
419 cmd.req.arg1 = recv_ctx->context_id;
420 cmd.req.arg2 = NX_DESTROY_CTX_RESET;
421 cmd.req.arg3 = 0;
422 cmd.req.cmd = NX_CDRP_CMD_DESTROY_RX_CTX;
423
424 if (netxen_issue_cmd(adapter, &cmd)) {
425 printk(KERN_WARNING
426 "%s: Failed to destroy rx ctx in firmware\n",
427 netxen_nic_driver_name);
428 }
429 }
430
431 static int
432 nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter)
433 {
434 nx_hostrq_tx_ctx_t *prq;
435 nx_hostrq_cds_ring_t *prq_cds;
436 nx_cardrsp_tx_ctx_t *prsp;
437 void *rq_addr, *rsp_addr;
438 size_t rq_size, rsp_size;
439 u32 temp;
440 int err = 0;
441 u64 offset, phys_addr;
442 dma_addr_t rq_phys_addr, rsp_phys_addr;
443 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
444 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
445 struct netxen_cmd_args cmd;
446
447 rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t);
448 rq_addr = pci_alloc_consistent(adapter->pdev,
449 rq_size, &rq_phys_addr);
450 if (!rq_addr)
451 return -ENOMEM;
452
453 rsp_size = SIZEOF_CARDRSP_TX(nx_cardrsp_tx_ctx_t);
454 rsp_addr = pci_alloc_consistent(adapter->pdev,
455 rsp_size, &rsp_phys_addr);
456 if (!rsp_addr) {
457 err = -ENOMEM;
458 goto out_free_rq;
459 }
460
461 memset(rq_addr, 0, rq_size);
462 prq = rq_addr;
463
464 memset(rsp_addr, 0, rsp_size);
465 prsp = rsp_addr;
466
467 prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
468
469 temp = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN | NX_CAP0_LSO);
470 prq->capabilities[0] = cpu_to_le32(temp);
471
472 prq->host_int_crb_mode =
473 cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
474
475 prq->interrupt_ctl = 0;
476 prq->msi_index = 0;
477
478 prq->dummy_dma_addr = cpu_to_le64(adapter->dummy_dma.phys_addr);
479
480 offset = recv_ctx->phys_addr + sizeof(struct netxen_ring_ctx);
481 prq->cmd_cons_dma_addr = cpu_to_le64(offset);
482
483 prq_cds = &prq->cds_ring;
484
485 prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
486 prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
487
488 phys_addr = rq_phys_addr;
489 memset(&cmd, 0, sizeof(cmd));
490 cmd.req.arg1 = (u32)(phys_addr >> 32);
491 cmd.req.arg2 = ((u32)phys_addr & 0xffffffff);
492 cmd.req.arg3 = rq_size;
493 cmd.req.cmd = NX_CDRP_CMD_CREATE_TX_CTX;
494 err = netxen_issue_cmd(adapter, &cmd);
495
496 if (err == NX_RCODE_SUCCESS) {
497 temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
498 tx_ring->crb_cmd_producer = netxen_get_ioaddr(adapter,
499 NETXEN_NIC_REG(temp - 0x200));
500 #if 0
501 adapter->tx_state =
502 le32_to_cpu(prsp->host_ctx_state);
503 #endif
504 adapter->tx_context_id =
505 le16_to_cpu(prsp->context_id);
506 } else {
507 printk(KERN_WARNING
508 "Failed to create tx ctx in firmware%d\n", err);
509 err = -EIO;
510 }
511
512 pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr);
513
514 out_free_rq:
515 pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr);
516
517 return err;
518 }
519
520 static void
521 nx_fw_cmd_destroy_tx_ctx(struct netxen_adapter *adapter)
522 {
523 struct netxen_cmd_args cmd;
524
525 memset(&cmd, 0, sizeof(cmd));
526 cmd.req.arg1 = adapter->tx_context_id;
527 cmd.req.arg2 = NX_DESTROY_CTX_RESET;
528 cmd.req.arg3 = 0;
529 cmd.req.cmd = NX_CDRP_CMD_DESTROY_TX_CTX;
530 if (netxen_issue_cmd(adapter, &cmd)) {
531 printk(KERN_WARNING
532 "%s: Failed to destroy tx ctx in firmware\n",
533 netxen_nic_driver_name);
534 }
535 }
536
537 int
538 nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val)
539 {
540 u32 rcode;
541 struct netxen_cmd_args cmd;
542
543 memset(&cmd, 0, sizeof(cmd));
544 cmd.req.arg1 = reg;
545 cmd.req.arg2 = 0;
546 cmd.req.arg3 = 0;
547 cmd.req.cmd = NX_CDRP_CMD_READ_PHY;
548 cmd.rsp.arg1 = 1;
549 rcode = netxen_issue_cmd(adapter, &cmd);
550 if (rcode != NX_RCODE_SUCCESS)
551 return -EIO;
552
553 if (val == NULL)
554 return -EIO;
555
556 *val = cmd.rsp.arg1;
557 return 0;
558 }
559
560 int
561 nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val)
562 {
563 u32 rcode;
564 struct netxen_cmd_args cmd;
565
566 memset(&cmd, 0, sizeof(cmd));
567 cmd.req.arg1 = reg;
568 cmd.req.arg2 = val;
569 cmd.req.arg3 = 0;
570 cmd.req.cmd = NX_CDRP_CMD_WRITE_PHY;
571 rcode = netxen_issue_cmd(adapter, &cmd);
572 if (rcode != NX_RCODE_SUCCESS)
573 return -EIO;
574
575 return 0;
576 }
577
578 static u64 ctx_addr_sig_regs[][3] = {
579 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
580 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
581 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
582 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
583 };
584
585 #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
586 #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
587 #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
588
589 #define lower32(x) ((u32)((x) & 0xffffffff))
590 #define upper32(x) ((u32)(((u64)(x) >> 32) & 0xffffffff))
591
592 static struct netxen_recv_crb recv_crb_registers[] = {
593 /* Instance 0 */
594 {
595 /* crb_rcv_producer: */
596 {
597 NETXEN_NIC_REG(0x100),
598 /* Jumbo frames */
599 NETXEN_NIC_REG(0x110),
600 /* LRO */
601 NETXEN_NIC_REG(0x120)
602 },
603 /* crb_sts_consumer: */
604 {
605 NETXEN_NIC_REG(0x138),
606 NETXEN_NIC_REG_2(0x000),
607 NETXEN_NIC_REG_2(0x004),
608 NETXEN_NIC_REG_2(0x008),
609 },
610 /* sw_int_mask */
611 {
612 CRB_SW_INT_MASK_0,
613 NETXEN_NIC_REG_2(0x044),
614 NETXEN_NIC_REG_2(0x048),
615 NETXEN_NIC_REG_2(0x04c),
616 },
617 },
618 /* Instance 1 */
619 {
620 /* crb_rcv_producer: */
621 {
622 NETXEN_NIC_REG(0x144),
623 /* Jumbo frames */
624 NETXEN_NIC_REG(0x154),
625 /* LRO */
626 NETXEN_NIC_REG(0x164)
627 },
628 /* crb_sts_consumer: */
629 {
630 NETXEN_NIC_REG(0x17c),
631 NETXEN_NIC_REG_2(0x020),
632 NETXEN_NIC_REG_2(0x024),
633 NETXEN_NIC_REG_2(0x028),
634 },
635 /* sw_int_mask */
636 {
637 CRB_SW_INT_MASK_1,
638 NETXEN_NIC_REG_2(0x064),
639 NETXEN_NIC_REG_2(0x068),
640 NETXEN_NIC_REG_2(0x06c),
641 },
642 },
643 /* Instance 2 */
644 {
645 /* crb_rcv_producer: */
646 {
647 NETXEN_NIC_REG(0x1d8),
648 /* Jumbo frames */
649 NETXEN_NIC_REG(0x1f8),
650 /* LRO */
651 NETXEN_NIC_REG(0x208)
652 },
653 /* crb_sts_consumer: */
654 {
655 NETXEN_NIC_REG(0x220),
656 NETXEN_NIC_REG_2(0x03c),
657 NETXEN_NIC_REG_2(0x03c),
658 NETXEN_NIC_REG_2(0x03c),
659 },
660 /* sw_int_mask */
661 {
662 CRB_SW_INT_MASK_2,
663 NETXEN_NIC_REG_2(0x03c),
664 NETXEN_NIC_REG_2(0x03c),
665 NETXEN_NIC_REG_2(0x03c),
666 },
667 },
668 /* Instance 3 */
669 {
670 /* crb_rcv_producer: */
671 {
672 NETXEN_NIC_REG(0x22c),
673 /* Jumbo frames */
674 NETXEN_NIC_REG(0x23c),
675 /* LRO */
676 NETXEN_NIC_REG(0x24c)
677 },
678 /* crb_sts_consumer: */
679 {
680 NETXEN_NIC_REG(0x264),
681 NETXEN_NIC_REG_2(0x03c),
682 NETXEN_NIC_REG_2(0x03c),
683 NETXEN_NIC_REG_2(0x03c),
684 },
685 /* sw_int_mask */
686 {
687 CRB_SW_INT_MASK_3,
688 NETXEN_NIC_REG_2(0x03c),
689 NETXEN_NIC_REG_2(0x03c),
690 NETXEN_NIC_REG_2(0x03c),
691 },
692 },
693 };
694
695 static int
696 netxen_init_old_ctx(struct netxen_adapter *adapter)
697 {
698 struct netxen_recv_context *recv_ctx;
699 struct nx_host_rds_ring *rds_ring;
700 struct nx_host_sds_ring *sds_ring;
701 struct nx_host_tx_ring *tx_ring;
702 int ring;
703 int port = adapter->portnum;
704 struct netxen_ring_ctx *hwctx;
705 u32 signature;
706
707 tx_ring = adapter->tx_ring;
708 recv_ctx = &adapter->recv_ctx;
709 hwctx = recv_ctx->hwctx;
710
711 hwctx->cmd_ring_addr = cpu_to_le64(tx_ring->phys_addr);
712 hwctx->cmd_ring_size = cpu_to_le32(tx_ring->num_desc);
713
714
715 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
716 rds_ring = &recv_ctx->rds_rings[ring];
717
718 hwctx->rcv_rings[ring].addr =
719 cpu_to_le64(rds_ring->phys_addr);
720 hwctx->rcv_rings[ring].size =
721 cpu_to_le32(rds_ring->num_desc);
722 }
723
724 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
725 sds_ring = &recv_ctx->sds_rings[ring];
726
727 if (ring == 0) {
728 hwctx->sts_ring_addr = cpu_to_le64(sds_ring->phys_addr);
729 hwctx->sts_ring_size = cpu_to_le32(sds_ring->num_desc);
730 }
731 hwctx->sts_rings[ring].addr = cpu_to_le64(sds_ring->phys_addr);
732 hwctx->sts_rings[ring].size = cpu_to_le32(sds_ring->num_desc);
733 hwctx->sts_rings[ring].msi_index = cpu_to_le16(ring);
734 }
735 hwctx->sts_ring_count = cpu_to_le32(adapter->max_sds_rings);
736
737 signature = (adapter->max_sds_rings > 1) ?
738 NETXEN_CTX_SIGNATURE_V2 : NETXEN_CTX_SIGNATURE;
739
740 NXWR32(adapter, CRB_CTX_ADDR_REG_LO(port),
741 lower32(recv_ctx->phys_addr));
742 NXWR32(adapter, CRB_CTX_ADDR_REG_HI(port),
743 upper32(recv_ctx->phys_addr));
744 NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
745 signature | port);
746 return 0;
747 }
748
749 int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
750 {
751 void *addr;
752 int err = 0;
753 int ring;
754 struct netxen_recv_context *recv_ctx;
755 struct nx_host_rds_ring *rds_ring;
756 struct nx_host_sds_ring *sds_ring;
757 struct nx_host_tx_ring *tx_ring;
758
759 struct pci_dev *pdev = adapter->pdev;
760 struct net_device *netdev = adapter->netdev;
761 int port = adapter->portnum;
762
763 recv_ctx = &adapter->recv_ctx;
764 tx_ring = adapter->tx_ring;
765
766 addr = pci_alloc_consistent(pdev,
767 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
768 &recv_ctx->phys_addr);
769 if (addr == NULL) {
770 dev_err(&pdev->dev, "failed to allocate hw context\n");
771 return -ENOMEM;
772 }
773
774 memset(addr, 0, sizeof(struct netxen_ring_ctx));
775 recv_ctx->hwctx = addr;
776 recv_ctx->hwctx->ctx_id = cpu_to_le32(port);
777 recv_ctx->hwctx->cmd_consumer_offset =
778 cpu_to_le64(recv_ctx->phys_addr +
779 sizeof(struct netxen_ring_ctx));
780 tx_ring->hw_consumer =
781 (__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx));
782
783 /* cmd desc ring */
784 addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring),
785 &tx_ring->phys_addr);
786
787 if (addr == NULL) {
788 dev_err(&pdev->dev, "%s: failed to allocate tx desc ring\n",
789 netdev->name);
790 err = -ENOMEM;
791 goto err_out_free;
792 }
793
794 tx_ring->desc_head = addr;
795
796 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
797 rds_ring = &recv_ctx->rds_rings[ring];
798 addr = pci_alloc_consistent(adapter->pdev,
799 RCV_DESC_RINGSIZE(rds_ring),
800 &rds_ring->phys_addr);
801 if (addr == NULL) {
802 dev_err(&pdev->dev,
803 "%s: failed to allocate rds ring [%d]\n",
804 netdev->name, ring);
805 err = -ENOMEM;
806 goto err_out_free;
807 }
808 rds_ring->desc_head = addr;
809
810 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
811 rds_ring->crb_rcv_producer =
812 netxen_get_ioaddr(adapter,
813 recv_crb_registers[port].crb_rcv_producer[ring]);
814 }
815
816 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
817 sds_ring = &recv_ctx->sds_rings[ring];
818
819 addr = pci_alloc_consistent(adapter->pdev,
820 STATUS_DESC_RINGSIZE(sds_ring),
821 &sds_ring->phys_addr);
822 if (addr == NULL) {
823 dev_err(&pdev->dev,
824 "%s: failed to allocate sds ring [%d]\n",
825 netdev->name, ring);
826 err = -ENOMEM;
827 goto err_out_free;
828 }
829 sds_ring->desc_head = addr;
830
831 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
832 sds_ring->crb_sts_consumer =
833 netxen_get_ioaddr(adapter,
834 recv_crb_registers[port].crb_sts_consumer[ring]);
835
836 sds_ring->crb_intr_mask =
837 netxen_get_ioaddr(adapter,
838 recv_crb_registers[port].sw_int_mask[ring]);
839 }
840 }
841
842
843 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
844 if (test_and_set_bit(__NX_FW_ATTACHED, &adapter->state))
845 goto done;
846 err = nx_fw_cmd_create_rx_ctx(adapter);
847 if (err)
848 goto err_out_free;
849 err = nx_fw_cmd_create_tx_ctx(adapter);
850 if (err)
851 goto err_out_free;
852 } else {
853 err = netxen_init_old_ctx(adapter);
854 if (err)
855 goto err_out_free;
856 }
857
858 done:
859 return 0;
860
861 err_out_free:
862 netxen_free_hw_resources(adapter);
863 return err;
864 }
865
866 void netxen_free_hw_resources(struct netxen_adapter *adapter)
867 {
868 struct netxen_recv_context *recv_ctx;
869 struct nx_host_rds_ring *rds_ring;
870 struct nx_host_sds_ring *sds_ring;
871 struct nx_host_tx_ring *tx_ring;
872 int ring;
873
874 int port = adapter->portnum;
875
876 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
877 if (!test_and_clear_bit(__NX_FW_ATTACHED, &adapter->state))
878 goto done;
879
880 nx_fw_cmd_destroy_rx_ctx(adapter);
881 nx_fw_cmd_destroy_tx_ctx(adapter);
882 } else {
883 netxen_api_lock(adapter);
884 NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
885 NETXEN_CTX_D3_RESET | port);
886 netxen_api_unlock(adapter);
887 }
888
889 /* Allow dma queues to drain after context reset */
890 msleep(20);
891
892 done:
893 recv_ctx = &adapter->recv_ctx;
894
895 if (recv_ctx->hwctx != NULL) {
896 pci_free_consistent(adapter->pdev,
897 sizeof(struct netxen_ring_ctx) +
898 sizeof(uint32_t),
899 recv_ctx->hwctx,
900 recv_ctx->phys_addr);
901 recv_ctx->hwctx = NULL;
902 }
903
904 tx_ring = adapter->tx_ring;
905 if (tx_ring->desc_head != NULL) {
906 pci_free_consistent(adapter->pdev,
907 TX_DESC_RINGSIZE(tx_ring),
908 tx_ring->desc_head, tx_ring->phys_addr);
909 tx_ring->desc_head = NULL;
910 }
911
912 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
913 rds_ring = &recv_ctx->rds_rings[ring];
914
915 if (rds_ring->desc_head != NULL) {
916 pci_free_consistent(adapter->pdev,
917 RCV_DESC_RINGSIZE(rds_ring),
918 rds_ring->desc_head,
919 rds_ring->phys_addr);
920 rds_ring->desc_head = NULL;
921 }
922 }
923
924 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
925 sds_ring = &recv_ctx->sds_rings[ring];
926
927 if (sds_ring->desc_head != NULL) {
928 pci_free_consistent(adapter->pdev,
929 STATUS_DESC_RINGSIZE(sds_ring),
930 sds_ring->desc_head,
931 sds_ring->phys_addr);
932 sds_ring->desc_head = NULL;
933 }
934 }
935 }
936
Linux with added FPC-III support