drivers/net/ethernet/qlogic/qed/qed_hsi.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _QED_HSI_H
  34 #define _QED_HSI_H
  35
  36 #include <linux/types.h>
  37 #include <linux/io.h>
  38 #include <linux/bitops.h>
  39 #include <linux/delay.h>
  40 #include <linux/kernel.h>
  41 #include <linux/list.h>
  42 #include <linux/slab.h>
  43 #include <linux/qed/common_hsi.h>
  44 #include <linux/qed/storage_common.h>
  45 #include <linux/qed/tcp_common.h>
  46 #include <linux/qed/fcoe_common.h>
  47 #include <linux/qed/eth_common.h>
  48 #include <linux/qed/iscsi_common.h>
  49 #include <linux/qed/iwarp_common.h>
  50 #include <linux/qed/rdma_common.h>
  51 #include <linux/qed/roce_common.h>
  52 #include <linux/qed/qed_fcoe_if.h>
  53
  54 struct qed_hwfn;
  55 struct qed_ptt;
  56
  57 /* Opcodes for the event ring */
  58 enum common_event_opcode {
  59         COMMON_EVENT_PF_START,
  60         COMMON_EVENT_PF_STOP,
  61         COMMON_EVENT_VF_START,
  62         COMMON_EVENT_VF_STOP,
  63         COMMON_EVENT_VF_PF_CHANNEL,
  64         COMMON_EVENT_VF_FLR,
  65         COMMON_EVENT_PF_UPDATE,
  66         COMMON_EVENT_MALICIOUS_VF,
  67         COMMON_EVENT_RL_UPDATE,
  68         COMMON_EVENT_EMPTY,
  69         MAX_COMMON_EVENT_OPCODE
  70 };
  71
  72 /* Common Ramrod Command IDs */
  73 enum common_ramrod_cmd_id {
  74         COMMON_RAMROD_UNUSED,
  75         COMMON_RAMROD_PF_START,
  76         COMMON_RAMROD_PF_STOP,
  77         COMMON_RAMROD_VF_START,
  78         COMMON_RAMROD_VF_STOP,
  79         COMMON_RAMROD_PF_UPDATE,
  80         COMMON_RAMROD_RL_UPDATE,
  81         COMMON_RAMROD_EMPTY,
  82         MAX_COMMON_RAMROD_CMD_ID
  83 };
  84
  85 /* How ll2 should deal with packet upon errors */
  86 enum core_error_handle {
  87         LL2_DROP_PACKET,
  88         LL2_DO_NOTHING,
  89         LL2_ASSERT,
  90         MAX_CORE_ERROR_HANDLE
  91 };
  92
  93 /* Opcodes for the event ring */
  94 enum core_event_opcode {
  95         CORE_EVENT_TX_QUEUE_START,
  96         CORE_EVENT_TX_QUEUE_STOP,
  97         CORE_EVENT_RX_QUEUE_START,
  98         CORE_EVENT_RX_QUEUE_STOP,
  99         CORE_EVENT_RX_QUEUE_FLUSH,
 100         CORE_EVENT_TX_QUEUE_UPDATE,
 101         MAX_CORE_EVENT_OPCODE
 102 };
 103
 104 /* The L4 pseudo checksum mode for Core */
 105 enum core_l4_pseudo_checksum_mode {
 106         CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
 107         CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
 108         MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
 109 };
 110
 111 /* Light-L2 RX Producers in Tstorm RAM */
 112 struct core_ll2_port_stats {
 113         struct regpair gsi_invalid_hdr;
 114         struct regpair gsi_invalid_pkt_length;
 115         struct regpair gsi_unsupported_pkt_typ;
 116         struct regpair gsi_crcchksm_error;
 117 };
 118
 119 /* Ethernet TX Per Queue Stats */
 120 struct core_ll2_pstorm_per_queue_stat {
 121         struct regpair sent_ucast_bytes;
 122         struct regpair sent_mcast_bytes;
 123         struct regpair sent_bcast_bytes;
 124         struct regpair sent_ucast_pkts;
 125         struct regpair sent_mcast_pkts;
 126         struct regpair sent_bcast_pkts;
 127 };
 128
 129 /* Light-L2 RX Producers in Tstorm RAM */
 130 struct core_ll2_rx_prod {
 131         __le16 bd_prod;
 132         __le16 cqe_prod;
 133         __le32 reserved;
 134 };
 135
 136 struct core_ll2_tstorm_per_queue_stat {
 137         struct regpair packet_too_big_discard;
 138         struct regpair no_buff_discard;
 139 };
 140
 141 struct core_ll2_ustorm_per_queue_stat {
 142         struct regpair rcv_ucast_bytes;
 143         struct regpair rcv_mcast_bytes;
 144         struct regpair rcv_bcast_bytes;
 145         struct regpair rcv_ucast_pkts;
 146         struct regpair rcv_mcast_pkts;
 147         struct regpair rcv_bcast_pkts;
 148 };
 149
 150 /* Core Ramrod Command IDs (light L2) */
 151 enum core_ramrod_cmd_id {
 152         CORE_RAMROD_UNUSED,
 153         CORE_RAMROD_RX_QUEUE_START,
 154         CORE_RAMROD_TX_QUEUE_START,
 155         CORE_RAMROD_RX_QUEUE_STOP,
 156         CORE_RAMROD_TX_QUEUE_STOP,
 157         CORE_RAMROD_RX_QUEUE_FLUSH,
 158         CORE_RAMROD_TX_QUEUE_UPDATE,
 159         MAX_CORE_RAMROD_CMD_ID
 160 };
 161
 162 /* Core RX CQE Type for Light L2 */
 163 enum core_roce_flavor_type {
 164         CORE_ROCE,
 165         CORE_RROCE,
 166         MAX_CORE_ROCE_FLAVOR_TYPE
 167 };
 168
 169 /* Specifies how ll2 should deal with packets errors: packet_too_big and
 170  * no_buff.
 171  */
 172 struct core_rx_action_on_error {
 173         u8 error_type;
 174 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK     0x3
 175 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT    0
 176 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK            0x3
 177 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT           2
 178 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK           0xF
 179 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT          4
 180 };
 181
 182 /* Core RX BD for Light L2 */
 183 struct core_rx_bd {
 184         struct regpair addr;
 185         __le16 reserved[4];
 186 };
 187
 188 /* Core RX CM offload BD for Light L2 */
 189 struct core_rx_bd_with_buff_len {
 190         struct regpair addr;
 191         __le16 buff_length;
 192         __le16 reserved[3];
 193 };
 194
 195 /* Core RX CM offload BD for Light L2 */
 196 union core_rx_bd_union {
 197         struct core_rx_bd rx_bd;
 198         struct core_rx_bd_with_buff_len rx_bd_with_len;
 199 };
 200
 201 /* Opaque Data for Light L2 RX CQE */
 202 struct core_rx_cqe_opaque_data {
 203         __le32 data[2];
 204 };
 205
 206 /* Core RX CQE Type for Light L2 */
 207 enum core_rx_cqe_type {
 208         CORE_RX_CQE_ILLEGAL_TYPE,
 209         CORE_RX_CQE_TYPE_REGULAR,
 210         CORE_RX_CQE_TYPE_GSI_OFFLOAD,
 211         CORE_RX_CQE_TYPE_SLOW_PATH,
 212         MAX_CORE_RX_CQE_TYPE
 213 };
 214
 215 /* Core RX CQE for Light L2 */
 216 struct core_rx_fast_path_cqe {
 217         u8 type;
 218         u8 placement_offset;
 219         struct parsing_and_err_flags parse_flags;
 220         __le16 packet_length;
 221         __le16 vlan;
 222         struct core_rx_cqe_opaque_data opaque_data;
 223         struct parsing_err_flags err_flags;
 224         __le16 reserved0;
 225         __le32 reserved1[3];
 226 };
 227
 228 /* Core Rx CM offload CQE */
 229 struct core_rx_gsi_offload_cqe {
 230         u8 type;
 231         u8 data_length_error;
 232         struct parsing_and_err_flags parse_flags;
 233         __le16 data_length;
 234         __le16 vlan;
 235         __le32 src_mac_addrhi;
 236         __le16 src_mac_addrlo;
 237         __le16 qp_id;
 238         __le32 src_qp;
 239         __le32 reserved[3];
 240 };
 241
 242 /* Core RX CQE for Light L2 */
 243 struct core_rx_slow_path_cqe {
 244         u8 type;
 245         u8 ramrod_cmd_id;
 246         __le16 echo;
 247         struct core_rx_cqe_opaque_data opaque_data;
 248         __le32 reserved1[5];
 249 };
 250
 251 /* Core RX CM offload BD for Light L2 */
 252 union core_rx_cqe_union {
 253         struct core_rx_fast_path_cqe rx_cqe_fp;
 254         struct core_rx_gsi_offload_cqe rx_cqe_gsi;
 255         struct core_rx_slow_path_cqe rx_cqe_sp;
 256 };
 257
 258 /* Ramrod data for rx queue start ramrod */
 259 struct core_rx_start_ramrod_data {
 260         struct regpair bd_base;
 261         struct regpair cqe_pbl_addr;
 262         __le16 mtu;
 263         __le16 sb_id;
 264         u8 sb_index;
 265         u8 complete_cqe_flg;
 266         u8 complete_event_flg;
 267         u8 drop_ttl0_flg;
 268         __le16 num_of_pbl_pages;
 269         u8 inner_vlan_stripping_en;
 270         u8 report_outer_vlan;
 271         u8 queue_id;
 272         u8 main_func_queue;
 273         u8 mf_si_bcast_accept_all;
 274         u8 mf_si_mcast_accept_all;
 275         struct core_rx_action_on_error action_on_error;
 276         u8 gsi_offload_flag;
 277         u8 reserved[6];
 278 };
 279
 280 /* Ramrod data for rx queue stop ramrod */
 281 struct core_rx_stop_ramrod_data {
 282         u8 complete_cqe_flg;
 283         u8 complete_event_flg;
 284         u8 queue_id;
 285         u8 reserved1;
 286         __le16 reserved2[2];
 287 };
 288
 289 /* Flags for Core TX BD */
 290 struct core_tx_bd_data {
 291         __le16 as_bitfield;
 292 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK            0x1
 293 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT           0
 294 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK             0x1
 295 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT            1
 296 #define CORE_TX_BD_DATA_START_BD_MASK                   0x1
 297 #define CORE_TX_BD_DATA_START_BD_SHIFT                  2
 298 #define CORE_TX_BD_DATA_IP_CSUM_MASK                    0x1
 299 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT                   3
 300 #define CORE_TX_BD_DATA_L4_CSUM_MASK                    0x1
 301 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT                   4
 302 #define CORE_TX_BD_DATA_IPV6_EXT_MASK                   0x1
 303 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT                  5
 304 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK                0x1
 305 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT               6
 306 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK        0x1
 307 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT       7
 308 #define CORE_TX_BD_DATA_NBDS_MASK                       0xF
 309 #define CORE_TX_BD_DATA_NBDS_SHIFT                      8
 310 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK                  0x1
 311 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT                 12
 312 #define CORE_TX_BD_DATA_IP_LEN_MASK                     0x1
 313 #define CORE_TX_BD_DATA_IP_LEN_SHIFT                    13
 314 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK     0x1
 315 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT    14
 316 #define CORE_TX_BD_DATA_RESERVED0_MASK                  0x1
 317 #define CORE_TX_BD_DATA_RESERVED0_SHIFT                 15
 318 };
 319
 320 /* Core TX BD for Light L2 */
 321 struct core_tx_bd {
 322         struct regpair addr;
 323         __le16 nbytes;
 324         __le16 nw_vlan_or_lb_echo;
 325         struct core_tx_bd_data bd_data;
 326         __le16 bitfield1;
 327 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK         0x3FFF
 328 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT        0
 329 #define CORE_TX_BD_TX_DST_MASK                  0x3
 330 #define CORE_TX_BD_TX_DST_SHIFT                 14
 331 };
 332
 333 /* Light L2 TX Destination */
 334 enum core_tx_dest {
 335         CORE_TX_DEST_NW,
 336         CORE_TX_DEST_LB,
 337         CORE_TX_DEST_RESERVED,
 338         CORE_TX_DEST_DROP,
 339         MAX_CORE_TX_DEST
 340 };
 341
 342 /* Ramrod data for tx queue start ramrod */
 343 struct core_tx_start_ramrod_data {
 344         struct regpair pbl_base_addr;
 345         __le16 mtu;
 346         __le16 sb_id;
 347         u8 sb_index;
 348         u8 stats_en;
 349         u8 stats_id;
 350         u8 conn_type;
 351         __le16 pbl_size;
 352         __le16 qm_pq_id;
 353         u8 gsi_offload_flag;
 354         u8 resrved[3];
 355 };
 356
 357 /* Ramrod data for tx queue stop ramrod */
 358 struct core_tx_stop_ramrod_data {
 359         __le32 reserved0[2];
 360 };
 361
 362 /* Ramrod data for tx queue update ramrod */
 363 struct core_tx_update_ramrod_data {
 364         u8 update_qm_pq_id_flg;
 365         u8 reserved0;
 366         __le16 qm_pq_id;
 367         __le32 reserved1[1];
 368 };
 369
 370 /* Enum flag for what type of dcb data to update */
 371 enum dcb_dscp_update_mode {
 372         DONT_UPDATE_DCB_DSCP,
 373         UPDATE_DCB,
 374         UPDATE_DSCP,
 375         UPDATE_DCB_DSCP,
 376         MAX_DCB_DSCP_UPDATE_MODE
 377 };
 378
 379 /* The core storm context for the Ystorm */
 380 struct ystorm_core_conn_st_ctx {
 381         __le32 reserved[4];
 382 };
 383
 384 /* The core storm context for the Pstorm */
 385 struct pstorm_core_conn_st_ctx {
 386         __le32 reserved[4];
 387 };
 388
 389 /* Core Slowpath Connection storm context of Xstorm */
 390 struct xstorm_core_conn_st_ctx {
 391         __le32 spq_base_lo;
 392         __le32 spq_base_hi;
 393         struct regpair consolid_base_addr;
 394         __le16 spq_cons;
 395         __le16 consolid_cons;
 396         __le32 reserved0[55];
 397 };
 398
 399 struct e4_xstorm_core_conn_ag_ctx {
 400         u8 reserved0;
 401         u8 state;
 402         u8 flags0;
 403 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK    0x1
 404 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT   0
 405 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK       0x1
 406 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT      1
 407 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK       0x1
 408 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT      2
 409 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK    0x1
 410 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT   3
 411 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK       0x1
 412 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT      4
 413 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK       0x1
 414 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT      5
 415 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK       0x1
 416 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT      6
 417 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK       0x1
 418 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT      7
 419         u8 flags1;
 420 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK       0x1
 421 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT      0
 422 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK       0x1
 423 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT      1
 424 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK       0x1
 425 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT      2
 426 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK           0x1
 427 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT          3
 428 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK           0x1
 429 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT          4
 430 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK           0x1
 431 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT          5
 432 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK  0x1
 433 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
 434 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK    0x1
 435 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT   7
 436         u8 flags2;
 437 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
 438 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    0
 439 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
 440 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    2
 441 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
 442 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    4
 443 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK     0x3
 444 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT    6
 445         u8 flags3;
 446 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK     0x3
 447 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT    0
 448 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK     0x3
 449 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT    2
 450 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK     0x3
 451 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT    4
 452 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK     0x3
 453 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT    6
 454         u8 flags4;
 455 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK     0x3
 456 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT    0
 457 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK     0x3
 458 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT    2
 459 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK    0x3
 460 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT   4
 461 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK    0x3
 462 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT   6
 463         u8 flags5;
 464 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK    0x3
 465 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT   0
 466 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK    0x3
 467 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT   2
 468 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK    0x3
 469 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT   4
 470 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK    0x3
 471 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT   6
 472         u8 flags6;
 473 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK        0x3
 474 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT       0
 475 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK                    0x3
 476 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT                   2
 477 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK                   0x3
 478 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT                  4
 479 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK            0x3
 480 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
 481         u8 flags7;
 482 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK        0x3
 483 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT       0
 484 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK      0x3
 485 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT     2
 486 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK       0x3
 487 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT      4
 488 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
 489 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          6
 490 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
 491 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          7
 492         u8 flags8;
 493 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK   0x1
 494 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT  0
 495 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK   0x1
 496 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT  1
 497 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK   0x1
 498 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT  2
 499 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK   0x1
 500 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT  3
 501 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK   0x1
 502 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT  4
 503 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK   0x1
 504 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT  5
 505 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK   0x1
 506 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT  6
 507 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK   0x1
 508 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT  7
 509         u8 flags9;
 510 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK                  0x1
 511 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT                 0
 512 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK                  0x1
 513 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT                 1
 514 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK                  0x1
 515 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT                 2
 516 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK                  0x1
 517 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT                 3
 518 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK                  0x1
 519 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT                 4
 520 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK                  0x1
 521 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT                 5
 522 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK     0x1
 523 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT    6
 524 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK                  0x1
 525 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT                 7
 526         u8 flags10;
 527 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK                0x1
 528 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
 529 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1
 530 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
 531 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1
 532 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
 533 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK              0x1
 534 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT             3
 535 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1
 536 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
 537 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK                  0x1
 538 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT                 5
 539 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK              0x1
 540 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT             6
 541 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK              0x1
 542 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT             7
 543         u8 flags11;
 544 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK      0x1
 545 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT     0
 546 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK      0x1
 547 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT     1
 548 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK  0x1
 549 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
 550 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK         0x1
 551 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT        3
 552 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK         0x1
 553 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT        4
 554 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK         0x1
 555 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT        5
 556 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK    0x1
 557 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT   6
 558 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK         0x1
 559 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT        7
 560         u8 flags12;
 561 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK        0x1
 562 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT       0
 563 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK        0x1
 564 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT       1
 565 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK    0x1
 566 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT   2
 567 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK    0x1
 568 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT   3
 569 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK        0x1
 570 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT       4
 571 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK        0x1
 572 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT       5
 573 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK        0x1
 574 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT       6
 575 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK        0x1
 576 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT       7
 577         u8 flags13;
 578 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK        0x1
 579 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT       0
 580 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK        0x1
 581 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT       1
 582 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK    0x1
 583 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT   2
 584 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK    0x1
 585 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT   3
 586 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK    0x1
 587 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT   4
 588 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK    0x1
 589 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT   5
 590 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK    0x1
 591 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT   6
 592 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK    0x1
 593 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT   7
 594         u8 flags14;
 595 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK   0x1
 596 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT  0
 597 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK   0x1
 598 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT  1
 599 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK   0x1
 600 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT  2
 601 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK   0x1
 602 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT  3
 603 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK   0x1
 604 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT  4
 605 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK   0x1
 606 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT  5
 607 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK    0x3
 608 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT   6
 609         u8 byte2;
 610         __le16 physical_q0;
 611         __le16 consolid_prod;
 612         __le16 reserved16;
 613         __le16 tx_bd_cons;
 614         __le16 tx_bd_or_spq_prod;
 615         __le16 updated_qm_pq_id;
 616         __le16 conn_dpi;
 617         u8 byte3;
 618         u8 byte4;
 619         u8 byte5;
 620         u8 byte6;
 621         __le32 reg0;
 622         __le32 reg1;
 623         __le32 reg2;
 624         __le32 reg3;
 625         __le32 reg4;
 626         __le32 reg5;
 627         __le32 reg6;
 628         __le16 word7;
 629         __le16 word8;
 630         __le16 word9;
 631         __le16 word10;
 632         __le32 reg7;
 633         __le32 reg8;
 634         __le32 reg9;
 635         u8 byte7;
 636         u8 byte8;
 637         u8 byte9;
 638         u8 byte10;
 639         u8 byte11;
 640         u8 byte12;
 641         u8 byte13;
 642         u8 byte14;
 643         u8 byte15;
 644         u8 e5_reserved;
 645         __le16 word11;
 646         __le32 reg10;
 647         __le32 reg11;
 648         __le32 reg12;
 649         __le32 reg13;
 650         __le32 reg14;
 651         __le32 reg15;
 652         __le32 reg16;
 653         __le32 reg17;
 654         __le32 reg18;
 655         __le32 reg19;
 656         __le16 word12;
 657         __le16 word13;
 658         __le16 word14;
 659         __le16 word15;
 660 };
 661
 662 struct e4_tstorm_core_conn_ag_ctx {
 663         u8 byte0;
 664         u8 byte1;
 665         u8 flags0;
 666 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
 667 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
 668 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
 669 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
 670 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK    0x1
 671 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT   2
 672 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK    0x1
 673 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT   3
 674 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK    0x1
 675 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT   4
 676 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK    0x1
 677 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT   5
 678 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
 679 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    6
 680         u8 flags1;
 681 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
 682 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    0
 683 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
 684 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    2
 685 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK     0x3
 686 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT    4
 687 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK     0x3
 688 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT    6
 689         u8 flags2;
 690 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK     0x3
 691 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT    0
 692 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK     0x3
 693 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT    2
 694 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK     0x3
 695 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT    4
 696 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK     0x3
 697 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT    6
 698         u8 flags3;
 699 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK     0x3
 700 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT    0
 701 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK    0x3
 702 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT   2
 703 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK   0x1
 704 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT  4
 705 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK   0x1
 706 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT  5
 707 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK   0x1
 708 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT  6
 709 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK   0x1
 710 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT  7
 711         u8 flags4;
 712 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK           0x1
 713 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT          0
 714 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK           0x1
 715 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT          1
 716 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK           0x1
 717 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT          2
 718 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK           0x1
 719 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT          3
 720 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK           0x1
 721 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT          4
 722 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK           0x1
 723 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT          5
 724 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK          0x1
 725 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT         6
 726 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
 727 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        7
 728         u8 flags5;
 729 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
 730 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        0
 731 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
 732 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        1
 733 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
 734 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        2
 735 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
 736 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        3
 737 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK         0x1
 738 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT        4
 739 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK         0x1
 740 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT        5
 741 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK         0x1
 742 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT        6
 743 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK         0x1
 744 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT        7
 745         __le32 reg0;
 746         __le32 reg1;
 747         __le32 reg2;
 748         __le32 reg3;
 749         __le32 reg4;
 750         __le32 reg5;
 751         __le32 reg6;
 752         __le32 reg7;
 753         __le32 reg8;
 754         u8 byte2;
 755         u8 byte3;
 756         __le16 word0;
 757         u8 byte4;
 758         u8 byte5;
 759         __le16 word1;
 760         __le16 word2;
 761         __le16 word3;
 762         __le32 reg9;
 763         __le32 reg10;
 764 };
 765
 766 struct e4_ustorm_core_conn_ag_ctx {
 767         u8 reserved;
 768         u8 byte1;
 769         u8 flags0;
 770 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
 771 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
 772 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
 773 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
 774 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
 775 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT    2
 776 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
 777 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT    4
 778 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
 779 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT    6
 780         u8 flags1;
 781 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK     0x3
 782 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT    0
 783 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK     0x3
 784 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT    2
 785 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK     0x3
 786 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT    4
 787 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK     0x3
 788 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT    6
 789         u8 flags2;
 790 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
 791 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          0
 792 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
 793 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          1
 794 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK           0x1
 795 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT          2
 796 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK           0x1
 797 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT          3
 798 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK           0x1
 799 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT          4
 800 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK           0x1
 801 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT          5
 802 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK           0x1
 803 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT          6
 804 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
 805 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        7
 806         u8 flags3;
 807 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
 808 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        0
 809 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
 810 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        1
 811 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
 812 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        2
 813 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
 814 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        3
 815 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK         0x1
 816 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT        4
 817 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK         0x1
 818 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT        5
 819 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK         0x1
 820 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT        6
 821 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK         0x1
 822 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT        7
 823         u8 byte2;
 824         u8 byte3;
 825         __le16 word0;
 826         __le16 word1;
 827         __le32 rx_producers;
 828         __le32 reg1;
 829         __le32 reg2;
 830         __le32 reg3;
 831         __le16 word2;
 832         __le16 word3;
 833 };
 834
 835 /* The core storm context for the Mstorm */
 836 struct mstorm_core_conn_st_ctx {
 837         __le32 reserved[24];
 838 };
 839
 840 /* The core storm context for the Ustorm */
 841 struct ustorm_core_conn_st_ctx {
 842         __le32 reserved[4];
 843 };
 844
 845 /* core connection context */
 846 struct e4_core_conn_context {
 847         struct ystorm_core_conn_st_ctx ystorm_st_context;
 848         struct regpair ystorm_st_padding[2];
 849         struct pstorm_core_conn_st_ctx pstorm_st_context;
 850         struct regpair pstorm_st_padding[2];
 851         struct xstorm_core_conn_st_ctx xstorm_st_context;
 852         struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
 853         struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
 854         struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
 855         struct mstorm_core_conn_st_ctx mstorm_st_context;
 856         struct ustorm_core_conn_st_ctx ustorm_st_context;
 857         struct regpair ustorm_st_padding[2];
 858 };
 859
 860 struct eth_mstorm_per_pf_stat {
 861         struct regpair gre_discard_pkts;
 862         struct regpair vxlan_discard_pkts;
 863         struct regpair geneve_discard_pkts;
 864         struct regpair lb_discard_pkts;
 865 };
 866
 867 struct eth_mstorm_per_queue_stat {
 868         struct regpair ttl0_discard;
 869         struct regpair packet_too_big_discard;
 870         struct regpair no_buff_discard;
 871         struct regpair not_active_discard;
 872         struct regpair tpa_coalesced_pkts;
 873         struct regpair tpa_coalesced_events;
 874         struct regpair tpa_aborts_num;
 875         struct regpair tpa_coalesced_bytes;
 876 };
 877
 878 /* Ethernet TX Per PF */
 879 struct eth_pstorm_per_pf_stat {
 880         struct regpair sent_lb_ucast_bytes;
 881         struct regpair sent_lb_mcast_bytes;
 882         struct regpair sent_lb_bcast_bytes;
 883         struct regpair sent_lb_ucast_pkts;
 884         struct regpair sent_lb_mcast_pkts;
 885         struct regpair sent_lb_bcast_pkts;
 886         struct regpair sent_gre_bytes;
 887         struct regpair sent_vxlan_bytes;
 888         struct regpair sent_geneve_bytes;
 889         struct regpair sent_gre_pkts;
 890         struct regpair sent_vxlan_pkts;
 891         struct regpair sent_geneve_pkts;
 892         struct regpair gre_drop_pkts;
 893         struct regpair vxlan_drop_pkts;
 894         struct regpair geneve_drop_pkts;
 895 };
 896
 897 /* Ethernet TX Per Queue Stats */
 898 struct eth_pstorm_per_queue_stat {
 899         struct regpair sent_ucast_bytes;
 900         struct regpair sent_mcast_bytes;
 901         struct regpair sent_bcast_bytes;
 902         struct regpair sent_ucast_pkts;
 903         struct regpair sent_mcast_pkts;
 904         struct regpair sent_bcast_pkts;
 905         struct regpair error_drop_pkts;
 906 };
 907
 908 /* ETH Rx producers data */
 909 struct eth_rx_rate_limit {
 910         __le16 mult;
 911         __le16 cnst;
 912         u8 add_sub_cnst;
 913         u8 reserved0;
 914         __le16 reserved1;
 915 };
 916
 917 struct eth_ustorm_per_pf_stat {
 918         struct regpair rcv_lb_ucast_bytes;
 919         struct regpair rcv_lb_mcast_bytes;
 920         struct regpair rcv_lb_bcast_bytes;
 921         struct regpair rcv_lb_ucast_pkts;
 922         struct regpair rcv_lb_mcast_pkts;
 923         struct regpair rcv_lb_bcast_pkts;
 924         struct regpair rcv_gre_bytes;
 925         struct regpair rcv_vxlan_bytes;
 926         struct regpair rcv_geneve_bytes;
 927         struct regpair rcv_gre_pkts;
 928         struct regpair rcv_vxlan_pkts;
 929         struct regpair rcv_geneve_pkts;
 930 };
 931
 932 struct eth_ustorm_per_queue_stat {
 933         struct regpair rcv_ucast_bytes;
 934         struct regpair rcv_mcast_bytes;
 935         struct regpair rcv_bcast_bytes;
 936         struct regpair rcv_ucast_pkts;
 937         struct regpair rcv_mcast_pkts;
 938         struct regpair rcv_bcast_pkts;
 939 };
 940
 941 /* Event Ring VF-PF Channel data */
 942 struct vf_pf_channel_eqe_data {
 943         struct regpair msg_addr;
 944 };
 945
 946 /* Event Ring malicious VF data */
 947 struct malicious_vf_eqe_data {
 948         u8 vf_id;
 949         u8 err_id;
 950         __le16 reserved[3];
 951 };
 952
 953 /* Event Ring initial cleanup data */
 954 struct initial_cleanup_eqe_data {
 955         u8 vf_id;
 956         u8 reserved[7];
 957 };
 958
 959 /* Event Data Union */
 960 union event_ring_data {
 961         u8 bytes[8];
 962         struct vf_pf_channel_eqe_data vf_pf_channel;
 963         struct iscsi_eqe_data iscsi_info;
 964         struct iscsi_connect_done_results iscsi_conn_done_info;
 965         union rdma_eqe_data rdma_data;
 966         struct malicious_vf_eqe_data malicious_vf;
 967         struct initial_cleanup_eqe_data vf_init_cleanup;
 968 };
 969
 970 /* Event Ring Entry */
 971 struct event_ring_entry {
 972         u8 protocol_id;
 973         u8 opcode;
 974         __le16 reserved0;
 975         __le16 echo;
 976         u8 fw_return_code;
 977         u8 flags;
 978 #define EVENT_RING_ENTRY_ASYNC_MASK             0x1
 979 #define EVENT_RING_ENTRY_ASYNC_SHIFT            0
 980 #define EVENT_RING_ENTRY_RESERVED1_MASK         0x7F
 981 #define EVENT_RING_ENTRY_RESERVED1_SHIFT        1
 982         union event_ring_data data;
 983 };
 984
 985 /* Event Ring Next Page Address */
 986 struct event_ring_next_addr {
 987         struct regpair addr;
 988         __le32 reserved[2];
 989 };
 990
 991 /* Event Ring Element */
 992 union event_ring_element {
 993         struct event_ring_entry entry;
 994         struct event_ring_next_addr next_addr;
 995 };
 996
 997 /* Ports mode */
 998 enum fw_flow_ctrl_mode {
 999         flow_ctrl_pause,
1000         flow_ctrl_pfc,
1001         MAX_FW_FLOW_CTRL_MODE
1002 };
1003
1004 /* GFT profile type */
1005 enum gft_profile_type {
1006         GFT_PROFILE_TYPE_4_TUPLE,
1007         GFT_PROFILE_TYPE_L4_DST_PORT,
1008         GFT_PROFILE_TYPE_IP_DST_ADDR,
1009         GFT_PROFILE_TYPE_IP_SRC_ADDR,
1010         GFT_PROFILE_TYPE_TUNNEL_TYPE,
1011         MAX_GFT_PROFILE_TYPE
1012 };
1013
1014 /* Major and Minor hsi Versions */
1015 struct hsi_fp_ver_struct {
1016         u8 minor_ver_arr[2];
1017         u8 major_ver_arr[2];
1018 };
1019
1020 enum iwarp_ll2_tx_queues {
1021         IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1022         IWARP_LL2_ALIGNED_TX_QUEUE,
1023         IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1024         IWARP_LL2_ERROR,
1025         MAX_IWARP_LL2_TX_QUEUES
1026 };
1027
1028 /* Malicious VF error ID */
1029 enum malicious_vf_error_id {
1030         MALICIOUS_VF_NO_ERROR,
1031         VF_PF_CHANNEL_NOT_READY,
1032         VF_ZONE_MSG_NOT_VALID,
1033         VF_ZONE_FUNC_NOT_ENABLED,
1034         ETH_PACKET_TOO_SMALL,
1035         ETH_ILLEGAL_VLAN_MODE,
1036         ETH_MTU_VIOLATION,
1037         ETH_ILLEGAL_INBAND_TAGS,
1038         ETH_VLAN_INSERT_AND_INBAND_VLAN,
1039         ETH_ILLEGAL_NBDS,
1040         ETH_FIRST_BD_WO_SOP,
1041         ETH_INSUFFICIENT_BDS,
1042         ETH_ILLEGAL_LSO_HDR_NBDS,
1043         ETH_ILLEGAL_LSO_MSS,
1044         ETH_ZERO_SIZE_BD,
1045         ETH_ILLEGAL_LSO_HDR_LEN,
1046         ETH_INSUFFICIENT_PAYLOAD,
1047         ETH_EDPM_OUT_OF_SYNC,
1048         ETH_TUNN_IPV6_EXT_NBD_ERR,
1049         ETH_CONTROL_PACKET_VIOLATION,
1050         ETH_ANTI_SPOOFING_ERR,
1051         ETH_PACKET_SIZE_TOO_LARGE,
1052         MAX_MALICIOUS_VF_ERROR_ID
1053 };
1054
1055 /* Mstorm non-triggering VF zone */
1056 struct mstorm_non_trigger_vf_zone {
1057         struct eth_mstorm_per_queue_stat eth_queue_stat;
1058         struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
1059 };
1060
1061 /* Mstorm VF zone */
1062 struct mstorm_vf_zone {
1063         struct mstorm_non_trigger_vf_zone non_trigger;
1064 };
1065
1066 /* vlan header including TPID and TCI fields */
1067 struct vlan_header {
1068         __le16 tpid;
1069         __le16 tci;
1070 };
1071
1072 /* outer tag configurations */
1073 struct outer_tag_config_struct {
1074         u8 enable_stag_pri_change;
1075         u8 pri_map_valid;
1076         u8 reserved[2];
1077         struct vlan_header outer_tag;
1078         u8 inner_to_outer_pri_map[8];
1079 };
1080
1081 /* personality per PF */
1082 enum personality_type {
1083         BAD_PERSONALITY_TYP,
1084         PERSONALITY_ISCSI,
1085         PERSONALITY_FCOE,
1086         PERSONALITY_RDMA_AND_ETH,
1087         PERSONALITY_RDMA,
1088         PERSONALITY_CORE,
1089         PERSONALITY_ETH,
1090         PERSONALITY_RESERVED,
1091         MAX_PERSONALITY_TYPE
1092 };
1093
1094 /* tunnel configuration */
1095 struct pf_start_tunnel_config {
1096         u8 set_vxlan_udp_port_flg;
1097         u8 set_geneve_udp_port_flg;
1098         u8 set_no_inner_l2_vxlan_udp_port_flg;
1099         u8 tunnel_clss_vxlan;
1100         u8 tunnel_clss_l2geneve;
1101         u8 tunnel_clss_ipgeneve;
1102         u8 tunnel_clss_l2gre;
1103         u8 tunnel_clss_ipgre;
1104         __le16 vxlan_udp_port;
1105         __le16 geneve_udp_port;
1106         __le16 no_inner_l2_vxlan_udp_port;
1107         __le16 reserved[3];
1108 };
1109
1110 /* Ramrod data for PF start ramrod */
1111 struct pf_start_ramrod_data {
1112         struct regpair event_ring_pbl_addr;
1113         struct regpair consolid_q_pbl_addr;
1114         struct pf_start_tunnel_config tunnel_config;
1115         __le16 event_ring_sb_id;
1116         u8 base_vf_id;
1117         u8 num_vfs;
1118         u8 event_ring_num_pages;
1119         u8 event_ring_sb_index;
1120         u8 path_id;
1121         u8 warning_as_error;
1122         u8 dont_log_ramrods;
1123         u8 personality;
1124         __le16 log_type_mask;
1125         u8 mf_mode;
1126         u8 integ_phase;
1127         u8 allow_npar_tx_switching;
1128         u8 reserved0;
1129         struct hsi_fp_ver_struct hsi_fp_ver;
1130         struct outer_tag_config_struct outer_tag_config;
1131 };
1132
1133 /* Data for port update ramrod */
1134 struct protocol_dcb_data {
1135         u8 dcb_enable_flag;
1136         u8 dscp_enable_flag;
1137         u8 dcb_priority;
1138         u8 dcb_tc;
1139         u8 dscp_val;
1140         u8 dcb_dont_add_vlan0;
1141 };
1142
1143 /* Update tunnel configuration */
1144 struct pf_update_tunnel_config {
1145         u8 update_rx_pf_clss;
1146         u8 update_rx_def_ucast_clss;
1147         u8 update_rx_def_non_ucast_clss;
1148         u8 set_vxlan_udp_port_flg;
1149         u8 set_geneve_udp_port_flg;
1150         u8 set_no_inner_l2_vxlan_udp_port_flg;
1151         u8 tunnel_clss_vxlan;
1152         u8 tunnel_clss_l2geneve;
1153         u8 tunnel_clss_ipgeneve;
1154         u8 tunnel_clss_l2gre;
1155         u8 tunnel_clss_ipgre;
1156         u8 reserved;
1157         __le16 vxlan_udp_port;
1158         __le16 geneve_udp_port;
1159         __le16 no_inner_l2_vxlan_udp_port;
1160         __le16 reserved1[3];
1161 };
1162
1163 /* Data for port update ramrod */
1164 struct pf_update_ramrod_data {
1165         u8 update_eth_dcb_data_mode;
1166         u8 update_fcoe_dcb_data_mode;
1167         u8 update_iscsi_dcb_data_mode;
1168         u8 update_roce_dcb_data_mode;
1169         u8 update_rroce_dcb_data_mode;
1170         u8 update_iwarp_dcb_data_mode;
1171         u8 update_mf_vlan_flag;
1172         u8 update_enable_stag_pri_change;
1173         struct protocol_dcb_data eth_dcb_data;
1174         struct protocol_dcb_data fcoe_dcb_data;
1175         struct protocol_dcb_data iscsi_dcb_data;
1176         struct protocol_dcb_data roce_dcb_data;
1177         struct protocol_dcb_data rroce_dcb_data;
1178         struct protocol_dcb_data iwarp_dcb_data;
1179         __le16 mf_vlan;
1180         u8 enable_stag_pri_change;
1181         u8 reserved;
1182         struct pf_update_tunnel_config tunnel_config;
1183 };
1184
1185 /* Ports mode */
1186 enum ports_mode {
1187         ENGX2_PORTX1,
1188         ENGX2_PORTX2,
1189         ENGX1_PORTX1,
1190         ENGX1_PORTX2,
1191         ENGX1_PORTX4,
1192         MAX_PORTS_MODE
1193 };
1194
1195 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1196 enum protocol_version_array_key {
1197         ETH_VER_KEY = 0,
1198         ROCE_VER_KEY,
1199         MAX_PROTOCOL_VERSION_ARRAY_KEY
1200 };
1201
1202 /* RDMA TX Stats */
1203 struct rdma_sent_stats {
1204         struct regpair sent_bytes;
1205         struct regpair sent_pkts;
1206 };
1207
1208 /* Pstorm non-triggering VF zone */
1209 struct pstorm_non_trigger_vf_zone {
1210         struct eth_pstorm_per_queue_stat eth_queue_stat;
1211         struct rdma_sent_stats rdma_stats;
1212 };
1213
1214 /* Pstorm VF zone */
1215 struct pstorm_vf_zone {
1216         struct pstorm_non_trigger_vf_zone non_trigger;
1217         struct regpair reserved[7];
1218 };
1219
1220 /* Ramrod Header of SPQE */
1221 struct ramrod_header {
1222         __le32 cid;
1223         u8 cmd_id;
1224         u8 protocol_id;
1225         __le16 echo;
1226 };
1227
1228 /* RDMA RX Stats */
1229 struct rdma_rcv_stats {
1230         struct regpair rcv_bytes;
1231         struct regpair rcv_pkts;
1232 };
1233
1234 /* Data for update QCN/DCQCN RL ramrod */
1235 struct rl_update_ramrod_data {
1236         u8 qcn_update_param_flg;
1237         u8 dcqcn_update_param_flg;
1238         u8 rl_init_flg;
1239         u8 rl_start_flg;
1240         u8 rl_stop_flg;
1241         u8 rl_id_first;
1242         u8 rl_id_last;
1243         u8 rl_dc_qcn_flg;
1244         __le32 rl_bc_rate;
1245         __le16 rl_max_rate;
1246         __le16 rl_r_ai;
1247         __le16 rl_r_hai;
1248         __le16 dcqcn_g;
1249         __le32 dcqcn_k_us;
1250         __le32 dcqcn_timeuot_us;
1251         __le32 qcn_timeuot_us;
1252         __le32 reserved[2];
1253 };
1254
1255 /* Slowpath Element (SPQE) */
1256 struct slow_path_element {
1257         struct ramrod_header hdr;
1258         struct regpair data_ptr;
1259 };
1260
1261 /* Tstorm non-triggering VF zone */
1262 struct tstorm_non_trigger_vf_zone {
1263         struct rdma_rcv_stats rdma_stats;
1264 };
1265
1266 struct tstorm_per_port_stat {
1267         struct regpair trunc_error_discard;
1268         struct regpair mac_error_discard;
1269         struct regpair mftag_filter_discard;
1270         struct regpair eth_mac_filter_discard;
1271         struct regpair ll2_mac_filter_discard;
1272         struct regpair ll2_conn_disabled_discard;
1273         struct regpair iscsi_irregular_pkt;
1274         struct regpair fcoe_irregular_pkt;
1275         struct regpair roce_irregular_pkt;
1276         struct regpair iwarp_irregular_pkt;
1277         struct regpair eth_irregular_pkt;
1278         struct regpair toe_irregular_pkt;
1279         struct regpair preroce_irregular_pkt;
1280         struct regpair eth_gre_tunn_filter_discard;
1281         struct regpair eth_vxlan_tunn_filter_discard;
1282         struct regpair eth_geneve_tunn_filter_discard;
1283         struct regpair eth_gft_drop_pkt;
1284 };
1285
1286 /* Tstorm VF zone */
1287 struct tstorm_vf_zone {
1288         struct tstorm_non_trigger_vf_zone non_trigger;
1289 };
1290
1291 /* Tunnel classification scheme */
1292 enum tunnel_clss {
1293         TUNNEL_CLSS_MAC_VLAN = 0,
1294         TUNNEL_CLSS_MAC_VNI,
1295         TUNNEL_CLSS_INNER_MAC_VLAN,
1296         TUNNEL_CLSS_INNER_MAC_VNI,
1297         TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1298         MAX_TUNNEL_CLSS
1299 };
1300
1301 /* Ustorm non-triggering VF zone */
1302 struct ustorm_non_trigger_vf_zone {
1303         struct eth_ustorm_per_queue_stat eth_queue_stat;
1304         struct regpair vf_pf_msg_addr;
1305 };
1306
1307 /* Ustorm triggering VF zone */
1308 struct ustorm_trigger_vf_zone {
1309         u8 vf_pf_msg_valid;
1310         u8 reserved[7];
1311 };
1312
1313 /* Ustorm VF zone */
1314 struct ustorm_vf_zone {
1315         struct ustorm_non_trigger_vf_zone non_trigger;
1316         struct ustorm_trigger_vf_zone trigger;
1317 };
1318
1319 /* VF-PF channel data */
1320 struct vf_pf_channel_data {
1321         __le32 ready;
1322         u8 valid;
1323         u8 reserved0;
1324         __le16 reserved1;
1325 };
1326
1327 /* Ramrod data for VF start ramrod */
1328 struct vf_start_ramrod_data {
1329         u8 vf_id;
1330         u8 enable_flr_ack;
1331         __le16 opaque_fid;
1332         u8 personality;
1333         u8 reserved[7];
1334         struct hsi_fp_ver_struct hsi_fp_ver;
1335
1336 };
1337
1338 /* Ramrod data for VF start ramrod */
1339 struct vf_stop_ramrod_data {
1340         u8 vf_id;
1341         u8 reserved0;
1342         __le16 reserved1;
1343         __le32 reserved2;
1344 };
1345
1346 /* VF zone size mode */
1347 enum vf_zone_size_mode {
1348         VF_ZONE_SIZE_MODE_DEFAULT,
1349         VF_ZONE_SIZE_MODE_DOUBLE,
1350         VF_ZONE_SIZE_MODE_QUAD,
1351         MAX_VF_ZONE_SIZE_MODE
1352 };
1353
1354 /* Attentions status block */
1355 struct atten_status_block {
1356         __le32 atten_bits;
1357         __le32 atten_ack;
1358         __le16 reserved0;
1359         __le16 sb_index;
1360         __le32 reserved1;
1361 };
1362
1363 /* DMAE command */
1364 struct dmae_cmd {
1365         __le32 opcode;
1366 #define DMAE_CMD_SRC_MASK               0x1
1367 #define DMAE_CMD_SRC_SHIFT              0
1368 #define DMAE_CMD_DST_MASK               0x3
1369 #define DMAE_CMD_DST_SHIFT              1
1370 #define DMAE_CMD_C_DST_MASK             0x1
1371 #define DMAE_CMD_C_DST_SHIFT            3
1372 #define DMAE_CMD_CRC_RESET_MASK         0x1
1373 #define DMAE_CMD_CRC_RESET_SHIFT        4
1374 #define DMAE_CMD_SRC_ADDR_RESET_MASK    0x1
1375 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT   5
1376 #define DMAE_CMD_DST_ADDR_RESET_MASK    0x1
1377 #define DMAE_CMD_DST_ADDR_RESET_SHIFT   6
1378 #define DMAE_CMD_COMP_FUNC_MASK         0x1
1379 #define DMAE_CMD_COMP_FUNC_SHIFT        7
1380 #define DMAE_CMD_COMP_WORD_EN_MASK      0x1
1381 #define DMAE_CMD_COMP_WORD_EN_SHIFT     8
1382 #define DMAE_CMD_COMP_CRC_EN_MASK       0x1
1383 #define DMAE_CMD_COMP_CRC_EN_SHIFT      9
1384 #define DMAE_CMD_COMP_CRC_OFFSET_MASK   0x7
1385 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1386 #define DMAE_CMD_RESERVED1_MASK         0x1
1387 #define DMAE_CMD_RESERVED1_SHIFT        13
1388 #define DMAE_CMD_ENDIANITY_MODE_MASK    0x3
1389 #define DMAE_CMD_ENDIANITY_MODE_SHIFT   14
1390 #define DMAE_CMD_ERR_HANDLING_MASK      0x3
1391 #define DMAE_CMD_ERR_HANDLING_SHIFT     16
1392 #define DMAE_CMD_PORT_ID_MASK           0x3
1393 #define DMAE_CMD_PORT_ID_SHIFT          18
1394 #define DMAE_CMD_SRC_PF_ID_MASK         0xF
1395 #define DMAE_CMD_SRC_PF_ID_SHIFT        20
1396 #define DMAE_CMD_DST_PF_ID_MASK         0xF
1397 #define DMAE_CMD_DST_PF_ID_SHIFT        24
1398 #define DMAE_CMD_SRC_VF_ID_VALID_MASK   0x1
1399 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1400 #define DMAE_CMD_DST_VF_ID_VALID_MASK   0x1
1401 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1402 #define DMAE_CMD_RESERVED2_MASK         0x3
1403 #define DMAE_CMD_RESERVED2_SHIFT        30
1404         __le32 src_addr_lo;
1405         __le32 src_addr_hi;
1406         __le32 dst_addr_lo;
1407         __le32 dst_addr_hi;
1408         __le16 length_dw;
1409         __le16 opcode_b;
1410 #define DMAE_CMD_SRC_VF_ID_MASK         0xFF
1411 #define DMAE_CMD_SRC_VF_ID_SHIFT        0
1412 #define DMAE_CMD_DST_VF_ID_MASK         0xFF
1413 #define DMAE_CMD_DST_VF_ID_SHIFT        8
1414         __le32 comp_addr_lo;
1415         __le32 comp_addr_hi;
1416         __le32 comp_val;
1417         __le32 crc32;
1418         __le32 crc_32_c;
1419         __le16 crc16;
1420         __le16 crc16_c;
1421         __le16 crc10;
1422         __le16 reserved;
1423         __le16 xsum16;
1424         __le16 xsum8;
1425 };
1426
1427 enum dmae_cmd_comp_crc_en_enum {
1428         dmae_cmd_comp_crc_disabled,
1429         dmae_cmd_comp_crc_enabled,
1430         MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1431 };
1432
1433 enum dmae_cmd_comp_func_enum {
1434         dmae_cmd_comp_func_to_src,
1435         dmae_cmd_comp_func_to_dst,
1436         MAX_DMAE_CMD_COMP_FUNC_ENUM
1437 };
1438
1439 enum dmae_cmd_comp_word_en_enum {
1440         dmae_cmd_comp_word_disabled,
1441         dmae_cmd_comp_word_enabled,
1442         MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1443 };
1444
1445 enum dmae_cmd_c_dst_enum {
1446         dmae_cmd_c_dst_pcie,
1447         dmae_cmd_c_dst_grc,
1448         MAX_DMAE_CMD_C_DST_ENUM
1449 };
1450
1451 enum dmae_cmd_dst_enum {
1452         dmae_cmd_dst_none_0,
1453         dmae_cmd_dst_pcie,
1454         dmae_cmd_dst_grc,
1455         dmae_cmd_dst_none_3,
1456         MAX_DMAE_CMD_DST_ENUM
1457 };
1458
1459 enum dmae_cmd_error_handling_enum {
1460         dmae_cmd_error_handling_send_regular_comp,
1461         dmae_cmd_error_handling_send_comp_with_err,
1462         dmae_cmd_error_handling_dont_send_comp,
1463         MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1464 };
1465
1466 enum dmae_cmd_src_enum {
1467         dmae_cmd_src_pcie,
1468         dmae_cmd_src_grc,
1469         MAX_DMAE_CMD_SRC_ENUM
1470 };
1471
1472 struct e4_mstorm_core_conn_ag_ctx {
1473         u8 byte0;
1474         u8 byte1;
1475         u8 flags0;
1476 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
1477 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
1478 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
1479 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
1480 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
1481 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    2
1482 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
1483 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    4
1484 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
1485 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    6
1486         u8 flags1;
1487 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
1488 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          0
1489 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
1490 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          1
1491 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK           0x1
1492 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT          2
1493 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
1494 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        3
1495 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
1496 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        4
1497 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
1498 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        5
1499 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
1500 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        6
1501 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
1502 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        7
1503         __le16 word0;
1504         __le16 word1;
1505         __le32 reg0;
1506         __le32 reg1;
1507 };
1508
1509 struct e4_ystorm_core_conn_ag_ctx {
1510         u8 byte0;
1511         u8 byte1;
1512         u8 flags0;
1513 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
1514 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
1515 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
1516 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
1517 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
1518 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    2
1519 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
1520 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    4
1521 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
1522 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    6
1523         u8 flags1;
1524 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
1525 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          0
1526 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
1527 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          1
1528 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK           0x1
1529 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT          2
1530 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
1531 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        3
1532 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
1533 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        4
1534 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
1535 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        5
1536 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
1537 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        6
1538 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
1539 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        7
1540         u8 byte2;
1541         u8 byte3;
1542         __le16 word0;
1543         __le32 reg0;
1544         __le32 reg1;
1545         __le16 word1;
1546         __le16 word2;
1547         __le16 word3;
1548         __le16 word4;
1549         __le32 reg2;
1550         __le32 reg3;
1551 };
1552
1553 /* IGU cleanup command */
1554 struct igu_cleanup {
1555         __le32 sb_id_and_flags;
1556 #define IGU_CLEANUP_RESERVED0_MASK      0x7FFFFFF
1557 #define IGU_CLEANUP_RESERVED0_SHIFT     0
1558 #define IGU_CLEANUP_CLEANUP_SET_MASK    0x1
1559 #define IGU_CLEANUP_CLEANUP_SET_SHIFT   27
1560 #define IGU_CLEANUP_CLEANUP_TYPE_MASK   0x7
1561 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT  28
1562 #define IGU_CLEANUP_COMMAND_TYPE_MASK   0x1
1563 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT  31
1564         __le32 reserved1;
1565 };
1566
1567 /* IGU firmware driver command */
1568 union igu_command {
1569         struct igu_prod_cons_update prod_cons_update;
1570         struct igu_cleanup cleanup;
1571 };
1572
1573 /* IGU firmware driver command */
1574 struct igu_command_reg_ctrl {
1575         __le16 opaque_fid;
1576         __le16 igu_command_reg_ctrl_fields;
1577 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK  0xFFF
1578 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1579 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK      0x7
1580 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT     12
1581 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK  0x1
1582 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1583 };
1584
1585 /* IGU mapping line structure */
1586 struct igu_mapping_line {
1587         __le32 igu_mapping_line_fields;
1588 #define IGU_MAPPING_LINE_VALID_MASK             0x1
1589 #define IGU_MAPPING_LINE_VALID_SHIFT            0
1590 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK     0xFF
1591 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT    1
1592 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK   0xFF
1593 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT  9
1594 #define IGU_MAPPING_LINE_PF_VALID_MASK          0x1
1595 #define IGU_MAPPING_LINE_PF_VALID_SHIFT         17
1596 #define IGU_MAPPING_LINE_IPS_GROUP_MASK         0x3F
1597 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT        18
1598 #define IGU_MAPPING_LINE_RESERVED_MASK          0xFF
1599 #define IGU_MAPPING_LINE_RESERVED_SHIFT         24
1600 };
1601
1602 /* IGU MSIX line structure */
1603 struct igu_msix_vector {
1604         struct regpair address;
1605         __le32 data;
1606         __le32 msix_vector_fields;
1607 #define IGU_MSIX_VECTOR_MASK_BIT_MASK           0x1
1608 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT          0
1609 #define IGU_MSIX_VECTOR_RESERVED0_MASK          0x7FFF
1610 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT         1
1611 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK       0xFF
1612 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT      16
1613 #define IGU_MSIX_VECTOR_RESERVED1_MASK          0xFF
1614 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT         24
1615 };
1616 /* per encapsulation type enabling flags */
1617 struct prs_reg_encapsulation_type_en {
1618         u8 flags;
1619 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK          0x1
1620 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT         0
1621 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK           0x1
1622 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT          1
1623 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK                 0x1
1624 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT                2
1625 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK                 0x1
1626 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT                3
1627 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK       0x1
1628 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT      4
1629 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK        0x1
1630 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT       5
1631 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK                     0x3
1632 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT                    6
1633 };
1634
1635 enum pxp_tph_st_hint {
1636         TPH_ST_HINT_BIDIR,
1637         TPH_ST_HINT_REQUESTER,
1638         TPH_ST_HINT_TARGET,
1639         TPH_ST_HINT_TARGET_PRIO,
1640         MAX_PXP_TPH_ST_HINT
1641 };
1642
1643 /* QM hardware structure of enable bypass credit mask */
1644 struct qm_rf_bypass_mask {
1645         u8 flags;
1646 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK          0x1
1647 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT         0
1648 #define QM_RF_BYPASS_MASK_RESERVED0_MASK        0x1
1649 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT       1
1650 #define QM_RF_BYPASS_MASK_PFWFQ_MASK            0x1
1651 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT           2
1652 #define QM_RF_BYPASS_MASK_VPWFQ_MASK            0x1
1653 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT           3
1654 #define QM_RF_BYPASS_MASK_PFRL_MASK             0x1
1655 #define QM_RF_BYPASS_MASK_PFRL_SHIFT            4
1656 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK          0x1
1657 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT         5
1658 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK          0x1
1659 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT         6
1660 #define QM_RF_BYPASS_MASK_RESERVED1_MASK        0x1
1661 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT       7
1662 };
1663
1664 /* QM hardware structure of opportunistic credit mask */
1665 struct qm_rf_opportunistic_mask {
1666         __le16 flags;
1667 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK           0x1
1668 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT          0
1669 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK           0x1
1670 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT          1
1671 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK             0x1
1672 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT            2
1673 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK             0x1
1674 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT            3
1675 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK              0x1
1676 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT             4
1677 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK           0x1
1678 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT          5
1679 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK           0x1
1680 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT          6
1681 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK         0x1
1682 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT        7
1683 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK        0x1
1684 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT       8
1685 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK         0x7F
1686 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT        9
1687 };
1688
1689 /* QM hardware structure of QM map memory */
1690 struct qm_rf_pq_map_e4 {
1691         __le32 reg;
1692 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK           0x1
1693 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT          0
1694 #define QM_RF_PQ_MAP_E4_RL_ID_MASK              0xFF
1695 #define QM_RF_PQ_MAP_E4_RL_ID_SHIFT             1
1696 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK           0x1FF
1697 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT          9
1698 #define QM_RF_PQ_MAP_E4_VOQ_MASK                0x1F
1699 #define QM_RF_PQ_MAP_E4_VOQ_SHIFT               18
1700 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK   0x3
1701 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT  23
1702 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK           0x1
1703 #define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT          25
1704 #define QM_RF_PQ_MAP_E4_RESERVED_MASK           0x3F
1705 #define QM_RF_PQ_MAP_E4_RESERVED_SHIFT          26
1706 };
1707
1708 /* Completion params for aggregated interrupt completion */
1709 struct sdm_agg_int_comp_params {
1710         __le16 params;
1711 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK      0x3F
1712 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT     0
1713 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK  0x1
1714 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1715 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK     0x1FF
1716 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT    7
1717 };
1718
1719 /* SDM operation gen command (generate aggregative interrupt) */
1720 struct sdm_op_gen {
1721         __le32 command;
1722 #define SDM_OP_GEN_COMP_PARAM_MASK      0xFFFF
1723 #define SDM_OP_GEN_COMP_PARAM_SHIFT     0
1724 #define SDM_OP_GEN_COMP_TYPE_MASK       0xF
1725 #define SDM_OP_GEN_COMP_TYPE_SHIFT      16
1726 #define SDM_OP_GEN_RESERVED_MASK        0xFFF
1727 #define SDM_OP_GEN_RESERVED_SHIFT       20
1728 };
1729
1730 /****************************************/
1731 /* Debug Tools HSI constants and macros */
1732 /****************************************/
1733
1734 enum block_addr {
1735         GRCBASE_GRC = 0x50000,
1736         GRCBASE_MISCS = 0x9000,
1737         GRCBASE_MISC = 0x8000,
1738         GRCBASE_DBU = 0xa000,
1739         GRCBASE_PGLUE_B = 0x2a8000,
1740         GRCBASE_CNIG = 0x218000,
1741         GRCBASE_CPMU = 0x30000,
1742         GRCBASE_NCSI = 0x40000,
1743         GRCBASE_OPTE = 0x53000,
1744         GRCBASE_BMB = 0x540000,
1745         GRCBASE_PCIE = 0x54000,
1746         GRCBASE_MCP = 0xe00000,
1747         GRCBASE_MCP2 = 0x52000,
1748         GRCBASE_PSWHST = 0x2a0000,
1749         GRCBASE_PSWHST2 = 0x29e000,
1750         GRCBASE_PSWRD = 0x29c000,
1751         GRCBASE_PSWRD2 = 0x29d000,
1752         GRCBASE_PSWWR = 0x29a000,
1753         GRCBASE_PSWWR2 = 0x29b000,
1754         GRCBASE_PSWRQ = 0x280000,
1755         GRCBASE_PSWRQ2 = 0x240000,
1756         GRCBASE_PGLCS = 0x0,
1757         GRCBASE_DMAE = 0xc000,
1758         GRCBASE_PTU = 0x560000,
1759         GRCBASE_TCM = 0x1180000,
1760         GRCBASE_MCM = 0x1200000,
1761         GRCBASE_UCM = 0x1280000,
1762         GRCBASE_XCM = 0x1000000,
1763         GRCBASE_YCM = 0x1080000,
1764         GRCBASE_PCM = 0x1100000,
1765         GRCBASE_QM = 0x2f0000,
1766         GRCBASE_TM = 0x2c0000,
1767         GRCBASE_DORQ = 0x100000,
1768         GRCBASE_BRB = 0x340000,
1769         GRCBASE_SRC = 0x238000,
1770         GRCBASE_PRS = 0x1f0000,
1771         GRCBASE_TSDM = 0xfb0000,
1772         GRCBASE_MSDM = 0xfc0000,
1773         GRCBASE_USDM = 0xfd0000,
1774         GRCBASE_XSDM = 0xf80000,
1775         GRCBASE_YSDM = 0xf90000,
1776         GRCBASE_PSDM = 0xfa0000,
1777         GRCBASE_TSEM = 0x1700000,
1778         GRCBASE_MSEM = 0x1800000,
1779         GRCBASE_USEM = 0x1900000,
1780         GRCBASE_XSEM = 0x1400000,
1781         GRCBASE_YSEM = 0x1500000,
1782         GRCBASE_PSEM = 0x1600000,
1783         GRCBASE_RSS = 0x238800,
1784         GRCBASE_TMLD = 0x4d0000,
1785         GRCBASE_MULD = 0x4e0000,
1786         GRCBASE_YULD = 0x4c8000,
1787         GRCBASE_XYLD = 0x4c0000,
1788         GRCBASE_PTLD = 0x5a0000,
1789         GRCBASE_YPLD = 0x5c0000,
1790         GRCBASE_PRM = 0x230000,
1791         GRCBASE_PBF_PB1 = 0xda0000,
1792         GRCBASE_PBF_PB2 = 0xda4000,
1793         GRCBASE_RPB = 0x23c000,
1794         GRCBASE_BTB = 0xdb0000,
1795         GRCBASE_PBF = 0xd80000,
1796         GRCBASE_RDIF = 0x300000,
1797         GRCBASE_TDIF = 0x310000,
1798         GRCBASE_CDU = 0x580000,
1799         GRCBASE_CCFC = 0x2e0000,
1800         GRCBASE_TCFC = 0x2d0000,
1801         GRCBASE_IGU = 0x180000,
1802         GRCBASE_CAU = 0x1c0000,
1803         GRCBASE_RGFS = 0xf00000,
1804         GRCBASE_RGSRC = 0x320000,
1805         GRCBASE_TGFS = 0xd00000,
1806         GRCBASE_TGSRC = 0x322000,
1807         GRCBASE_UMAC = 0x51000,
1808         GRCBASE_XMAC = 0x210000,
1809         GRCBASE_DBG = 0x10000,
1810         GRCBASE_NIG = 0x500000,
1811         GRCBASE_WOL = 0x600000,
1812         GRCBASE_BMBN = 0x610000,
1813         GRCBASE_IPC = 0x20000,
1814         GRCBASE_NWM = 0x800000,
1815         GRCBASE_NWS = 0x700000,
1816         GRCBASE_MS = 0x6a0000,
1817         GRCBASE_PHY_PCIE = 0x620000,
1818         GRCBASE_LED = 0x6b8000,
1819         GRCBASE_AVS_WRAP = 0x6b0000,
1820         GRCBASE_PXPREQBUS = 0x56000,
1821         GRCBASE_MISC_AEU = 0x8000,
1822         GRCBASE_BAR0_MAP = 0x1c00000,
1823         MAX_BLOCK_ADDR
1824 };
1825
1826 enum block_id {
1827         BLOCK_GRC,
1828         BLOCK_MISCS,
1829         BLOCK_MISC,
1830         BLOCK_DBU,
1831         BLOCK_PGLUE_B,
1832         BLOCK_CNIG,
1833         BLOCK_CPMU,
1834         BLOCK_NCSI,
1835         BLOCK_OPTE,
1836         BLOCK_BMB,
1837         BLOCK_PCIE,
1838         BLOCK_MCP,
1839         BLOCK_MCP2,
1840         BLOCK_PSWHST,
1841         BLOCK_PSWHST2,
1842         BLOCK_PSWRD,
1843         BLOCK_PSWRD2,
1844         BLOCK_PSWWR,
1845         BLOCK_PSWWR2,
1846         BLOCK_PSWRQ,
1847         BLOCK_PSWRQ2,
1848         BLOCK_PGLCS,
1849         BLOCK_DMAE,
1850         BLOCK_PTU,
1851         BLOCK_TCM,
1852         BLOCK_MCM,
1853         BLOCK_UCM,
1854         BLOCK_XCM,
1855         BLOCK_YCM,
1856         BLOCK_PCM,
1857         BLOCK_QM,
1858         BLOCK_TM,
1859         BLOCK_DORQ,
1860         BLOCK_BRB,
1861         BLOCK_SRC,
1862         BLOCK_PRS,
1863         BLOCK_TSDM,
1864         BLOCK_MSDM,
1865         BLOCK_USDM,
1866         BLOCK_XSDM,
1867         BLOCK_YSDM,
1868         BLOCK_PSDM,
1869         BLOCK_TSEM,
1870         BLOCK_MSEM,
1871         BLOCK_USEM,
1872         BLOCK_XSEM,
1873         BLOCK_YSEM,
1874         BLOCK_PSEM,
1875         BLOCK_RSS,
1876         BLOCK_TMLD,
1877         BLOCK_MULD,
1878         BLOCK_YULD,
1879         BLOCK_XYLD,
1880         BLOCK_PTLD,
1881         BLOCK_YPLD,
1882         BLOCK_PRM,
1883         BLOCK_PBF_PB1,
1884         BLOCK_PBF_PB2,
1885         BLOCK_RPB,
1886         BLOCK_BTB,
1887         BLOCK_PBF,
1888         BLOCK_RDIF,
1889         BLOCK_TDIF,
1890         BLOCK_CDU,
1891         BLOCK_CCFC,
1892         BLOCK_TCFC,
1893         BLOCK_IGU,
1894         BLOCK_CAU,
1895         BLOCK_RGFS,
1896         BLOCK_RGSRC,
1897         BLOCK_TGFS,
1898         BLOCK_TGSRC,
1899         BLOCK_UMAC,
1900         BLOCK_XMAC,
1901         BLOCK_DBG,
1902         BLOCK_NIG,
1903         BLOCK_WOL,
1904         BLOCK_BMBN,
1905         BLOCK_IPC,
1906         BLOCK_NWM,
1907         BLOCK_NWS,
1908         BLOCK_MS,
1909         BLOCK_PHY_PCIE,
1910         BLOCK_LED,
1911         BLOCK_AVS_WRAP,
1912         BLOCK_PXPREQBUS,
1913         BLOCK_MISC_AEU,
1914         BLOCK_BAR0_MAP,
1915         MAX_BLOCK_ID
1916 };
1917
1918 /* binary debug buffer types */
1919 enum bin_dbg_buffer_type {
1920         BIN_BUF_DBG_MODE_TREE,
1921         BIN_BUF_DBG_DUMP_REG,
1922         BIN_BUF_DBG_DUMP_MEM,
1923         BIN_BUF_DBG_IDLE_CHK_REGS,
1924         BIN_BUF_DBG_IDLE_CHK_IMMS,
1925         BIN_BUF_DBG_IDLE_CHK_RULES,
1926         BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1927         BIN_BUF_DBG_ATTN_BLOCKS,
1928         BIN_BUF_DBG_ATTN_REGS,
1929         BIN_BUF_DBG_ATTN_INDEXES,
1930         BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1931         BIN_BUF_DBG_BUS_BLOCKS,
1932         BIN_BUF_DBG_BUS_LINES,
1933         BIN_BUF_DBG_BUS_BLOCKS_USER_DATA,
1934         BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
1935         BIN_BUF_DBG_PARSING_STRINGS,
1936         MAX_BIN_DBG_BUFFER_TYPE
1937 };
1938
1939
1940 /* Attention bit mapping */
1941 struct dbg_attn_bit_mapping {
1942         u16 data;
1943 #define DBG_ATTN_BIT_MAPPING_VAL_MASK                   0x7FFF
1944 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT                  0
1945 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK     0x1
1946 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT    15
1947 };
1948
1949 /* Attention block per-type data */
1950 struct dbg_attn_block_type_data {
1951         u16 names_offset;
1952         u16 reserved1;
1953         u8 num_regs;
1954         u8 reserved2;
1955         u16 regs_offset;
1956
1957 };
1958
1959 /* Block attentions */
1960 struct dbg_attn_block {
1961         struct dbg_attn_block_type_data per_type_data[2];
1962 };
1963
1964 /* Attention register result */
1965 struct dbg_attn_reg_result {
1966         u32 data;
1967 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK    0xFFFFFF
1968 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT   0
1969 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK   0xFF
1970 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT  24
1971         u16 block_attn_offset;
1972         u16 reserved;
1973         u32 sts_val;
1974         u32 mask_val;
1975 };
1976
1977 /* Attention block result */
1978 struct dbg_attn_block_result {
1979         u8 block_id;
1980         u8 data;
1981 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK    0x3
1982 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT   0
1983 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK     0x3F
1984 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT    2
1985         u16 names_offset;
1986         struct dbg_attn_reg_result reg_results[15];
1987 };
1988
1989 /* Mode header */
1990 struct dbg_mode_hdr {
1991         u16 data;
1992 #define DBG_MODE_HDR_EVAL_MODE_MASK             0x1
1993 #define DBG_MODE_HDR_EVAL_MODE_SHIFT            0
1994 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK      0x7FFF
1995 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT     1
1996 };
1997
1998 /* Attention register */
1999 struct dbg_attn_reg {
2000         struct dbg_mode_hdr mode;
2001         u16 block_attn_offset;
2002         u32 data;
2003 #define DBG_ATTN_REG_STS_ADDRESS_MASK   0xFFFFFF
2004 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT  0
2005 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK  0xFF
2006 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
2007         u32 sts_clr_address;
2008         u32 mask_address;
2009 };
2010
2011 /* Attention types */
2012 enum dbg_attn_type {
2013         ATTN_TYPE_INTERRUPT,
2014         ATTN_TYPE_PARITY,
2015         MAX_DBG_ATTN_TYPE
2016 };
2017
2018 /* Debug Bus block data */
2019 struct dbg_bus_block {
2020         u8 num_of_lines;
2021         u8 has_latency_events;
2022         u16 lines_offset;
2023 };
2024
2025 /* Debug Bus block user data */
2026 struct dbg_bus_block_user_data {
2027         u8 num_of_lines;
2028         u8 has_latency_events;
2029         u16 names_offset;
2030 };
2031
2032 /* Block Debug line data */
2033 struct dbg_bus_line {
2034         u8 data;
2035 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK         0xF
2036 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT        0
2037 #define DBG_BUS_LINE_IS_256B_MASK               0x1
2038 #define DBG_BUS_LINE_IS_256B_SHIFT              4
2039 #define DBG_BUS_LINE_RESERVED_MASK              0x7
2040 #define DBG_BUS_LINE_RESERVED_SHIFT             5
2041         u8 group_sizes;
2042 };
2043
2044 /* Condition header for registers dump */
2045 struct dbg_dump_cond_hdr {
2046         struct dbg_mode_hdr mode; /* Mode header */
2047         u8 block_id; /* block ID */
2048         u8 data_size; /* size in dwords of the data following this header */
2049 };
2050
2051 /* Memory data for registers dump */
2052 struct dbg_dump_mem {
2053         u32 dword0;
2054 #define DBG_DUMP_MEM_ADDRESS_MASK       0xFFFFFF
2055 #define DBG_DUMP_MEM_ADDRESS_SHIFT      0
2056 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK  0xFF
2057 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
2058         u32 dword1;
2059 #define DBG_DUMP_MEM_LENGTH_MASK        0xFFFFFF
2060 #define DBG_DUMP_MEM_LENGTH_SHIFT       0
2061 #define DBG_DUMP_MEM_WIDE_BUS_MASK      0x1
2062 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT     24
2063 #define DBG_DUMP_MEM_RESERVED_MASK      0x7F
2064 #define DBG_DUMP_MEM_RESERVED_SHIFT     25
2065 };
2066
2067 /* Register data for registers dump */
2068 struct dbg_dump_reg {
2069         u32 data;
2070 #define DBG_DUMP_REG_ADDRESS_MASK       0x7FFFFF
2071 #define DBG_DUMP_REG_ADDRESS_SHIFT      0
2072 #define DBG_DUMP_REG_WIDE_BUS_MASK      0x1
2073 #define DBG_DUMP_REG_WIDE_BUS_SHIFT     23
2074 #define DBG_DUMP_REG_LENGTH_MASK        0xFF
2075 #define DBG_DUMP_REG_LENGTH_SHIFT       24
2076 };
2077
2078 /* Split header for registers dump */
2079 struct dbg_dump_split_hdr {
2080         u32 hdr;
2081 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK       0xFFFFFF
2082 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT      0
2083 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK   0xFF
2084 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT  24
2085 };
2086
2087 /* Condition header for idle check */
2088 struct dbg_idle_chk_cond_hdr {
2089         struct dbg_mode_hdr mode; /* Mode header */
2090         u16 data_size; /* size in dwords of the data following this header */
2091 };
2092
2093 /* Idle Check condition register */
2094 struct dbg_idle_chk_cond_reg {
2095         u32 data;
2096 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK      0x7FFFFF
2097 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT     0
2098 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK     0x1
2099 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT    23
2100 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK     0xFF
2101 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT    24
2102         u16 num_entries;
2103         u8 entry_size;
2104         u8 start_entry;
2105 };
2106
2107 /* Idle Check info register */
2108 struct dbg_idle_chk_info_reg {
2109         u32 data;
2110 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK      0x7FFFFF
2111 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT     0
2112 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK     0x1
2113 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT    23
2114 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK     0xFF
2115 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT    24
2116         u16 size; /* register size in dwords */
2117         struct dbg_mode_hdr mode; /* Mode header */
2118 };
2119
2120 /* Idle Check register */
2121 union dbg_idle_chk_reg {
2122         struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
2123         struct dbg_idle_chk_info_reg info_reg; /* info register */
2124 };
2125
2126 /* Idle Check result header */
2127 struct dbg_idle_chk_result_hdr {
2128         u16 rule_id; /* Failing rule index */
2129         u16 mem_entry_id; /* Failing memory entry index */
2130         u8 num_dumped_cond_regs; /* number of dumped condition registers */
2131         u8 num_dumped_info_regs; /* number of dumped condition registers */
2132         u8 severity; /* from dbg_idle_chk_severity_types enum */
2133         u8 reserved;
2134 };
2135
2136 /* Idle Check result register header */
2137 struct dbg_idle_chk_result_reg_hdr {
2138         u8 data;
2139 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK  0x1
2140 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
2141 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK  0x7F
2142 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
2143         u8 start_entry; /* index of the first checked entry */
2144         u16 size; /* register size in dwords */
2145 };
2146
2147 /* Idle Check rule */
2148 struct dbg_idle_chk_rule {
2149         u16 rule_id; /* Idle Check rule ID */
2150         u8 severity; /* value from dbg_idle_chk_severity_types enum */
2151         u8 cond_id; /* Condition ID */
2152         u8 num_cond_regs; /* number of condition registers */
2153         u8 num_info_regs; /* number of info registers */
2154         u8 num_imms; /* number of immediates in the condition */
2155         u8 reserved1;
2156         u16 reg_offset; /* offset of this rules registers in the idle check
2157                          * register array (in dbg_idle_chk_reg units).
2158                          */
2159         u16 imm_offset; /* offset of this rules immediate values in the
2160                          * immediate values array (in dwords).
2161                          */
2162 };
2163
2164 /* Idle Check rule parsing data */
2165 struct dbg_idle_chk_rule_parsing_data {
2166         u32 data;
2167 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK  0x1
2168 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
2169 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK  0x7FFFFFFF
2170 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
2171 };
2172
2173 /* Idle check severity types */
2174 enum dbg_idle_chk_severity_types {
2175         /* idle check failure should cause an error */
2176         IDLE_CHK_SEVERITY_ERROR,
2177         /* idle check failure should cause an error only if theres no traffic */
2178         IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
2179         /* idle check failure should cause a warning */
2180         IDLE_CHK_SEVERITY_WARNING,
2181         MAX_DBG_IDLE_CHK_SEVERITY_TYPES
2182 };
2183
2184 /* Debug Bus block data */
2185 struct dbg_bus_block_data {
2186         u16 data;
2187 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK             0xF
2188 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT            0
2189 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK             0xF
2190 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT            4
2191 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK        0xF
2192 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT       8
2193 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK        0xF
2194 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT       12
2195         u8 line_num;
2196         u8 hw_id;
2197 };
2198
2199 /* Debug Bus Clients */
2200 enum dbg_bus_clients {
2201         DBG_BUS_CLIENT_RBCN,
2202         DBG_BUS_CLIENT_RBCP,
2203         DBG_BUS_CLIENT_RBCR,
2204         DBG_BUS_CLIENT_RBCT,
2205         DBG_BUS_CLIENT_RBCU,
2206         DBG_BUS_CLIENT_RBCF,
2207         DBG_BUS_CLIENT_RBCX,
2208         DBG_BUS_CLIENT_RBCS,
2209         DBG_BUS_CLIENT_RBCH,
2210         DBG_BUS_CLIENT_RBCZ,
2211         DBG_BUS_CLIENT_OTHER_ENGINE,
2212         DBG_BUS_CLIENT_TIMESTAMP,
2213         DBG_BUS_CLIENT_CPU,
2214         DBG_BUS_CLIENT_RBCY,
2215         DBG_BUS_CLIENT_RBCQ,
2216         DBG_BUS_CLIENT_RBCM,
2217         DBG_BUS_CLIENT_RBCB,
2218         DBG_BUS_CLIENT_RBCW,
2219         DBG_BUS_CLIENT_RBCV,
2220         MAX_DBG_BUS_CLIENTS
2221 };
2222
2223 /* Debug Bus constraint operation types */
2224 enum dbg_bus_constraint_ops {
2225         DBG_BUS_CONSTRAINT_OP_EQ,
2226         DBG_BUS_CONSTRAINT_OP_NE,
2227         DBG_BUS_CONSTRAINT_OP_LT,
2228         DBG_BUS_CONSTRAINT_OP_LTC,
2229         DBG_BUS_CONSTRAINT_OP_LE,
2230         DBG_BUS_CONSTRAINT_OP_LEC,
2231         DBG_BUS_CONSTRAINT_OP_GT,
2232         DBG_BUS_CONSTRAINT_OP_GTC,
2233         DBG_BUS_CONSTRAINT_OP_GE,
2234         DBG_BUS_CONSTRAINT_OP_GEC,
2235         MAX_DBG_BUS_CONSTRAINT_OPS
2236 };
2237
2238 /* Debug Bus trigger state data */
2239 struct dbg_bus_trigger_state_data {
2240         u8 data;
2241 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK       0xF
2242 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT      0
2243 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK           0xF
2244 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT          4
2245 };
2246
2247 /* Debug Bus memory address */
2248 struct dbg_bus_mem_addr {
2249         u32 lo;
2250         u32 hi;
2251 };
2252
2253 /* Debug Bus PCI buffer data */
2254 struct dbg_bus_pci_buf_data {
2255         struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
2256         struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
2257         u32 size; /* PCI buffer size in bytes */
2258 };
2259
2260 /* Debug Bus Storm EID range filter params */
2261 struct dbg_bus_storm_eid_range_params {
2262         u8 min; /* Minimal event ID to filter on */
2263         u8 max; /* Maximal event ID to filter on */
2264 };
2265
2266 /* Debug Bus Storm EID mask filter params */
2267 struct dbg_bus_storm_eid_mask_params {
2268         u8 val; /* Event ID value */
2269         u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2270 };
2271
2272 /* Debug Bus Storm EID filter params */
2273 union dbg_bus_storm_eid_params {
2274         struct dbg_bus_storm_eid_range_params range;
2275         struct dbg_bus_storm_eid_mask_params mask;
2276 };
2277
2278 /* Debug Bus Storm data */
2279 struct dbg_bus_storm_data {
2280         u8 enabled;
2281         u8 mode;
2282         u8 hw_id;
2283         u8 eid_filter_en;
2284         u8 eid_range_not_mask;
2285         u8 cid_filter_en;
2286         union dbg_bus_storm_eid_params eid_filter_params;
2287         u32 cid;
2288 };
2289
2290 /* Debug Bus data */
2291 struct dbg_bus_data {
2292         u32 app_version;
2293         u8 state;
2294         u8 hw_dwords;
2295         u16 hw_id_mask;
2296         u8 num_enabled_blocks;
2297         u8 num_enabled_storms;
2298         u8 target;
2299         u8 one_shot_en;
2300         u8 grc_input_en;
2301         u8 timestamp_input_en;
2302         u8 filter_en;
2303         u8 adding_filter;
2304         u8 filter_pre_trigger;
2305         u8 filter_post_trigger;
2306         u16 reserved;
2307         u8 trigger_en;
2308         struct dbg_bus_trigger_state_data trigger_states[3];
2309         u8 next_trigger_state;
2310         u8 next_constraint_id;
2311         u8 unify_inputs;
2312         u8 rcv_from_other_engine;
2313         struct dbg_bus_pci_buf_data pci_buf;
2314         struct dbg_bus_block_data blocks[88];
2315         struct dbg_bus_storm_data storms[6];
2316 };
2317
2318 /* Debug bus filter types */
2319 enum dbg_bus_filter_types {
2320         DBG_BUS_FILTER_TYPE_OFF,
2321         DBG_BUS_FILTER_TYPE_PRE,
2322         DBG_BUS_FILTER_TYPE_POST,
2323         DBG_BUS_FILTER_TYPE_ON,
2324         MAX_DBG_BUS_FILTER_TYPES
2325 };
2326
2327 /* Debug bus frame modes */
2328 enum dbg_bus_frame_modes {
2329         DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
2330         DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
2331         DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
2332         MAX_DBG_BUS_FRAME_MODES
2333 };
2334
2335 /* Debug bus other engine mode */
2336 enum dbg_bus_other_engine_modes {
2337         DBG_BUS_OTHER_ENGINE_MODE_NONE,
2338         DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
2339         DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
2340         DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
2341         DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
2342         MAX_DBG_BUS_OTHER_ENGINE_MODES
2343 };
2344
2345 /* Debug bus post-trigger recording types */
2346 enum dbg_bus_post_trigger_types {
2347         DBG_BUS_POST_TRIGGER_RECORD,
2348         DBG_BUS_POST_TRIGGER_DROP,
2349         MAX_DBG_BUS_POST_TRIGGER_TYPES
2350 };
2351
2352 /* Debug bus pre-trigger recording types */
2353 enum dbg_bus_pre_trigger_types {
2354         DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
2355         DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
2356         DBG_BUS_PRE_TRIGGER_DROP,
2357         MAX_DBG_BUS_PRE_TRIGGER_TYPES
2358 };
2359
2360 /* Debug bus SEMI frame modes */
2361 enum dbg_bus_semi_frame_modes {
2362         DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
2363         DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
2364         MAX_DBG_BUS_SEMI_FRAME_MODES
2365 };
2366
2367 /* Debug bus states */
2368 enum dbg_bus_states {
2369         DBG_BUS_STATE_IDLE,
2370         DBG_BUS_STATE_READY,
2371         DBG_BUS_STATE_RECORDING,
2372         DBG_BUS_STATE_STOPPED,
2373         MAX_DBG_BUS_STATES
2374 };
2375
2376 /* Debug Bus Storm modes */
2377 enum dbg_bus_storm_modes {
2378         DBG_BUS_STORM_MODE_PRINTF,
2379         DBG_BUS_STORM_MODE_PRAM_ADDR,
2380         DBG_BUS_STORM_MODE_DRA_RW,
2381         DBG_BUS_STORM_MODE_DRA_W,
2382         DBG_BUS_STORM_MODE_LD_ST_ADDR,
2383         DBG_BUS_STORM_MODE_DRA_FSM,
2384         DBG_BUS_STORM_MODE_RH,
2385         DBG_BUS_STORM_MODE_FOC,
2386         DBG_BUS_STORM_MODE_EXT_STORE,
2387         MAX_DBG_BUS_STORM_MODES
2388 };
2389
2390 /* Debug bus target IDs */
2391 enum dbg_bus_targets {
2392         DBG_BUS_TARGET_ID_INT_BUF,
2393         DBG_BUS_TARGET_ID_NIG,
2394         DBG_BUS_TARGET_ID_PCI,
2395         MAX_DBG_BUS_TARGETS
2396 };
2397
2398 /* GRC Dump data */
2399 struct dbg_grc_data {
2400         u8 params_initialized;
2401         u8 reserved1;
2402         u16 reserved2;
2403         u32 param_val[48];
2404 };
2405
2406 /* Debug GRC params */
2407 enum dbg_grc_params {
2408         DBG_GRC_PARAM_DUMP_TSTORM,
2409         DBG_GRC_PARAM_DUMP_MSTORM,
2410         DBG_GRC_PARAM_DUMP_USTORM,
2411         DBG_GRC_PARAM_DUMP_XSTORM,
2412         DBG_GRC_PARAM_DUMP_YSTORM,
2413         DBG_GRC_PARAM_DUMP_PSTORM,
2414         DBG_GRC_PARAM_DUMP_REGS,
2415         DBG_GRC_PARAM_DUMP_RAM,
2416         DBG_GRC_PARAM_DUMP_PBUF,
2417         DBG_GRC_PARAM_DUMP_IOR,
2418         DBG_GRC_PARAM_DUMP_VFC,
2419         DBG_GRC_PARAM_DUMP_CM_CTX,
2420         DBG_GRC_PARAM_DUMP_PXP,
2421         DBG_GRC_PARAM_DUMP_RSS,
2422         DBG_GRC_PARAM_DUMP_CAU,
2423         DBG_GRC_PARAM_DUMP_QM,
2424         DBG_GRC_PARAM_DUMP_MCP,
2425         DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
2426         DBG_GRC_PARAM_DUMP_CFC,
2427         DBG_GRC_PARAM_DUMP_IGU,
2428         DBG_GRC_PARAM_DUMP_BRB,
2429         DBG_GRC_PARAM_DUMP_BTB,
2430         DBG_GRC_PARAM_DUMP_BMB,
2431         DBG_GRC_PARAM_DUMP_NIG,
2432         DBG_GRC_PARAM_DUMP_MULD,
2433         DBG_GRC_PARAM_DUMP_PRS,
2434         DBG_GRC_PARAM_DUMP_DMAE,
2435         DBG_GRC_PARAM_DUMP_TM,
2436         DBG_GRC_PARAM_DUMP_SDM,
2437         DBG_GRC_PARAM_DUMP_DIF,
2438         DBG_GRC_PARAM_DUMP_STATIC,
2439         DBG_GRC_PARAM_UNSTALL,
2440         DBG_GRC_PARAM_NUM_LCIDS,
2441         DBG_GRC_PARAM_NUM_LTIDS,
2442         DBG_GRC_PARAM_EXCLUDE_ALL,
2443         DBG_GRC_PARAM_CRASH,
2444         DBG_GRC_PARAM_PARITY_SAFE,
2445         DBG_GRC_PARAM_DUMP_CM,
2446         DBG_GRC_PARAM_DUMP_PHY,
2447         DBG_GRC_PARAM_NO_MCP,
2448         DBG_GRC_PARAM_NO_FW_VER,
2449         MAX_DBG_GRC_PARAMS
2450 };
2451
2452 /* Debug reset registers */
2453 enum dbg_reset_regs {
2454         DBG_RESET_REG_MISCS_PL_UA,
2455         DBG_RESET_REG_MISCS_PL_HV,
2456         DBG_RESET_REG_MISCS_PL_HV_2,
2457         DBG_RESET_REG_MISC_PL_UA,
2458         DBG_RESET_REG_MISC_PL_HV,
2459         DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
2460         DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
2461         DBG_RESET_REG_MISC_PL_PDA_VAUX,
2462         MAX_DBG_RESET_REGS
2463 };
2464
2465 /* Debug status codes */
2466 enum dbg_status {
2467         DBG_STATUS_OK,
2468         DBG_STATUS_APP_VERSION_NOT_SET,
2469         DBG_STATUS_UNSUPPORTED_APP_VERSION,
2470         DBG_STATUS_DBG_BLOCK_NOT_RESET,
2471         DBG_STATUS_INVALID_ARGS,
2472         DBG_STATUS_OUTPUT_ALREADY_SET,
2473         DBG_STATUS_INVALID_PCI_BUF_SIZE,
2474         DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2475         DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2476         DBG_STATUS_TOO_MANY_INPUTS,
2477         DBG_STATUS_INPUT_OVERLAP,
2478         DBG_STATUS_HW_ONLY_RECORDING,
2479         DBG_STATUS_STORM_ALREADY_ENABLED,
2480         DBG_STATUS_STORM_NOT_ENABLED,
2481         DBG_STATUS_BLOCK_ALREADY_ENABLED,
2482         DBG_STATUS_BLOCK_NOT_ENABLED,
2483         DBG_STATUS_NO_INPUT_ENABLED,
2484         DBG_STATUS_NO_FILTER_TRIGGER_64B,
2485         DBG_STATUS_FILTER_ALREADY_ENABLED,
2486         DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2487         DBG_STATUS_TRIGGER_NOT_ENABLED,
2488         DBG_STATUS_CANT_ADD_CONSTRAINT,
2489         DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2490         DBG_STATUS_TOO_MANY_CONSTRAINTS,
2491         DBG_STATUS_RECORDING_NOT_STARTED,
2492         DBG_STATUS_DATA_DIDNT_TRIGGER,
2493         DBG_STATUS_NO_DATA_RECORDED,
2494         DBG_STATUS_DUMP_BUF_TOO_SMALL,
2495         DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2496         DBG_STATUS_UNKNOWN_CHIP,
2497         DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2498         DBG_STATUS_BLOCK_IN_RESET,
2499         DBG_STATUS_INVALID_TRACE_SIGNATURE,
2500         DBG_STATUS_INVALID_NVRAM_BUNDLE,
2501         DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2502         DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2503         DBG_STATUS_NVRAM_READ_FAILED,
2504         DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2505         DBG_STATUS_MCP_TRACE_BAD_DATA,
2506         DBG_STATUS_MCP_TRACE_NO_META,
2507         DBG_STATUS_MCP_COULD_NOT_HALT,
2508         DBG_STATUS_MCP_COULD_NOT_RESUME,
2509         DBG_STATUS_RESERVED2,
2510         DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2511         DBG_STATUS_IGU_FIFO_BAD_DATA,
2512         DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2513         DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2514         DBG_STATUS_REG_FIFO_BAD_DATA,
2515         DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2516         DBG_STATUS_DBG_ARRAY_NOT_SET,
2517         DBG_STATUS_FILTER_BUG,
2518         DBG_STATUS_NON_MATCHING_LINES,
2519         DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET,
2520         DBG_STATUS_DBG_BUS_IN_USE,
2521         MAX_DBG_STATUS
2522 };
2523
2524 /* Debug Storms IDs */
2525 enum dbg_storms {
2526         DBG_TSTORM_ID,
2527         DBG_MSTORM_ID,
2528         DBG_USTORM_ID,
2529         DBG_XSTORM_ID,
2530         DBG_YSTORM_ID,
2531         DBG_PSTORM_ID,
2532         MAX_DBG_STORMS
2533 };
2534
2535 /* Idle Check data */
2536 struct idle_chk_data {
2537         u32 buf_size;
2538         u8 buf_size_set;
2539         u8 reserved1;
2540         u16 reserved2;
2541 };
2542
2543 struct pretend_params {
2544         u8 split_type;
2545         u8 reserved;
2546         u16 split_id;
2547 };
2548
2549 /* Debug Tools data (per HW function)
2550  */
2551 struct dbg_tools_data {
2552         struct dbg_grc_data grc;
2553         struct dbg_bus_data bus;
2554         struct idle_chk_data idle_chk;
2555         u8 mode_enable[40];
2556         u8 block_in_reset[88];
2557         u8 chip_id;
2558         u8 platform_id;
2559         u8 num_ports;
2560         u8 num_pfs_per_port;
2561         u8 num_vfs;
2562         u8 initialized;
2563         u8 use_dmae;
2564         u8 reserved;
2565         struct pretend_params pretend;
2566         u32 num_regs_read;
2567 };
2568
2569 /********************************/
2570 /* HSI Init Functions constants */
2571 /********************************/
2572
2573 /* Number of VLAN priorities */
2574 #define NUM_OF_VLAN_PRIORITIES  8
2575
2576 /* BRB RAM init requirements */
2577 struct init_brb_ram_req {
2578         u32 guranteed_per_tc;
2579         u32 headroom_per_tc;
2580         u32 min_pkt_size;
2581         u32 max_ports_per_engine;
2582         u8 num_active_tcs[MAX_NUM_PORTS];
2583 };
2584
2585 /* ETS per-TC init requirements */
2586 struct init_ets_tc_req {
2587         u8 use_sp;
2588         u8 use_wfq;
2589         u16 weight;
2590 };
2591
2592 /* ETS init requirements */
2593 struct init_ets_req {
2594         u32 mtu;
2595         struct init_ets_tc_req tc_req[NUM_OF_TCS];
2596 };
2597
2598 /* NIG LB RL init requirements */
2599 struct init_nig_lb_rl_req {
2600         u16 lb_mac_rate;
2601         u16 lb_rate;
2602         u32 mtu;
2603         u16 tc_rate[NUM_OF_PHYS_TCS];
2604 };
2605
2606 /* NIG TC mapping for each priority */
2607 struct init_nig_pri_tc_map_entry {
2608         u8 tc_id;
2609         u8 valid;
2610 };
2611
2612 /* NIG priority to TC map init requirements */
2613 struct init_nig_pri_tc_map_req {
2614         struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2615 };
2616
2617 /* QM per-port init parameters */
2618 struct init_qm_port_params {
2619         u8 active;
2620         u8 active_phys_tcs;
2621         u16 num_pbf_cmd_lines;
2622         u16 num_btb_blocks;
2623         u16 reserved;
2624 };
2625
2626 /* QM per-PQ init parameters */
2627 struct init_qm_pq_params {
2628         u8 vport_id;
2629         u8 tc_id;
2630         u8 wrr_group;
2631         u8 rl_valid;
2632         u8 port_id;
2633         u8 reserved0;
2634         u16 reserved1;
2635 };
2636
2637 /* QM per-vport init parameters */
2638 struct init_qm_vport_params {
2639         u32 vport_rl;
2640         u16 vport_wfq;
2641         u16 first_tx_pq_id[NUM_OF_TCS];
2642 };
2643
2644 /**************************************/
2645 /* Init Tool HSI constants and macros */
2646 /**************************************/
2647
2648 /* Width of GRC address in bits (addresses are specified in dwords) */
2649 #define GRC_ADDR_BITS   23
2650 #define MAX_GRC_ADDR    (BIT(GRC_ADDR_BITS) - 1)
2651
2652 /* indicates an init that should be applied to any phase ID */
2653 #define ANY_PHASE_ID    0xffff
2654
2655 /* Max size in dwords of a zipped array */
2656 #define MAX_ZIPPED_SIZE 8192
2657 enum chip_ids {
2658         CHIP_BB,
2659         CHIP_K2,
2660         CHIP_RESERVED,
2661         MAX_CHIP_IDS
2662 };
2663
2664 struct fw_asserts_ram_section {
2665         u16 section_ram_line_offset;
2666         u16 section_ram_line_size;
2667         u8 list_dword_offset;
2668         u8 list_element_dword_size;
2669         u8 list_num_elements;
2670         u8 list_next_index_dword_offset;
2671 };
2672
2673 struct fw_ver_num {
2674         u8 major;
2675         u8 minor;
2676         u8 rev;
2677         u8 eng;
2678 };
2679
2680 struct fw_ver_info {
2681         __le16 tools_ver;
2682         u8 image_id;
2683         u8 reserved1;
2684         struct fw_ver_num num;
2685         __le32 timestamp;
2686         __le32 reserved2;
2687 };
2688
2689 struct fw_info {
2690         struct fw_ver_info ver;
2691         struct fw_asserts_ram_section fw_asserts_section;
2692 };
2693
2694 struct fw_info_location {
2695         __le32 grc_addr;
2696         __le32 size;
2697 };
2698
2699 enum init_modes {
2700         MODE_RESERVED,
2701         MODE_BB,
2702         MODE_K2,
2703         MODE_ASIC,
2704         MODE_RESERVED2,
2705         MODE_RESERVED3,
2706         MODE_RESERVED4,
2707         MODE_RESERVED5,
2708         MODE_SF,
2709         MODE_MF_SD,
2710         MODE_MF_SI,
2711         MODE_PORTS_PER_ENG_1,
2712         MODE_PORTS_PER_ENG_2,
2713         MODE_PORTS_PER_ENG_4,
2714         MODE_100G,
2715         MODE_RESERVED6,
2716         MAX_INIT_MODES
2717 };
2718
2719 enum init_phases {
2720         PHASE_ENGINE,
2721         PHASE_PORT,
2722         PHASE_PF,
2723         PHASE_VF,
2724         PHASE_QM_PF,
2725         MAX_INIT_PHASES
2726 };
2727
2728 enum init_split_types {
2729         SPLIT_TYPE_NONE,
2730         SPLIT_TYPE_PORT,
2731         SPLIT_TYPE_PF,
2732         SPLIT_TYPE_PORT_PF,
2733         SPLIT_TYPE_VF,
2734         MAX_INIT_SPLIT_TYPES
2735 };
2736
2737 /* Binary buffer header */
2738 struct bin_buffer_hdr {
2739         u32 offset;
2740         u32 length;
2741 };
2742
2743 /* Binary init buffer types */
2744 enum bin_init_buffer_type {
2745         BIN_BUF_INIT_FW_VER_INFO,
2746         BIN_BUF_INIT_CMD,
2747         BIN_BUF_INIT_VAL,
2748         BIN_BUF_INIT_MODE_TREE,
2749         BIN_BUF_INIT_IRO,
2750         MAX_BIN_INIT_BUFFER_TYPE
2751 };
2752
2753 /* init array header: raw */
2754 struct init_array_raw_hdr {
2755         u32 data;
2756 #define INIT_ARRAY_RAW_HDR_TYPE_MASK    0xF
2757 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT   0
2758 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK  0xFFFFFFF
2759 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
2760 };
2761
2762 /* init array header: standard */
2763 struct init_array_standard_hdr {
2764         u32 data;
2765 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK       0xF
2766 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT      0
2767 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK       0xFFFFFFF
2768 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT      4
2769 };
2770
2771 /* init array header: zipped */
2772 struct init_array_zipped_hdr {
2773         u32 data;
2774 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK         0xF
2775 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT        0
2776 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK  0xFFFFFFF
2777 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
2778 };
2779
2780 /* init array header: pattern */
2781 struct init_array_pattern_hdr {
2782         u32 data;
2783 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK                0xF
2784 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT               0
2785 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK        0xF
2786 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT       4
2787 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK         0xFFFFFF
2788 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT        8
2789 };
2790
2791 /* init array header union */
2792 union init_array_hdr {
2793         struct init_array_raw_hdr raw;
2794         struct init_array_standard_hdr standard;
2795         struct init_array_zipped_hdr zipped;
2796         struct init_array_pattern_hdr pattern;
2797 };
2798
2799 /* init array types */
2800 enum init_array_types {
2801         INIT_ARR_STANDARD,
2802         INIT_ARR_ZIPPED,
2803         INIT_ARR_PATTERN,
2804         MAX_INIT_ARRAY_TYPES
2805 };
2806
2807 /* init operation: callback */
2808 struct init_callback_op {
2809         u32 op_data;
2810 #define INIT_CALLBACK_OP_OP_MASK        0xF
2811 #define INIT_CALLBACK_OP_OP_SHIFT       0
2812 #define INIT_CALLBACK_OP_RESERVED_MASK  0xFFFFFFF
2813 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
2814         u16 callback_id;
2815         u16 block_id;
2816 };
2817
2818 /* init operation: delay */
2819 struct init_delay_op {
2820         u32 op_data;
2821 #define INIT_DELAY_OP_OP_MASK           0xF
2822 #define INIT_DELAY_OP_OP_SHIFT          0
2823 #define INIT_DELAY_OP_RESERVED_MASK     0xFFFFFFF
2824 #define INIT_DELAY_OP_RESERVED_SHIFT    4
2825         u32 delay;
2826 };
2827
2828 /* init operation: if_mode */
2829 struct init_if_mode_op {
2830         u32 op_data;
2831 #define INIT_IF_MODE_OP_OP_MASK                 0xF
2832 #define INIT_IF_MODE_OP_OP_SHIFT                0
2833 #define INIT_IF_MODE_OP_RESERVED1_MASK          0xFFF
2834 #define INIT_IF_MODE_OP_RESERVED1_SHIFT         4
2835 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK         0xFFFF
2836 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT        16
2837         u16 reserved2;
2838         u16 modes_buf_offset;
2839 };
2840
2841 /* init operation: if_phase */
2842 struct init_if_phase_op {
2843         u32 op_data;
2844 #define INIT_IF_PHASE_OP_OP_MASK                0xF
2845 #define INIT_IF_PHASE_OP_OP_SHIFT               0
2846 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK       0x1
2847 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT      4
2848 #define INIT_IF_PHASE_OP_RESERVED1_MASK         0x7FF
2849 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT        5
2850 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK        0xFFFF
2851 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT       16
2852         u32 phase_data;
2853 #define INIT_IF_PHASE_OP_PHASE_MASK             0xFF
2854 #define INIT_IF_PHASE_OP_PHASE_SHIFT            0
2855 #define INIT_IF_PHASE_OP_RESERVED2_MASK         0xFF
2856 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT        8
2857 #define INIT_IF_PHASE_OP_PHASE_ID_MASK          0xFFFF
2858 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT         16
2859 };
2860
2861 /* init mode operators */
2862 enum init_mode_ops {
2863         INIT_MODE_OP_NOT,
2864         INIT_MODE_OP_OR,
2865         INIT_MODE_OP_AND,
2866         MAX_INIT_MODE_OPS
2867 };
2868
2869 /* init operation: raw */
2870 struct init_raw_op {
2871         u32 op_data;
2872 #define INIT_RAW_OP_OP_MASK             0xF
2873 #define INIT_RAW_OP_OP_SHIFT            0
2874 #define INIT_RAW_OP_PARAM1_MASK         0xFFFFFFF
2875 #define INIT_RAW_OP_PARAM1_SHIFT        4
2876         u32 param2;
2877 };
2878
2879 /* init array params */
2880 struct init_op_array_params {
2881         u16 size;
2882         u16 offset;
2883 };
2884
2885 /* Write init operation arguments */
2886 union init_write_args {
2887         u32 inline_val;
2888         u32 zeros_count;
2889         u32 array_offset;
2890         struct init_op_array_params runtime;
2891 };
2892
2893 /* init operation: write */
2894 struct init_write_op {
2895         u32 data;
2896 #define INIT_WRITE_OP_OP_MASK           0xF
2897 #define INIT_WRITE_OP_OP_SHIFT          0
2898 #define INIT_WRITE_OP_SOURCE_MASK       0x7
2899 #define INIT_WRITE_OP_SOURCE_SHIFT      4
2900 #define INIT_WRITE_OP_RESERVED_MASK     0x1
2901 #define INIT_WRITE_OP_RESERVED_SHIFT    7
2902 #define INIT_WRITE_OP_WIDE_BUS_MASK     0x1
2903 #define INIT_WRITE_OP_WIDE_BUS_SHIFT    8
2904 #define INIT_WRITE_OP_ADDRESS_MASK      0x7FFFFF
2905 #define INIT_WRITE_OP_ADDRESS_SHIFT     9
2906         union init_write_args args;
2907 };
2908
2909 /* init operation: read */
2910 struct init_read_op {
2911         u32 op_data;
2912 #define INIT_READ_OP_OP_MASK            0xF
2913 #define INIT_READ_OP_OP_SHIFT           0
2914 #define INIT_READ_OP_POLL_TYPE_MASK     0xF
2915 #define INIT_READ_OP_POLL_TYPE_SHIFT    4
2916 #define INIT_READ_OP_RESERVED_MASK      0x1
2917 #define INIT_READ_OP_RESERVED_SHIFT     8
2918 #define INIT_READ_OP_ADDRESS_MASK       0x7FFFFF
2919 #define INIT_READ_OP_ADDRESS_SHIFT      9
2920         u32 expected_val;
2921 };
2922
2923 /* Init operations union */
2924 union init_op {
2925         struct init_raw_op raw;
2926         struct init_write_op write;
2927         struct init_read_op read;
2928         struct init_if_mode_op if_mode;
2929         struct init_if_phase_op if_phase;
2930         struct init_callback_op callback;
2931         struct init_delay_op delay;
2932 };
2933
2934 /* Init command operation types */
2935 enum init_op_types {
2936         INIT_OP_READ,
2937         INIT_OP_WRITE,
2938         INIT_OP_IF_MODE,
2939         INIT_OP_IF_PHASE,
2940         INIT_OP_DELAY,
2941         INIT_OP_CALLBACK,
2942         MAX_INIT_OP_TYPES
2943 };
2944
2945 /* init polling types */
2946 enum init_poll_types {
2947         INIT_POLL_NONE,
2948         INIT_POLL_EQ,
2949         INIT_POLL_OR,
2950         INIT_POLL_AND,
2951         MAX_INIT_POLL_TYPES
2952 };
2953
2954 /* init source types */
2955 enum init_source_types {
2956         INIT_SRC_INLINE,
2957         INIT_SRC_ZEROS,
2958         INIT_SRC_ARRAY,
2959         INIT_SRC_RUNTIME,
2960         MAX_INIT_SOURCE_TYPES
2961 };
2962
2963 /* Internal RAM Offsets macro data */
2964 struct iro {
2965         u32 base;
2966         u16 m1;
2967         u16 m2;
2968         u16 m3;
2969         u16 size;
2970 };
2971
2972 /***************************** Public Functions *******************************/
2973
2974 /**
2975  * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
2976  *      arrays.
2977  *
2978  * @param bin_ptr - a pointer to the binary data with debug arrays.
2979  */
2980 enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
2981
2982 /**
2983  * @brief qed_read_regs - Reads registers into a buffer (using GRC).
2984  *
2985  * @param p_hwfn - HW device data
2986  * @param p_ptt - Ptt window used for writing the registers.
2987  * @param buf - Destination buffer.
2988  * @param addr - Source GRC address in dwords.
2989  * @param len - Number of registers to read.
2990  */
2991 void qed_read_regs(struct qed_hwfn *p_hwfn,
2992                    struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len);
2993
2994 /**
2995  * @brief qed_read_fw_info - Reads FW info from the chip.
2996  *
2997  * The FW info contains FW-related information, such as the FW version,
2998  * FW image (main/L2B/kuku), FW timestamp, etc.
2999  * The FW info is read from the internal RAM of the first Storm that is not in
3000  * reset.
3001  *
3002  * @param p_hwfn -          HW device data
3003  * @param p_ptt -           Ptt window used for writing the registers.
3004  * @param fw_info -     Out: a pointer to write the FW info into.
3005  *
3006  * @return true if the FW info was read successfully from one of the Storms,
3007  * or false if all Storms are in reset.
3008  */
3009 bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
3010                       struct qed_ptt *p_ptt, struct fw_info *fw_info);
3011
3012 /**
3013  * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
3014  *      default value.
3015  *
3016  * @param p_hwfn                - HW device data
3017  */
3018 void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
3019 /**
3020  * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
3021  *      GRC Dump.
3022  *
3023  * @param p_hwfn - HW device data
3024  * @param p_ptt - Ptt window used for writing the registers.
3025  * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
3026  *      data.
3027  *
3028  * @return error if one of the following holds:
3029  *      - the version wasn't set
3030  * Otherwise, returns ok.
3031  */
3032 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3033                                               struct qed_ptt *p_ptt,
3034                                               u32 *buf_size);
3035
3036 /**
3037  * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
3038  *
3039  * @param p_hwfn - HW device data
3040  * @param p_ptt - Ptt window used for writing the registers.
3041  * @param dump_buf - Pointer to write the collected GRC data into.
3042  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3043  * @param num_dumped_dwords - OUT: number of dumped dwords.
3044  *
3045  * @return error if one of the following holds:
3046  *      - the version wasn't set
3047  *      - the specified dump buffer is too small
3048  * Otherwise, returns ok.
3049  */
3050 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
3051                                  struct qed_ptt *p_ptt,
3052                                  u32 *dump_buf,
3053                                  u32 buf_size_in_dwords,
3054                                  u32 *num_dumped_dwords);
3055
3056 /**
3057  * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
3058  *      for idle check results.
3059  *
3060  * @param p_hwfn - HW device data
3061  * @param p_ptt - Ptt window used for writing the registers.
3062  * @param buf_size - OUT: required buffer size (in dwords) for the idle check
3063  *      data.
3064  *
3065  * @return error if one of the following holds:
3066  *      - the version wasn't set
3067  * Otherwise, returns ok.
3068  */
3069 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3070                                                    struct qed_ptt *p_ptt,
3071                                                    u32 *buf_size);
3072
3073 /**
3074  * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
3075  *      into the specified buffer.
3076  *
3077  * @param p_hwfn - HW device data
3078  * @param p_ptt - Ptt window used for writing the registers.
3079  * @param dump_buf - Pointer to write the idle check data into.
3080  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3081  * @param num_dumped_dwords - OUT: number of dumped dwords.
3082  *
3083  * @return error if one of the following holds:
3084  *      - the version wasn't set
3085  *      - the specified buffer is too small
3086  * Otherwise, returns ok.
3087  */
3088 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
3089                                       struct qed_ptt *p_ptt,
3090                                       u32 *dump_buf,
3091                                       u32 buf_size_in_dwords,
3092                                       u32 *num_dumped_dwords);
3093
3094 /**
3095  * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
3096  *      for mcp trace results.
3097  *
3098  * @param p_hwfn - HW device data
3099  * @param p_ptt - Ptt window used for writing the registers.
3100  * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
3101  *
3102  * @return error if one of the following holds:
3103  *      - the version wasn't set
3104  *      - the trace data in MCP scratchpad contain an invalid signature
3105  *      - the bundle ID in NVRAM is invalid
3106  *      - the trace meta data cannot be found (in NVRAM or image file)
3107  * Otherwise, returns ok.
3108  */
3109 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3110                                                     struct qed_ptt *p_ptt,
3111                                                     u32 *buf_size);
3112
3113 /**
3114  * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
3115  *      into the specified buffer.
3116  *
3117  * @param p_hwfn - HW device data
3118  * @param p_ptt - Ptt window used for writing the registers.
3119  * @param dump_buf - Pointer to write the mcp trace data into.
3120  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3121  * @param num_dumped_dwords - OUT: number of dumped dwords.
3122  *
3123  * @return error if one of the following holds:
3124  *      - the version wasn't set
3125  *      - the specified buffer is too small
3126  *      - the trace data in MCP scratchpad contain an invalid signature
3127  *      - the bundle ID in NVRAM is invalid
3128  *      - the trace meta data cannot be found (in NVRAM or image file)
3129  *      - the trace meta data cannot be read (from NVRAM or image file)
3130  * Otherwise, returns ok.
3131  */
3132 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
3133                                        struct qed_ptt *p_ptt,
3134                                        u32 *dump_buf,
3135                                        u32 buf_size_in_dwords,
3136                                        u32 *num_dumped_dwords);
3137
3138 /**
3139  * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
3140  *      for grc trace fifo results.
3141  *
3142  * @param p_hwfn - HW device data
3143  * @param p_ptt - Ptt window used for writing the registers.
3144  * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
3145  *
3146  * @return error if one of the following holds:
3147  *      - the version wasn't set
3148  * Otherwise, returns ok.
3149  */
3150 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3151                                                    struct qed_ptt *p_ptt,
3152                                                    u32 *buf_size);
3153
3154 /**
3155  * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
3156  *      the specified buffer.
3157  *
3158  * @param p_hwfn - HW device data
3159  * @param p_ptt - Ptt window used for writing the registers.
3160  * @param dump_buf - Pointer to write the reg fifo data into.
3161  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3162  * @param num_dumped_dwords - OUT: number of dumped dwords.
3163  *
3164  * @return error if one of the following holds:
3165  *      - the version wasn't set
3166  *      - the specified buffer is too small
3167  *      - DMAE transaction failed
3168  * Otherwise, returns ok.
3169  */
3170 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
3171                                       struct qed_ptt *p_ptt,
3172                                       u32 *dump_buf,
3173                                       u32 buf_size_in_dwords,
3174                                       u32 *num_dumped_dwords);
3175
3176 /**
3177  * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
3178  *      for the IGU fifo results.
3179  *
3180  * @param p_hwfn - HW device data
3181  * @param p_ptt - Ptt window used for writing the registers.
3182  * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
3183  *      data.
3184  *
3185  * @return error if one of the following holds:
3186  *      - the version wasn't set
3187  * Otherwise, returns ok.
3188  */
3189 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3190                                                    struct qed_ptt *p_ptt,
3191                                                    u32 *buf_size);
3192
3193 /**
3194  * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
3195  *      the specified buffer.
3196  *
3197  * @param p_hwfn - HW device data
3198  * @param p_ptt - Ptt window used for writing the registers.
3199  * @param dump_buf - Pointer to write the IGU fifo data into.
3200  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3201  * @param num_dumped_dwords - OUT: number of dumped dwords.
3202  *
3203  * @return error if one of the following holds:
3204  *      - the version wasn't set
3205  *      - the specified buffer is too small
3206  *      - DMAE transaction failed
3207  * Otherwise, returns ok.
3208  */
3209 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
3210                                       struct qed_ptt *p_ptt,
3211                                       u32 *dump_buf,
3212                                       u32 buf_size_in_dwords,
3213                                       u32 *num_dumped_dwords);
3214
3215 /**
3216  * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
3217  *      buffer size for protection override window results.
3218  *
3219  * @param p_hwfn - HW device data
3220  * @param p_ptt - Ptt window used for writing the registers.
3221  * @param buf_size - OUT: required buffer size (in dwords) for protection
3222  *      override data.
3223  *
3224  * @return error if one of the following holds:
3225  *      - the version wasn't set
3226  * Otherwise, returns ok.
3227  */
3228 enum dbg_status
3229 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3230                                               struct qed_ptt *p_ptt,
3231                                               u32 *buf_size);
3232 /**
3233  * @brief qed_dbg_protection_override_dump - Reads protection override window
3234  *      entries and writes the results into the specified buffer.
3235  *
3236  * @param p_hwfn - HW device data
3237  * @param p_ptt - Ptt window used for writing the registers.
3238  * @param dump_buf - Pointer to write the protection override data into.
3239  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3240  * @param num_dumped_dwords - OUT: number of dumped dwords.
3241  *
3242  * @return error if one of the following holds:
3243  *      - the version wasn't set
3244  *      - the specified buffer is too small
3245  *      - DMAE transaction failed
3246  * Otherwise, returns ok.
3247  */
3248 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
3249                                                  struct qed_ptt *p_ptt,
3250                                                  u32 *dump_buf,
3251                                                  u32 buf_size_in_dwords,
3252                                                  u32 *num_dumped_dwords);
3253 /**
3254  * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
3255  *      size for FW Asserts results.
3256  *
3257  * @param p_hwfn - HW device data
3258  * @param p_ptt - Ptt window used for writing the registers.
3259  * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
3260  *
3261  * @return error if one of the following holds:
3262  *      - the version wasn't set
3263  * Otherwise, returns ok.
3264  */
3265 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3266                                                      struct qed_ptt *p_ptt,
3267                                                      u32 *buf_size);
3268 /**
3269  * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
3270  *      into the specified buffer.
3271  *
3272  * @param p_hwfn - HW device data
3273  * @param p_ptt - Ptt window used for writing the registers.
3274  * @param dump_buf - Pointer to write the FW Asserts data into.
3275  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3276  * @param num_dumped_dwords - OUT: number of dumped dwords.
3277  *
3278  * @return error if one of the following holds:
3279  *      - the version wasn't set
3280  *      - the specified buffer is too small
3281  * Otherwise, returns ok.
3282  */
3283 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
3284                                         struct qed_ptt *p_ptt,
3285                                         u32 *dump_buf,
3286                                         u32 buf_size_in_dwords,
3287                                         u32 *num_dumped_dwords);
3288
3289 /**
3290  * @brief qed_dbg_read_attn - Reads the attention registers of the specified
3291  * block and type, and writes the results into the specified buffer.
3292  *
3293  * @param p_hwfn -       HW device data
3294  * @param p_ptt -        Ptt window used for writing the registers.
3295  * @param block -        Block ID.
3296  * @param attn_type -    Attention type.
3297  * @param clear_status - Indicates if the attention status should be cleared.
3298  * @param results -      OUT: Pointer to write the read results into
3299  *
3300  * @return error if one of the following holds:
3301  *      - the version wasn't set
3302  * Otherwise, returns ok.
3303  */
3304 enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn,
3305                                   struct qed_ptt *p_ptt,
3306                                   enum block_id block,
3307                                   enum dbg_attn_type attn_type,
3308                                   bool clear_status,
3309                                   struct dbg_attn_block_result *results);
3310
3311 /**
3312  * @brief qed_dbg_print_attn - Prints attention registers values in the
3313  *      specified results struct.
3314  *
3315  * @param p_hwfn
3316  * @param results - Pointer to the attention read results
3317  *
3318  * @return error if one of the following holds:
3319  *      - the version wasn't set
3320  * Otherwise, returns ok.
3321  */
3322 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3323                                    struct dbg_attn_block_result *results);
3324
3325 /******************************** Constants **********************************/
3326
3327 #define MAX_NAME_LEN    16
3328
3329 /***************************** Public Functions *******************************/
3330
3331 /**
3332  * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3333  *      debug arrays.
3334  *
3335  * @param bin_ptr - a pointer to the binary data with debug arrays.
3336  */
3337 enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
3338
3339 /**
3340  * @brief qed_dbg_get_status_str - Returns a string for the specified status.
3341  *
3342  * @param status - a debug status code.
3343  *
3344  * @return a string for the specified status
3345  */
3346 const char *qed_dbg_get_status_str(enum dbg_status status);
3347
3348 /**
3349  * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
3350  *      for idle check results (in bytes).
3351  *
3352  * @param p_hwfn - HW device data
3353  * @param dump_buf - idle check dump buffer.
3354  * @param num_dumped_dwords - number of dwords that were dumped.
3355  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3356  *      results.
3357  *
3358  * @return error if the parsing fails, ok otherwise.
3359  */
3360 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
3361                                                   u32 *dump_buf,
3362                                                   u32  num_dumped_dwords,
3363                                                   u32 *results_buf_size);
3364 /**
3365  * @brief qed_print_idle_chk_results - Prints idle check results
3366  *
3367  * @param p_hwfn - HW device data
3368  * @param dump_buf - idle check dump buffer.
3369  * @param num_dumped_dwords - number of dwords that were dumped.
3370  * @param results_buf - buffer for printing the idle check results.
3371  * @param num_errors - OUT: number of errors found in idle check.
3372  * @param num_warnings - OUT: number of warnings found in idle check.
3373  *
3374  * @return error if the parsing fails, ok otherwise.
3375  */
3376 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
3377                                            u32 *dump_buf,
3378                                            u32 num_dumped_dwords,
3379                                            char *results_buf,
3380                                            u32 *num_errors,
3381                                            u32 *num_warnings);
3382
3383 /**
3384  * @brief qed_dbg_mcp_trace_set_meta_data - Sets a pointer to the MCP Trace
3385  *      meta data.
3386  *
3387  * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to
3388  * no NVRAM access).
3389  *
3390  * @param data - pointer to MCP Trace meta data
3391  * @param size - size of MCP Trace meta data in dwords
3392  */
3393 void qed_dbg_mcp_trace_set_meta_data(u32 *data, u32 size);
3394
3395 /**
3396  * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
3397  *      for MCP Trace results (in bytes).
3398  *
3399  * @param p_hwfn - HW device data
3400  * @param dump_buf - MCP Trace dump buffer.
3401  * @param num_dumped_dwords - number of dwords that were dumped.
3402  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3403  *      results.
3404  *
3405  * @return error if the parsing fails, ok otherwise.
3406  */
3407 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3408                                                    u32 *dump_buf,
3409                                                    u32 num_dumped_dwords,
3410                                                    u32 *results_buf_size);
3411
3412 /**
3413  * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3414  *
3415  * @param p_hwfn - HW device data
3416  * @param dump_buf - mcp trace dump buffer, starting from the header.
3417  * @param num_dumped_dwords - number of dwords that were dumped.
3418  * @param results_buf - buffer for printing the mcp trace results.
3419  *
3420  * @return error if the parsing fails, ok otherwise.
3421  */
3422 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3423                                             u32 *dump_buf,
3424                                             u32 num_dumped_dwords,
3425                                             char *results_buf);
3426
3427 /**
3428  * @brief print_mcp_trace_line - Prints MCP Trace results for a single line
3429  *
3430  * @param dump_buf -          mcp trace dump buffer, starting from the header.
3431  * @param num_dumped_bytes -  number of bytes that were dumped.
3432  * @param results_buf -       buffer for printing the mcp trace results.
3433  *
3434  * @return error if the parsing fails, ok otherwise.
3435  */
3436 enum dbg_status qed_print_mcp_trace_line(u8 *dump_buf,
3437                                          u32 num_dumped_bytes,
3438                                          char *results_buf);
3439
3440 /**
3441  * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3442  *      for reg_fifo results (in bytes).
3443  *
3444  * @param p_hwfn - HW device data
3445  * @param dump_buf - reg fifo dump buffer.
3446  * @param num_dumped_dwords - number of dwords that were dumped.
3447  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3448  *      results.
3449  *
3450  * @return error if the parsing fails, ok otherwise.
3451  */
3452 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3453                                                   u32 *dump_buf,
3454                                                   u32 num_dumped_dwords,
3455                                                   u32 *results_buf_size);
3456
3457 /**
3458  * @brief qed_print_reg_fifo_results - Prints reg fifo results
3459  *
3460  * @param p_hwfn - HW device data
3461  * @param dump_buf - reg fifo dump buffer, starting from the header.
3462  * @param num_dumped_dwords - number of dwords that were dumped.
3463  * @param results_buf - buffer for printing the reg fifo results.
3464  *
3465  * @return error if the parsing fails, ok otherwise.
3466  */
3467 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3468                                            u32 *dump_buf,
3469                                            u32 num_dumped_dwords,
3470                                            char *results_buf);
3471
3472 /**
3473  * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3474  *      for igu_fifo results (in bytes).
3475  *
3476  * @param p_hwfn - HW device data
3477  * @param dump_buf - IGU fifo dump buffer.
3478  * @param num_dumped_dwords - number of dwords that were dumped.
3479  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3480  *      results.
3481  *
3482  * @return error if the parsing fails, ok otherwise.
3483  */
3484 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3485                                                   u32 *dump_buf,
3486                                                   u32 num_dumped_dwords,
3487                                                   u32 *results_buf_size);
3488
3489 /**
3490  * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3491  *
3492  * @param p_hwfn - HW device data
3493  * @param dump_buf - IGU fifo dump buffer, starting from the header.
3494  * @param num_dumped_dwords - number of dwords that were dumped.
3495  * @param results_buf - buffer for printing the IGU fifo results.
3496  *
3497  * @return error if the parsing fails, ok otherwise.
3498  */
3499 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3500                                            u32 *dump_buf,
3501                                            u32 num_dumped_dwords,
3502                                            char *results_buf);
3503
3504 /**
3505  * @brief qed_get_protection_override_results_buf_size - Returns the required
3506  *      buffer size for protection override results (in bytes).
3507  *
3508  * @param p_hwfn - HW device data
3509  * @param dump_buf - protection override dump buffer.
3510  * @param num_dumped_dwords - number of dwords that were dumped.
3511  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3512  *      results.
3513  *
3514  * @return error if the parsing fails, ok otherwise.
3515  */
3516 enum dbg_status
3517 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3518                                              u32 *dump_buf,
3519                                              u32 num_dumped_dwords,
3520                                              u32 *results_buf_size);
3521
3522 /**
3523  * @brief qed_print_protection_override_results - Prints protection override
3524  *      results.
3525  *
3526  * @param p_hwfn - HW device data
3527  * @param dump_buf - protection override dump buffer, starting from the header.
3528  * @param num_dumped_dwords - number of dwords that were dumped.
3529  * @param results_buf - buffer for printing the reg fifo results.
3530  *
3531  * @return error if the parsing fails, ok otherwise.
3532  */
3533 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3534                                                       u32 *dump_buf,
3535                                                       u32 num_dumped_dwords,
3536                                                       char *results_buf);
3537
3538 /**
3539  * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3540  *      for FW Asserts results (in bytes).
3541  *
3542  * @param p_hwfn - HW device data
3543  * @param dump_buf - FW Asserts dump buffer.
3544  * @param num_dumped_dwords - number of dwords that were dumped.
3545  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3546  *      results.
3547  *
3548  * @return error if the parsing fails, ok otherwise.
3549  */
3550 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3551                                                     u32 *dump_buf,
3552                                                     u32 num_dumped_dwords,
3553                                                     u32 *results_buf_size);
3554
3555 /**
3556  * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3557  *
3558  * @param p_hwfn - HW device data
3559  * @param dump_buf - FW Asserts dump buffer, starting from the header.
3560  * @param num_dumped_dwords - number of dwords that were dumped.
3561  * @param results_buf - buffer for printing the FW Asserts results.
3562  *
3563  * @return error if the parsing fails, ok otherwise.
3564  */
3565 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3566                                              u32 *dump_buf,
3567                                              u32 num_dumped_dwords,
3568                                              char *results_buf);
3569
3570 /**
3571  * @brief qed_dbg_parse_attn - Parses and prints attention registers values in
3572  * the specified results struct.
3573  *
3574  * @param p_hwfn -  HW device data
3575  * @param results - Pointer to the attention read results
3576  *
3577  * @return error if one of the following holds:
3578  *      - the version wasn't set
3579  * Otherwise, returns ok.
3580  */
3581 enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
3582                                    struct dbg_attn_block_result *results);
3583
3584 /* Debug Bus blocks */
3585 static const u32 dbg_bus_blocks[] = {
3586         0x0000000f,             /* grc, bb, 15 lines */
3587         0x0000000f,             /* grc, k2, 15 lines */
3588         0x00000000,
3589         0x00000000,             /* miscs, bb, 0 lines */
3590         0x00000000,             /* miscs, k2, 0 lines */
3591         0x00000000,
3592         0x00000000,             /* misc, bb, 0 lines */
3593         0x00000000,             /* misc, k2, 0 lines */
3594         0x00000000,
3595         0x00000000,             /* dbu, bb, 0 lines */
3596         0x00000000,             /* dbu, k2, 0 lines */
3597         0x00000000,
3598         0x000f0127,             /* pglue_b, bb, 39 lines */
3599         0x0036012a,             /* pglue_b, k2, 42 lines */
3600         0x00000000,
3601         0x00000000,             /* cnig, bb, 0 lines */
3602         0x00120102,             /* cnig, k2, 2 lines */
3603         0x00000000,
3604         0x00000000,             /* cpmu, bb, 0 lines */
3605         0x00000000,             /* cpmu, k2, 0 lines */
3606         0x00000000,
3607         0x00000001,             /* ncsi, bb, 1 lines */
3608         0x00000001,             /* ncsi, k2, 1 lines */
3609         0x00000000,
3610         0x00000000,             /* opte, bb, 0 lines */
3611         0x00000000,             /* opte, k2, 0 lines */
3612         0x00000000,
3613         0x00600085,             /* bmb, bb, 133 lines */
3614         0x00600085,             /* bmb, k2, 133 lines */
3615         0x00000000,
3616         0x00000000,             /* pcie, bb, 0 lines */
3617         0x00e50033,             /* pcie, k2, 51 lines */
3618         0x00000000,
3619         0x00000000,             /* mcp, bb, 0 lines */
3620         0x00000000,             /* mcp, k2, 0 lines */
3621         0x00000000,
3622         0x01180009,             /* mcp2, bb, 9 lines */
3623         0x01180009,             /* mcp2, k2, 9 lines */
3624         0x00000000,
3625         0x01210104,             /* pswhst, bb, 4 lines */
3626         0x01210104,             /* pswhst, k2, 4 lines */
3627         0x00000000,
3628         0x01250103,             /* pswhst2, bb, 3 lines */
3629         0x01250103,             /* pswhst2, k2, 3 lines */
3630         0x00000000,
3631         0x00340101,             /* pswrd, bb, 1 lines */
3632         0x00340101,             /* pswrd, k2, 1 lines */
3633         0x00000000,
3634         0x01280119,             /* pswrd2, bb, 25 lines */
3635         0x01280119,             /* pswrd2, k2, 25 lines */
3636         0x00000000,
3637         0x01410109,             /* pswwr, bb, 9 lines */
3638         0x01410109,             /* pswwr, k2, 9 lines */
3639         0x00000000,
3640         0x00000000,             /* pswwr2, bb, 0 lines */
3641         0x00000000,             /* pswwr2, k2, 0 lines */
3642         0x00000000,
3643         0x001c0001,             /* pswrq, bb, 1 lines */
3644         0x001c0001,             /* pswrq, k2, 1 lines */
3645         0x00000000,
3646         0x014a0015,             /* pswrq2, bb, 21 lines */
3647         0x014a0015,             /* pswrq2, k2, 21 lines */
3648         0x00000000,
3649         0x00000000,             /* pglcs, bb, 0 lines */
3650         0x00120006,             /* pglcs, k2, 6 lines */
3651         0x00000000,
3652         0x00100001,             /* dmae, bb, 1 lines */
3653         0x00100001,             /* dmae, k2, 1 lines */
3654         0x00000000,
3655         0x015f0105,             /* ptu, bb, 5 lines */
3656         0x015f0105,             /* ptu, k2, 5 lines */
3657         0x00000000,
3658         0x01640120,             /* tcm, bb, 32 lines */
3659         0x01640120,             /* tcm, k2, 32 lines */
3660         0x00000000,
3661         0x01640120,             /* mcm, bb, 32 lines */
3662         0x01640120,             /* mcm, k2, 32 lines */
3663         0x00000000,
3664         0x01640120,             /* ucm, bb, 32 lines */
3665         0x01640120,             /* ucm, k2, 32 lines */
3666         0x00000000,
3667         0x01640120,             /* xcm, bb, 32 lines */
3668         0x01640120,             /* xcm, k2, 32 lines */
3669         0x00000000,
3670         0x01640120,             /* ycm, bb, 32 lines */
3671         0x01640120,             /* ycm, k2, 32 lines */
3672         0x00000000,
3673         0x01640120,             /* pcm, bb, 32 lines */
3674         0x01640120,             /* pcm, k2, 32 lines */
3675         0x00000000,
3676         0x01840062,             /* qm, bb, 98 lines */
3677         0x01840062,             /* qm, k2, 98 lines */
3678         0x00000000,
3679         0x01e60021,             /* tm, bb, 33 lines */
3680         0x01e60021,             /* tm, k2, 33 lines */
3681         0x00000000,
3682         0x02070107,             /* dorq, bb, 7 lines */
3683         0x02070107,             /* dorq, k2, 7 lines */
3684         0x00000000,
3685         0x00600185,             /* brb, bb, 133 lines */
3686         0x00600185,             /* brb, k2, 133 lines */
3687         0x00000000,
3688         0x020e0019,             /* src, bb, 25 lines */
3689         0x020c001a,             /* src, k2, 26 lines */
3690         0x00000000,
3691         0x02270104,             /* prs, bb, 4 lines */
3692         0x02270104,             /* prs, k2, 4 lines */
3693         0x00000000,
3694         0x022b0133,             /* tsdm, bb, 51 lines */
3695         0x022b0133,             /* tsdm, k2, 51 lines */
3696         0x00000000,
3697         0x022b0133,             /* msdm, bb, 51 lines */
3698         0x022b0133,             /* msdm, k2, 51 lines */
3699         0x00000000,
3700         0x022b0133,             /* usdm, bb, 51 lines */
3701         0x022b0133,             /* usdm, k2, 51 lines */
3702         0x00000000,
3703         0x022b0133,             /* xsdm, bb, 51 lines */
3704         0x022b0133,             /* xsdm, k2, 51 lines */
3705         0x00000000,
3706         0x022b0133,             /* ysdm, bb, 51 lines */
3707         0x022b0133,             /* ysdm, k2, 51 lines */
3708         0x00000000,
3709         0x022b0133,             /* psdm, bb, 51 lines */
3710         0x022b0133,             /* psdm, k2, 51 lines */
3711         0x00000000,
3712         0x025e010c,             /* tsem, bb, 12 lines */
3713         0x025e010c,             /* tsem, k2, 12 lines */
3714         0x00000000,
3715         0x025e010c,             /* msem, bb, 12 lines */
3716         0x025e010c,             /* msem, k2, 12 lines */
3717         0x00000000,
3718         0x025e010c,             /* usem, bb, 12 lines */
3719         0x025e010c,             /* usem, k2, 12 lines */
3720         0x00000000,
3721         0x025e010c,             /* xsem, bb, 12 lines */
3722         0x025e010c,             /* xsem, k2, 12 lines */
3723         0x00000000,
3724         0x025e010c,             /* ysem, bb, 12 lines */
3725         0x025e010c,             /* ysem, k2, 12 lines */
3726         0x00000000,
3727         0x025e010c,             /* psem, bb, 12 lines */
3728         0x025e010c,             /* psem, k2, 12 lines */
3729         0x00000000,
3730         0x026a000d,             /* rss, bb, 13 lines */
3731         0x026a000d,             /* rss, k2, 13 lines */
3732         0x00000000,
3733         0x02770106,             /* tmld, bb, 6 lines */
3734         0x02770106,             /* tmld, k2, 6 lines */
3735         0x00000000,
3736         0x027d0106,             /* muld, bb, 6 lines */
3737         0x027d0106,             /* muld, k2, 6 lines */
3738         0x00000000,
3739         0x02770005,             /* yuld, bb, 5 lines */
3740         0x02770005,             /* yuld, k2, 5 lines */
3741         0x00000000,
3742         0x02830107,             /* xyld, bb, 7 lines */
3743         0x027d0107,             /* xyld, k2, 7 lines */
3744         0x00000000,
3745         0x00000000,             /* ptld, bb, 0 lines */
3746         0x00000000,             /* ptld, k2, 0 lines */
3747         0x00000000,
3748         0x00000000,             /* ypld, bb, 0 lines */
3749         0x00000000,             /* ypld, k2, 0 lines */
3750         0x00000000,
3751         0x028a010e,             /* prm, bb, 14 lines */
3752         0x02980110,             /* prm, k2, 16 lines */
3753         0x00000000,
3754         0x02a8000d,             /* pbf_pb1, bb, 13 lines */
3755         0x02a8000d,             /* pbf_pb1, k2, 13 lines */
3756         0x00000000,
3757         0x02a8000d,             /* pbf_pb2, bb, 13 lines */
3758         0x02a8000d,             /* pbf_pb2, k2, 13 lines */
3759         0x00000000,
3760         0x02a8000d,             /* rpb, bb, 13 lines */
3761         0x02a8000d,             /* rpb, k2, 13 lines */
3762         0x00000000,
3763         0x00600185,             /* btb, bb, 133 lines */
3764         0x00600185,             /* btb, k2, 133 lines */
3765         0x00000000,
3766         0x02b50117,             /* pbf, bb, 23 lines */
3767         0x02b50117,             /* pbf, k2, 23 lines */
3768         0x00000000,
3769         0x02cc0006,             /* rdif, bb, 6 lines */
3770         0x02cc0006,             /* rdif, k2, 6 lines */
3771         0x00000000,
3772         0x02d20006,             /* tdif, bb, 6 lines */
3773         0x02d20006,             /* tdif, k2, 6 lines */
3774         0x00000000,
3775         0x02d80003,             /* cdu, bb, 3 lines */
3776         0x02db000e,             /* cdu, k2, 14 lines */
3777         0x00000000,
3778         0x02e9010d,             /* ccfc, bb, 13 lines */
3779         0x02f60117,             /* ccfc, k2, 23 lines */
3780         0x00000000,
3781         0x02e9010d,             /* tcfc, bb, 13 lines */
3782         0x02f60117,             /* tcfc, k2, 23 lines */
3783         0x00000000,
3784         0x030d0133,             /* igu, bb, 51 lines */
3785         0x030d0133,             /* igu, k2, 51 lines */
3786         0x00000000,
3787         0x03400106,             /* cau, bb, 6 lines */
3788         0x03400106,             /* cau, k2, 6 lines */
3789         0x00000000,
3790         0x00000000,             /* rgfs, bb, 0 lines */
3791         0x00000000,             /* rgfs, k2, 0 lines */
3792         0x00000000,
3793         0x00000000,             /* rgsrc, bb, 0 lines */
3794         0x00000000,             /* rgsrc, k2, 0 lines */
3795         0x00000000,
3796         0x00000000,             /* tgfs, bb, 0 lines */
3797         0x00000000,             /* tgfs, k2, 0 lines */
3798         0x00000000,
3799         0x00000000,             /* tgsrc, bb, 0 lines */
3800         0x00000000,             /* tgsrc, k2, 0 lines */
3801         0x00000000,
3802         0x00000000,             /* umac, bb, 0 lines */
3803         0x00120006,             /* umac, k2, 6 lines */
3804         0x00000000,
3805         0x00000000,             /* xmac, bb, 0 lines */
3806         0x00000000,             /* xmac, k2, 0 lines */
3807         0x00000000,
3808         0x00000000,             /* dbg, bb, 0 lines */
3809         0x00000000,             /* dbg, k2, 0 lines */
3810         0x00000000,
3811         0x0346012b,             /* nig, bb, 43 lines */
3812         0x0346011d,             /* nig, k2, 29 lines */
3813         0x00000000,
3814         0x00000000,             /* wol, bb, 0 lines */
3815         0x001c0002,             /* wol, k2, 2 lines */
3816         0x00000000,
3817         0x00000000,             /* bmbn, bb, 0 lines */
3818         0x00210008,             /* bmbn, k2, 8 lines */
3819         0x00000000,
3820         0x00000000,             /* ipc, bb, 0 lines */
3821         0x00000000,             /* ipc, k2, 0 lines */
3822         0x00000000,
3823         0x00000000,             /* nwm, bb, 0 lines */
3824         0x0371000b,             /* nwm, k2, 11 lines */
3825         0x00000000,
3826         0x00000000,             /* nws, bb, 0 lines */
3827         0x037c0009,             /* nws, k2, 9 lines */
3828         0x00000000,
3829         0x00000000,             /* ms, bb, 0 lines */
3830         0x00120004,             /* ms, k2, 4 lines */
3831         0x00000000,
3832         0x00000000,             /* phy_pcie, bb, 0 lines */
3833         0x00e5001a,             /* phy_pcie, k2, 26 lines */
3834         0x00000000,
3835         0x00000000,             /* led, bb, 0 lines */
3836         0x00000000,             /* led, k2, 0 lines */
3837         0x00000000,
3838         0x00000000,             /* avs_wrap, bb, 0 lines */
3839         0x00000000,             /* avs_wrap, k2, 0 lines */
3840         0x00000000,
3841         0x00000000,             /* bar0_map, bb, 0 lines */
3842         0x00000000,             /* bar0_map, k2, 0 lines */
3843         0x00000000,
3844         0x00000000,             /* bar0_map, bb, 0 lines */
3845         0x00000000,             /* bar0_map, k2, 0 lines */
3846         0x00000000,
3847 };
3848
3849 /* Win 2 */
3850 #define GTT_BAR0_MAP_REG_IGU_CMD        0x00f000UL
3851
3852 /* Win 3 */
3853 #define GTT_BAR0_MAP_REG_TSDM_RAM       0x010000UL
3854
3855 /* Win 4 */
3856 #define GTT_BAR0_MAP_REG_MSDM_RAM       0x011000UL
3857
3858 /* Win 5 */
3859 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024  0x012000UL
3860
3861 /* Win 6 */
3862 #define GTT_BAR0_MAP_REG_USDM_RAM       0x013000UL
3863
3864 /* Win 7 */
3865 #define GTT_BAR0_MAP_REG_USDM_RAM_1024  0x014000UL
3866
3867 /* Win 8 */
3868 #define GTT_BAR0_MAP_REG_USDM_RAM_2048  0x015000UL
3869
3870 /* Win 9 */
3871 #define GTT_BAR0_MAP_REG_XSDM_RAM       0x016000UL
3872
3873 /* Win 10 */
3874 #define GTT_BAR0_MAP_REG_YSDM_RAM       0x017000UL
3875
3876 /* Win 11 */
3877 #define GTT_BAR0_MAP_REG_PSDM_RAM       0x018000UL
3878
3879 /**
3880  * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
3881  *
3882  * Returns the required host memory size in 4KB units.
3883  * Must be called before all QM init HSI functions.
3884  *
3885  * @param num_pf_cids - number of connections used by this PF
3886  * @param num_vf_cids - number of connections used by VFs of this PF
3887  * @param num_tids - number of tasks used by this PF
3888  * @param num_pf_pqs - number of PQs used by this PF
3889  * @param num_vf_pqs - number of PQs used by VFs of this PF
3890  *
3891  * @return The required host memory size in 4KB units.
3892  */
3893 u32 qed_qm_pf_mem_size(u32 num_pf_cids,
3894                        u32 num_vf_cids,
3895                        u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
3896
3897 struct qed_qm_common_rt_init_params {
3898         u8 max_ports_per_engine;
3899         u8 max_phys_tcs_per_port;
3900         bool pf_rl_en;
3901         bool pf_wfq_en;
3902         bool vport_rl_en;
3903         bool vport_wfq_en;
3904         struct init_qm_port_params *port_params;
3905 };
3906
3907 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
3908                           struct qed_qm_common_rt_init_params *p_params);
3909
3910 struct qed_qm_pf_rt_init_params {
3911         u8 port_id;
3912         u8 pf_id;
3913         u8 max_phys_tcs_per_port;
3914         bool is_pf_loading;
3915         u32 num_pf_cids;
3916         u32 num_vf_cids;
3917         u32 num_tids;
3918         u16 start_pq;
3919         u16 num_pf_pqs;
3920         u16 num_vf_pqs;
3921         u8 start_vport;
3922         u8 num_vports;
3923         u16 pf_wfq;
3924         u32 pf_rl;
3925         u32 link_speed;
3926         struct init_qm_pq_params *pq_params;
3927         struct init_qm_vport_params *vport_params;
3928 };
3929
3930 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
3931         struct qed_ptt *p_ptt,
3932         struct qed_qm_pf_rt_init_params *p_params);
3933
3934 /**
3935  * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
3936  *
3937  * @param p_hwfn
3938  * @param p_ptt - ptt window used for writing the registers
3939  * @param pf_id - PF ID
3940  * @param pf_wfq - WFQ weight. Must be non-zero.
3941  *
3942  * @return 0 on success, -1 on error.
3943  */
3944 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
3945                     struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
3946
3947 /**
3948  * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
3949  *
3950  * @param p_hwfn
3951  * @param p_ptt - ptt window used for writing the registers
3952  * @param pf_id - PF ID
3953  * @param pf_rl - rate limit in Mb/sec units
3954  *
3955  * @return 0 on success, -1 on error.
3956  */
3957 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
3958                    struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
3959
3960 /**
3961  * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
3962  *
3963  * @param p_hwfn
3964  * @param p_ptt - ptt window used for writing the registers
3965  * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
3966  *        with the VPORT for each TC. This array is filled by
3967  *        qed_qm_pf_rt_init
3968  * @param vport_wfq - WFQ weight. Must be non-zero.
3969  *
3970  * @return 0 on success, -1 on error.
3971  */
3972 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
3973                        struct qed_ptt *p_ptt,
3974                        u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
3975
3976 /**
3977  * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT
3978  *
3979  * @param p_hwfn
3980  * @param p_ptt - ptt window used for writing the registers
3981  * @param vport_id - VPORT ID
3982  * @param vport_rl - rate limit in Mb/sec units
3983  * @param link_speed - link speed in Mbps.
3984  *
3985  * @return 0 on success, -1 on error.
3986  */
3987 int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
3988                       struct qed_ptt *p_ptt,
3989                       u8 vport_id, u32 vport_rl, u32 link_speed);
3990
3991 /**
3992  * @brief qed_send_qm_stop_cmd  Sends a stop command to the QM
3993  *
3994  * @param p_hwfn
3995  * @param p_ptt
3996  * @param is_release_cmd - true for release, false for stop.
3997  * @param is_tx_pq - true for Tx PQs, false for Other PQs.
3998  * @param start_pq - first PQ ID to stop
3999  * @param num_pqs - Number of PQs to stop, starting from start_pq.
4000  *
4001  * @return bool, true if successful, false if timeout occurred while waiting for
4002  *      QM command done.
4003  */
4004 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
4005                           struct qed_ptt *p_ptt,
4006                           bool is_release_cmd,
4007                           bool is_tx_pq, u16 start_pq, u16 num_pqs);
4008
4009 /**
4010  * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
4011  *
4012  * @param p_hwfn
4013  * @param p_ptt - ptt window used for writing the registers.
4014  * @param dest_port - vxlan destination udp port.
4015  */
4016 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
4017                              struct qed_ptt *p_ptt, u16 dest_port);
4018
4019 /**
4020  * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
4021  *
4022  * @param p_hwfn
4023  * @param p_ptt - ptt window used for writing the registers.
4024  * @param vxlan_enable - vxlan enable flag.
4025  */
4026 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
4027                           struct qed_ptt *p_ptt, bool vxlan_enable);
4028
4029 /**
4030  * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
4031  *
4032  * @param p_hwfn
4033  * @param p_ptt - ptt window used for writing the registers.
4034  * @param eth_gre_enable - eth GRE enable enable flag.
4035  * @param ip_gre_enable - IP GRE enable enable flag.
4036  */
4037 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
4038                         struct qed_ptt *p_ptt,
4039                         bool eth_gre_enable, bool ip_gre_enable);
4040
4041 /**
4042  * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
4043  *
4044  * @param p_hwfn
4045  * @param p_ptt - ptt window used for writing the registers.
4046  * @param dest_port - geneve destination udp port.
4047  */
4048 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
4049                               struct qed_ptt *p_ptt, u16 dest_port);
4050
4051 /**
4052  * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
4053  *
4054  * @param p_ptt - ptt window used for writing the registers.
4055  * @param eth_geneve_enable - eth GENEVE enable enable flag.
4056  * @param ip_geneve_enable - IP GENEVE enable enable flag.
4057  */
4058 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
4059                            struct qed_ptt *p_ptt,
4060                            bool eth_geneve_enable, bool ip_geneve_enable);
4061
4062 void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
4063                                 struct qed_ptt *p_ptt, bool enable);
4064
4065 /**
4066  * @brief qed_gft_disable - Disable GFT
4067  *
4068  * @param p_hwfn
4069  * @param p_ptt - ptt window used for writing the registers.
4070  * @param pf_id - pf on which to disable GFT.
4071  */
4072 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id);
4073
4074 /**
4075  * @brief qed_gft_config - Enable and configure HW for GFT
4076  *
4077  * @param p_hwfn
4078  * @param p_ptt - ptt window used for writing the registers.
4079  * @param pf_id - pf on which to enable GFT.
4080  * @param tcp - set profile tcp packets.
4081  * @param udp - set profile udp  packet.
4082  * @param ipv4 - set profile ipv4 packet.
4083  * @param ipv6 - set profile ipv6 packet.
4084  * @param profile_type - define packet same fields. Use enum gft_profile_type.
4085  */
4086 void qed_gft_config(struct qed_hwfn *p_hwfn,
4087                     struct qed_ptt *p_ptt,
4088                     u16 pf_id,
4089                     bool tcp,
4090                     bool udp,
4091                     bool ipv4, bool ipv6, enum gft_profile_type profile_type);
4092
4093 /**
4094  * @brief qed_enable_context_validation - Enable and configure context
4095  *      validation.
4096  *
4097  * @param p_hwfn
4098  * @param p_ptt - ptt window used for writing the registers.
4099  */
4100 void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
4101                                    struct qed_ptt *p_ptt);
4102
4103 /**
4104  * @brief qed_calc_session_ctx_validation - Calcualte validation byte for
4105  *      session context.
4106  *
4107  * @param p_ctx_mem - pointer to context memory.
4108  * @param ctx_size - context size.
4109  * @param ctx_type - context type.
4110  * @param cid - context cid.
4111  */
4112 void qed_calc_session_ctx_validation(void *p_ctx_mem,
4113                                      u16 ctx_size, u8 ctx_type, u32 cid);
4114
4115 /**
4116  * @brief qed_calc_task_ctx_validation - Calcualte validation byte for task
4117  *      context.
4118  *
4119  * @param p_ctx_mem - pointer to context memory.
4120  * @param ctx_size - context size.
4121  * @param ctx_type - context type.
4122  * @param tid - context tid.
4123  */
4124 void qed_calc_task_ctx_validation(void *p_ctx_mem,
4125                                   u16 ctx_size, u8 ctx_type, u32 tid);
4126
4127 /**
4128  * @brief qed_memset_session_ctx - Memset session context to 0 while
4129  *      preserving validation bytes.
4130  *
4131  * @param p_hwfn -
4132  * @param p_ctx_mem - pointer to context memory.
4133  * @param ctx_size - size to initialzie.
4134  * @param ctx_type - context type.
4135  */
4136 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4137
4138 /**
4139  * @brief qed_memset_task_ctx - Memset task context to 0 while preserving
4140  *      validation bytes.
4141  *
4142  * @param p_ctx_mem - pointer to context memory.
4143  * @param ctx_size - size to initialzie.
4144  * @param ctx_type - context type.
4145  */
4146 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4147
4148 #define NUM_STORMS 6
4149
4150 /**
4151  * @brief qed_set_rdma_error_level - Sets the RDMA assert level.
4152  *                                   If the severity of the error will be
4153  *                                   above the level, the FW will assert.
4154  * @param p_hwfn - HW device data
4155  * @param p_ptt - ptt window used for writing the registers
4156  * @param assert_level - An array of assert levels for each storm.
4157  *
4158  */
4159 void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
4160                               struct qed_ptt *p_ptt,
4161                               u8 assert_level[NUM_STORMS]);
4162
4163 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
4164 #define YSTORM_FLOW_CONTROL_MODE_OFFSET                 (IRO[0].base)
4165 #define YSTORM_FLOW_CONTROL_MODE_SIZE                   (IRO[0].size)
4166
4167 /* Tstorm port statistics */
4168 #define TSTORM_PORT_STAT_OFFSET(port_id) \
4169         (IRO[1].base + ((port_id) * IRO[1].m1))
4170 #define TSTORM_PORT_STAT_SIZE                           (IRO[1].size)
4171
4172 /* Tstorm ll2 port statistics */
4173 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
4174         (IRO[2].base + ((port_id) * IRO[2].m1))
4175 #define TSTORM_LL2_PORT_STAT_SIZE                       (IRO[2].size)
4176
4177 /* Ustorm VF-PF Channel ready flag */
4178 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
4179         (IRO[3].base + ((vf_id) * IRO[3].m1))
4180 #define USTORM_VF_PF_CHANNEL_READY_SIZE                 (IRO[3].size)
4181
4182 /* Ustorm Final flr cleanup ack */
4183 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
4184         (IRO[4].base + ((pf_id) * IRO[4].m1))
4185 #define USTORM_FLR_FINAL_ACK_SIZE                       (IRO[4].size)
4186
4187 /* Ustorm Event ring consumer */
4188 #define USTORM_EQE_CONS_OFFSET(pf_id) \
4189         (IRO[5].base + ((pf_id) * IRO[5].m1))
4190 #define USTORM_EQE_CONS_SIZE                            (IRO[5].size)
4191
4192 /* Ustorm eth queue zone */
4193 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
4194         (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
4195 #define USTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[6].size)
4196
4197 /* Ustorm Common Queue ring consumer */
4198 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
4199         (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
4200 #define USTORM_COMMON_QUEUE_CONS_SIZE                   (IRO[7].size)
4201
4202 /* Xstorm Integration Test Data */
4203 #define XSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[8].base)
4204 #define XSTORM_INTEG_TEST_DATA_SIZE                     (IRO[8].size)
4205
4206 /* Ystorm Integration Test Data */
4207 #define YSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[9].base)
4208 #define YSTORM_INTEG_TEST_DATA_SIZE                     (IRO[9].size)
4209
4210 /* Pstorm Integration Test Data */
4211 #define PSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[10].base)
4212 #define PSTORM_INTEG_TEST_DATA_SIZE                     (IRO[10].size)
4213
4214 /* Tstorm Integration Test Data */
4215 #define TSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[11].base)
4216 #define TSTORM_INTEG_TEST_DATA_SIZE                     (IRO[11].size)
4217
4218 /* Mstorm Integration Test Data */
4219 #define MSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[12].base)
4220 #define MSTORM_INTEG_TEST_DATA_SIZE                     (IRO[12].size)
4221
4222 /* Ustorm Integration Test Data */
4223 #define USTORM_INTEG_TEST_DATA_OFFSET                   (IRO[13].base)
4224 #define USTORM_INTEG_TEST_DATA_SIZE                     (IRO[13].size)
4225
4226 /* Tstorm producers */
4227 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
4228         (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
4229 #define TSTORM_LL2_RX_PRODS_SIZE                        (IRO[14].size)
4230
4231 /* Tstorm LightL2 queue statistics */
4232 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4233         (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
4234 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE             (IRO[15].size)
4235
4236 /* Ustorm LiteL2 queue statistics */
4237 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4238         (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
4239 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE             (IRO[16].size)
4240
4241 /* Pstorm LiteL2 queue statistics */
4242 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
4243         (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
4244 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE             (IRO[17].size)
4245
4246 /* Mstorm queue statistics */
4247 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4248         (IRO[18].base + ((stat_counter_id) * IRO[18].m1))
4249 #define MSTORM_QUEUE_STAT_SIZE                          (IRO[18].size)
4250
4251 /* Mstorm ETH PF queues producers */
4252 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
4253         (IRO[19].base + ((queue_id) * IRO[19].m1))
4254 #define MSTORM_ETH_PF_PRODS_SIZE                        (IRO[19].size)
4255
4256 /* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
4257  * mode.
4258  */
4259 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
4260         (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
4261 #define MSTORM_ETH_VF_PRODS_SIZE                        (IRO[20].size)
4262
4263 /* TPA agregation timeout in us resolution (on ASIC) */
4264 #define MSTORM_TPA_TIMEOUT_US_OFFSET                    (IRO[21].base)
4265 #define MSTORM_TPA_TIMEOUT_US_SIZE                      (IRO[21].size)
4266
4267 /* Mstorm pf statistics */
4268 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4269         (IRO[22].base + ((pf_id) * IRO[22].m1))
4270 #define MSTORM_ETH_PF_STAT_SIZE                         (IRO[22].size)
4271
4272 /* Ustorm queue statistics */
4273 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4274         (IRO[23].base + ((stat_counter_id) * IRO[23].m1))
4275 #define USTORM_QUEUE_STAT_SIZE                          (IRO[23].size)
4276
4277 /* Ustorm pf statistics */
4278 #define USTORM_ETH_PF_STAT_OFFSET(pf_id)\
4279         (IRO[24].base + ((pf_id) * IRO[24].m1))
4280 #define USTORM_ETH_PF_STAT_SIZE                         (IRO[24].size)
4281
4282 /* Pstorm queue statistics */
4283 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4284         (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
4285 #define PSTORM_QUEUE_STAT_SIZE                          (IRO[25].size)
4286
4287 /* Pstorm pf statistics */
4288 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4289         (IRO[26].base + ((pf_id) * IRO[26].m1))
4290 #define PSTORM_ETH_PF_STAT_SIZE                         (IRO[26].size)
4291
4292 /* Control frame's EthType configuration for TX control frame security */
4293 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \
4294         (IRO[27].base + ((eth_type_id) * IRO[27].m1))
4295 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE                   (IRO[27].size)
4296
4297 /* Tstorm last parser message */
4298 #define TSTORM_ETH_PRS_INPUT_OFFSET                     (IRO[28].base)
4299 #define TSTORM_ETH_PRS_INPUT_SIZE                       (IRO[28].size)
4300
4301 /* Tstorm Eth limit Rx rate */
4302 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
4303         (IRO[29].base + ((pf_id) * IRO[29].m1))
4304 #define ETH_RX_RATE_LIMIT_SIZE                          (IRO[29].size)
4305
4306 /* Xstorm queue zone */
4307 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
4308         (IRO[30].base + ((queue_id) * IRO[30].m1))
4309 #define XSTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[30].size)
4310
4311 /* Ystorm cqe producer */
4312 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4313         (IRO[31].base + ((rss_id) * IRO[31].m1))
4314 #define YSTORM_TOE_CQ_PROD_SIZE                         (IRO[31].size)
4315
4316 /* Ustorm cqe producer */
4317 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4318         (IRO[32].base + ((rss_id) * IRO[32].m1))
4319 #define USTORM_TOE_CQ_PROD_SIZE                         (IRO[32].size)
4320
4321 /* Ustorm grq producer */
4322 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
4323         (IRO[33].base + ((pf_id) * IRO[33].m1))
4324 #define USTORM_TOE_GRQ_PROD_SIZE                        (IRO[33].size)
4325
4326 /* Tstorm cmdq-cons of given command queue-id */
4327 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
4328         (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
4329 #define TSTORM_SCSI_CMDQ_CONS_SIZE                      (IRO[34].size)
4330
4331 /* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
4332  * BDqueue-id.
4333  */
4334 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
4335         (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
4336 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE                   (IRO[35].size)
4337
4338 /* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
4339 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
4340         (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
4341 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE                   (IRO[36].size)
4342
4343 /* Tstorm iSCSI RX stats */
4344 #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4345         (IRO[37].base + ((pf_id) * IRO[37].m1))
4346 #define TSTORM_ISCSI_RX_STATS_SIZE                      (IRO[37].size)
4347
4348 /* Mstorm iSCSI RX stats */
4349 #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4350         (IRO[38].base + ((pf_id) * IRO[38].m1))
4351 #define MSTORM_ISCSI_RX_STATS_SIZE                      (IRO[38].size)
4352
4353 /* Ustorm iSCSI RX stats */
4354 #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4355         (IRO[39].base + ((pf_id) * IRO[39].m1))
4356 #define USTORM_ISCSI_RX_STATS_SIZE                      (IRO[39].size)
4357
4358 /* Xstorm iSCSI TX stats */
4359 #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4360         (IRO[40].base + ((pf_id) * IRO[40].m1))
4361 #define XSTORM_ISCSI_TX_STATS_SIZE                      (IRO[40].size)
4362
4363 /* Ystorm iSCSI TX stats */
4364 #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4365         (IRO[41].base + ((pf_id) * IRO[41].m1))
4366 #define YSTORM_ISCSI_TX_STATS_SIZE                      (IRO[41].size)
4367
4368 /* Pstorm iSCSI TX stats */
4369 #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4370         (IRO[42].base + ((pf_id) * IRO[42].m1))
4371 #define PSTORM_ISCSI_TX_STATS_SIZE                      (IRO[42].size)
4372
4373 /* Tstorm FCoE RX stats */
4374 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
4375         (IRO[43].base + ((pf_id) * IRO[43].m1))
4376 #define TSTORM_FCOE_RX_STATS_SIZE                       (IRO[43].size)
4377
4378 /* Pstorm FCoE TX stats */
4379 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
4380         (IRO[44].base + ((pf_id) * IRO[44].m1))
4381 #define PSTORM_FCOE_TX_STATS_SIZE                       (IRO[44].size)
4382
4383 /* Pstorm RDMA queue statistics */
4384 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4385         (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
4386 #define PSTORM_RDMA_QUEUE_STAT_SIZE                     (IRO[45].size)
4387
4388 /* Tstorm RDMA queue statistics */
4389 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4390         (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
4391 #define TSTORM_RDMA_QUEUE_STAT_SIZE                     (IRO[46].size)
4392
4393 /* Xstorm error level for assert */
4394 #define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4395         (IRO[47].base + ((pf_id) * IRO[47].m1))
4396 #define XSTORM_RDMA_ASSERT_LEVEL_SIZE                   (IRO[47].size)
4397
4398 /* Ystorm error level for assert */
4399 #define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4400         (IRO[48].base + ((pf_id) * IRO[48].m1))
4401 #define YSTORM_RDMA_ASSERT_LEVEL_SIZE                   (IRO[48].size)
4402
4403 /* Pstorm error level for assert */
4404 #define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4405         (IRO[49].base + ((pf_id) * IRO[49].m1))
4406 #define PSTORM_RDMA_ASSERT_LEVEL_SIZE                   (IRO[49].size)
4407
4408 /* Tstorm error level for assert */
4409 #define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4410         (IRO[50].base + ((pf_id) * IRO[50].m1))
4411 #define TSTORM_RDMA_ASSERT_LEVEL_SIZE                   (IRO[50].size)
4412
4413 /* Mstorm error level for assert */
4414 #define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4415         (IRO[51].base + ((pf_id) * IRO[51].m1))
4416 #define MSTORM_RDMA_ASSERT_LEVEL_SIZE                   (IRO[51].size)
4417
4418 /* Ustorm error level for assert */
4419 #define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4420         (IRO[52].base + ((pf_id) * IRO[52].m1))
4421 #define USTORM_RDMA_ASSERT_LEVEL_SIZE                   (IRO[52].size)
4422
4423 /* Xstorm iWARP rxmit stats */
4424 #define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \
4425         (IRO[53].base + ((pf_id) * IRO[53].m1))
4426 #define XSTORM_IWARP_RXMIT_STATS_SIZE                   (IRO[53].size)
4427
4428 /* Tstorm RoCE Event Statistics */
4429 #define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
4430         (IRO[54].base + ((roce_pf_id) * IRO[54].m1))
4431 #define TSTORM_ROCE_EVENTS_STAT_SIZE                    (IRO[54].size)
4432
4433 /* DCQCN Received Statistics */
4434 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) \
4435         (IRO[55].base + ((roce_pf_id) * IRO[55].m1))
4436 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE           (IRO[55].size)
4437
4438 /* RoCE Error Statistics */
4439 #define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \
4440         (IRO[56].base + ((roce_pf_id) * IRO[56].m1))
4441 #define YSTORM_ROCE_ERROR_STATS_SIZE                    (IRO[56].size)
4442
4443 /* DCQCN Sent Statistics */
4444 #define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
4445         (IRO[57].base + ((roce_pf_id) * IRO[57].m1))
4446 #define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE               (IRO[57].size)
4447
4448 /* RoCE CQEs Statistics */
4449 #define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \
4450         (IRO[58].base + ((roce_pf_id) * IRO[58].m1))
4451 #define USTORM_ROCE_CQE_STATS_SIZE                      (IRO[58].size)
4452
4453 static const struct iro iro_arr[59] = {
4454         {0x0, 0x0, 0x0, 0x0, 0x8},
4455         {0x4cb8, 0x88, 0x0, 0x0, 0x88},
4456         {0x6530, 0x20, 0x0, 0x0, 0x20},
4457         {0xb00, 0x8, 0x0, 0x0, 0x4},
4458         {0xa80, 0x8, 0x0, 0x0, 0x4},
4459         {0x0, 0x8, 0x0, 0x0, 0x2},
4460         {0x80, 0x8, 0x0, 0x0, 0x4},
4461         {0x84, 0x8, 0x0, 0x0, 0x2},
4462         {0x4c48, 0x0, 0x0, 0x0, 0x78},
4463         {0x3e38, 0x0, 0x0, 0x0, 0x78},
4464         {0x2b78, 0x0, 0x0, 0x0, 0x78},
4465         {0x4c40, 0x0, 0x0, 0x0, 0x78},
4466         {0x4998, 0x0, 0x0, 0x0, 0x78},
4467         {0x7f50, 0x0, 0x0, 0x0, 0x78},
4468         {0xa28, 0x8, 0x0, 0x0, 0x8},
4469         {0x6210, 0x10, 0x0, 0x0, 0x10},
4470         {0xb820, 0x30, 0x0, 0x0, 0x30},
4471         {0x96c0, 0x30, 0x0, 0x0, 0x30},
4472         {0x4b68, 0x80, 0x0, 0x0, 0x40},
4473         {0x1f8, 0x4, 0x0, 0x0, 0x4},
4474         {0x53a8, 0x80, 0x4, 0x0, 0x4},
4475         {0xc7d0, 0x0, 0x0, 0x0, 0x4},
4476         {0x4ba8, 0x80, 0x0, 0x0, 0x20},
4477         {0x8158, 0x40, 0x0, 0x0, 0x30},
4478         {0xe770, 0x60, 0x0, 0x0, 0x60},
4479         {0x2d10, 0x80, 0x0, 0x0, 0x38},
4480         {0xf2b8, 0x78, 0x0, 0x0, 0x78},
4481         {0x1f8, 0x4, 0x0, 0x0, 0x4},
4482         {0xaf20, 0x0, 0x0, 0x0, 0xf0},
4483         {0xb010, 0x8, 0x0, 0x0, 0x8},
4484         {0x1f8, 0x8, 0x0, 0x0, 0x8},
4485         {0xac0, 0x8, 0x0, 0x0, 0x8},
4486         {0x2578, 0x8, 0x0, 0x0, 0x8},
4487         {0x24f8, 0x8, 0x0, 0x0, 0x8},
4488         {0x0, 0x8, 0x0, 0x0, 0x8},
4489         {0x400, 0x18, 0x8, 0x0, 0x8},
4490         {0xb78, 0x18, 0x8, 0x0, 0x2},
4491         {0xd898, 0x50, 0x0, 0x0, 0x3c},
4492         {0x12908, 0x18, 0x0, 0x0, 0x10},
4493         {0x11aa8, 0x40, 0x0, 0x0, 0x18},
4494         {0xa588, 0x50, 0x0, 0x0, 0x20},
4495         {0x8700, 0x40, 0x0, 0x0, 0x28},
4496         {0x10300, 0x18, 0x0, 0x0, 0x10},
4497         {0xde48, 0x48, 0x0, 0x0, 0x38},
4498         {0x10768, 0x20, 0x0, 0x0, 0x20},
4499         {0x2d48, 0x80, 0x0, 0x0, 0x10},
4500         {0x5048, 0x10, 0x0, 0x0, 0x10},
4501         {0xc748, 0x8, 0x0, 0x0, 0x1},
4502         {0xa128, 0x8, 0x0, 0x0, 0x1},
4503         {0x10f00, 0x8, 0x0, 0x0, 0x1},
4504         {0xf030, 0x8, 0x0, 0x0, 0x1},
4505         {0x13028, 0x8, 0x0, 0x0, 0x1},
4506         {0x12c58, 0x8, 0x0, 0x0, 0x1},
4507         {0xc9b8, 0x30, 0x0, 0x0, 0x10},
4508         {0xed90, 0x28, 0x0, 0x0, 0x28},
4509         {0xa520, 0x18, 0x0, 0x0, 0x18},
4510         {0xa6a0, 0x8, 0x0, 0x0, 0x8},
4511         {0x13108, 0x8, 0x0, 0x0, 0x8},
4512         {0x13c50, 0x18, 0x0, 0x0, 0x18},
4513 };
4514
4515 /* Runtime array offsets */
4516 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET                        0
4517 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET                        1
4518 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET                        2
4519 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET                        3
4520 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET                        4
4521 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET                        5
4522 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET                        6
4523 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET                        7
4524 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET                        8
4525 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET                        9
4526 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET                        10
4527 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET                        11
4528 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET                        12
4529 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET                        13
4530 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET                        14
4531 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET                        15
4532 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET                          16
4533 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET                       17
4534 #define DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET                       18
4535 #define DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET                       19
4536 #define DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET                20
4537 #define DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET                21
4538 #define DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET                    22
4539 #define DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET                    23
4540 #define DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET                    24
4541 #define DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET                    25
4542 #define DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET                    26
4543 #define DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET                    27
4544 #define DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET                    28
4545 #define DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET                    29
4546 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET             30
4547 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET             31
4548 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET             32
4549 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET             33
4550 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET             34
4551 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET             35
4552 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET             36
4553 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET             37
4554 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET                      38
4555 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET                      39
4556 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET                       40
4557 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET                       41
4558 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET                    42
4559 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET                   43
4560 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET                     44
4561 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                         45
4562 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE                           1024
4563 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET                        1069
4564 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE                          1024
4565 #define CAU_REG_PI_MEMORY_RT_OFFSET                             2093
4566 #define CAU_REG_PI_MEMORY_RT_SIZE                               4416
4567 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET            6509
4568 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET              6510
4569 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET              6511
4570 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET                 6512
4571 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET                 6513
4572 #define PRS_REG_SEARCH_TCP_RT_OFFSET                            6514
4573 #define PRS_REG_SEARCH_FCOE_RT_OFFSET                           6515
4574 #define PRS_REG_SEARCH_ROCE_RT_OFFSET                           6516
4575 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET                   6517
4576 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET                   6518
4577 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET                       6519
4578 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET             6520
4579 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET   6521
4580 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET              6522
4581 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET                       6523
4582 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET                 6524
4583 #define SRC_REG_FIRSTFREE_RT_OFFSET                             6525
4584 #define SRC_REG_FIRSTFREE_RT_SIZE                               2
4585 #define SRC_REG_LASTFREE_RT_OFFSET                              6527
4586 #define SRC_REG_LASTFREE_RT_SIZE                                2
4587 #define SRC_REG_COUNTFREE_RT_OFFSET                             6529
4588 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET                      6530
4589 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET                        6531
4590 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET                        6532
4591 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET                          6533
4592 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET                          6534
4593 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET                         6535
4594 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET                        6536
4595 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET                       6537
4596 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET                        6538
4597 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET                       6539
4598 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET                        6540
4599 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET                      6541
4600 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET                       6542
4601 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET                     6543
4602 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET                      6544
4603 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET                     6545
4604 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET                      6546
4605 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET                     6547
4606 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET                      6548
4607 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET             6549
4608 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET           6550
4609 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET           6551
4610 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET                       6552
4611 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET                     6553
4612 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET                     6554
4613 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET                   6555
4614 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET                 6556
4615 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET                 6557
4616 #define PSWRQ2_REG_VF_BASE_RT_OFFSET                            6558
4617 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET                        6559
4618 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET                      6560
4619 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET                      6561
4620 #define PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET                    6562
4621 #define PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET                    6563
4622 #define PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET                     6564
4623 #define PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET                     6565
4624 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET                         6566
4625 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE                           26414
4626 #define PGLUE_REG_B_VF_BASE_RT_OFFSET                           32980
4627 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET                32981
4628 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET                   32982
4629 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET                   32983
4630 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET                      32984
4631 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET                      32985
4632 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET                      32986
4633 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET                         32987
4634 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET                         32988
4635 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET                         32989
4636 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET             32990
4637 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET             32991
4638 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET                        32992
4639 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE                          416
4640 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET                        33408
4641 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE                          608
4642 #define QM_REG_MAXPQSIZE_0_RT_OFFSET                            34016
4643 #define QM_REG_MAXPQSIZE_1_RT_OFFSET                            34017
4644 #define QM_REG_MAXPQSIZE_2_RT_OFFSET                            34018
4645 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET                       34019
4646 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET                       34020
4647 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET                       34021
4648 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET                       34022
4649 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET                       34023
4650 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET                       34024
4651 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET                       34025
4652 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET                       34026
4653 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET                       34027
4654 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET                       34028
4655 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET                      34029
4656 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET                      34030
4657 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET                      34031
4658 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET                      34032
4659 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET                      34033
4660 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET                      34034
4661 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET                      34035
4662 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET                      34036
4663 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET                      34037
4664 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET                      34038
4665 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET                      34039
4666 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET                      34040
4667 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET                      34041
4668 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET                      34042
4669 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET                      34043
4670 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET                      34044
4671 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET                      34045
4672 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET                      34046
4673 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET                      34047
4674 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET                      34048
4675 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET                      34049
4676 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET                      34050
4677 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET                      34051
4678 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET                      34052
4679 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET                      34053
4680 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET                      34054
4681 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET                      34055
4682 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET                      34056
4683 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET                      34057
4684 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET                      34058
4685 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET                      34059
4686 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET                      34060
4687 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET                      34061
4688 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET                      34062
4689 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET                      34063
4690 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET                      34064
4691 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET                      34065
4692 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET                      34066
4693 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET                      34067
4694 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET                      34068
4695 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET                      34069
4696 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET                      34070
4697 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET                      34071
4698 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET                      34072
4699 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET                      34073
4700 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET                      34074
4701 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET                      34075
4702 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET                      34076
4703 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET                      34077
4704 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET                      34078
4705 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET                      34079
4706 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET                      34080
4707 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET                      34081
4708 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET                      34082
4709 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET                        34083
4710 #define QM_REG_BASEADDROTHERPQ_RT_SIZE                          128
4711 #define QM_REG_PTRTBLOTHER_RT_OFFSET                            34211
4712 #define QM_REG_PTRTBLOTHER_RT_SIZE                              256
4713 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET                     34467
4714 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET                     34468
4715 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET                      34469
4716 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET                    34470
4717 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET                   34471
4718 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET                        34472
4719 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET                        34473
4720 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET                        34474
4721 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET                        34475
4722 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET                        34476
4723 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET                        34477
4724 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET                        34478
4725 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET                        34479
4726 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET                        34480
4727 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET                        34481
4728 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET                       34482
4729 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET                       34483
4730 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET                       34484
4731 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET                       34485
4732 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET                       34486
4733 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET                       34487
4734 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET                    34488
4735 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET                    34489
4736 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET                    34490
4737 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET                    34491
4738 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET                       34492
4739 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET                       34493
4740 #define QM_REG_PQTX2PF_0_RT_OFFSET                              34494
4741 #define QM_REG_PQTX2PF_1_RT_OFFSET                              34495
4742 #define QM_REG_PQTX2PF_2_RT_OFFSET                              34496
4743 #define QM_REG_PQTX2PF_3_RT_OFFSET                              34497
4744 #define QM_REG_PQTX2PF_4_RT_OFFSET                              34498
4745 #define QM_REG_PQTX2PF_5_RT_OFFSET                              34499
4746 #define QM_REG_PQTX2PF_6_RT_OFFSET                              34500
4747 #define QM_REG_PQTX2PF_7_RT_OFFSET                              34501
4748 #define QM_REG_PQTX2PF_8_RT_OFFSET                              34502
4749 #define QM_REG_PQTX2PF_9_RT_OFFSET                              34503
4750 #define QM_REG_PQTX2PF_10_RT_OFFSET                             34504
4751 #define QM_REG_PQTX2PF_11_RT_OFFSET                             34505
4752 #define QM_REG_PQTX2PF_12_RT_OFFSET                             34506
4753 #define QM_REG_PQTX2PF_13_RT_OFFSET                             34507
4754 #define QM_REG_PQTX2PF_14_RT_OFFSET                             34508
4755 #define QM_REG_PQTX2PF_15_RT_OFFSET                             34509
4756 #define QM_REG_PQTX2PF_16_RT_OFFSET                             34510
4757 #define QM_REG_PQTX2PF_17_RT_OFFSET                             34511
4758 #define QM_REG_PQTX2PF_18_RT_OFFSET                             34512
4759 #define QM_REG_PQTX2PF_19_RT_OFFSET                             34513
4760 #define QM_REG_PQTX2PF_20_RT_OFFSET                             34514
4761 #define QM_REG_PQTX2PF_21_RT_OFFSET                             34515
4762 #define QM_REG_PQTX2PF_22_RT_OFFSET                             34516
4763 #define QM_REG_PQTX2PF_23_RT_OFFSET                             34517
4764 #define QM_REG_PQTX2PF_24_RT_OFFSET                             34518
4765 #define QM_REG_PQTX2PF_25_RT_OFFSET                             34519
4766 #define QM_REG_PQTX2PF_26_RT_OFFSET                             34520
4767 #define QM_REG_PQTX2PF_27_RT_OFFSET                             34521
4768 #define QM_REG_PQTX2PF_28_RT_OFFSET                             34522
4769 #define QM_REG_PQTX2PF_29_RT_OFFSET                             34523
4770 #define QM_REG_PQTX2PF_30_RT_OFFSET                             34524
4771 #define QM_REG_PQTX2PF_31_RT_OFFSET                             34525
4772 #define QM_REG_PQTX2PF_32_RT_OFFSET                             34526
4773 #define QM_REG_PQTX2PF_33_RT_OFFSET                             34527
4774 #define QM_REG_PQTX2PF_34_RT_OFFSET                             34528
4775 #define QM_REG_PQTX2PF_35_RT_OFFSET                             34529
4776 #define QM_REG_PQTX2PF_36_RT_OFFSET                             34530
4777 #define QM_REG_PQTX2PF_37_RT_OFFSET                             34531
4778 #define QM_REG_PQTX2PF_38_RT_OFFSET                             34532
4779 #define QM_REG_PQTX2PF_39_RT_OFFSET                             34533
4780 #define QM_REG_PQTX2PF_40_RT_OFFSET                             34534
4781 #define QM_REG_PQTX2PF_41_RT_OFFSET                             34535
4782 #define QM_REG_PQTX2PF_42_RT_OFFSET                             34536
4783 #define QM_REG_PQTX2PF_43_RT_OFFSET                             34537
4784 #define QM_REG_PQTX2PF_44_RT_OFFSET                             34538
4785 #define QM_REG_PQTX2PF_45_RT_OFFSET                             34539
4786 #define QM_REG_PQTX2PF_46_RT_OFFSET                             34540
4787 #define QM_REG_PQTX2PF_47_RT_OFFSET                             34541
4788 #define QM_REG_PQTX2PF_48_RT_OFFSET                             34542
4789 #define QM_REG_PQTX2PF_49_RT_OFFSET                             34543
4790 #define QM_REG_PQTX2PF_50_RT_OFFSET                             34544
4791 #define QM_REG_PQTX2PF_51_RT_OFFSET                             34545
4792 #define QM_REG_PQTX2PF_52_RT_OFFSET                             34546
4793 #define QM_REG_PQTX2PF_53_RT_OFFSET                             34547
4794 #define QM_REG_PQTX2PF_54_RT_OFFSET                             34548
4795 #define QM_REG_PQTX2PF_55_RT_OFFSET                             34549
4796 #define QM_REG_PQTX2PF_56_RT_OFFSET                             34550
4797 #define QM_REG_PQTX2PF_57_RT_OFFSET                             34551
4798 #define QM_REG_PQTX2PF_58_RT_OFFSET                             34552
4799 #define QM_REG_PQTX2PF_59_RT_OFFSET                             34553
4800 #define QM_REG_PQTX2PF_60_RT_OFFSET                             34554
4801 #define QM_REG_PQTX2PF_61_RT_OFFSET                             34555
4802 #define QM_REG_PQTX2PF_62_RT_OFFSET                             34556
4803 #define QM_REG_PQTX2PF_63_RT_OFFSET                             34557
4804 #define QM_REG_PQOTHER2PF_0_RT_OFFSET                           34558
4805 #define QM_REG_PQOTHER2PF_1_RT_OFFSET                           34559
4806 #define QM_REG_PQOTHER2PF_2_RT_OFFSET                           34560
4807 #define QM_REG_PQOTHER2PF_3_RT_OFFSET                           34561
4808 #define QM_REG_PQOTHER2PF_4_RT_OFFSET                           34562
4809 #define QM_REG_PQOTHER2PF_5_RT_OFFSET                           34563
4810 #define QM_REG_PQOTHER2PF_6_RT_OFFSET                           34564
4811 #define QM_REG_PQOTHER2PF_7_RT_OFFSET                           34565
4812 #define QM_REG_PQOTHER2PF_8_RT_OFFSET                           34566
4813 #define QM_REG_PQOTHER2PF_9_RT_OFFSET                           34567
4814 #define QM_REG_PQOTHER2PF_10_RT_OFFSET                          34568
4815 #define QM_REG_PQOTHER2PF_11_RT_OFFSET                          34569
4816 #define QM_REG_PQOTHER2PF_12_RT_OFFSET                          34570
4817 #define QM_REG_PQOTHER2PF_13_RT_OFFSET                          34571
4818 #define QM_REG_PQOTHER2PF_14_RT_OFFSET                          34572
4819 #define QM_REG_PQOTHER2PF_15_RT_OFFSET                          34573
4820 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET                         34574
4821 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET                         34575
4822 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET                    34576
4823 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET                    34577
4824 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET                      34578
4825 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET                      34579
4826 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET                      34580
4827 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET                      34581
4828 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET                      34582
4829 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET                      34583
4830 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET                      34584
4831 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET                      34585
4832 #define QM_REG_RLGLBLINCVAL_RT_OFFSET                           34586
4833 #define QM_REG_RLGLBLINCVAL_RT_SIZE                             256
4834 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET                       34842
4835 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE                         256
4836 #define QM_REG_RLGLBLCRD_RT_OFFSET                              35098
4837 #define QM_REG_RLGLBLCRD_RT_SIZE                                256
4838 #define QM_REG_RLGLBLENABLE_RT_OFFSET                           35354
4839 #define QM_REG_RLPFPERIOD_RT_OFFSET                             35355
4840 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET                        35356
4841 #define QM_REG_RLPFINCVAL_RT_OFFSET                             35357
4842 #define QM_REG_RLPFINCVAL_RT_SIZE                               16
4843 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET                         35373
4844 #define QM_REG_RLPFUPPERBOUND_RT_SIZE                           16
4845 #define QM_REG_RLPFCRD_RT_OFFSET                                35389
4846 #define QM_REG_RLPFCRD_RT_SIZE                                  16
4847 #define QM_REG_RLPFENABLE_RT_OFFSET                             35405
4848 #define QM_REG_RLPFVOQENABLE_RT_OFFSET                          35406
4849 #define QM_REG_WFQPFWEIGHT_RT_OFFSET                            35407
4850 #define QM_REG_WFQPFWEIGHT_RT_SIZE                              16
4851 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET                        35423
4852 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE                          16
4853 #define QM_REG_WFQPFCRD_RT_OFFSET                               35439
4854 #define QM_REG_WFQPFCRD_RT_SIZE                                 256
4855 #define QM_REG_WFQPFENABLE_RT_OFFSET                            35695
4856 #define QM_REG_WFQVPENABLE_RT_OFFSET                            35696
4857 #define QM_REG_BASEADDRTXPQ_RT_OFFSET                           35697
4858 #define QM_REG_BASEADDRTXPQ_RT_SIZE                             512
4859 #define QM_REG_TXPQMAP_RT_OFFSET                                36209
4860 #define QM_REG_TXPQMAP_RT_SIZE                                  512
4861 #define QM_REG_WFQVPWEIGHT_RT_OFFSET                            36721
4862 #define QM_REG_WFQVPWEIGHT_RT_SIZE                              512
4863 #define QM_REG_WFQVPCRD_RT_OFFSET                               37233
4864 #define QM_REG_WFQVPCRD_RT_SIZE                                 512
4865 #define QM_REG_WFQVPMAP_RT_OFFSET                               37745
4866 #define QM_REG_WFQVPMAP_RT_SIZE                                 512
4867 #define QM_REG_PTRTBLTX_RT_OFFSET                               38257
4868 #define QM_REG_PTRTBLTX_RT_SIZE                                 1024
4869 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET                           39281
4870 #define QM_REG_WFQPFCRD_MSB_RT_SIZE                             320
4871 #define QM_REG_VOQCRDLINE_RT_OFFSET                             39601
4872 #define QM_REG_VOQCRDLINE_RT_SIZE                               36
4873 #define QM_REG_VOQINITCRDLINE_RT_OFFSET                         39637
4874 #define QM_REG_VOQINITCRDLINE_RT_SIZE                           36
4875 #define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET                      39673
4876 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET                       39674
4877 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET                  39675
4878 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET                 39676
4879 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET                 39677
4880 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET                 39678
4881 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET                 39679
4882 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET              39680
4883 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET                       39681
4884 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE                         4
4885 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET                    39685
4886 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE                      4
4887 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET                 39689
4888 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE                   32
4889 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET                    39721
4890 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE                      16
4891 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET                  39737
4892 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE                    16
4893 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET         39753
4894 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE           16
4895 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET               39769
4896 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE                 16
4897 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET                          39785
4898 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET                             39786
4899 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE                               8
4900 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET                  39794
4901 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE                    1024
4902 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET                     40818
4903 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE                       512
4904 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET                   41330
4905 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE                     512
4906 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET          41842
4907 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE            512
4908 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET                42354
4909 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE                  512
4910 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET                        42866
4911 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE                          32
4912 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET                               42898
4913 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET                               42899
4914 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET                               42900
4915 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET                           42901
4916 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET                           42902
4917 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET                           42903
4918 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET                           42904
4919 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET                        42905
4920 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET                        42906
4921 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET                        42907
4922 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET                        42908
4923 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET                            42909
4924 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET                         42910
4925 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET                               42911
4926 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET                          42912
4927 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET                        42913
4928 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET                           42914
4929 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET                    42915
4930 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET                        42916
4931 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET                           42917
4932 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET                    42918
4933 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET                        42919
4934 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET                           42920
4935 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET                    42921
4936 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET                        42922
4937 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET                           42923
4938 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET                    42924
4939 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET                        42925
4940 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET                           42926
4941 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET                    42927
4942 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET                        42928
4943 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET                           42929
4944 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET                    42930
4945 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET                        42931
4946 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET                           42932
4947 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET                    42933
4948 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET                        42934
4949 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET                           42935
4950 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET                    42936
4951 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET                        42937
4952 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET                           42938
4953 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET                    42939
4954 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET                        42940
4955 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET                           42941
4956 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET                    42942
4957 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET                       42943
4958 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET                          42944
4959 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET                   42945
4960 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET                       42946
4961 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET                          42947
4962 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET                   42948
4963 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET                       42949
4964 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET                          42950
4965 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET                   42951
4966 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET                       42952
4967 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET                          42953
4968 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET                   42954
4969 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET                       42955
4970 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET                          42956
4971 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET                   42957
4972 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET                       42958
4973 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET                          42959
4974 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET                   42960
4975 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET                       42961
4976 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET                          42962
4977 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET                   42963
4978 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET                       42964
4979 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET                          42965
4980 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET                   42966
4981 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET                       42967
4982 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET                          42968
4983 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET                   42969
4984 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET                       42970
4985 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET                          42971
4986 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET                   42972
4987 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET                       42973
4988 #define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET                          42974
4989 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET                   42975
4990 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET                       42976
4991 #define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET                          42977
4992 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET                   42978
4993 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET                       42979
4994 #define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET                          42980
4995 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET                   42981
4996 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET                       42982
4997 #define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET                          42983
4998 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET                   42984
4999 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET                       42985
5000 #define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET                          42986
5001 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET                   42987
5002 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET                       42988
5003 #define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET                          42989
5004 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET                   42990
5005 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET                       42991
5006 #define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET                          42992
5007 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET                   42993
5008 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET                       42994
5009 #define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET                          42995
5010 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET                   42996
5011 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET                       42997
5012 #define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET                          42998
5013 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET                   42999
5014 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET                       43000
5015 #define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET                          43001
5016 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET                   43002
5017 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET                       43003
5018 #define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET                          43004
5019 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET                   43005
5020 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET                       43006
5021 #define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET                          43007
5022 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET                   43008
5023 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET                       43009
5024 #define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET                          43010
5025 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET                   43011
5026 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET                       43012
5027 #define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET                          43013
5028 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET                   43014
5029 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET                       43015
5030 #define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET                          43016
5031 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET                   43017
5032 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET                       43018
5033 #define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET                          43019
5034 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET                   43020
5035 #define XCM_REG_CON_PHY_Q3_RT_OFFSET                                    43021
5036
5037 #define RUNTIME_ARRAY_SIZE 43022
5038
5039
5040 /* Init Callbacks */
5041 #define DMAE_READY_CB   0
5042
5043 /* The eth storm context for the Tstorm */
5044 struct tstorm_eth_conn_st_ctx {
5045         __le32 reserved[4];
5046 };
5047
5048 /* The eth storm context for the Pstorm */
5049 struct pstorm_eth_conn_st_ctx {
5050         __le32 reserved[8];
5051 };
5052
5053 /* The eth storm context for the Xstorm */
5054 struct xstorm_eth_conn_st_ctx {
5055         __le32 reserved[60];
5056 };
5057
5058 struct e4_xstorm_eth_conn_ag_ctx {
5059         u8 reserved0;
5060         u8 state;
5061         u8 flags0;
5062 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK     0x1
5063 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT    0
5064 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK        0x1
5065 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT       1
5066 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK        0x1
5067 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT       2
5068 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK     0x1
5069 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT    3
5070 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK        0x1
5071 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT       4
5072 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK        0x1
5073 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT       5
5074 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK        0x1
5075 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT       6
5076 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK        0x1
5077 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT       7
5078                 u8 flags1;
5079 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK        0x1
5080 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT       0
5081 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK        0x1
5082 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT       1
5083 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK        0x1
5084 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT       2
5085 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK            0x1
5086 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT           3
5087 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK     0x1
5088 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT    4
5089 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK     0x1
5090 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT    5
5091 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK   0x1
5092 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT  6
5093 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK     0x1
5094 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT    7
5095         u8 flags2;
5096 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK      0x3
5097 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT     0
5098 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK      0x3
5099 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT     2
5100 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK      0x3
5101 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT     4
5102 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK      0x3
5103 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT     6
5104         u8 flags3;
5105 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK      0x3
5106 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT     0
5107 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK      0x3
5108 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT     2
5109 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK      0x3
5110 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT     4
5111 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK      0x3
5112 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT     6
5113                 u8 flags4;
5114 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK      0x3
5115 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT     0
5116 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK      0x3
5117 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT     2
5118 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK     0x3
5119 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT    4
5120 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK     0x3
5121 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT    6
5122         u8 flags5;
5123 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK     0x3
5124 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT    0
5125 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK     0x3
5126 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT    2
5127 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK     0x3
5128 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT    4
5129 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK     0x3
5130 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT    6
5131         u8 flags6;
5132 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK         0x3
5133 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT        0
5134 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK         0x3
5135 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT        2
5136 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK                    0x3
5137 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT                   4
5138 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK             0x3
5139 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT            6
5140         u8 flags7;
5141 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK         0x3
5142 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT        0
5143 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK       0x3
5144 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT      2
5145 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK        0x3
5146 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT       4
5147 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK            0x1
5148 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT           6
5149 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK            0x1
5150 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT           7
5151         u8 flags8;
5152 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK    0x1
5153 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT   0
5154 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK    0x1
5155 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT   1
5156 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK    0x1
5157 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT   2
5158 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK    0x1
5159 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT   3
5160 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK    0x1
5161 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT   4
5162 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK    0x1
5163 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT   5
5164 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK    0x1
5165 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT   6
5166 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK    0x1
5167 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT   7
5168         u8 flags9;
5169 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK                   0x1
5170 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT                  0
5171 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK                   0x1
5172 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT                  1
5173 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK                   0x1
5174 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT                  2
5175 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK                   0x1
5176 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT                  3
5177 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK                   0x1
5178 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT                  4
5179 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK                   0x1
5180 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT                  5
5181 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK      0x1
5182 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT     6
5183 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK      0x1
5184 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT     7
5185         u8 flags10;
5186 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK                 0x1
5187 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT                0
5188 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK          0x1
5189 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT         1
5190 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK              0x1
5191 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT             2
5192 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK               0x1
5193 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT              3
5194 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK             0x1
5195 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT            4
5196 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK   0x1
5197 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT  5
5198 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK               0x1
5199 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT              6
5200 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK               0x1
5201 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT              7
5202         u8 flags11;
5203 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK       0x1
5204 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT      0
5205 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK       0x1
5206 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT      1
5207 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK   0x1
5208 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT  2
5209 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK          0x1
5210 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT         3
5211 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK          0x1
5212 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT         4
5213 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK          0x1
5214 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT         5
5215 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK     0x1
5216 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT    6
5217 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK          0x1
5218 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT         7
5219         u8 flags12;
5220 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK         0x1
5221 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT        0
5222 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK         0x1
5223 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT        1
5224 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK     0x1
5225 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT    2
5226 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK     0x1
5227 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT    3
5228 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK         0x1
5229 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT        4
5230 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK         0x1
5231 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT        5
5232 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK         0x1
5233 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT        6
5234 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK         0x1
5235 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT        7
5236         u8 flags13;
5237 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK         0x1
5238 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT        0
5239 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK         0x1
5240 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT        1
5241 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK     0x1
5242 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT    2
5243 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK     0x1
5244 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT    3
5245 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK     0x1
5246 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT    4
5247 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK     0x1
5248 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT    5
5249 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK     0x1
5250 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT    6
5251 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK     0x1
5252 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT    7
5253         u8 flags14;
5254 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK         0x1
5255 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT        0
5256 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK       0x1
5257 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT      1
5258 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK     0x1
5259 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT    2
5260 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK     0x1
5261 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT    3
5262 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK           0x1
5263 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT          4
5264 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK         0x1
5265 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT        5
5266 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK               0x3
5267 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT              6
5268         u8 edpm_event_id;
5269         __le16 physical_q0;
5270         __le16 e5_reserved1;
5271         __le16 edpm_num_bds;
5272         __le16 tx_bd_cons;
5273         __le16 tx_bd_prod;
5274         __le16 updated_qm_pq_id;
5275         __le16 conn_dpi;
5276         u8 byte3;
5277         u8 byte4;
5278         u8 byte5;
5279         u8 byte6;
5280         __le32 reg0;
5281         __le32 reg1;
5282         __le32 reg2;
5283         __le32 reg3;
5284         __le32 reg4;
5285         __le32 reg5;
5286         __le32 reg6;
5287         __le16 word7;
5288         __le16 word8;
5289         __le16 word9;
5290         __le16 word10;
5291         __le32 reg7;
5292         __le32 reg8;
5293         __le32 reg9;
5294         u8 byte7;
5295         u8 byte8;
5296         u8 byte9;
5297         u8 byte10;
5298         u8 byte11;
5299         u8 byte12;
5300         u8 byte13;
5301         u8 byte14;
5302         u8 byte15;
5303         u8 e5_reserved;
5304         __le16 word11;
5305         __le32 reg10;
5306         __le32 reg11;
5307         __le32 reg12;
5308         __le32 reg13;
5309         __le32 reg14;
5310         __le32 reg15;
5311         __le32 reg16;
5312         __le32 reg17;
5313         __le32 reg18;
5314         __le32 reg19;
5315         __le16 word12;
5316         __le16 word13;
5317         __le16 word14;
5318         __le16 word15;
5319 };
5320
5321 /* The eth storm context for the Ystorm */
5322 struct ystorm_eth_conn_st_ctx {
5323         __le32 reserved[8];
5324 };
5325
5326 struct e4_ystorm_eth_conn_ag_ctx {
5327         u8 byte0;
5328         u8 state;
5329         u8 flags0;
5330 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK                     0x1
5331 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                    0
5332 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK                     0x1
5333 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                    1
5334 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK        0x3
5335 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT       2
5336 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK         0x3
5337 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT        4
5338 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK                      0x3
5339 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                     6
5340         u8 flags1;
5341 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK     0x1
5342 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT    0
5343 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK      0x1
5344 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT     1
5345 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK                    0x1
5346 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                   2
5347 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK                  0x1
5348 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT                 3
5349 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK                  0x1
5350 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT                 4
5351 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK                  0x1
5352 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT                 5
5353 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK                  0x1
5354 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT                 6
5355 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK                  0x1
5356 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT                 7
5357         u8 tx_q0_int_coallecing_timeset;
5358         u8 byte3;
5359         __le16 word0;
5360         __le32 terminate_spqe;
5361         __le32 reg1;
5362         __le16 tx_bd_cons_upd;
5363         __le16 word2;
5364         __le16 word3;
5365         __le16 word4;
5366         __le32 reg2;
5367         __le32 reg3;
5368 };
5369
5370 struct e4_tstorm_eth_conn_ag_ctx {
5371         u8 byte0;
5372         u8 byte1;
5373         u8 flags0;
5374 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK     0x1
5375 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT    0
5376 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK     0x1
5377 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT    1
5378 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK     0x1
5379 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT    2
5380 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK     0x1
5381 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT    3
5382 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK     0x1
5383 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT    4
5384 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK     0x1
5385 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT    5
5386 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK      0x3
5387 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT     6
5388         u8 flags1;
5389 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK      0x3
5390 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT     0
5391 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK      0x3
5392 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT     2
5393 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK      0x3
5394 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT     4
5395 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK      0x3
5396 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT     6
5397         u8 flags2;
5398 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK      0x3
5399 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT     0
5400 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK      0x3
5401 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT     2
5402 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK      0x3
5403 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT     4
5404 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK      0x3
5405 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT     6
5406         u8 flags3;
5407 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK      0x3
5408 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT     0
5409 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK     0x3
5410 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT    2
5411 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK    0x1
5412 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT   4
5413 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK    0x1
5414 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT   5
5415 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK    0x1
5416 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT   6
5417 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK    0x1
5418 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT   7
5419         u8 flags4;
5420 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK    0x1
5421 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT   0
5422 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK    0x1
5423 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT   1
5424 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK    0x1
5425 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT   2
5426 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK    0x1
5427 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT   3
5428 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK    0x1
5429 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT   4
5430 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK    0x1
5431 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT   5
5432 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK   0x1
5433 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT  6
5434 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK  0x1
5435 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
5436         u8 flags5;
5437 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK          0x1
5438 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT         0
5439 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK          0x1
5440 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT         1
5441 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK          0x1
5442 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT         2
5443 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK          0x1
5444 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT         3
5445 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK          0x1
5446 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT         4
5447 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK         0x1
5448 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT        5
5449 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK          0x1
5450 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT         6
5451 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK          0x1
5452 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT         7
5453         __le32 reg0;
5454         __le32 reg1;
5455         __le32 reg2;
5456         __le32 reg3;
5457         __le32 reg4;
5458         __le32 reg5;
5459         __le32 reg6;
5460         __le32 reg7;
5461         __le32 reg8;
5462         u8 byte2;
5463         u8 byte3;
5464         __le16 rx_bd_cons;
5465         u8 byte4;
5466         u8 byte5;
5467         __le16 rx_bd_prod;
5468         __le16 word2;
5469         __le16 word3;
5470         __le32 reg9;
5471         __le32 reg10;
5472 };
5473
5474 struct e4_ustorm_eth_conn_ag_ctx {
5475         u8 byte0;
5476         u8 byte1;
5477         u8 flags0;
5478 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK                     0x1
5479 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                    0
5480 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK                     0x1
5481 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                    1
5482 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK      0x3
5483 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT     2
5484 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK      0x3
5485 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT     4
5486 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK                      0x3
5487 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT                     6
5488         u8 flags1;
5489 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK                      0x3
5490 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT                     0
5491 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK                0x3
5492 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT               2
5493 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK                0x3
5494 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT               4
5495 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK        0x3
5496 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT       6
5497         u8 flags2;
5498 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK   0x1
5499 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT  0
5500 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK   0x1
5501 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT  1
5502 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK                    0x1
5503 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                   2
5504 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK                    0x1
5505 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                   3
5506 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK             0x1
5507 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT            4
5508 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK             0x1
5509 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT            5
5510 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK     0x1
5511 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT    6
5512 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK                  0x1
5513 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT                 7
5514         u8 flags3;
5515 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK  0x1
5516 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
5517 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK  0x1
5518 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
5519 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK  0x1
5520 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
5521 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK  0x1
5522 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
5523 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK  0x1
5524 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
5525 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK  0x1
5526 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
5527 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK  0x1
5528 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
5529 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK  0x1
5530 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
5531         u8 byte2;
5532         u8 byte3;
5533         __le16 word0;
5534         __le16 tx_bd_cons;
5535         __le32 reg0;
5536         __le32 reg1;
5537         __le32 reg2;
5538         __le32 tx_int_coallecing_timeset;
5539         __le16 tx_drv_bd_cons;
5540         __le16 rx_drv_cqe_cons;
5541 };
5542
5543 /* The eth storm context for the Ustorm */
5544 struct ustorm_eth_conn_st_ctx {
5545         __le32 reserved[40];
5546 };
5547
5548 /* The eth storm context for the Mstorm */
5549 struct mstorm_eth_conn_st_ctx {
5550         __le32 reserved[8];
5551 };
5552
5553 /* eth connection context */
5554 struct e4_eth_conn_context {
5555         struct tstorm_eth_conn_st_ctx tstorm_st_context;
5556         struct regpair tstorm_st_padding[2];
5557         struct pstorm_eth_conn_st_ctx pstorm_st_context;
5558         struct xstorm_eth_conn_st_ctx xstorm_st_context;
5559         struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
5560         struct ystorm_eth_conn_st_ctx ystorm_st_context;
5561         struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
5562         struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
5563         struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
5564         struct ustorm_eth_conn_st_ctx ustorm_st_context;
5565         struct mstorm_eth_conn_st_ctx mstorm_st_context;
5566 };
5567
5568 /* Ethernet filter types: mac/vlan/pair */
5569 enum eth_error_code {
5570         ETH_OK = 0x00,
5571         ETH_FILTERS_MAC_ADD_FAIL_FULL,
5572         ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
5573         ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
5574         ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
5575         ETH_FILTERS_MAC_DEL_FAIL_NOF,
5576         ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
5577         ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
5578         ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
5579         ETH_FILTERS_VLAN_ADD_FAIL_FULL,
5580         ETH_FILTERS_VLAN_ADD_FAIL_DUP,
5581         ETH_FILTERS_VLAN_DEL_FAIL_NOF,
5582         ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
5583         ETH_FILTERS_PAIR_ADD_FAIL_DUP,
5584         ETH_FILTERS_PAIR_ADD_FAIL_FULL,
5585         ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
5586         ETH_FILTERS_PAIR_DEL_FAIL_NOF,
5587         ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
5588         ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
5589         ETH_FILTERS_VNI_ADD_FAIL_FULL,
5590         ETH_FILTERS_VNI_ADD_FAIL_DUP,
5591         ETH_FILTERS_GFT_UPDATE_FAIL,
5592         MAX_ETH_ERROR_CODE
5593 };
5594
5595 /* Opcodes for the event ring */
5596 enum eth_event_opcode {
5597         ETH_EVENT_UNUSED,
5598         ETH_EVENT_VPORT_START,
5599         ETH_EVENT_VPORT_UPDATE,
5600         ETH_EVENT_VPORT_STOP,
5601         ETH_EVENT_TX_QUEUE_START,
5602         ETH_EVENT_TX_QUEUE_STOP,
5603         ETH_EVENT_RX_QUEUE_START,
5604         ETH_EVENT_RX_QUEUE_UPDATE,
5605         ETH_EVENT_RX_QUEUE_STOP,
5606         ETH_EVENT_FILTERS_UPDATE,
5607         ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
5608         ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
5609         ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
5610         ETH_EVENT_RX_ADD_UDP_FILTER,
5611         ETH_EVENT_RX_DELETE_UDP_FILTER,
5612         ETH_EVENT_RX_CREATE_GFT_ACTION,
5613         ETH_EVENT_RX_GFT_UPDATE_FILTER,
5614         ETH_EVENT_TX_QUEUE_UPDATE,
5615         MAX_ETH_EVENT_OPCODE
5616 };
5617
5618 /* Classify rule types in E2/E3 */
5619 enum eth_filter_action {
5620         ETH_FILTER_ACTION_UNUSED,
5621         ETH_FILTER_ACTION_REMOVE,
5622         ETH_FILTER_ACTION_ADD,
5623         ETH_FILTER_ACTION_REMOVE_ALL,
5624         MAX_ETH_FILTER_ACTION
5625 };
5626
5627 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
5628 struct eth_filter_cmd {
5629         u8 type;
5630         u8 vport_id;
5631         u8 action;
5632         u8 reserved0;
5633         __le32 vni;
5634         __le16 mac_lsb;
5635         __le16 mac_mid;
5636         __le16 mac_msb;
5637         __le16 vlan_id;
5638 };
5639
5640 /*      $$KEEP_ENDIANNESS$$ */
5641 struct eth_filter_cmd_header {
5642         u8 rx;
5643         u8 tx;
5644         u8 cmd_cnt;
5645         u8 assert_on_error;
5646         u8 reserved1[4];
5647 };
5648
5649 /* Ethernet filter types: mac/vlan/pair */
5650 enum eth_filter_type {
5651         ETH_FILTER_TYPE_UNUSED,
5652         ETH_FILTER_TYPE_MAC,
5653         ETH_FILTER_TYPE_VLAN,
5654         ETH_FILTER_TYPE_PAIR,
5655         ETH_FILTER_TYPE_INNER_MAC,
5656         ETH_FILTER_TYPE_INNER_VLAN,
5657         ETH_FILTER_TYPE_INNER_PAIR,
5658         ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
5659         ETH_FILTER_TYPE_MAC_VNI_PAIR,
5660         ETH_FILTER_TYPE_VNI,
5661         MAX_ETH_FILTER_TYPE
5662 };
5663
5664 /* Eth IPv4 Fragment Type */
5665 enum eth_ipv4_frag_type {
5666         ETH_IPV4_NOT_FRAG,
5667         ETH_IPV4_FIRST_FRAG,
5668         ETH_IPV4_NON_FIRST_FRAG,
5669         MAX_ETH_IPV4_FRAG_TYPE
5670 };
5671
5672 /* eth IPv4 Fragment Type */
5673 enum eth_ip_type {
5674         ETH_IPV4,
5675         ETH_IPV6,
5676         MAX_ETH_IP_TYPE
5677 };
5678
5679 /* Ethernet Ramrod Command IDs */
5680 enum eth_ramrod_cmd_id {
5681         ETH_RAMROD_UNUSED,
5682         ETH_RAMROD_VPORT_START,
5683         ETH_RAMROD_VPORT_UPDATE,
5684         ETH_RAMROD_VPORT_STOP,
5685         ETH_RAMROD_RX_QUEUE_START,
5686         ETH_RAMROD_RX_QUEUE_STOP,
5687         ETH_RAMROD_TX_QUEUE_START,
5688         ETH_RAMROD_TX_QUEUE_STOP,
5689         ETH_RAMROD_FILTERS_UPDATE,
5690         ETH_RAMROD_RX_QUEUE_UPDATE,
5691         ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
5692         ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
5693         ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
5694         ETH_RAMROD_RX_ADD_UDP_FILTER,
5695         ETH_RAMROD_RX_DELETE_UDP_FILTER,
5696         ETH_RAMROD_RX_CREATE_GFT_ACTION,
5697         ETH_RAMROD_GFT_UPDATE_FILTER,
5698         ETH_RAMROD_TX_QUEUE_UPDATE,
5699         MAX_ETH_RAMROD_CMD_ID
5700 };
5701
5702 /* Return code from eth sp ramrods */
5703 struct eth_return_code {
5704         u8 value;
5705 #define ETH_RETURN_CODE_ERR_CODE_MASK   0x1F
5706 #define ETH_RETURN_CODE_ERR_CODE_SHIFT  0
5707 #define ETH_RETURN_CODE_RESERVED_MASK   0x3
5708 #define ETH_RETURN_CODE_RESERVED_SHIFT  5
5709 #define ETH_RETURN_CODE_RX_TX_MASK      0x1
5710 #define ETH_RETURN_CODE_RX_TX_SHIFT     7
5711 };
5712
5713 /* What to do in case an error occurs */
5714 enum eth_tx_err {
5715         ETH_TX_ERR_DROP,
5716         ETH_TX_ERR_ASSERT_MALICIOUS,
5717         MAX_ETH_TX_ERR
5718 };
5719
5720 /* Array of the different error type behaviors */
5721 struct eth_tx_err_vals {
5722         __le16 values;
5723 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK                  0x1
5724 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT                 0
5725 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK                   0x1
5726 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT                  1
5727 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK                  0x1
5728 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT                 2
5729 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK                0x1
5730 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT               3
5731 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK        0x1
5732 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT       4
5733 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK                      0x1
5734 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT                     5
5735 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK              0x1
5736 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT             6
5737 #define ETH_TX_ERR_VALS_RESERVED_MASK                           0x1FF
5738 #define ETH_TX_ERR_VALS_RESERVED_SHIFT                          7
5739 };
5740
5741 /* vport rss configuration data */
5742 struct eth_vport_rss_config {
5743         __le16 capabilities;
5744 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK               0x1
5745 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT              0
5746 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK               0x1
5747 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT              1
5748 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK           0x1
5749 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT          2
5750 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK           0x1
5751 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT          3
5752 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK           0x1
5753 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT          4
5754 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK           0x1
5755 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT          5
5756 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK         0x1
5757 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT        6
5758 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK                     0x1FF
5759 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT                    7
5760         u8 rss_id;
5761         u8 rss_mode;
5762         u8 update_rss_key;
5763         u8 update_rss_ind_table;
5764         u8 update_rss_capabilities;
5765         u8 tbl_size;
5766         __le32 reserved2[2];
5767         __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
5768
5769         __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
5770         __le32 reserved3[2];
5771 };
5772
5773 /* eth vport RSS mode */
5774 enum eth_vport_rss_mode {
5775         ETH_VPORT_RSS_MODE_DISABLED,
5776         ETH_VPORT_RSS_MODE_REGULAR,
5777         MAX_ETH_VPORT_RSS_MODE
5778 };
5779
5780 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5781 struct eth_vport_rx_mode {
5782         __le16 state;
5783 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK           0x1
5784 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT          0
5785 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK         0x1
5786 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT        1
5787 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK   0x1
5788 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT  2
5789 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK           0x1
5790 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT          3
5791 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK         0x1
5792 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT        4
5793 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK         0x1
5794 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT        5
5795 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK           0x1
5796 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT          6
5797 #define ETH_VPORT_RX_MODE_RESERVED1_MASK                0x1FF
5798 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT               7
5799 };
5800
5801 /* Command for setting tpa parameters */
5802 struct eth_vport_tpa_param {
5803         u8 tpa_ipv4_en_flg;
5804         u8 tpa_ipv6_en_flg;
5805         u8 tpa_ipv4_tunn_en_flg;
5806         u8 tpa_ipv6_tunn_en_flg;
5807         u8 tpa_pkt_split_flg;
5808         u8 tpa_hdr_data_split_flg;
5809         u8 tpa_gro_consistent_flg;
5810
5811         u8 tpa_max_aggs_num;
5812
5813         __le16 tpa_max_size;
5814         __le16 tpa_min_size_to_start;
5815
5816         __le16 tpa_min_size_to_cont;
5817         u8 max_buff_num;
5818         u8 reserved;
5819 };
5820
5821 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5822 struct eth_vport_tx_mode {
5823         __le16 state;
5824 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK           0x1
5825 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT          0
5826 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK         0x1
5827 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT        1
5828 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK           0x1
5829 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT          2
5830 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK         0x1
5831 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT        3
5832 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK         0x1
5833 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT        4
5834 #define ETH_VPORT_TX_MODE_RESERVED1_MASK                0x7FF
5835 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT               5
5836 };
5837
5838 /* GFT filter update action type */
5839 enum gft_filter_update_action {
5840         GFT_ADD_FILTER,
5841         GFT_DELETE_FILTER,
5842         MAX_GFT_FILTER_UPDATE_ACTION
5843 };
5844
5845 /* Ramrod data for rx add openflow filter */
5846 struct rx_add_openflow_filter_data {
5847         __le16 action_icid;
5848         u8 priority;
5849         u8 reserved0;
5850         __le32 tenant_id;
5851         __le16 dst_mac_hi;
5852         __le16 dst_mac_mid;
5853         __le16 dst_mac_lo;
5854         __le16 src_mac_hi;
5855         __le16 src_mac_mid;
5856         __le16 src_mac_lo;
5857         __le16 vlan_id;
5858         __le16 l2_eth_type;
5859         u8 ipv4_dscp;
5860         u8 ipv4_frag_type;
5861         u8 ipv4_over_ip;
5862         u8 tenant_id_exists;
5863         __le32 ipv4_dst_addr;
5864         __le32 ipv4_src_addr;
5865         __le16 l4_dst_port;
5866         __le16 l4_src_port;
5867 };
5868
5869 /* Ramrod data for rx create gft action */
5870 struct rx_create_gft_action_data {
5871         u8 vport_id;
5872         u8 reserved[7];
5873 };
5874
5875 /* Ramrod data for rx create openflow action */
5876 struct rx_create_openflow_action_data {
5877         u8 vport_id;
5878         u8 reserved[7];
5879 };
5880
5881 /* Ramrod data for rx queue start ramrod */
5882 struct rx_queue_start_ramrod_data {
5883         __le16 rx_queue_id;
5884         __le16 num_of_pbl_pages;
5885         __le16 bd_max_bytes;
5886         __le16 sb_id;
5887         u8 sb_index;
5888         u8 vport_id;
5889         u8 default_rss_queue_flg;
5890         u8 complete_cqe_flg;
5891         u8 complete_event_flg;
5892         u8 stats_counter_id;
5893         u8 pin_context;
5894         u8 pxp_tph_valid_bd;
5895         u8 pxp_tph_valid_pkt;
5896         u8 pxp_st_hint;
5897
5898         __le16 pxp_st_index;
5899         u8 pmd_mode;
5900
5901         u8 notify_en;
5902         u8 toggle_val;
5903
5904         u8 vf_rx_prod_index;
5905         u8 vf_rx_prod_use_zone_a;
5906         u8 reserved[5];
5907         __le16 reserved1;
5908         struct regpair cqe_pbl_addr;
5909         struct regpair bd_base;
5910         struct regpair reserved2;
5911 };
5912
5913 /* Ramrod data for rx queue stop ramrod */
5914 struct rx_queue_stop_ramrod_data {
5915         __le16 rx_queue_id;
5916         u8 complete_cqe_flg;
5917         u8 complete_event_flg;
5918         u8 vport_id;
5919         u8 reserved[3];
5920 };
5921
5922 /* Ramrod data for rx queue update ramrod */
5923 struct rx_queue_update_ramrod_data {
5924         __le16 rx_queue_id;
5925         u8 complete_cqe_flg;
5926         u8 complete_event_flg;
5927         u8 vport_id;
5928         u8 set_default_rss_queue;
5929         u8 reserved[3];
5930         u8 reserved1;
5931         u8 reserved2;
5932         u8 reserved3;
5933         __le16 reserved4;
5934         __le16 reserved5;
5935         struct regpair reserved6;
5936 };
5937
5938 /* Ramrod data for rx Add UDP Filter */
5939 struct rx_udp_filter_data {
5940         __le16 action_icid;
5941         __le16 vlan_id;
5942         u8 ip_type;
5943         u8 tenant_id_exists;
5944         __le16 reserved1;
5945         __le32 ip_dst_addr[4];
5946         __le32 ip_src_addr[4];
5947         __le16 udp_dst_port;
5948         __le16 udp_src_port;
5949         __le32 tenant_id;
5950 };
5951
5952 /* Add or delete GFT filter - filter is packet header of type of packet wished
5953  * to pass certain FW flow.
5954  */
5955 struct rx_update_gft_filter_data {
5956         struct regpair pkt_hdr_addr;
5957         __le16 pkt_hdr_length;
5958         __le16 action_icid;
5959         __le16 rx_qid;
5960         __le16 flow_id;
5961         __le16 vport_id;
5962         u8 action_icid_valid;
5963         u8 rx_qid_valid;
5964         u8 flow_id_valid;
5965         u8 filter_action;
5966         u8 assert_on_error;
5967         u8 inner_vlan_removal_en;
5968 };
5969
5970 /* Ramrod data for rx queue start ramrod */
5971 struct tx_queue_start_ramrod_data {
5972         __le16 sb_id;
5973         u8 sb_index;
5974         u8 vport_id;
5975         u8 reserved0;
5976         u8 stats_counter_id;
5977         __le16 qm_pq_id;
5978         u8 flags;
5979 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK   0x1
5980 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT  0
5981 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK       0x1
5982 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT      1
5983 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK       0x1
5984 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT      2
5985 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK                0x1
5986 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT               3
5987 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK               0x1
5988 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT              4
5989 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK             0x1
5990 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT            5
5991 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK               0x3
5992 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT              6
5993         u8 pxp_st_hint;
5994         u8 pxp_tph_valid_bd;
5995         u8 pxp_tph_valid_pkt;
5996         __le16 pxp_st_index;
5997         __le16 comp_agg_size;
5998         __le16 queue_zone_id;
5999         __le16 reserved2;
6000         __le16 pbl_size;
6001         __le16 tx_queue_id;
6002         __le16 same_as_last_id;
6003         __le16 reserved[3];
6004         struct regpair pbl_base_addr;
6005         struct regpair bd_cons_address;
6006 };
6007
6008 /* Ramrod data for tx queue stop ramrod */
6009 struct tx_queue_stop_ramrod_data {
6010         __le16 reserved[4];
6011 };
6012
6013 /* Ramrod data for tx queue update ramrod */
6014 struct tx_queue_update_ramrod_data {
6015         __le16 update_qm_pq_id_flg;
6016         __le16 qm_pq_id;
6017         __le32 reserved0;
6018         struct regpair reserved1[5];
6019 };
6020
6021 /* Ramrod data for vport update ramrod */
6022 struct vport_filter_update_ramrod_data {
6023         struct eth_filter_cmd_header filter_cmd_hdr;
6024         struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
6025 };
6026
6027 /* Ramrod data for vport start ramrod */
6028 struct vport_start_ramrod_data {
6029         u8 vport_id;
6030         u8 sw_fid;
6031         __le16 mtu;
6032         u8 drop_ttl0_en;
6033         u8 inner_vlan_removal_en;
6034         struct eth_vport_rx_mode rx_mode;
6035         struct eth_vport_tx_mode tx_mode;
6036         struct eth_vport_tpa_param tpa_param;
6037         __le16 default_vlan;
6038         u8 tx_switching_en;
6039         u8 anti_spoofing_en;
6040
6041         u8 default_vlan_en;
6042
6043         u8 handle_ptp_pkts;
6044         u8 silent_vlan_removal_en;
6045         u8 untagged;
6046         struct eth_tx_err_vals tx_err_behav;
6047
6048         u8 zero_placement_offset;
6049         u8 ctl_frame_mac_check_en;
6050         u8 ctl_frame_ethtype_check_en;
6051         u8 reserved[1];
6052 };
6053
6054 /* Ramrod data for vport stop ramrod */
6055 struct vport_stop_ramrod_data {
6056         u8 vport_id;
6057         u8 reserved[7];
6058 };
6059
6060 /* Ramrod data for vport update ramrod */
6061 struct vport_update_ramrod_data_cmn {
6062         u8 vport_id;
6063         u8 update_rx_active_flg;
6064         u8 rx_active_flg;
6065         u8 update_tx_active_flg;
6066         u8 tx_active_flg;
6067         u8 update_rx_mode_flg;
6068         u8 update_tx_mode_flg;
6069         u8 update_approx_mcast_flg;
6070
6071         u8 update_rss_flg;
6072         u8 update_inner_vlan_removal_en_flg;
6073
6074         u8 inner_vlan_removal_en;
6075         u8 update_tpa_param_flg;
6076         u8 update_tpa_en_flg;
6077         u8 update_tx_switching_en_flg;
6078
6079         u8 tx_switching_en;
6080         u8 update_anti_spoofing_en_flg;
6081
6082         u8 anti_spoofing_en;
6083         u8 update_handle_ptp_pkts;
6084
6085         u8 handle_ptp_pkts;
6086         u8 update_default_vlan_en_flg;
6087
6088         u8 default_vlan_en;
6089
6090         u8 update_default_vlan_flg;
6091
6092         __le16 default_vlan;
6093         u8 update_accept_any_vlan_flg;
6094
6095         u8 accept_any_vlan;
6096         u8 silent_vlan_removal_en;
6097         u8 update_mtu_flg;
6098
6099         __le16 mtu;
6100         u8 update_ctl_frame_checks_en_flg;
6101         u8 ctl_frame_mac_check_en;
6102         u8 ctl_frame_ethtype_check_en;
6103         u8 reserved[15];
6104 };
6105
6106 struct vport_update_ramrod_mcast {
6107         __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
6108 };
6109
6110 /* Ramrod data for vport update ramrod */
6111 struct vport_update_ramrod_data {
6112         struct vport_update_ramrod_data_cmn common;
6113
6114         struct eth_vport_rx_mode rx_mode;
6115         struct eth_vport_tx_mode tx_mode;
6116         __le32 reserved[3];
6117         struct eth_vport_tpa_param tpa_param;
6118         struct vport_update_ramrod_mcast approx_mcast;
6119         struct eth_vport_rss_config rss_config;
6120 };
6121
6122 struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart {
6123         u8 reserved0;
6124         u8 state;
6125         u8 flags0;
6126 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK       0x1
6127 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT      0
6128 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK          0x1
6129 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT         1
6130 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK          0x1
6131 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT         2
6132 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK       0x1
6133 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT      3
6134 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK          0x1
6135 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT         4
6136 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK          0x1
6137 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT         5
6138 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK          0x1
6139 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT         6
6140 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK          0x1
6141 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT         7
6142         u8 flags1;
6143 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK          0x1
6144 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT         0
6145 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK          0x1
6146 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT         1
6147 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK          0x1
6148 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT         2
6149 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK              0x1
6150 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT             3
6151 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK       0x1
6152 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT      4
6153 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK       0x1
6154 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT      5
6155 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK     0x1
6156 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT    6
6157 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK       0x1
6158 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT      7
6159         u8 flags2;
6160 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK        0x3
6161 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT       0
6162 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK        0x3
6163 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT       2
6164 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK        0x3
6165 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT       4
6166 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK        0x3
6167 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT       6
6168         u8 flags3;
6169 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK        0x3
6170 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT       0
6171 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK        0x3
6172 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT       2
6173 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK        0x3
6174 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT       4
6175 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK        0x3
6176 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT       6
6177         u8 flags4;
6178 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK        0x3
6179 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT       0
6180 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK        0x3
6181 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT       2
6182 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK       0x3
6183 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT      4
6184 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK       0x3
6185 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT      6
6186         u8 flags5;
6187 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK       0x3
6188 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT      0
6189 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK       0x3
6190 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT      2
6191 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK       0x3
6192 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT      4
6193 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK       0x3
6194 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT      6
6195         u8 flags6;
6196 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK   0x3
6197 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT  0
6198 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK   0x3
6199 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT  2
6200 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK              0x3
6201 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT             4
6202 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK       0x3
6203 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT      6
6204         u8 flags7;
6205 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK           0x3
6206 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT          0
6207 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK         0x3
6208 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT        2
6209 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK          0x3
6210 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT         4
6211 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK              0x1
6212 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT             6
6213 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK              0x1
6214 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT             7
6215         u8 flags8;
6216 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK      0x1
6217 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT     0
6218 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK      0x1
6219 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT     1
6220 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK      0x1
6221 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT     2
6222 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK      0x1
6223 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT     3
6224 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK      0x1
6225 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT     4
6226 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK      0x1
6227 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT     5
6228 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK      0x1
6229 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT     6
6230 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK      0x1
6231 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT     7
6232         u8 flags9;
6233 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK                     0x1
6234 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT                    0
6235 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK                     0x1
6236 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT                    1
6237 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK                     0x1
6238 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT                    2
6239 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK                     0x1
6240 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT                    3
6241 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK                     0x1
6242 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT                    4
6243 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK                     0x1
6244 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT                    5
6245 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK        0x1
6246 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT       6
6247 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK        0x1
6248 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT       7
6249         u8 flags10;
6250 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK                   0x1
6251 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT                  0
6252 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK            0x1
6253 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT           1
6254 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK                0x1
6255 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT               2
6256 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK                 0x1
6257 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT                3
6258 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK               0x1
6259 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT              4
6260 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK     0x1
6261 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT    5
6262 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK                 0x1
6263 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT                6
6264 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK                 0x1
6265 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT                7
6266         u8 flags11;
6267 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK         0x1
6268 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT        0
6269 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK         0x1
6270 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT        1
6271 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK     0x1
6272 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT    2
6273 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK            0x1
6274 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT           3
6275 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK            0x1
6276 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT           4
6277 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK            0x1
6278 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT           5
6279 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK       0x1
6280 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT      6
6281 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK            0x1
6282 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT           7
6283         u8 flags12;
6284 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK           0x1
6285 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT          0
6286 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK           0x1
6287 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT          1
6288 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK       0x1
6289 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT      2
6290 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK       0x1
6291 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT      3
6292 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK           0x1
6293 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT          4
6294 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK           0x1
6295 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT          5
6296 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK           0x1
6297 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT          6
6298 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK           0x1
6299 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT          7
6300         u8 flags13;
6301 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK           0x1
6302 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT          0
6303 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK           0x1
6304 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT          1
6305 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK       0x1
6306 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT      2
6307 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK       0x1
6308 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT      3
6309 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK       0x1
6310 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT      4
6311 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK       0x1
6312 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT      5
6313 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK       0x1
6314 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT      6
6315 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK       0x1
6316 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT      7
6317         u8 flags14;
6318 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK           0x1
6319 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT          0
6320 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK         0x1
6321 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT        1
6322 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK       0x1
6323 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT      2
6324 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK       0x1
6325 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT      3
6326 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK             0x1
6327 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT            4
6328 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK           0x1
6329 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT          5
6330 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK                 0x3
6331 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT                6
6332         u8 edpm_event_id;
6333         __le16 physical_q0;
6334         __le16 e5_reserved1;
6335         __le16 edpm_num_bds;
6336         __le16 tx_bd_cons;
6337         __le16 tx_bd_prod;
6338         __le16 updated_qm_pq_id;
6339         __le16 conn_dpi;
6340         u8 byte3;
6341         u8 byte4;
6342         u8 byte5;
6343         u8 byte6;
6344         __le32 reg0;
6345         __le32 reg1;
6346         __le32 reg2;
6347         __le32 reg3;
6348         __le32 reg4;
6349 };
6350
6351 struct e4_mstorm_eth_conn_ag_ctx {
6352         u8 byte0;
6353         u8 byte1;
6354         u8 flags0;
6355 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK     0x1
6356 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
6357 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK             0x1
6358 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT            1
6359 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK              0x3
6360 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT             2
6361 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK              0x3
6362 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT             4
6363 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK              0x3
6364 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT             6
6365         u8 flags1;
6366 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK    0x1
6367 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT   0
6368 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK    0x1
6369 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT   1
6370 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK    0x1
6371 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT   2
6372 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK  0x1
6373 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
6374 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK  0x1
6375 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
6376 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK  0x1
6377 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
6378 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK  0x1
6379 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
6380 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK  0x1
6381 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
6382         __le16 word0;
6383         __le16 word1;
6384         __le32 reg0;
6385         __le32 reg1;
6386 };
6387
6388 struct e4_xstorm_eth_hw_conn_ag_ctx {
6389         u8 reserved0;
6390         u8 state;
6391         u8 flags0;
6392 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK  0x1
6393 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6394 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK     0x1
6395 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT    1
6396 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK     0x1
6397 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT    2
6398 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK  0x1
6399 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
6400 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK     0x1
6401 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT    4
6402 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK     0x1
6403 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT    5
6404 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK     0x1
6405 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT    6
6406 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK     0x1
6407 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT    7
6408         u8 flags1;
6409 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK             0x1
6410 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT            0
6411 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK             0x1
6412 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT            1
6413 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK             0x1
6414 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT            2
6415 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK                 0x1
6416 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT                3
6417 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK          0x1
6418 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT         4
6419 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK          0x1
6420 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT         5
6421 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK        0x1
6422 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT       6
6423 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK          0x1
6424 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT         7
6425         u8 flags2;
6426 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK   0x3
6427 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT  0
6428 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK   0x3
6429 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT  2
6430 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK   0x3
6431 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT  4
6432 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK   0x3
6433 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT  6
6434         u8 flags3;
6435 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK   0x3
6436 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT  0
6437 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK   0x3
6438 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT  2
6439 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK   0x3
6440 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT  4
6441 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK   0x3
6442 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT  6
6443         u8 flags4;
6444 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK   0x3
6445 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT  0
6446 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK   0x3
6447 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT  2
6448 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK  0x3
6449 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
6450 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK  0x3
6451 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
6452         u8 flags5;
6453 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK  0x3
6454 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
6455 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK  0x3
6456 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
6457 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK  0x3
6458 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
6459 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK  0x3
6460 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
6461         u8 flags6;
6462 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK      0x3
6463 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT     0
6464 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK      0x3
6465 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT     2
6466 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK                 0x3
6467 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT                4
6468 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK          0x3
6469 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT         6
6470         u8 flags7;
6471 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK      0x3
6472 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT     0
6473 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK    0x3
6474 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT   2
6475 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK     0x3
6476 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT    4
6477 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK         0x1
6478 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT        6
6479 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK         0x1
6480 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT        7
6481         u8 flags8;
6482 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK         0x1
6483 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT        0
6484 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK         0x1
6485 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT        1
6486 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK         0x1
6487 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT        2
6488 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK         0x1
6489 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT        3
6490 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK         0x1
6491 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT        4
6492 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK         0x1
6493 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT        5
6494 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK         0x1
6495 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT        6
6496 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK         0x1
6497 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT        7
6498         u8 flags9;
6499 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK                0x1
6500 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT               0
6501 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK                0x1
6502 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT               1
6503 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK                0x1
6504 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT               2
6505 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK                0x1
6506 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT               3
6507 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK                0x1
6508 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT               4
6509 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK                0x1
6510 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT               5
6511 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK   0x1
6512 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT  6
6513 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK   0x1
6514 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT  7
6515         u8 flags10;
6516 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK                      0x1
6517 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT                     0
6518 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK               0x1
6519 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT              1
6520 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK                   0x1
6521 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT                  2
6522 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK                    0x1
6523 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT                   3
6524 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK                  0x1
6525 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT                 4
6526 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK        0x1
6527 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT       5
6528 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK                    0x1
6529 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT                   6
6530 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK                    0x1
6531 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT                   7
6532         u8 flags11;
6533 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK            0x1
6534 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT           0
6535 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK            0x1
6536 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT           1
6537 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK        0x1
6538 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT       2
6539 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK               0x1
6540 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT              3
6541 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK               0x1
6542 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT              4
6543 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK               0x1
6544 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT              5
6545 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK          0x1
6546 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT         6
6547 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK               0x1
6548 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT              7
6549         u8 flags12;
6550 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK      0x1
6551 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT     0
6552 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK      0x1
6553 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT     1
6554 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK  0x1
6555 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
6556 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK  0x1
6557 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
6558 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK      0x1
6559 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT     4
6560 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK      0x1
6561 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT     5
6562 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK      0x1
6563 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT     6
6564 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK      0x1
6565 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT     7
6566         u8 flags13;
6567 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK      0x1
6568 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT     0
6569 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK      0x1
6570 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT     1
6571 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK  0x1
6572 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
6573 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK  0x1
6574 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
6575 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK  0x1
6576 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
6577 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK  0x1
6578 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
6579 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK  0x1
6580 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
6581 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK  0x1
6582 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
6583         u8 flags14;
6584 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK      0x1
6585 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT     0
6586 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK    0x1
6587 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT   1
6588 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK  0x1
6589 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
6590 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK  0x1
6591 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
6592 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK        0x1
6593 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT       4
6594 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK      0x1
6595 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT     5
6596 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK            0x3
6597 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT           6
6598         u8 edpm_event_id;
6599         __le16 physical_q0;
6600         __le16 e5_reserved1;
6601         __le16 edpm_num_bds;
6602         __le16 tx_bd_cons;
6603         __le16 tx_bd_prod;
6604         __le16 updated_qm_pq_id;
6605         __le16 conn_dpi;
6606 };
6607
6608 /* GFT CAM line struct */
6609 struct gft_cam_line {
6610         __le32 camline;
6611 #define GFT_CAM_LINE_VALID_MASK         0x1
6612 #define GFT_CAM_LINE_VALID_SHIFT        0
6613 #define GFT_CAM_LINE_DATA_MASK          0x3FFF
6614 #define GFT_CAM_LINE_DATA_SHIFT         1
6615 #define GFT_CAM_LINE_MASK_BITS_MASK     0x3FFF
6616 #define GFT_CAM_LINE_MASK_BITS_SHIFT    15
6617 #define GFT_CAM_LINE_RESERVED1_MASK     0x7
6618 #define GFT_CAM_LINE_RESERVED1_SHIFT    29
6619 };
6620
6621 /* GFT CAM line struct with fields breakout */
6622 struct gft_cam_line_mapped {
6623         __le32 camline;
6624 #define GFT_CAM_LINE_MAPPED_VALID_MASK                          0x1
6625 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT                         0
6626 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK                     0x1
6627 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT                    1
6628 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK              0x1
6629 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT             2
6630 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK            0xF
6631 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT           3
6632 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK                    0xF
6633 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT                   7
6634 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK                          0xF
6635 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT                         11
6636 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK                0x1
6637 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT               15
6638 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK         0x1
6639 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT        16
6640 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK       0xF
6641 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT      17
6642 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK               0xF
6643 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT              21
6644 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK                     0xF
6645 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT                    25
6646 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK                      0x7
6647 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT                     29
6648 };
6649
6650 union gft_cam_line_union {
6651         struct gft_cam_line cam_line;
6652         struct gft_cam_line_mapped cam_line_mapped;
6653 };
6654
6655 /* Used in gft_profile_key: Indication for ip version */
6656 enum gft_profile_ip_version {
6657         GFT_PROFILE_IPV4 = 0,
6658         GFT_PROFILE_IPV6 = 1,
6659         MAX_GFT_PROFILE_IP_VERSION
6660 };
6661
6662 /* Profile key stucr fot GFT logic in Prs */
6663 struct gft_profile_key {
6664         __le16 profile_key;
6665 #define GFT_PROFILE_KEY_IP_VERSION_MASK                 0x1
6666 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT                0
6667 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK          0x1
6668 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT         1
6669 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK        0xF
6670 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT       2
6671 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK                0xF
6672 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT               6
6673 #define GFT_PROFILE_KEY_PF_ID_MASK                      0xF
6674 #define GFT_PROFILE_KEY_PF_ID_SHIFT                     10
6675 #define GFT_PROFILE_KEY_RESERVED0_MASK                  0x3
6676 #define GFT_PROFILE_KEY_RESERVED0_SHIFT                 14
6677 };
6678
6679 /* Used in gft_profile_key: Indication for tunnel type */
6680 enum gft_profile_tunnel_type {
6681         GFT_PROFILE_NO_TUNNEL = 0,
6682         GFT_PROFILE_VXLAN_TUNNEL = 1,
6683         GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
6684         GFT_PROFILE_GRE_IP_TUNNEL = 3,
6685         GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
6686         GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
6687         MAX_GFT_PROFILE_TUNNEL_TYPE
6688 };
6689
6690 /* Used in gft_profile_key: Indication for protocol type */
6691 enum gft_profile_upper_protocol_type {
6692         GFT_PROFILE_ROCE_PROTOCOL = 0,
6693         GFT_PROFILE_RROCE_PROTOCOL = 1,
6694         GFT_PROFILE_FCOE_PROTOCOL = 2,
6695         GFT_PROFILE_ICMP_PROTOCOL = 3,
6696         GFT_PROFILE_ARP_PROTOCOL = 4,
6697         GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
6698         GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
6699         GFT_PROFILE_TCP_PROTOCOL = 7,
6700         GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
6701         GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
6702         GFT_PROFILE_UDP_PROTOCOL = 10,
6703         GFT_PROFILE_USER_IP_1_INNER = 11,
6704         GFT_PROFILE_USER_IP_2_OUTER = 12,
6705         GFT_PROFILE_USER_ETH_1_INNER = 13,
6706         GFT_PROFILE_USER_ETH_2_OUTER = 14,
6707         GFT_PROFILE_RAW = 15,
6708         MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
6709 };
6710
6711 /* GFT RAM line struct */
6712 struct gft_ram_line {
6713         __le32 lo;
6714 #define GFT_RAM_LINE_VLAN_SELECT_MASK                   0x3
6715 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT                  0
6716 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK               0x1
6717 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT              2
6718 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK          0x1
6719 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT         3
6720 #define GFT_RAM_LINE_TUNNEL_TTL_MASK                    0x1
6721 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT                   4
6722 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK              0x1
6723 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT             5
6724 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK               0x1
6725 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT              6
6726 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK               0x1
6727 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT              7
6728 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK                   0x1
6729 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT                  8
6730 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK       0x1
6731 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT      9
6732 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK                 0x1
6733 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT                10
6734 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK                 0x1
6735 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT                11
6736 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK               0x1
6737 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT              12
6738 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK          0x1
6739 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT         13
6740 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK                   0x1
6741 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT                  14
6742 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK                0x1
6743 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT               15
6744 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK                0x1
6745 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT               16
6746 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK                 0x1
6747 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT                17
6748 #define GFT_RAM_LINE_TTL_MASK                           0x1
6749 #define GFT_RAM_LINE_TTL_SHIFT                          18
6750 #define GFT_RAM_LINE_ETHERTYPE_MASK                     0x1
6751 #define GFT_RAM_LINE_ETHERTYPE_SHIFT                    19
6752 #define GFT_RAM_LINE_RESERVED0_MASK                     0x1
6753 #define GFT_RAM_LINE_RESERVED0_SHIFT                    20
6754 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK                  0x1
6755 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT                 21
6756 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK                  0x1
6757 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT                 22
6758 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK                  0x1
6759 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT                 23
6760 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK                  0x1
6761 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT                 24
6762 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK                  0x1
6763 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT                 25
6764 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK                  0x1
6765 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT                 26
6766 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK                  0x1
6767 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT                 27
6768 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK                  0x1
6769 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT                 28
6770 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK                   0x1
6771 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT                  29
6772 #define GFT_RAM_LINE_DST_PORT_MASK                      0x1
6773 #define GFT_RAM_LINE_DST_PORT_SHIFT                     30
6774 #define GFT_RAM_LINE_SRC_PORT_MASK                      0x1
6775 #define GFT_RAM_LINE_SRC_PORT_SHIFT                     31
6776         __le32 hi;
6777 #define GFT_RAM_LINE_DSCP_MASK                          0x1
6778 #define GFT_RAM_LINE_DSCP_SHIFT                         0
6779 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK              0x1
6780 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT             1
6781 #define GFT_RAM_LINE_DST_IP_MASK                        0x1
6782 #define GFT_RAM_LINE_DST_IP_SHIFT                       2
6783 #define GFT_RAM_LINE_SRC_IP_MASK                        0x1
6784 #define GFT_RAM_LINE_SRC_IP_SHIFT                       3
6785 #define GFT_RAM_LINE_PRIORITY_MASK                      0x1
6786 #define GFT_RAM_LINE_PRIORITY_SHIFT                     4
6787 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK                 0x1
6788 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT                5
6789 #define GFT_RAM_LINE_VLAN_MASK                          0x1
6790 #define GFT_RAM_LINE_VLAN_SHIFT                         6
6791 #define GFT_RAM_LINE_DST_MAC_MASK                       0x1
6792 #define GFT_RAM_LINE_DST_MAC_SHIFT                      7
6793 #define GFT_RAM_LINE_SRC_MAC_MASK                       0x1
6794 #define GFT_RAM_LINE_SRC_MAC_SHIFT                      8
6795 #define GFT_RAM_LINE_TENANT_ID_MASK                     0x1
6796 #define GFT_RAM_LINE_TENANT_ID_SHIFT                    9
6797 #define GFT_RAM_LINE_RESERVED1_MASK                     0x3FFFFF
6798 #define GFT_RAM_LINE_RESERVED1_SHIFT                    10
6799 };
6800
6801 /* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */
6802 enum gft_vlan_select {
6803         INNER_PROVIDER_VLAN = 0,
6804         INNER_VLAN = 1,
6805         OUTER_PROVIDER_VLAN = 2,
6806         OUTER_VLAN = 3,
6807         MAX_GFT_VLAN_SELECT
6808 };
6809
6810 /* The rdma task context of Mstorm */
6811 struct ystorm_rdma_task_st_ctx {
6812         struct regpair temp[4];
6813 };
6814
6815 struct e4_ystorm_rdma_task_ag_ctx {
6816         u8 reserved;
6817         u8 byte1;
6818         __le16 msem_ctx_upd_seq;
6819         u8 flags0;
6820 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF
6821 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
6822 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1
6823 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
6824 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK                    0x1
6825 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT                   5
6826 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK                   0x1
6827 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT                  6
6828 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK            0x1
6829 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT           7
6830         u8 flags1;
6831 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK             0x3
6832 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT            0
6833 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK             0x3
6834 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT            2
6835 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK      0x3
6836 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT     4
6837 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK           0x1
6838 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT          6
6839 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK           0x1
6840 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT          7
6841         u8 flags2;
6842 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK            0x1
6843 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT           0
6844 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK         0x1
6845 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT        1
6846 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK         0x1
6847 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT        2
6848 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK         0x1
6849 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT        3
6850 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK         0x1
6851 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT        4
6852 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK         0x1
6853 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT        5
6854 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK         0x1
6855 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT        6
6856 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK         0x1
6857 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT        7
6858         u8 key;
6859         __le32 mw_cnt_or_qp_id;
6860         u8 ref_cnt_seq;
6861         u8 ctx_upd_seq;
6862         __le16 dif_flags;
6863         __le16 tx_ref_count;
6864         __le16 last_used_ltid;
6865         __le16 parent_mr_lo;
6866         __le16 parent_mr_hi;
6867         __le32 fbo_lo;
6868         __le32 fbo_hi;
6869 };
6870
6871 struct e4_mstorm_rdma_task_ag_ctx {
6872         u8 reserved;
6873         u8 byte1;
6874         __le16 icid;
6875         u8 flags0;
6876 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF
6877 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
6878 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1
6879 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
6880 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK                    0x1
6881 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT                   5
6882 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK                    0x1
6883 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT                   6
6884 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK            0x1
6885 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT           7
6886         u8 flags1;
6887 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK     0x3
6888 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT    0
6889 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK     0x3
6890 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT    2
6891 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK     0x3
6892 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT    4
6893 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK   0x1
6894 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT  6
6895 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK   0x1
6896 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT  7
6897         u8 flags2;
6898 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK           0x1
6899 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT          0
6900 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK         0x1
6901 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT        1
6902 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK         0x1
6903 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT        2
6904 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK         0x1
6905 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT        3
6906 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK         0x1
6907 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT        4
6908 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK         0x1
6909 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT        5
6910 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK         0x1
6911 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT        6
6912 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK         0x1
6913 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT        7
6914         u8 key;
6915         __le32 mw_cnt_or_qp_id;
6916         u8 ref_cnt_seq;
6917         u8 ctx_upd_seq;
6918         __le16 dif_flags;
6919         __le16 tx_ref_count;
6920         __le16 last_used_ltid;
6921         __le16 parent_mr_lo;
6922         __le16 parent_mr_hi;
6923         __le32 fbo_lo;
6924         __le32 fbo_hi;
6925 };
6926
6927 /* The roce task context of Mstorm */
6928 struct mstorm_rdma_task_st_ctx {
6929         struct regpair temp[4];
6930 };
6931
6932 /* The roce task context of Ustorm */
6933 struct ustorm_rdma_task_st_ctx {
6934         struct regpair temp[2];
6935 };
6936
6937 struct e4_ustorm_rdma_task_ag_ctx {
6938         u8 reserved;
6939         u8 state;
6940         __le16 icid;
6941         u8 flags0;
6942 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF
6943 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
6944 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1
6945 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
6946 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK          0x1
6947 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT         5
6948 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK     0x3
6949 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT    6
6950         u8 flags1;
6951 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK   0x3
6952 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT  0
6953 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK           0x3
6954 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT          2
6955 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK          0x3
6956 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT         4
6957 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK            0x3
6958 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT           6
6959         u8 flags2;
6960 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK  0x1
6961 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
6962 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK               0x1
6963 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT              1
6964 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK               0x1
6965 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT              2
6966 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK               0x1
6967 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT              3
6968 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK         0x1
6969 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT        4
6970 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK                 0x1
6971 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT                5
6972 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK                 0x1
6973 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT                6
6974 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK                 0x1
6975 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT                7
6976         u8 flags3;
6977 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK         0x1
6978 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT        0
6979 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK         0x1
6980 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT        1
6981 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK         0x1
6982 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT        2
6983 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK         0x1
6984 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT        3
6985 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK  0xF
6986 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
6987         __le32 dif_err_intervals;
6988         __le32 dif_error_1st_interval;
6989         __le32 sq_cons;
6990         __le32 dif_runt_value;
6991         __le32 sge_index;
6992         __le32 reg5;
6993         u8 byte2;
6994         u8 byte3;
6995         __le16 word1;
6996         __le16 word2;
6997         __le16 word3;
6998         __le32 reg6;
6999         __le32 reg7;
7000 };
7001
7002 /* RDMA task context */
7003 struct e4_rdma_task_context {
7004         struct ystorm_rdma_task_st_ctx ystorm_st_context;
7005         struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context;
7006         struct tdif_task_context tdif_context;
7007         struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context;
7008         struct mstorm_rdma_task_st_ctx mstorm_st_context;
7009         struct rdif_task_context rdif_context;
7010         struct ustorm_rdma_task_st_ctx ustorm_st_context;
7011         struct regpair ustorm_st_padding[2];
7012         struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context;
7013 };
7014
7015 /* rdma function init ramrod data */
7016 struct rdma_close_func_ramrod_data {
7017         u8 cnq_start_offset;
7018         u8 num_cnqs;
7019         u8 vf_id;
7020         u8 vf_valid;
7021         u8 reserved[4];
7022 };
7023
7024 /* rdma function init CNQ parameters */
7025 struct rdma_cnq_params {
7026         __le16 sb_num;
7027         u8 sb_index;
7028         u8 num_pbl_pages;
7029         __le32 reserved;
7030         struct regpair pbl_base_addr;
7031         __le16 queue_zone_num;
7032         u8 reserved1[6];
7033 };
7034
7035 /* rdma create cq ramrod data */
7036 struct rdma_create_cq_ramrod_data {
7037         struct regpair cq_handle;
7038         struct regpair pbl_addr;
7039         __le32 max_cqes;
7040         __le16 pbl_num_pages;
7041         __le16 dpi;
7042         u8 is_two_level_pbl;
7043         u8 cnq_id;
7044         u8 pbl_log_page_size;
7045         u8 toggle_bit;
7046         __le16 int_timeout;
7047         __le16 reserved1;
7048 };
7049
7050 /* rdma deregister tid ramrod data */
7051 struct rdma_deregister_tid_ramrod_data {
7052         __le32 itid;
7053         __le32 reserved;
7054 };
7055
7056 /* rdma destroy cq output params */
7057 struct rdma_destroy_cq_output_params {
7058         __le16 cnq_num;
7059         __le16 reserved0;
7060         __le32 reserved1;
7061 };
7062
7063 /* rdma destroy cq ramrod data */
7064 struct rdma_destroy_cq_ramrod_data {
7065         struct regpair output_params_addr;
7066 };
7067
7068 /* RDMA slow path EQ cmd IDs */
7069 enum rdma_event_opcode {
7070         RDMA_EVENT_UNUSED,
7071         RDMA_EVENT_FUNC_INIT,
7072         RDMA_EVENT_FUNC_CLOSE,
7073         RDMA_EVENT_REGISTER_MR,
7074         RDMA_EVENT_DEREGISTER_MR,
7075         RDMA_EVENT_CREATE_CQ,
7076         RDMA_EVENT_RESIZE_CQ,
7077         RDMA_EVENT_DESTROY_CQ,
7078         RDMA_EVENT_CREATE_SRQ,
7079         RDMA_EVENT_MODIFY_SRQ,
7080         RDMA_EVENT_DESTROY_SRQ,
7081         MAX_RDMA_EVENT_OPCODE
7082 };
7083
7084 /* RDMA FW return code for slow path ramrods */
7085 enum rdma_fw_return_code {
7086         RDMA_RETURN_OK = 0,
7087         RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
7088         RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
7089         RDMA_RETURN_RESIZE_CQ_ERR,
7090         RDMA_RETURN_NIG_DRAIN_REQ,
7091         MAX_RDMA_FW_RETURN_CODE
7092 };
7093
7094 /* rdma function init header */
7095 struct rdma_init_func_hdr {
7096         u8 cnq_start_offset;
7097         u8 num_cnqs;
7098         u8 cq_ring_mode;
7099         u8 vf_id;
7100         u8 vf_valid;
7101         u8 relaxed_ordering;
7102         __le16 first_reg_srq_id;
7103         __le32 reg_srq_base_addr;
7104         __le32 reserved;
7105 };
7106
7107 /* rdma function init ramrod data */
7108 struct rdma_init_func_ramrod_data {
7109         struct rdma_init_func_hdr params_header;
7110         struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
7111 };
7112
7113 /* RDMA ramrod command IDs */
7114 enum rdma_ramrod_cmd_id {
7115         RDMA_RAMROD_UNUSED,
7116         RDMA_RAMROD_FUNC_INIT,
7117         RDMA_RAMROD_FUNC_CLOSE,
7118         RDMA_RAMROD_REGISTER_MR,
7119         RDMA_RAMROD_DEREGISTER_MR,
7120         RDMA_RAMROD_CREATE_CQ,
7121         RDMA_RAMROD_RESIZE_CQ,
7122         RDMA_RAMROD_DESTROY_CQ,
7123         RDMA_RAMROD_CREATE_SRQ,
7124         RDMA_RAMROD_MODIFY_SRQ,
7125         RDMA_RAMROD_DESTROY_SRQ,
7126         MAX_RDMA_RAMROD_CMD_ID
7127 };
7128
7129 /* rdma register tid ramrod data */
7130 struct rdma_register_tid_ramrod_data {
7131         __le16 flags;
7132 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK        0x1F
7133 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT       0
7134 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK        0x1
7135 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT       5
7136 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK           0x1
7137 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT          6
7138 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK               0x1
7139 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT              7
7140 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK          0x1
7141 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT         8
7142 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK         0x1
7143 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT        9
7144 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK        0x1
7145 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT       10
7146 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK          0x1
7147 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT         11
7148 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK           0x1
7149 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT          12
7150 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK       0x1
7151 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT      13
7152 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK             0x3
7153 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT            14
7154         u8 flags1;
7155 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK    0x1F
7156 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT   0
7157 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK             0x7
7158 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT            5
7159         u8 flags2;
7160 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK               0x1
7161 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT              0
7162 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK      0x1
7163 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT     1
7164 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK            0x3F
7165 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT           2
7166         u8 key;
7167         u8 length_hi;
7168         u8 vf_id;
7169         u8 vf_valid;
7170         __le16 pd;
7171         __le16 reserved2;
7172         __le32 length_lo;
7173         __le32 itid;
7174         __le32 reserved3;
7175         struct regpair va;
7176         struct regpair pbl_base;
7177         struct regpair dif_error_addr;
7178         __le32 reserved4[4];
7179 };
7180
7181 /* rdma resize cq output params */
7182 struct rdma_resize_cq_output_params {
7183         __le32 old_cq_cons;
7184         __le32 old_cq_prod;
7185 };
7186
7187 /* rdma resize cq ramrod data */
7188 struct rdma_resize_cq_ramrod_data {
7189         u8 flags;
7190 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK              0x1
7191 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT             0
7192 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK        0x1
7193 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT       1
7194 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK                0x3F
7195 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT               2
7196         u8 pbl_log_page_size;
7197         __le16 pbl_num_pages;
7198         __le32 max_cqes;
7199         struct regpair pbl_addr;
7200         struct regpair output_params_addr;
7201 };
7202
7203 /* The rdma storm context of Mstorm */
7204 struct rdma_srq_context {
7205         struct regpair temp[8];
7206 };
7207
7208 /* rdma create qp requester ramrod data */
7209 struct rdma_srq_create_ramrod_data {
7210         u8 flags;
7211 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK         0x1
7212 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT        0
7213 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK  0x1
7214 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1
7215 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK        0x3F
7216 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT       2
7217         u8 reserved2;
7218         __le16 xrc_domain;
7219         __le32 xrc_srq_cq_cid;
7220         struct regpair pbl_base_addr;
7221         __le16 pages_in_srq_pbl;
7222         __le16 pd_id;
7223         struct rdma_srq_id srq_id;
7224         __le16 page_size;
7225         __le16 reserved3;
7226         __le32 reserved4;
7227         struct regpair producers_addr;
7228 };
7229
7230 /* rdma create qp requester ramrod data */
7231 struct rdma_srq_destroy_ramrod_data {
7232         struct rdma_srq_id srq_id;
7233         __le32 reserved;
7234 };
7235
7236 /* rdma create qp requester ramrod data */
7237 struct rdma_srq_modify_ramrod_data {
7238         struct rdma_srq_id srq_id;
7239         __le32 wqe_limit;
7240 };
7241
7242 /* RDMA Tid type enumeration (for register_tid ramrod) */
7243 enum rdma_tid_type {
7244         RDMA_TID_REGISTERED_MR,
7245         RDMA_TID_FMR,
7246         RDMA_TID_MW,
7247         MAX_RDMA_TID_TYPE
7248 };
7249
7250 struct rdma_xrc_srq_context {
7251         struct regpair temp[9];
7252 };
7253
7254 struct e4_tstorm_rdma_task_ag_ctx {
7255         u8 byte0;
7256         u8 byte1;
7257         __le16 word0;
7258         u8 flags0;
7259 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK         0xF
7260 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT        0
7261 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK            0x1
7262 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT           4
7263 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK            0x1
7264 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT           5
7265 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK            0x1
7266 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT           6
7267 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK            0x1
7268 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT           7
7269         u8 flags1;
7270 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK    0x1
7271 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT   0
7272 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK    0x1
7273 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT   1
7274 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK     0x3
7275 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT    2
7276 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK     0x3
7277 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT    4
7278 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK     0x3
7279 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT    6
7280         u8 flags2;
7281 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK     0x3
7282 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT    0
7283 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK     0x3
7284 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT    2
7285 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK     0x3
7286 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT    4
7287 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK     0x3
7288 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT    6
7289         u8 flags3;
7290 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK     0x3
7291 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT    0
7292 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK   0x1
7293 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT  2
7294 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK   0x1
7295 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT  3
7296 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK   0x1
7297 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT  4
7298 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK   0x1
7299 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT  5
7300 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK   0x1
7301 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT  6
7302 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK   0x1
7303 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT  7
7304         u8 flags4;
7305 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK           0x1
7306 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT          0
7307 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK           0x1
7308 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT          1
7309 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK         0x1
7310 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT        2
7311 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK         0x1
7312 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT        3
7313 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK         0x1
7314 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT        4
7315 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK         0x1
7316 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT        5
7317 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK         0x1
7318 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT        6
7319 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK         0x1
7320 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT        7
7321         u8 byte2;
7322         __le16 word1;
7323         __le32 reg0;
7324         u8 byte3;
7325         u8 byte4;
7326         __le16 word2;
7327         __le16 word3;
7328         __le16 word4;
7329         __le32 reg1;
7330         __le32 reg2;
7331 };
7332
7333 struct e4_ustorm_rdma_conn_ag_ctx {
7334         u8 reserved;
7335         u8 byte1;
7336         u8 flags0;
7337 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK    0x1
7338 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT   0
7339 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK  0x1
7340 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1
7341 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK     0x3
7342 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT    2
7343 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK             0x3
7344 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT            4
7345 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK             0x3
7346 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT            6
7347         u8 flags1;
7348 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK             0x3
7349 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT            0
7350 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK    0x3
7351 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT   2
7352 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK       0x3
7353 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT      4
7354 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK             0x3
7355 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT            6
7356         u8 flags2;
7357 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK          0x1
7358 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT         0
7359 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK                   0x1
7360 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT                  1
7361 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK                   0x1
7362 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT                  2
7363 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK                   0x1
7364 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT                  3
7365 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK         0x1
7366 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT        4
7367 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK            0x1
7368 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT           5
7369 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK                   0x1
7370 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT                  6
7371 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK                0x1
7372 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT               7
7373         u8 flags3;
7374 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK           0x1
7375 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT          0
7376 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK         0x1
7377 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT        1
7378 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK         0x1
7379 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT        2
7380 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK         0x1
7381 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT        3
7382 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK         0x1
7383 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT        4
7384 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK         0x1
7385 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT        5
7386 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK         0x1
7387 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT        6
7388 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK         0x1
7389 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT        7
7390         u8 byte2;
7391         u8 byte3;
7392         __le16 conn_dpi;
7393         __le16 word1;
7394         __le32 cq_cons;
7395         __le32 cq_se_prod;
7396         __le32 cq_prod;
7397         __le32 reg3;
7398         __le16 int_timeout;
7399         __le16 word3;
7400 };
7401
7402 struct e4_xstorm_roce_conn_ag_ctx {
7403         u8 reserved0;
7404         u8 state;
7405         u8 flags0;
7406 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1
7407 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
7408 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK              0x1
7409 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT             1
7410 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK              0x1
7411 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT             2
7412 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1
7413 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
7414 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK              0x1
7415 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT             4
7416 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK              0x1
7417 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT             5
7418 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK              0x1
7419 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT             6
7420 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK              0x1
7421 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT             7
7422         u8 flags1;
7423 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK              0x1
7424 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT             0
7425 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK              0x1
7426 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT             1
7427 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK             0x1
7428 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT            2
7429 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK             0x1
7430 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT            3
7431 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_MASK             0x1
7432 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_SHIFT            4
7433 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK        0x1
7434 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT       5
7435 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK        0x1
7436 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT       6
7437 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1
7438 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
7439         u8 flags2;
7440 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_MASK               0x3
7441 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT              0
7442 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_MASK               0x3
7443 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT              2
7444 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_MASK               0x3
7445 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT              4
7446 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_MASK               0x3
7447 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT              6
7448         u8 flags3;
7449 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_MASK               0x3
7450 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT              0
7451 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_MASK               0x3
7452 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT              2
7453 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_MASK               0x3
7454 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT              4
7455 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3
7456 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
7457         u8 flags4;
7458 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_MASK               0x3
7459 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT              0
7460 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_MASK               0x3
7461 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT              2
7462 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_MASK              0x3
7463 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT             4
7464 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_MASK              0x3
7465 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT             6
7466         u8 flags5;
7467 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_MASK              0x3
7468 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT             0
7469 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_MASK              0x3
7470 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT             2
7471 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_MASK              0x3
7472 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT             4
7473 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_MASK              0x3
7474 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT             6
7475         u8 flags6;
7476 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_MASK              0x3
7477 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT             0
7478 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_MASK              0x3
7479 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT             2
7480 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_MASK              0x3
7481 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT             4
7482 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_MASK              0x3
7483 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT             6
7484         u8 flags7;
7485 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_MASK              0x3
7486 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT             0
7487 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_MASK              0x3
7488 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT             2
7489 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK         0x3
7490 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT        4
7491 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK             0x1
7492 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT            6
7493 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK             0x1
7494 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT            7
7495         u8 flags8;
7496 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK             0x1
7497 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT            0
7498 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK             0x1
7499 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT            1
7500 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK             0x1
7501 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT            2
7502 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK             0x1
7503 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT            3
7504 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK             0x1
7505 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT            4
7506 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1
7507 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
7508 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK             0x1
7509 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT            6
7510 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK             0x1
7511 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT            7
7512         u8 flags9;
7513 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK            0x1
7514 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT           0
7515 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK            0x1
7516 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT           1
7517 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK            0x1
7518 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT           2
7519 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK            0x1
7520 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT           3
7521 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK            0x1
7522 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT           4
7523 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK            0x1
7524 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT           5
7525 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK            0x1
7526 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT           6
7527 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK            0x1
7528 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT           7
7529         u8 flags10;
7530 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK            0x1
7531 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT           0
7532 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK            0x1
7533 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT           1
7534 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK            0x1
7535 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT           2
7536 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK            0x1
7537 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT           3
7538 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1
7539 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
7540 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK            0x1
7541 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT           5
7542 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK           0x1
7543 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT          6
7544 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK           0x1
7545 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT          7
7546         u8 flags11;
7547 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK           0x1
7548 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT          0
7549 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK           0x1
7550 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT          1
7551 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK           0x1
7552 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT          2
7553 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK           0x1
7554 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT          3
7555 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK           0x1
7556 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT          4
7557 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK           0x1
7558 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT          5
7559 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK      0x1
7560 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
7561 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK           0x1
7562 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT          7
7563         u8 flags12;
7564 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK          0x1
7565 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT         0
7566 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK          0x1
7567 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT         1
7568 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK      0x1
7569 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
7570 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK      0x1
7571 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
7572 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK          0x1
7573 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT         4
7574 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK          0x1
7575 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT         5
7576 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK          0x1
7577 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT         6
7578 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK          0x1
7579 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT         7
7580         u8 flags13;
7581 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK          0x1
7582 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT         0
7583 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK          0x1
7584 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT         1
7585 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK      0x1
7586 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
7587 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK      0x1
7588 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
7589 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK      0x1
7590 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
7591 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK      0x1
7592 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
7593 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK      0x1
7594 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
7595 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK      0x1
7596 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
7597         u8 flags14;
7598 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK         0x1
7599 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT        0
7600 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK             0x1
7601 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT            1
7602 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK      0x3
7603 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT     2
7604 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK          0x1
7605 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT         4
7606 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK  0x1
7607 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
7608 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_MASK              0x3
7609 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT             6
7610         u8 byte2;
7611         __le16 physical_q0;
7612         __le16 word1;
7613         __le16 word2;
7614         __le16 word3;
7615         __le16 word4;
7616         __le16 word5;
7617         __le16 conn_dpi;
7618         u8 byte3;
7619         u8 byte4;
7620         u8 byte5;
7621         u8 byte6;
7622         __le32 reg0;
7623         __le32 reg1;
7624         __le32 reg2;
7625         __le32 snd_nxt_psn;
7626         __le32 reg4;
7627         __le32 reg5;
7628         __le32 reg6;
7629 };
7630
7631 struct e4_tstorm_roce_conn_ag_ctx {
7632         u8 reserved0;
7633         u8 byte1;
7634         u8 flags0;
7635 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1
7636 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
7637 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK                  0x1
7638 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT                 1
7639 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK                  0x1
7640 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT                 2
7641 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK                  0x1
7642 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT                 3
7643 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK                  0x1
7644 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT                 4
7645 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK                  0x1
7646 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT                 5
7647 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_MASK                   0x3
7648 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT                  6
7649         u8 flags1;
7650 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK       0x3
7651 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT      0
7652 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_MASK                   0x3
7653 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT                  2
7654 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3
7655 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
7656 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3
7657 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          6
7658         u8 flags2;
7659 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_MASK                   0x3
7660 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT                  0
7661 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_MASK                   0x3
7662 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT                  2
7663 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_MASK                   0x3
7664 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT                  4
7665 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_MASK                   0x3
7666 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT                  6
7667         u8 flags3;
7668 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_MASK                   0x3
7669 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT                  0
7670 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_MASK                  0x3
7671 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT                 2
7672 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK                 0x1
7673 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT                4
7674 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK    0x1
7675 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT   5
7676 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK                 0x1
7677 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT                6
7678 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1
7679 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
7680         u8 flags4;
7681 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1
7682 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       0
7683 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK                 0x1
7684 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT                1
7685 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK                 0x1
7686 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT                2
7687 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK                 0x1
7688 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT                3
7689 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK                 0x1
7690 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT                4
7691 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK                 0x1
7692 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT                5
7693 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK                0x1
7694 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT               6
7695 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK               0x1
7696 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT              7
7697         u8 flags5;
7698 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK               0x1
7699 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT              0
7700 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK               0x1
7701 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT              1
7702 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK               0x1
7703 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT              2
7704 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK               0x1
7705 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT              3
7706 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK               0x1
7707 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT              4
7708 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK               0x1
7709 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT              5
7710 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK               0x1
7711 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT              6
7712 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK               0x1
7713 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT              7
7714         __le32 reg0;
7715         __le32 reg1;
7716         __le32 reg2;
7717         __le32 reg3;
7718         __le32 reg4;
7719         __le32 reg5;
7720         __le32 reg6;
7721         __le32 reg7;
7722         __le32 reg8;
7723         u8 byte2;
7724         u8 byte3;
7725         __le16 word0;
7726         u8 byte4;
7727         u8 byte5;
7728         __le16 word1;
7729         __le16 word2;
7730         __le16 word3;
7731         __le32 reg9;
7732         __le32 reg10;
7733 };
7734
7735 /* The roce storm context of Ystorm */
7736 struct ystorm_roce_conn_st_ctx {
7737         struct regpair temp[2];
7738 };
7739
7740 /* The roce storm context of Mstorm */
7741 struct pstorm_roce_conn_st_ctx {
7742         struct regpair temp[16];
7743 };
7744
7745 /* The roce storm context of Xstorm */
7746 struct xstorm_roce_conn_st_ctx {
7747         struct regpair temp[24];
7748 };
7749
7750 /* The roce storm context of Tstorm */
7751 struct tstorm_roce_conn_st_ctx {
7752         struct regpair temp[30];
7753 };
7754
7755 /* The roce storm context of Mstorm */
7756 struct mstorm_roce_conn_st_ctx {
7757         struct regpair temp[6];
7758 };
7759
7760 /* The roce storm context of Ystorm */
7761 struct ustorm_roce_conn_st_ctx {
7762         struct regpair temp[12];
7763 };
7764
7765 /* roce connection context */
7766 struct e4_roce_conn_context {
7767         struct ystorm_roce_conn_st_ctx ystorm_st_context;
7768         struct regpair ystorm_st_padding[2];
7769         struct pstorm_roce_conn_st_ctx pstorm_st_context;
7770         struct xstorm_roce_conn_st_ctx xstorm_st_context;
7771         struct e4_xstorm_roce_conn_ag_ctx xstorm_ag_context;
7772         struct e4_tstorm_roce_conn_ag_ctx tstorm_ag_context;
7773         struct timers_context timer_context;
7774         struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
7775         struct tstorm_roce_conn_st_ctx tstorm_st_context;
7776         struct regpair tstorm_st_padding[2];
7777         struct mstorm_roce_conn_st_ctx mstorm_st_context;
7778         struct regpair mstorm_st_padding[2];
7779         struct ustorm_roce_conn_st_ctx ustorm_st_context;
7780 };
7781
7782 /* roce cqes statistics */
7783 struct roce_cqe_stats {
7784         __le32 req_cqe_error;
7785         __le32 req_remote_access_errors;
7786         __le32 req_remote_invalid_request;
7787         __le32 resp_cqe_error;
7788         __le32 resp_local_length_error;
7789         __le32 reserved;
7790 };
7791
7792 /* roce create qp requester ramrod data */
7793 struct roce_create_qp_req_ramrod_data {
7794         __le16 flags;
7795 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK                 0x3
7796 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT                0
7797 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK         0x1
7798 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT        2
7799 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK               0x1
7800 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT              3
7801 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK                         0x7
7802 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT                        4
7803 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK                    0x1
7804 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT                   7
7805 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK               0xF
7806 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT              8
7807 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK                 0xF
7808 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT                12
7809         u8 max_ord;
7810         u8 traffic_class;
7811         u8 hop_limit;
7812         u8 orq_num_pages;
7813         __le16 p_key;
7814         __le32 flow_label;
7815         __le32 dst_qp_id;
7816         __le32 ack_timeout_val;
7817         __le32 initial_psn;
7818         __le16 mtu;
7819         __le16 pd;
7820         __le16 sq_num_pages;
7821         __le16 low_latency_phy_queue;
7822         struct regpair sq_pbl_addr;
7823         struct regpair orq_pbl_addr;
7824         __le16 local_mac_addr[3];
7825         __le16 remote_mac_addr[3];
7826         __le16 vlan_id;
7827         __le16 udp_src_port;
7828         __le32 src_gid[4];
7829         __le32 dst_gid[4];
7830         __le32 cq_cid;
7831         struct regpair qp_handle_for_cqe;
7832         struct regpair qp_handle_for_async;
7833         u8 stats_counter_id;
7834         u8 reserved3[7];
7835         __le16 regular_latency_phy_queue;
7836         __le16 dpi;
7837 };
7838
7839 /* roce create qp responder ramrod data */
7840 struct roce_create_qp_resp_ramrod_data {
7841         __le32 flags;
7842 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK                0x3
7843 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT               0
7844 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK                 0x1
7845 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT                2
7846 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK                 0x1
7847 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT                3
7848 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK                  0x1
7849 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT                 4
7850 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK                    0x1
7851 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT                   5
7852 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK        0x1
7853 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT       6
7854 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK            0x1
7855 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT           7
7856 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK                        0x7
7857 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT                       8
7858 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK          0x1F
7859 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT         11
7860 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK             0x1
7861 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT            16
7862 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK             0x7FFF
7863 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT            17
7864         __le16 xrc_domain;
7865         u8 max_ird;
7866         u8 traffic_class;
7867         u8 hop_limit;
7868         u8 irq_num_pages;
7869         __le16 p_key;
7870         __le32 flow_label;
7871         __le32 dst_qp_id;
7872         u8 stats_counter_id;
7873         u8 reserved1;
7874         __le16 mtu;
7875         __le32 initial_psn;
7876         __le16 pd;
7877         __le16 rq_num_pages;
7878         struct rdma_srq_id srq_id;
7879         struct regpair rq_pbl_addr;
7880         struct regpair irq_pbl_addr;
7881         __le16 local_mac_addr[3];
7882         __le16 remote_mac_addr[3];
7883         __le16 vlan_id;
7884         __le16 udp_src_port;
7885         __le32 src_gid[4];
7886         __le32 dst_gid[4];
7887         struct regpair qp_handle_for_cqe;
7888         struct regpair qp_handle_for_async;
7889         __le16 low_latency_phy_queue;
7890         u8 reserved2[2];
7891         __le32 cq_cid;
7892         __le16 regular_latency_phy_queue;
7893         __le16 dpi;
7894 };
7895
7896 /* roce DCQCN received statistics */
7897 struct roce_dcqcn_received_stats {
7898         struct regpair ecn_pkt_rcv;
7899         struct regpair cnp_pkt_rcv;
7900 };
7901
7902 /* roce DCQCN sent statistics */
7903 struct roce_dcqcn_sent_stats {
7904         struct regpair cnp_pkt_sent;
7905 };
7906
7907 /* RoCE destroy qp requester output params */
7908 struct roce_destroy_qp_req_output_params {
7909         __le32 cq_prod;
7910         __le32 reserved;
7911 };
7912
7913 /* RoCE destroy qp requester ramrod data */
7914 struct roce_destroy_qp_req_ramrod_data {
7915         struct regpair output_params_addr;
7916 };
7917
7918 /* RoCE destroy qp responder output params */
7919 struct roce_destroy_qp_resp_output_params {
7920         __le32 cq_prod;
7921         __le32 reserved;
7922 };
7923
7924 /* RoCE destroy qp responder ramrod data */
7925 struct roce_destroy_qp_resp_ramrod_data {
7926         struct regpair output_params_addr;
7927 };
7928
7929 /* roce error statistics */
7930 struct roce_error_stats {
7931         __le32 resp_remote_access_errors;
7932         __le32 reserved;
7933 };
7934
7935 /* roce special events statistics */
7936 struct roce_events_stats {
7937         __le32 silent_drops;
7938         __le32 rnr_naks_sent;
7939         __le32 retransmit_count;
7940         __le32 icrc_error_count;
7941         __le32 implied_nak_seq_err;
7942         __le32 duplicate_request;
7943         __le32 local_ack_timeout_err;
7944         __le32 out_of_sequence;
7945         __le32 packet_seq_err;
7946         __le32 rnr_nak_retry_err;
7947 };
7948
7949 /* roce slow path EQ cmd IDs */
7950 enum roce_event_opcode {
7951         ROCE_EVENT_CREATE_QP = 11,
7952         ROCE_EVENT_MODIFY_QP,
7953         ROCE_EVENT_QUERY_QP,
7954         ROCE_EVENT_DESTROY_QP,
7955         ROCE_EVENT_CREATE_UD_QP,
7956         ROCE_EVENT_DESTROY_UD_QP,
7957         MAX_ROCE_EVENT_OPCODE
7958 };
7959
7960 /* roce func init ramrod data */
7961 struct roce_init_func_params {
7962         u8 ll2_queue_id;
7963         u8 cnp_vlan_priority;
7964         u8 cnp_dscp;
7965         u8 reserved;
7966         __le32 cnp_send_timeout;
7967         __le16 rl_offset;
7968         u8 rl_count_log;
7969         u8 reserved1[5];
7970 };
7971
7972 /* roce func init ramrod data */
7973 struct roce_init_func_ramrod_data {
7974         struct rdma_init_func_ramrod_data rdma;
7975         struct roce_init_func_params roce;
7976 };
7977
7978 /* roce modify qp requester ramrod data */
7979 struct roce_modify_qp_req_ramrod_data {
7980         __le16 flags;
7981 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK             0x1
7982 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT            0
7983 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK             0x1
7984 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT            1
7985 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK         0x1
7986 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT        2
7987 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK                   0x1
7988 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT                  3
7989 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK          0x1
7990 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT         4
7991 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK                 0x1
7992 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT                5
7993 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK             0x1
7994 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT            6
7995 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK           0x1
7996 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT          7
7997 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK             0x1
7998 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT            8
7999 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK                     0x1
8000 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT                    9
8001 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK                         0x7
8002 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT                        10
8003 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK         0x1
8004 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT        13
8005 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK                   0x3
8006 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT                  14
8007         u8 fields;
8008 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK       0xF
8009 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT      0
8010 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK         0xF
8011 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT        4
8012         u8 max_ord;
8013         u8 traffic_class;
8014         u8 hop_limit;
8015         __le16 p_key;
8016         __le32 flow_label;
8017         __le32 ack_timeout_val;
8018         __le16 mtu;
8019         __le16 reserved2;
8020         __le32 reserved3[2];
8021         __le16 low_latency_phy_queue;
8022         __le16 regular_latency_phy_queue;
8023         __le32 src_gid[4];
8024         __le32 dst_gid[4];
8025 };
8026
8027 /* roce modify qp responder ramrod data */
8028 struct roce_modify_qp_resp_ramrod_data {
8029         __le16 flags;
8030 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK            0x1
8031 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT           0
8032 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK                 0x1
8033 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT                1
8034 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK                 0x1
8035 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT                2
8036 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK                  0x1
8037 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT                 3
8038 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK                  0x1
8039 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT                 4
8040 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK         0x1
8041 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT        5
8042 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK                0x1
8043 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT               6
8044 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK                    0x1
8045 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT                   7
8046 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK      0x1
8047 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT     8
8048 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK            0x1
8049 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT           9
8050 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK        0x1
8051 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT       10
8052 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK                  0x1F
8053 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT                 11
8054         u8 fields;
8055 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK                0x7
8056 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT               0
8057 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK  0x1F
8058 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
8059         u8 max_ird;
8060         u8 traffic_class;
8061         u8 hop_limit;
8062         __le16 p_key;
8063         __le32 flow_label;
8064         __le16 mtu;
8065         __le16 low_latency_phy_queue;
8066         __le16 regular_latency_phy_queue;
8067         u8 reserved2[6];
8068         __le32 src_gid[4];
8069         __le32 dst_gid[4];
8070 };
8071
8072 /* RoCE query qp requester output params */
8073 struct roce_query_qp_req_output_params {
8074         __le32 psn;
8075         __le32 flags;
8076 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK            0x1
8077 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT           0
8078 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK    0x1
8079 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT   1
8080 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK          0x3FFFFFFF
8081 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT         2
8082 };
8083
8084 /* RoCE query qp requester ramrod data */
8085 struct roce_query_qp_req_ramrod_data {
8086         struct regpair output_params_addr;
8087 };
8088
8089 /* RoCE query qp responder output params */
8090 struct roce_query_qp_resp_output_params {
8091         __le32 psn;
8092         __le32 err_flag;
8093 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK  0x1
8094 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
8095 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK  0x7FFFFFFF
8096 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
8097 };
8098
8099 /* RoCE query qp responder ramrod data */
8100 struct roce_query_qp_resp_ramrod_data {
8101         struct regpair output_params_addr;
8102 };
8103
8104 /* ROCE ramrod command IDs */
8105 enum roce_ramrod_cmd_id {
8106         ROCE_RAMROD_CREATE_QP = 11,
8107         ROCE_RAMROD_MODIFY_QP,
8108         ROCE_RAMROD_QUERY_QP,
8109         ROCE_RAMROD_DESTROY_QP,
8110         ROCE_RAMROD_CREATE_UD_QP,
8111         ROCE_RAMROD_DESTROY_UD_QP,
8112         MAX_ROCE_RAMROD_CMD_ID
8113 };
8114
8115 struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
8116         u8 reserved0;
8117         u8 state;
8118         u8 flags0;
8119 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK      0x1
8120 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT     0
8121 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK              0x1
8122 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT             1
8123 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK              0x1
8124 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT             2
8125 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK      0x1
8126 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT     3
8127 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK              0x1
8128 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT             4
8129 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK              0x1
8130 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT             5
8131 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK              0x1
8132 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT             6
8133 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK              0x1
8134 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT             7
8135         u8 flags1;
8136 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK              0x1
8137 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT             0
8138 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK              0x1
8139 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT             1
8140 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK             0x1
8141 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT            2
8142 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK             0x1
8143 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT            3
8144 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK             0x1
8145 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT            4
8146 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK        0x1
8147 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT       5
8148 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK        0x1
8149 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT       6
8150 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK      0x1
8151 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT     7
8152         u8 flags2;
8153 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK       0x3
8154 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT      0
8155 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK       0x3
8156 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT      2
8157 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK       0x3
8158 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT      4
8159 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK       0x3
8160 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT      6
8161         u8 flags3;
8162 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK               0x3
8163 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT              0
8164 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK               0x3
8165 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT              2
8166 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK               0x3
8167 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT              4
8168 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK       0x3
8169 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT      6
8170         u8 flags4;
8171 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK       0x3
8172 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT      0
8173 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK       0x3
8174 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT      2
8175 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK      0x3
8176 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT     4
8177 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK      0x3
8178 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT     6
8179         u8 flags5;
8180 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK      0x3
8181 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT     0
8182 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK      0x3
8183 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT     2
8184 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK      0x3
8185 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT     4
8186 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK      0x3
8187 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT     6
8188         u8 flags6;
8189 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK      0x3
8190 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT     0
8191 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK      0x3
8192 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT     2
8193 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK      0x3
8194 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT     4
8195 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK      0x3
8196 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT     6
8197         u8 flags7;
8198 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK              0x3
8199 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT             0
8200 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK              0x3
8201 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT             2
8202 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK         0x3
8203 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT        4
8204 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK             0x1
8205 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT            6
8206 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK             0x1
8207 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT            7
8208         u8 flags8;
8209 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK             0x1
8210 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT            0
8211 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK             0x1
8212 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT            1
8213 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK             0x1
8214 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT            2
8215 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK             0x1
8216 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT            3
8217 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK             0x1
8218 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT            4
8219 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK    0x1
8220 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT   5
8221 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK             0x1
8222 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT            6
8223 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK             0x1
8224 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT            7
8225         u8 flags9;
8226 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK    0x1
8227 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT   0
8228 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK    0x1
8229 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT   1
8230 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK    0x1
8231 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT   2
8232 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK    0x1
8233 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT   3
8234 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK    0x1
8235 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT   4
8236 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK    0x1
8237 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT   5
8238 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK    0x1
8239 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT   6
8240 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK    0x1
8241 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT   7
8242         u8 flags10;
8243 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK            0x1
8244 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT           0
8245 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK            0x1
8246 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT           1
8247 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK            0x1
8248 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT           2
8249 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK            0x1
8250 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT           3
8251 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK      0x1
8252 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT     4
8253 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK            0x1
8254 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT           5
8255 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK           0x1
8256 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT          6
8257 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK           0x1
8258 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT          7
8259         u8 flags11;
8260 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK           0x1
8261 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT          0
8262 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK           0x1
8263 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT          1
8264 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK           0x1
8265 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT          2
8266 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK           0x1
8267 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT          3
8268 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK           0x1
8269 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT          4
8270 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK           0x1
8271 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT          5
8272 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK      0x1
8273 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT     6
8274 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK           0x1
8275 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT          7
8276         u8 flags12;
8277 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK          0x1
8278 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT         0
8279 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK          0x1
8280 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT         1
8281 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK      0x1
8282 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT     2
8283 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK      0x1
8284 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT     3
8285 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK          0x1
8286 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT         4
8287 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK          0x1
8288 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT         5
8289 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK          0x1
8290 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT         6
8291 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK          0x1
8292 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT         7
8293         u8 flags13;
8294 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK          0x1
8295 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT         0
8296 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK          0x1
8297 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT         1
8298 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK      0x1
8299 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT     2
8300 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK      0x1
8301 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT     3
8302 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK      0x1
8303 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT     4
8304 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK      0x1
8305 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT     5
8306 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK      0x1
8307 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT     6
8308 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK      0x1
8309 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT     7
8310         u8 flags14;
8311 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK         0x1
8312 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT        0
8313 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK             0x1
8314 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT            1
8315 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK      0x3
8316 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT     2
8317 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK          0x1
8318 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT         4
8319 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK  0x1
8320 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
8321 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK              0x3
8322 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT             6
8323         u8 byte2;
8324         __le16 physical_q0;
8325         __le16 word1;
8326         __le16 word2;
8327         __le16 word3;
8328         __le16 word4;
8329         __le16 word5;
8330         __le16 conn_dpi;
8331         u8 byte3;
8332         u8 byte4;
8333         u8 byte5;
8334         u8 byte6;
8335         __le32 reg0;
8336         __le32 reg1;
8337         __le32 reg2;
8338         __le32 snd_nxt_psn;
8339         __le32 reg4;
8340 };
8341
8342 struct e4_mstorm_roce_conn_ag_ctx {
8343         u8 byte0;
8344         u8 byte1;
8345         u8 flags0;
8346 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK     0x1
8347 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT    0
8348 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK     0x1
8349 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT    1
8350 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_MASK      0x3
8351 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT     2
8352 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_MASK      0x3
8353 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT     4
8354 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_MASK      0x3
8355 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT     6
8356         u8 flags1;
8357 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK    0x1
8358 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT   0
8359 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK    0x1
8360 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT   1
8361 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK    0x1
8362 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT   2
8363 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK  0x1
8364 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
8365 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK  0x1
8366 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
8367 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK  0x1
8368 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
8369 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK  0x1
8370 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
8371 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK  0x1
8372 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
8373         __le16 word0;
8374         __le16 word1;
8375         __le32 reg0;
8376         __le32 reg1;
8377 };
8378
8379 struct e4_mstorm_roce_req_conn_ag_ctx {
8380         u8 byte0;
8381         u8 byte1;
8382         u8 flags0;
8383 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK        0x1
8384 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT       0
8385 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK        0x1
8386 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT       1
8387 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK         0x3
8388 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT        2
8389 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK         0x3
8390 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT        4
8391 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK         0x3
8392 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT        6
8393         u8 flags1;
8394 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK       0x1
8395 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT      0
8396 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK       0x1
8397 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT      1
8398 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK       0x1
8399 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT      2
8400 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK     0x1
8401 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT    3
8402 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK     0x1
8403 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT    4
8404 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK     0x1
8405 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT    5
8406 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK     0x1
8407 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT    6
8408 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK     0x1
8409 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT    7
8410         __le16 word0;
8411         __le16 word1;
8412         __le32 reg0;
8413         __le32 reg1;
8414 };
8415
8416 struct e4_mstorm_roce_resp_conn_ag_ctx {
8417         u8 byte0;
8418         u8 byte1;
8419         u8 flags0;
8420 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK       0x1
8421 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT      0
8422 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK       0x1
8423 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT      1
8424 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK        0x3
8425 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT       2
8426 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK        0x3
8427 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT       4
8428 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK        0x3
8429 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT       6
8430         u8 flags1;
8431 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK      0x1
8432 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT     0
8433 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK      0x1
8434 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT     1
8435 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK      0x1
8436 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT     2
8437 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK    0x1
8438 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT   3
8439 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK    0x1
8440 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT   4
8441 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK    0x1
8442 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT   5
8443 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK    0x1
8444 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT   6
8445 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK    0x1
8446 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT   7
8447         __le16 word0;
8448         __le16 word1;
8449         __le32 reg0;
8450         __le32 reg1;
8451 };
8452
8453 struct e4_tstorm_roce_req_conn_ag_ctx {
8454         u8 reserved0;
8455         u8 state;
8456         u8 flags0;
8457 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK                0x1
8458 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT               0
8459 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK           0x1
8460 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT          1
8461 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK       0x1
8462 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT      2
8463 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK                        0x1
8464 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT                       3
8465 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK                0x1
8466 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT               4
8467 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK                  0x1
8468 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT                 5
8469 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK                    0x3
8470 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT                   6
8471         u8 flags1;
8472 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK             0x3
8473 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT            0
8474 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK                 0x3
8475 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT                2
8476 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK           0x3
8477 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT          4
8478 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK                 0x3
8479 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT                6
8480         u8 flags2;
8481 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK               0x3
8482 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT              0
8483 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK        0x3
8484 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT       2
8485 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK   0x3
8486 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT  4
8487 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK       0x3
8488 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT      6
8489         u8 flags3;
8490 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK     0x3
8491 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT    0
8492 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK       0x3
8493 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT      2
8494 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK                 0x1
8495 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT                4
8496 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK          0x1
8497 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT         5
8498 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK              0x1
8499 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT             6
8500 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK        0x1
8501 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT       7
8502         u8 flags4;
8503 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK              0x1
8504 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT             0
8505 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK            0x1
8506 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT           1
8507 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK             0x1
8508 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT            2
8509 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK        0x1
8510 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT       3
8511 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK            0x1
8512 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT           4
8513 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK  0x1
8514 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
8515 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK    0x1
8516 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT   6
8517 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK                     0x1
8518 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT                    7
8519         u8 flags5;
8520 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK             0x1
8521 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT            0
8522 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK             0x1
8523 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT            1
8524 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK             0x1
8525 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT            2
8526 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK             0x1
8527 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT            3
8528 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK             0x1
8529 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT            4
8530 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK      0x1
8531 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT     5
8532 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK             0x1
8533 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT            6
8534 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK             0x1
8535 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT            7
8536         __le32 reg0;
8537         __le32 snd_nxt_psn;
8538         __le32 snd_max_psn;
8539         __le32 orq_prod;
8540         __le32 reg4;
8541         __le32 reg5;
8542         __le32 reg6;
8543         __le32 reg7;
8544         __le32 reg8;
8545         u8 tx_cqe_error_type;
8546         u8 orq_cache_idx;
8547         __le16 snd_sq_cons_th;
8548         u8 byte4;
8549         u8 byte5;
8550         __le16 snd_sq_cons;
8551         __le16 conn_dpi;
8552         __le16 force_comp_cons;
8553         __le32 reg9;
8554         __le32 reg10;
8555 };
8556
8557 struct e4_tstorm_roce_resp_conn_ag_ctx {
8558         u8 byte0;
8559         u8 state;
8560         u8 flags0;
8561 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK               0x1
8562 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT              0
8563 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK  0x1
8564 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
8565 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK                       0x1
8566 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT                      2
8567 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK                       0x1
8568 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT                      3
8569 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK               0x1
8570 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT              4
8571 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK                       0x1
8572 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT                      5
8573 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK                        0x3
8574 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT                       6
8575         u8 flags1;
8576 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK            0x3
8577 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT           0
8578 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK        0x3
8579 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT       2
8580 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK                0x3
8581 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT               4
8582 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK        0x3
8583 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT       6
8584         u8 flags2;
8585 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK                0x3
8586 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT               0
8587 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK                0x3
8588 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT               2
8589 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK                0x3
8590 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT               4
8591 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK                0x3
8592 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT               6
8593         u8 flags3;
8594 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK                0x3
8595 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT               0
8596 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK               0x3
8597 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT              2
8598 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK              0x1
8599 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT             4
8600 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK         0x1
8601 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT        5
8602 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK     0x1
8603 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT    6
8604 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK              0x1
8605 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT             7
8606         u8 flags4;
8607 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK             0x1
8608 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT            0
8609 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK             0x1
8610 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT            1
8611 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK                      0x1
8612 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT                     2
8613 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK                      0x1
8614 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT                     3
8615 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK                      0x1
8616 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT                     4
8617 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK                      0x1
8618 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT                     5
8619 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK                     0x1
8620 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT                    6
8621 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK                    0x1
8622 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT                   7
8623         u8 flags5;
8624 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK            0x1
8625 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT           0
8626 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK            0x1
8627 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT           1
8628 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK            0x1
8629 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT           2
8630 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK            0x1
8631 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT           3
8632 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK            0x1
8633 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT           4
8634 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK         0x1
8635 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT        5
8636 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK            0x1
8637 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT           6
8638 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK            0x1
8639 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT           7
8640         __le32 psn_and_rxmit_id_echo;
8641         __le32 reg1;
8642         __le32 reg2;
8643         __le32 reg3;
8644         __le32 reg4;
8645         __le32 reg5;
8646         __le32 reg6;
8647         __le32 reg7;
8648         __le32 reg8;
8649         u8 tx_async_error_type;
8650         u8 byte3;
8651         __le16 rq_cons;
8652         u8 byte4;
8653         u8 byte5;
8654         __le16 rq_prod;
8655         __le16 conn_dpi;
8656         __le16 irq_cons;
8657         __le32 reg9;
8658         __le32 reg10;
8659 };
8660
8661 struct e4_ustorm_roce_req_conn_ag_ctx {
8662         u8 byte0;
8663         u8 byte1;
8664         u8 flags0;
8665 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK        0x1
8666 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT       0
8667 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK        0x1
8668 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT       1
8669 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK         0x3
8670 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT        2
8671 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK         0x3
8672 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT        4
8673 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK         0x3
8674 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT        6
8675         u8 flags1;
8676 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK         0x3
8677 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT        0
8678 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK         0x3
8679 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT        2
8680 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK         0x3
8681 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT        4
8682 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK         0x3
8683 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT        6
8684         u8 flags2;
8685 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK       0x1
8686 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT      0
8687 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK       0x1
8688 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT      1
8689 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK       0x1
8690 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT      2
8691 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK       0x1
8692 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT      3
8693 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK       0x1
8694 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT      4
8695 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK       0x1
8696 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT      5
8697 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK       0x1
8698 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT      6
8699 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK     0x1
8700 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT    7
8701         u8 flags3;
8702 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK     0x1
8703 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT    0
8704 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK     0x1
8705 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT    1
8706 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK     0x1
8707 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT    2
8708 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK     0x1
8709 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT    3
8710 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK     0x1
8711 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT    4
8712 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK     0x1
8713 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT    5
8714 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK     0x1
8715 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT    6
8716 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK     0x1
8717 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT    7
8718         u8 byte2;
8719         u8 byte3;
8720         __le16 word0;
8721         __le16 word1;
8722         __le32 reg0;
8723         __le32 reg1;
8724         __le32 reg2;
8725         __le32 reg3;
8726         __le16 word2;
8727         __le16 word3;
8728 };
8729
8730 struct e4_ustorm_roce_resp_conn_ag_ctx {
8731         u8 byte0;
8732         u8 byte1;
8733         u8 flags0;
8734 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK       0x1
8735 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT      0
8736 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK       0x1
8737 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT      1
8738 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK        0x3
8739 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT       2
8740 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK        0x3
8741 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT       4
8742 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK        0x3
8743 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT       6
8744         u8 flags1;
8745 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK        0x3
8746 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT       0
8747 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK        0x3
8748 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT       2
8749 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK        0x3
8750 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT       4
8751 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK        0x3
8752 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT       6
8753         u8 flags2;
8754 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK      0x1
8755 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT     0
8756 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK      0x1
8757 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT     1
8758 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK      0x1
8759 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT     2
8760 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK      0x1
8761 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT     3
8762 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK      0x1
8763 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT     4
8764 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK      0x1
8765 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT     5
8766 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK      0x1
8767 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT     6
8768 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK    0x1
8769 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT   7
8770         u8 flags3;
8771 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK    0x1
8772 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT   0
8773 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK    0x1
8774 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT   1
8775 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK    0x1
8776 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT   2
8777 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK    0x1
8778 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT   3
8779 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK    0x1
8780 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT   4
8781 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK    0x1
8782 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT   5
8783 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK    0x1
8784 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT   6
8785 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK    0x1
8786 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT   7
8787         u8 byte2;
8788         u8 byte3;
8789         __le16 word0;
8790         __le16 word1;
8791         __le32 reg0;
8792         __le32 reg1;
8793         __le32 reg2;
8794         __le32 reg3;
8795         __le16 word2;
8796         __le16 word3;
8797 };
8798
8799 struct e4_xstorm_roce_req_conn_ag_ctx {
8800         u8 reserved0;
8801         u8 state;
8802         u8 flags0;
8803 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK        0x1
8804 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT       0
8805 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK           0x1
8806 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT          1
8807 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK           0x1
8808 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT          2
8809 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK        0x1
8810 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT       3
8811 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK           0x1
8812 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT          4
8813 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK           0x1
8814 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT          5
8815 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK           0x1
8816 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT          6
8817 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK           0x1
8818 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT          7
8819         u8 flags1;
8820 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK           0x1
8821 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT          0
8822 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK           0x1
8823 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT          1
8824 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK               0x1
8825 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT              2
8826 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK               0x1
8827 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT              3
8828 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK               0x1
8829 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT              4
8830 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK               0x1
8831 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT              5
8832 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK         0x1
8833 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT        6
8834 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK        0x1
8835 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT       7
8836         u8 flags2;
8837 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK         0x3
8838 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT        0
8839 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK         0x3
8840 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT        2
8841 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK         0x3
8842 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT        4
8843 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK         0x3
8844 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT        6
8845         u8 flags3;
8846 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK         0x3
8847 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT        0
8848 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK         0x3
8849 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT        2
8850 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK        0x3
8851 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT       4
8852 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK         0x3
8853 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT        6
8854         u8 flags4;
8855 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK        0x3
8856 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT       0
8857 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK     0x3
8858 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT    2
8859 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK        0x3
8860 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT       4
8861 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK        0x3
8862 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT       6
8863         u8 flags5;
8864 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK                0x3
8865 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT               0
8866 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK                0x3
8867 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT               2
8868 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK        0x3
8869 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT       4
8870 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK                0x3
8871 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT               6
8872         u8 flags6;
8873 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK        0x3
8874 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT       0
8875 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK        0x3
8876 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT       2
8877 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK        0x3
8878 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT       4
8879 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK        0x3
8880 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT       6
8881         u8 flags7;
8882 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK        0x3
8883 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT       0
8884 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK        0x3
8885 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT       2
8886 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK   0x3
8887 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT  4
8888 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK       0x1
8889 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT      6
8890 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK       0x1
8891 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT      7
8892         u8 flags8;
8893 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK               0x1
8894 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT              0
8895 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK               0x1
8896 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT              1
8897 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK      0x1
8898 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT     2
8899 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK      0x1
8900 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT     3
8901 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK     0x1
8902 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT    4
8903 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK      0x1
8904 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT     5
8905 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK     0x1
8906 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT    6
8907 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK  0x1
8908 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7
8909         u8 flags9;
8910 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK              0x1
8911 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT             0
8912 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK              0x1
8913 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT             1
8914 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK              0x1
8915 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT             2
8916 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK              0x1
8917 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT             3
8918 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK     0x1
8919 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT    4
8920 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK              0x1
8921 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT             5
8922 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK              0x1
8923 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT             6
8924 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK              0x1
8925 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT             7
8926         u8 flags10;
8927 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK              0x1
8928 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT             0
8929 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK              0x1
8930 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT             1
8931 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK              0x1
8932 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT             2
8933 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK              0x1
8934 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT             3
8935 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK        0x1
8936 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT       4
8937 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK              0x1
8938 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT             5
8939 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK             0x1
8940 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT            6
8941 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK             0x1
8942 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT            7
8943         u8 flags11;
8944 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK             0x1
8945 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT            0
8946 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK             0x1
8947 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT            1
8948 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK             0x1
8949 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT            2
8950 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK             0x1
8951 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT            3
8952 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK             0x1
8953 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT            4
8954 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK  0x1
8955 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
8956 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK        0x1
8957 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT       6
8958 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK             0x1
8959 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT            7
8960         u8 flags12;
8961 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK          0x1
8962 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT         0
8963 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK            0x1
8964 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT           1
8965 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK        0x1
8966 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT       2
8967 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK        0x1
8968 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT       3
8969 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK   0x1
8970 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT  4
8971 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK            0x1
8972 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT           5
8973 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK   0x1
8974 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT  6
8975 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK     0x1
8976 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT    7
8977         u8 flags13;
8978 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK            0x1
8979 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT           0
8980 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK            0x1
8981 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT           1
8982 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK        0x1
8983 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT       2
8984 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK        0x1
8985 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT       3
8986 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK        0x1
8987 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT       4
8988 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK        0x1
8989 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT       5
8990 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK        0x1
8991 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT       6
8992 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK        0x1
8993 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT       7
8994         u8 flags14;
8995 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK      0x1
8996 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT     0
8997 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK               0x1
8998 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT              1
8999 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK        0x3
9000 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT       2
9001 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK            0x1
9002 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT           4
9003 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK    0x1
9004 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT   5
9005 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK                0x3
9006 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT               6
9007         u8 byte2;
9008         __le16 physical_q0;
9009         __le16 word1;
9010         __le16 sq_cmp_cons;
9011         __le16 sq_cons;
9012         __le16 sq_prod;
9013         __le16 dif_error_first_sq_cons;
9014         __le16 conn_dpi;
9015         u8 dif_error_sge_index;
9016         u8 byte4;
9017         u8 byte5;
9018         u8 byte6;
9019         __le32 lsn;
9020         __le32 ssn;
9021         __le32 snd_una_psn;
9022         __le32 snd_nxt_psn;
9023         __le32 dif_error_offset;
9024         __le32 orq_cons_th;
9025         __le32 orq_cons;
9026 };
9027
9028 struct e4_xstorm_roce_resp_conn_ag_ctx {
9029         u8 reserved0;
9030         u8 state;
9031         u8 flags0;
9032 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1
9033 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
9034 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK          0x1
9035 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT         1
9036 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK          0x1
9037 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT         2
9038 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK       0x1
9039 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT      3
9040 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK          0x1
9041 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT         4
9042 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK          0x1
9043 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT         5
9044 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK          0x1
9045 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT         6
9046 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK          0x1
9047 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT         7
9048         u8 flags1;
9049 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK          0x1
9050 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT         0
9051 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK          0x1
9052 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT         1
9053 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK              0x1
9054 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT             2
9055 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK              0x1
9056 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT             3
9057 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK              0x1
9058 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT             4
9059 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK              0x1
9060 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT             5
9061 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK        0x1
9062 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT       6
9063 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK       0x1
9064 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT      7
9065         u8 flags2;
9066 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK        0x3
9067 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT       0
9068 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK        0x3
9069 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT       2
9070 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK        0x3
9071 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT       4
9072 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK        0x3
9073 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT       6
9074         u8 flags3;
9075 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK           0x3
9076 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT          0
9077 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK        0x3
9078 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT       2
9079 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK       0x3
9080 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT      4
9081 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK        0x3
9082 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT       6
9083         u8 flags4;
9084 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK        0x3
9085 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT       0
9086 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK        0x3
9087 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT       2
9088 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK       0x3
9089 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT      4
9090 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK       0x3
9091 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT      6
9092         u8 flags5;
9093 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK       0x3
9094 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT      0
9095 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK       0x3
9096 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT      2
9097 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK       0x3
9098 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT      4
9099 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK       0x3
9100 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT      6
9101         u8 flags6;
9102 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK       0x3
9103 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT      0
9104 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK       0x3
9105 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT      2
9106 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK       0x3
9107 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT      4
9108 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK       0x3
9109 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT      6
9110         u8 flags7;
9111 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK       0x3
9112 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT      0
9113 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK       0x3
9114 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT      2
9115 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK  0x3
9116 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
9117 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK      0x1
9118 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT     6
9119 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK      0x1
9120 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT     7
9121         u8 flags8;
9122 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK              0x1
9123 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT             0
9124 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK              0x1
9125 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT             1
9126 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK        0x1
9127 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT       2
9128 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK     0x1
9129 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT    3
9130 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK    0x1
9131 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT   4
9132 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK     0x1
9133 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT    5
9134 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK              0x1
9135 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT             6
9136 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK              0x1
9137 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT             7
9138         u8 flags9;
9139 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK     0x1
9140 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT    0
9141 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK     0x1
9142 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT    1
9143 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK     0x1
9144 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT    2
9145 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK     0x1
9146 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT    3
9147 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK     0x1
9148 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT    4
9149 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK     0x1
9150 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT    5
9151 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK     0x1
9152 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT    6
9153 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK     0x1
9154 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT    7
9155         u8 flags10;
9156 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK             0x1
9157 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT            0
9158 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK             0x1
9159 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT            1
9160 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK             0x1
9161 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT            2
9162 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK             0x1
9163 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT            3
9164 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK       0x1
9165 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT      4
9166 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK             0x1
9167 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT            5
9168 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK            0x1
9169 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT           6
9170 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK            0x1
9171 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT           7
9172         u8 flags11;
9173 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK            0x1
9174 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT           0
9175 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK            0x1
9176 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT           1
9177 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK            0x1
9178 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT           2
9179 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK            0x1
9180 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT           3
9181 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK            0x1
9182 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT           4
9183 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK            0x1
9184 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT           5
9185 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK       0x1
9186 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT      6
9187 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK            0x1
9188 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT           7
9189         u8 flags12;
9190 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK   0x1
9191 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT  0
9192 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK           0x1
9193 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT          1
9194 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK       0x1
9195 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT      2
9196 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK       0x1
9197 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT      3
9198 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK           0x1
9199 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT          4
9200 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK           0x1
9201 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT          5
9202 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK           0x1
9203 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT          6
9204 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK           0x1
9205 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT          7
9206         u8 flags13;
9207 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK           0x1
9208 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT          0
9209 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK           0x1
9210 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT          1
9211 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK       0x1
9212 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT      2
9213 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK       0x1
9214 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT      3
9215 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK       0x1
9216 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT      4
9217 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK       0x1
9218 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT      5
9219 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK       0x1
9220 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT      6
9221 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK       0x1
9222 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT      7
9223         u8 flags14;
9224 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK      0x1
9225 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT     0
9226 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK      0x1
9227 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT     1
9228 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK      0x1
9229 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT     2
9230 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK      0x1
9231 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT     3
9232 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK      0x1
9233 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT     4
9234 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK      0x1
9235 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT     5
9236 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK       0x3
9237 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT      6
9238         u8 byte2;
9239         __le16 physical_q0;
9240         __le16 irq_prod_shadow;
9241         __le16 word2;
9242         __le16 irq_cons;
9243         __le16 irq_prod;
9244         __le16 e5_reserved1;
9245         __le16 conn_dpi;
9246         u8 rxmit_opcode;
9247         u8 byte4;
9248         u8 byte5;
9249         u8 byte6;
9250         __le32 rxmit_psn_and_id;
9251         __le32 rxmit_bytes_length;
9252         __le32 psn;
9253         __le32 reg3;
9254         __le32 reg4;
9255         __le32 reg5;
9256         __le32 msn_and_syndrome;
9257 };
9258
9259 struct e4_ystorm_roce_conn_ag_ctx {
9260         u8 byte0;
9261         u8 byte1;
9262         u8 flags0;
9263 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK     0x1
9264 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT    0
9265 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK     0x1
9266 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT    1
9267 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_MASK      0x3
9268 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT     2
9269 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_MASK      0x3
9270 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT     4
9271 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_MASK      0x3
9272 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT     6
9273         u8 flags1;
9274 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK    0x1
9275 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT   0
9276 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK    0x1
9277 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT   1
9278 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK    0x1
9279 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT   2
9280 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK  0x1
9281 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
9282 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK  0x1
9283 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
9284 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK  0x1
9285 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
9286 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK  0x1
9287 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
9288 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK  0x1
9289 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
9290         u8 byte2;
9291         u8 byte3;
9292         __le16 word0;
9293         __le32 reg0;
9294         __le32 reg1;
9295         __le16 word1;
9296         __le16 word2;
9297         __le16 word3;
9298         __le16 word4;
9299         __le32 reg2;
9300         __le32 reg3;
9301 };
9302
9303 struct e4_ystorm_roce_req_conn_ag_ctx {
9304         u8 byte0;
9305         u8 byte1;
9306         u8 flags0;
9307 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK        0x1
9308 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT       0
9309 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK        0x1
9310 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT       1
9311 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK         0x3
9312 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT        2
9313 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK         0x3
9314 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT        4
9315 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK         0x3
9316 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT        6
9317         u8 flags1;
9318 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK       0x1
9319 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT      0
9320 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK       0x1
9321 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT      1
9322 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK       0x1
9323 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT      2
9324 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK     0x1
9325 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT    3
9326 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK     0x1
9327 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT    4
9328 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK     0x1
9329 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT    5
9330 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK     0x1
9331 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT    6
9332 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK     0x1
9333 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT    7
9334         u8 byte2;
9335         u8 byte3;
9336         __le16 word0;
9337         __le32 reg0;
9338         __le32 reg1;
9339         __le16 word1;
9340         __le16 word2;
9341         __le16 word3;
9342         __le16 word4;
9343         __le32 reg2;
9344         __le32 reg3;
9345 };
9346
9347 struct e4_ystorm_roce_resp_conn_ag_ctx {
9348         u8 byte0;
9349         u8 byte1;
9350         u8 flags0;
9351 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK       0x1
9352 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT      0
9353 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK       0x1
9354 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT      1
9355 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK        0x3
9356 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT       2
9357 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK        0x3
9358 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT       4
9359 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK        0x3
9360 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT       6
9361         u8 flags1;
9362 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK      0x1
9363 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT     0
9364 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK      0x1
9365 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT     1
9366 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK      0x1
9367 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT     2
9368 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK    0x1
9369 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT   3
9370 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK    0x1
9371 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT   4
9372 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK    0x1
9373 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT   5
9374 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK    0x1
9375 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT   6
9376 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK    0x1
9377 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT   7
9378         u8 byte2;
9379         u8 byte3;
9380         __le16 word0;
9381         __le32 reg0;
9382         __le32 reg1;
9383         __le16 word1;
9384         __le16 word2;
9385         __le16 word3;
9386         __le16 word4;
9387         __le32 reg2;
9388         __le32 reg3;
9389 };
9390
9391 /* Roce doorbell data */
9392 enum roce_flavor {
9393         PLAIN_ROCE,
9394         RROCE_IPV4,
9395         RROCE_IPV6,
9396         MAX_ROCE_FLAVOR
9397 };
9398
9399 /* The iwarp storm context of Ystorm */
9400 struct ystorm_iwarp_conn_st_ctx {
9401         __le32 reserved[4];
9402 };
9403
9404 /* The iwarp storm context of Pstorm */
9405 struct pstorm_iwarp_conn_st_ctx {
9406         __le32 reserved[36];
9407 };
9408
9409 /* The iwarp storm context of Xstorm */
9410 struct xstorm_iwarp_conn_st_ctx {
9411         __le32 reserved[48];
9412 };
9413
9414 struct e4_xstorm_iwarp_conn_ag_ctx {
9415         u8 reserved0;
9416         u8 state;
9417         u8 flags0;
9418 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK   0x1
9419 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT  0
9420 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK   0x1
9421 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT  1
9422 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK   0x1
9423 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT  2
9424 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK   0x1
9425 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT  3
9426 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK           0x1
9427 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT          4
9428 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK      0x1
9429 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT     5
9430 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK           0x1
9431 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT          6
9432 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK           0x1
9433 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT          7
9434         u8 flags1;
9435 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK                           0x1
9436 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT                          0
9437 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK                           0x1
9438 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT                          1
9439 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK                          0x1
9440 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT                         2
9441 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK                          0x1
9442 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT                         3
9443 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK                          0x1
9444 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT                         4
9445 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK                          0x1
9446 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT                         5
9447 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK                          0x1
9448 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT                         6
9449 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
9450 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
9451         u8 flags2;
9452 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK                    0x3
9453 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT                   0
9454 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK                    0x3
9455 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT                   2
9456 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK                    0x3
9457 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT                   4
9458 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK         0x3
9459 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT        6
9460         u8 flags3;
9461 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK    0x3
9462 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT   0
9463 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK    0x3
9464 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT   2
9465 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK    0x3
9466 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT   4
9467 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK    0x3
9468 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT   6
9469         u8 flags4;
9470 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK    0x3
9471 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT   0
9472 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK    0x3
9473 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT   2
9474 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK   0x3
9475 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT  4
9476 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK   0x3
9477 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT  6
9478         u8 flags5;
9479 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK           0x3
9480 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT          0
9481 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK           0x3
9482 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT          2
9483 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK    0x3
9484 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT   4
9485 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK           0x3
9486 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT          6
9487         u8 flags6;
9488 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
9489 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
9490 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK                           0x3
9491 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT                          2
9492 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK                           0x3
9493 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT                          4
9494 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK                       0x3
9495 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT                      6
9496         u8 flags7;
9497 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK       0x3
9498 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT      0
9499 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK       0x3
9500 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT      2
9501 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK      0x3
9502 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT     4
9503 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK          0x1
9504 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT         6
9505 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK          0x1
9506 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT         7
9507         u8 flags8;
9508 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK                  0x1
9509 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT                 0
9510 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK      0x1
9511 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT     1
9512 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK                  0x1
9513 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT                 2
9514 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK                  0x1
9515 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT                 3
9516 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK                  0x1
9517 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT                 4
9518 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK                  0x1
9519 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT                 5
9520 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK                  0x1
9521 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT                 6
9522 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK                  0x1
9523 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT                 7
9524         u8 flags9;
9525 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK                         0x1
9526 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT                        0
9527 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK                         0x1
9528 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT                        1
9529 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK                         0x1
9530 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT                        2
9531 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK                         0x1
9532 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT                        3
9533 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK                 0x1
9534 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT                4
9535 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK                         0x1
9536 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT                        5
9537 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
9538 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
9539 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK                         0x1
9540 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT                        7
9541         u8 flags10;
9542 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK                 0x1
9543 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT                0
9544 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK            0x1
9545 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT           1
9546 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK            0x1
9547 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT           2
9548 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK            0x1
9549 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT           3
9550 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK           0x1
9551 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT          4
9552 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK               0x1
9553 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT              5
9554 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK                0x1
9555 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT               6
9556 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK   0x1
9557 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT  7
9558         u8 flags11;
9559 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK  0x1
9560 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
9561 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK        0x1
9562 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT       1
9563 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK      0x1
9564 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT     2
9565 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK        0x1
9566 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT       3
9567 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK        0x1
9568 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT       4
9569 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK        0x1
9570 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT       5
9571 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK   0x1
9572 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT  6
9573 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK        0x1
9574 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT       7
9575         u8 flags12;
9576 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK   0x1
9577 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT  0
9578 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK               0x1
9579 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT              1
9580 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK           0x1
9581 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT          2
9582 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK           0x1
9583 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT          3
9584 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK       0x1
9585 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT      4
9586 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK               0x1
9587 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT              5
9588 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK               0x1
9589 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT              6
9590 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK               0x1
9591 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT              7
9592         u8 flags13;
9593 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK  0x1
9594 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
9595 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK    0x1
9596 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT   1
9597 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK   0x1
9598 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT  2
9599 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK               0x1
9600 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT              3
9601 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK           0x1
9602 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT          4
9603 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK   0x1
9604 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT  5
9605 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK           0x1
9606 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT          6
9607 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK           0x1
9608 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT          7
9609         u8 flags14;
9610 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK          0x1
9611 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT         0
9612 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK          0x1
9613 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT         1
9614 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK          0x1
9615 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT         2
9616 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK   0x1
9617 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT  3
9618 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK   0x1
9619 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT  4
9620 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK   0x1
9621 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT  5
9622 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK      0x3
9623 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT     6
9624         u8 byte2;
9625         __le16 physical_q0;
9626         __le16 physical_q1;
9627         __le16 sq_comp_cons;
9628         __le16 sq_tx_cons;
9629         __le16 sq_prod;
9630         __le16 word5;
9631         __le16 conn_dpi;
9632         u8 byte3;
9633         u8 byte4;
9634         u8 byte5;
9635         u8 byte6;
9636         __le32 reg0;
9637         __le32 reg1;
9638         __le32 reg2;
9639         __le32 more_to_send_seq;
9640         __le32 reg4;
9641         __le32 rewinded_snd_max_or_term_opcode;
9642         __le32 rd_msn;
9643         __le16 irq_prod_via_msdm;
9644         __le16 irq_cons;
9645         __le16 hq_cons_th_or_mpa_data;
9646         __le16 hq_cons;
9647         __le32 atom_msn;
9648         __le32 orq_cons;
9649         __le32 orq_cons_th;
9650         u8 byte7;
9651         u8 wqe_data_pad_bytes;
9652         u8 max_ord;
9653         u8 former_hq_prod;
9654         u8 irq_prod_via_msem;
9655         u8 byte12;
9656         u8 max_pkt_pdu_size_lo;
9657         u8 max_pkt_pdu_size_hi;
9658         u8 byte15;
9659         u8 e5_reserved;
9660         __le16 e5_reserved4;
9661         __le32 reg10;
9662         __le32 reg11;
9663         __le32 shared_queue_page_addr_lo;
9664         __le32 shared_queue_page_addr_hi;
9665         __le32 reg14;
9666         __le32 reg15;
9667         __le32 reg16;
9668         __le32 reg17;
9669 };
9670
9671 struct e4_tstorm_iwarp_conn_ag_ctx {
9672         u8 reserved0;
9673         u8 state;
9674         u8 flags0;
9675 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK   0x1
9676 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT  0
9677 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK           0x1
9678 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT          1
9679 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK           0x1
9680 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT          2
9681 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK  0x1
9682 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3
9683 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK           0x1
9684 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT          4
9685 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK     0x1
9686 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT    5
9687 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK            0x3
9688 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT           6
9689         u8 flags1;
9690 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK             0x3
9691 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT            0
9692 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK         0x3
9693 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT        2
9694 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK         0x3
9695 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT        4
9696 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK                    0x3
9697 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT                   6
9698         u8 flags2;
9699 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK    0x3
9700 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT   0
9701 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK    0x3
9702 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT   2
9703 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK    0x3
9704 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT   4
9705 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK    0x3
9706 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT   6
9707         u8 flags3;
9708 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
9709 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
9710 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK        0x3
9711 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT       2
9712 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK                          0x1
9713 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT                         4
9714 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK                  0x1
9715 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT                 5
9716 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK              0x1
9717 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT             6
9718 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK              0x1
9719 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT             7
9720         u8 flags4;
9721 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK                          0x1
9722 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT                         0
9723 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK                          0x1
9724 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT                         1
9725 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK                          0x1
9726 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT                         2
9727 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK                          0x1
9728 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT                         3
9729 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK                          0x1
9730 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT                         4
9731 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9732 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5
9733 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK     0x1
9734 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT    6
9735 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK                        0x1
9736 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT                       7
9737         u8 flags5;
9738 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK                0x1
9739 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT               0
9740 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK                0x1
9741 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT               1
9742 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK                0x1
9743 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT               2
9744 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK                0x1
9745 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT               3
9746 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK                0x1
9747 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT               4
9748 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK       0x1
9749 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT      5
9750 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK                0x1
9751 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT               6
9752 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK                0x1
9753 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT               7
9754         __le32 reg0;
9755         __le32 reg1;
9756         __le32 unaligned_nxt_seq;
9757         __le32 reg3;
9758         __le32 reg4;
9759         __le32 reg5;
9760         __le32 reg6;
9761         __le32 reg7;
9762         __le32 reg8;
9763         u8 orq_cache_idx;
9764         u8 hq_prod;
9765         __le16 sq_tx_cons_th;
9766         u8 orq_prod;
9767         u8 irq_cons;
9768         __le16 sq_tx_cons;
9769         __le16 conn_dpi;
9770         __le16 rq_prod;
9771         __le32 snd_seq;
9772         __le32 last_hq_sequence;
9773 };
9774
9775 /* The iwarp storm context of Tstorm */
9776 struct tstorm_iwarp_conn_st_ctx {
9777         __le32 reserved[60];
9778 };
9779
9780 /* The iwarp storm context of Mstorm */
9781 struct mstorm_iwarp_conn_st_ctx {
9782         __le32 reserved[32];
9783 };
9784
9785 /* The iwarp storm context of Ustorm */
9786 struct ustorm_iwarp_conn_st_ctx {
9787         __le32 reserved[24];
9788 };
9789
9790 /* iwarp connection context */
9791 struct e4_iwarp_conn_context {
9792         struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
9793         struct regpair ystorm_st_padding[2];
9794         struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
9795         struct regpair pstorm_st_padding[2];
9796         struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
9797         struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
9798         struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
9799         struct timers_context timer_context;
9800         struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
9801         struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
9802         struct regpair tstorm_st_padding[2];
9803         struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
9804         struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
9805 };
9806
9807 /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
9808 struct iwarp_create_qp_ramrod_data {
9809         u8 flags;
9810 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK    0x1
9811 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT   0
9812 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK          0x1
9813 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT         1
9814 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK             0x1
9815 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT            2
9816 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK             0x1
9817 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT            3
9818 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK              0x1
9819 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT             4
9820 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK                0x1
9821 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT               5
9822 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK   0x1
9823 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT  6
9824 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK              0x1
9825 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT             7
9826         u8 reserved1;
9827         __le16 pd;
9828         __le16 sq_num_pages;
9829         __le16 rq_num_pages;
9830         __le32 reserved3[2];
9831         struct regpair qp_handle_for_cqe;
9832         struct rdma_srq_id srq_id;
9833         __le32 cq_cid_for_sq;
9834         __le32 cq_cid_for_rq;
9835         __le16 dpi;
9836         __le16 physical_q0;
9837         __le16 physical_q1;
9838         u8 reserved2[6];
9839 };
9840
9841 /* iWARP completion queue types */
9842 enum iwarp_eqe_async_opcode {
9843         IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
9844         IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
9845         IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE,
9846         IWARP_EVENT_TYPE_ASYNC_CID_CLEANED,
9847         IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED,
9848         IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE,
9849         IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW,
9850         IWARP_EVENT_TYPE_ASYNC_SRQ_EMPTY,
9851         IWARP_EVENT_TYPE_ASYNC_SRQ_LIMIT,
9852         MAX_IWARP_EQE_ASYNC_OPCODE
9853 };
9854
9855 struct iwarp_eqe_data_mpa_async_completion {
9856         __le16 ulp_data_len;
9857         u8 reserved[6];
9858 };
9859
9860 struct iwarp_eqe_data_tcp_async_completion {
9861         __le16 ulp_data_len;
9862         u8 mpa_handshake_mode;
9863         u8 reserved[5];
9864 };
9865
9866 /* iWARP completion queue types */
9867 enum iwarp_eqe_sync_opcode {
9868         IWARP_EVENT_TYPE_TCP_OFFLOAD =
9869         11,
9870         IWARP_EVENT_TYPE_MPA_OFFLOAD,
9871         IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR,
9872         IWARP_EVENT_TYPE_CREATE_QP,
9873         IWARP_EVENT_TYPE_QUERY_QP,
9874         IWARP_EVENT_TYPE_MODIFY_QP,
9875         IWARP_EVENT_TYPE_DESTROY_QP,
9876         IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD,
9877         MAX_IWARP_EQE_SYNC_OPCODE
9878 };
9879
9880 /* iWARP EQE completion status */
9881 enum iwarp_fw_return_code {
9882         IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5,
9883         IWARP_CONN_ERROR_TCP_CONNECTION_RST,
9884         IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
9885         IWARP_CONN_ERROR_MPA_ERROR_REJECT,
9886         IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER,
9887         IWARP_CONN_ERROR_MPA_RST,
9888         IWARP_CONN_ERROR_MPA_FIN,
9889         IWARP_CONN_ERROR_MPA_RTR_MISMATCH,
9890         IWARP_CONN_ERROR_MPA_INSUF_IRD,
9891         IWARP_CONN_ERROR_MPA_INVALID_PACKET,
9892         IWARP_CONN_ERROR_MPA_LOCAL_ERROR,
9893         IWARP_CONN_ERROR_MPA_TIMEOUT,
9894         IWARP_CONN_ERROR_MPA_TERMINATE,
9895         IWARP_QP_IN_ERROR_GOOD_CLOSE,
9896         IWARP_QP_IN_ERROR_BAD_CLOSE,
9897         IWARP_EXCEPTION_DETECTED_LLP_CLOSED,
9898         IWARP_EXCEPTION_DETECTED_LLP_RESET,
9899         IWARP_EXCEPTION_DETECTED_IRQ_FULL,
9900         IWARP_EXCEPTION_DETECTED_RQ_EMPTY,
9901         IWARP_EXCEPTION_DETECTED_SRQ_EMPTY,
9902         IWARP_EXCEPTION_DETECTED_SRQ_LIMIT,
9903         IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT,
9904         IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR,
9905         IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW,
9906         IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC,
9907         IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR,
9908         IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR,
9909         IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED,
9910         MAX_IWARP_FW_RETURN_CODE
9911 };
9912
9913 /* unaligned opaque data received from LL2 */
9914 struct iwarp_init_func_params {
9915         u8 ll2_ooo_q_index;
9916         u8 reserved1[7];
9917 };
9918
9919 /* iwarp func init ramrod data */
9920 struct iwarp_init_func_ramrod_data {
9921         struct rdma_init_func_ramrod_data rdma;
9922         struct tcp_init_params tcp;
9923         struct iwarp_init_func_params iwarp;
9924 };
9925
9926 /* iWARP QP - possible states to transition to */
9927 enum iwarp_modify_qp_new_state_type {
9928         IWARP_MODIFY_QP_STATE_CLOSING = 1,
9929         IWARP_MODIFY_QP_STATE_ERROR = 2,
9930         MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
9931 };
9932
9933 /* iwarp modify qp responder ramrod data */
9934 struct iwarp_modify_qp_ramrod_data {
9935         __le16 transition_to_state;
9936         __le16 flags;
9937 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK             0x1
9938 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT            0
9939 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK             0x1
9940 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT            1
9941 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK              0x1
9942 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT             2
9943 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK         0x1
9944 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT        3
9945 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK        0x1
9946 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT       4
9947 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK     0x1
9948 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT    5
9949 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK               0x3FF
9950 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT              6
9951         __le16 physical_q0;
9952         __le16 physical_q1;
9953         __le32 reserved1[10];
9954 };
9955
9956 /* MPA params for Enhanced mode */
9957 struct mpa_rq_params {
9958         __le32 ird;
9959         __le32 ord;
9960 };
9961
9962 /* MPA host Address-Len for private data */
9963 struct mpa_ulp_buffer {
9964         struct regpair addr;
9965         __le16 len;
9966         __le16 reserved[3];
9967 };
9968
9969 /* iWARP MPA offload params common to Basic and Enhanced modes */
9970 struct mpa_outgoing_params {
9971         u8 crc_needed;
9972         u8 reject;
9973         u8 reserved[6];
9974         struct mpa_rq_params out_rq;
9975         struct mpa_ulp_buffer outgoing_ulp_buffer;
9976 };
9977
9978 /* iWARP MPA offload params passed by driver to FW in MPA Offload Request
9979  * Ramrod.
9980  */
9981 struct iwarp_mpa_offload_ramrod_data {
9982         struct mpa_outgoing_params common;
9983         __le32 tcp_cid;
9984         u8 mode;
9985         u8 tcp_connect_side;
9986         u8 rtr_pref;
9987 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK        0x7
9988 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT       0
9989 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK            0x1F
9990 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT           3
9991         u8 reserved2;
9992         struct mpa_ulp_buffer incoming_ulp_buffer;
9993         struct regpair async_eqe_output_buf;
9994         struct regpair handle_for_async;
9995         struct regpair shared_queue_addr;
9996         __le16 rcv_wnd;
9997         u8 stats_counter_id;
9998         u8 reserved3[13];
9999 };
10000
10001 /* iWARP TCP connection offload params passed by driver to FW */
10002 struct iwarp_offload_params {
10003         struct mpa_ulp_buffer incoming_ulp_buffer;
10004         struct regpair async_eqe_output_buf;
10005         struct regpair handle_for_async;
10006         __le16 physical_q0;
10007         __le16 physical_q1;
10008         u8 stats_counter_id;
10009         u8 mpa_mode;
10010         u8 reserved[10];
10011 };
10012
10013 /* iWARP query QP output params */
10014 struct iwarp_query_qp_output_params {
10015         __le32 flags;
10016 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK     0x1
10017 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT    0
10018 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK     0x7FFFFFFF
10019 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT    1
10020         u8 reserved1[4];
10021 };
10022
10023 /* iWARP query QP ramrod data */
10024 struct iwarp_query_qp_ramrod_data {
10025         struct regpair output_params_addr;
10026 };
10027
10028 /* iWARP Ramrod Command IDs */
10029 enum iwarp_ramrod_cmd_id {
10030         IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11,
10031         IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
10032         IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
10033         IWARP_RAMROD_CMD_ID_CREATE_QP,
10034         IWARP_RAMROD_CMD_ID_QUERY_QP,
10035         IWARP_RAMROD_CMD_ID_MODIFY_QP,
10036         IWARP_RAMROD_CMD_ID_DESTROY_QP,
10037         IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD,
10038         MAX_IWARP_RAMROD_CMD_ID
10039 };
10040
10041 /* Per PF iWARP retransmit path statistics */
10042 struct iwarp_rxmit_stats_drv {
10043         struct regpair tx_go_to_slow_start_event_cnt;
10044         struct regpair tx_fast_retransmit_event_cnt;
10045 };
10046
10047 /* iWARP and TCP connection offload params passed by driver to FW in iWARP
10048  * offload ramrod.
10049  */
10050 struct iwarp_tcp_offload_ramrod_data {
10051         struct iwarp_offload_params iwarp;
10052         struct tcp_offload_params_opt2 tcp;
10053 };
10054
10055 /* iWARP MPA negotiation types */
10056 enum mpa_negotiation_mode {
10057         MPA_NEGOTIATION_TYPE_BASIC = 1,
10058         MPA_NEGOTIATION_TYPE_ENHANCED = 2,
10059         MAX_MPA_NEGOTIATION_MODE
10060 };
10061
10062 /* iWARP MPA Enhanced mode RTR types */
10063 enum mpa_rtr_type {
10064         MPA_RTR_TYPE_NONE = 0,
10065         MPA_RTR_TYPE_ZERO_SEND = 1,
10066         MPA_RTR_TYPE_ZERO_WRITE = 2,
10067         MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3,
10068         MPA_RTR_TYPE_ZERO_READ = 4,
10069         MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5,
10070         MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6,
10071         MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7,
10072         MAX_MPA_RTR_TYPE
10073 };
10074
10075 /* unaligned opaque data received from LL2 */
10076 struct unaligned_opaque_data {
10077         __le16 first_mpa_offset;
10078         u8 tcp_payload_offset;
10079         u8 flags;
10080 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK   0x1
10081 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT  0
10082 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK            0x1
10083 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT           1
10084 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK                     0x3F
10085 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT                    2
10086         __le32 cid;
10087 };
10088
10089 struct e4_mstorm_iwarp_conn_ag_ctx {
10090         u8 reserved;
10091         u8 state;
10092         u8 flags0;
10093 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK           0x1
10094 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT          0
10095 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK                   0x1
10096 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT                  1
10097 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK       0x3
10098 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT      2
10099 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK                    0x3
10100 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT                   4
10101 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK                    0x3
10102 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT                   6
10103         u8 flags1;
10104 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK    0x1
10105 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT   0
10106 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK                  0x1
10107 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT                 1
10108 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK                  0x1
10109 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT                 2
10110 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK                0x1
10111 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT               3
10112 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK                0x1
10113 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT               4
10114 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK                0x1
10115 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT               5
10116 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK            0x1
10117 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT           6
10118 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK                0x1
10119 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT               7
10120         __le16 rcq_cons;
10121         __le16 rcq_cons_th;
10122         __le32 reg0;
10123         __le32 reg1;
10124 };
10125
10126 struct e4_ustorm_iwarp_conn_ag_ctx {
10127         u8 reserved;
10128         u8 byte1;
10129         u8 flags0;
10130 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK   0x1
10131 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT  0
10132 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK           0x1
10133 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT          1
10134 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK            0x3
10135 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT           2
10136 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK            0x3
10137 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT           4
10138 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK            0x3
10139 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT           6
10140         u8 flags1;
10141 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK            0x3
10142 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT           0
10143 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK   0x3
10144 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT  2
10145 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK      0x3
10146 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT     4
10147 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK            0x3
10148 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT           6
10149         u8 flags2;
10150 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK                  0x1
10151 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT                 0
10152 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK                  0x1
10153 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT                 1
10154 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK                  0x1
10155 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT                 2
10156 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK                  0x1
10157 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT                 3
10158 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK        0x1
10159 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT       4
10160 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK           0x1
10161 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT          5
10162 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK                  0x1
10163 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT                 6
10164 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK               0x1
10165 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT              7
10166         u8 flags3;
10167 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK          0x1
10168 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT         0
10169 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK        0x1
10170 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT       1
10171 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK        0x1
10172 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT       2
10173 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK        0x1
10174 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT       3
10175 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK        0x1
10176 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT       4
10177 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK        0x1
10178 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT       5
10179 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK        0x1
10180 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT       6
10181 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK        0x1
10182 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT       7
10183         u8 byte2;
10184         u8 byte3;
10185         __le16 word0;
10186         __le16 word1;
10187         __le32 cq_cons;
10188         __le32 cq_se_prod;
10189         __le32 cq_prod;
10190         __le32 reg3;
10191         __le16 word2;
10192         __le16 word3;
10193 };
10194
10195 struct e4_ystorm_iwarp_conn_ag_ctx {
10196         u8 byte0;
10197         u8 byte1;
10198         u8 flags0;
10199 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK   0x1
10200 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT  0
10201 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK   0x1
10202 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT  1
10203 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK    0x3
10204 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT   2
10205 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK    0x3
10206 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT   4
10207 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK    0x3
10208 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT   6
10209         u8 flags1;
10210 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK          0x1
10211 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT         0
10212 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK          0x1
10213 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT         1
10214 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK          0x1
10215 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT         2
10216 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK        0x1
10217 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT       3
10218 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK        0x1
10219 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT       4
10220 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK        0x1
10221 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT       5
10222 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK        0x1
10223 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT       6
10224 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK        0x1
10225 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT       7
10226         u8 byte2;
10227         u8 byte3;
10228         __le16 word0;
10229         __le32 reg0;
10230         __le32 reg1;
10231         __le16 word1;
10232         __le16 word2;
10233         __le16 word3;
10234         __le16 word4;
10235         __le32 reg2;
10236         __le32 reg3;
10237 };
10238
10239 /* The fcoe storm context of Ystorm */
10240 struct ystorm_fcoe_conn_st_ctx {
10241         u8 func_mode;
10242         u8 cos;
10243         u8 conf_version;
10244         u8 eth_hdr_size;
10245         __le16 stat_ram_addr;
10246         __le16 mtu;
10247         __le16 max_fc_payload_len;
10248         __le16 tx_max_fc_pay_len;
10249         u8 fcp_cmd_size;
10250         u8 fcp_rsp_size;
10251         __le16 mss;
10252         struct regpair reserved;
10253         __le16 min_frame_size;
10254         u8 protection_info_flags;
10255 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK         0x1
10256 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT        0
10257 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK                      0x1
10258 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT                     1
10259 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK                  0x3F
10260 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT                 2
10261         u8 dst_protection_per_mss;
10262         u8 src_protection_per_mss;
10263         u8 ptu_log_page_size;
10264         u8 flags;
10265 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK    0x1
10266 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT   0
10267 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK    0x1
10268 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT   1
10269 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK               0x3F
10270 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT              2
10271         u8 fcp_xfer_size;
10272 };
10273
10274 /* FCoE 16-bits vlan structure */
10275 struct fcoe_vlan_fields {
10276         __le16 fields;
10277 #define FCOE_VLAN_FIELDS_VID_MASK       0xFFF
10278 #define FCOE_VLAN_FIELDS_VID_SHIFT      0
10279 #define FCOE_VLAN_FIELDS_CLI_MASK       0x1
10280 #define FCOE_VLAN_FIELDS_CLI_SHIFT      12
10281 #define FCOE_VLAN_FIELDS_PRI_MASK       0x7
10282 #define FCOE_VLAN_FIELDS_PRI_SHIFT      13
10283 };
10284
10285 /* FCoE 16-bits vlan union */
10286 union fcoe_vlan_field_union {
10287         struct fcoe_vlan_fields fields;
10288         __le16 val;
10289 };
10290
10291 /* FCoE 16-bits vlan, vif union */
10292 union fcoe_vlan_vif_field_union {
10293         union fcoe_vlan_field_union vlan;
10294         __le16 vif;
10295 };
10296
10297 /* Ethernet context section */
10298 struct pstorm_fcoe_eth_context_section {
10299         u8 remote_addr_3;
10300         u8 remote_addr_2;
10301         u8 remote_addr_1;
10302         u8 remote_addr_0;
10303         u8 local_addr_1;
10304         u8 local_addr_0;
10305         u8 remote_addr_5;
10306         u8 remote_addr_4;
10307         u8 local_addr_5;
10308         u8 local_addr_4;
10309         u8 local_addr_3;
10310         u8 local_addr_2;
10311         union fcoe_vlan_vif_field_union vif_outer_vlan;
10312         __le16 vif_outer_eth_type;
10313         union fcoe_vlan_vif_field_union inner_vlan;
10314         __le16 inner_eth_type;
10315 };
10316
10317 /* The fcoe storm context of Pstorm */
10318 struct pstorm_fcoe_conn_st_ctx {
10319         u8 func_mode;
10320         u8 cos;
10321         u8 conf_version;
10322         u8 rsrv;
10323         __le16 stat_ram_addr;
10324         __le16 mss;
10325         struct regpair abts_cleanup_addr;
10326         struct pstorm_fcoe_eth_context_section eth;
10327         u8 sid_2;
10328         u8 sid_1;
10329         u8 sid_0;
10330         u8 flags;
10331 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK                 0x1
10332 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT                0
10333 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK         0x1
10334 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT        1
10335 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK            0x1
10336 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT           2
10337 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK            0x1
10338 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT           3
10339 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK           0x1
10340 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT          4
10341 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK                   0x7
10342 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT                  5
10343         u8 did_2;
10344         u8 did_1;
10345         u8 did_0;
10346         u8 src_mac_index;
10347         __le16 rec_rr_tov_val;
10348         u8 q_relative_offset;
10349         u8 reserved1;
10350 };
10351
10352 /* The fcoe storm context of Xstorm */
10353 struct xstorm_fcoe_conn_st_ctx {
10354         u8 func_mode;
10355         u8 src_mac_index;
10356         u8 conf_version;
10357         u8 cached_wqes_avail;
10358         __le16 stat_ram_addr;
10359         u8 flags;
10360 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK                0x1
10361 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT               0
10362 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK            0x1
10363 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT           1
10364 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK       0x1
10365 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT      2
10366 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK         0x3
10367 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT        3
10368 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK                       0x7
10369 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT                      5
10370         u8 cached_wqes_offset;
10371         u8 reserved2;
10372         u8 eth_hdr_size;
10373         u8 seq_id;
10374         u8 max_conc_seqs;
10375         __le16 num_pages_in_pbl;
10376         __le16 reserved;
10377         struct regpair sq_pbl_addr;
10378         struct regpair sq_curr_page_addr;
10379         struct regpair sq_next_page_addr;
10380         struct regpair xferq_pbl_addr;
10381         struct regpair xferq_curr_page_addr;
10382         struct regpair xferq_next_page_addr;
10383         struct regpair respq_pbl_addr;
10384         struct regpair respq_curr_page_addr;
10385         struct regpair respq_next_page_addr;
10386         __le16 mtu;
10387         __le16 tx_max_fc_pay_len;
10388         __le16 max_fc_payload_len;
10389         __le16 min_frame_size;
10390         __le16 sq_pbl_next_index;
10391         __le16 respq_pbl_next_index;
10392         u8 fcp_cmd_byte_credit;
10393         u8 fcp_rsp_byte_credit;
10394         __le16 protection_info;
10395 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK            0x1
10396 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT           0
10397 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK         0x1
10398 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT        1
10399 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK                      0x1
10400 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT                     2
10401 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK         0x1
10402 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT        3
10403 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK                  0xF
10404 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT                 4
10405 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK     0xFF
10406 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT    8
10407         __le16 xferq_pbl_next_index;
10408         __le16 page_size;
10409         u8 mid_seq;
10410         u8 fcp_xfer_byte_credit;
10411         u8 reserved1[2];
10412         struct fcoe_wqe cached_wqes[16];
10413 };
10414
10415 struct e4_xstorm_fcoe_conn_ag_ctx {
10416         u8 reserved0;
10417         u8 state;
10418         u8 flags0;
10419 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK    0x1
10420 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT   0
10421 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK       0x1
10422 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT      1
10423 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK       0x1
10424 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT      2
10425 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK    0x1
10426 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT   3
10427 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK       0x1
10428 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT      4
10429 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK       0x1
10430 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT      5
10431 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK       0x1
10432 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT      6
10433 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK       0x1
10434 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT      7
10435         u8 flags1;
10436 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK       0x1
10437 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT      0
10438 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK       0x1
10439 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT      1
10440 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK       0x1
10441 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT      2
10442 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK           0x1
10443 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT          3
10444 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK           0x1
10445 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT          4
10446 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK           0x1
10447 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT          5
10448 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK           0x1
10449 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT          6
10450 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK           0x1
10451 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT          7
10452         u8 flags2;
10453 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK     0x3
10454 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT    0
10455 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK     0x3
10456 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT    2
10457 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK     0x3
10458 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT    4
10459 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK     0x3
10460 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT    6
10461         u8 flags3;
10462 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK     0x3
10463 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT    0
10464 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK     0x3
10465 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT    2
10466 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK     0x3
10467 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT    4
10468 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK     0x3
10469 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT    6
10470         u8 flags4;
10471 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK     0x3
10472 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT    0
10473 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK     0x3
10474 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT    2
10475 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK    0x3
10476 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT   4
10477 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK    0x3
10478 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT   6
10479         u8 flags5;
10480 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK    0x3
10481 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT   0
10482 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK    0x3
10483 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT   2
10484 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK    0x3
10485 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT   4
10486 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK    0x3
10487 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT   6
10488         u8 flags6;
10489 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK    0x3
10490 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT   0
10491 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK    0x3
10492 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT   2
10493 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK    0x3
10494 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT   4
10495 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK   0x3
10496 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT  6
10497         u8 flags7;
10498 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK        0x3
10499 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT       0
10500 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK      0x3
10501 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT     2
10502 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK       0x3
10503 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT      4
10504 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK           0x1
10505 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT          6
10506 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK           0x1
10507 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT          7
10508         u8 flags8;
10509 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK   0x1
10510 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT  0
10511 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK   0x1
10512 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT  1
10513 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK   0x1
10514 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT  2
10515 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK   0x1
10516 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT  3
10517 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK   0x1
10518 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT  4
10519 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK   0x1
10520 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT  5
10521 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK   0x1
10522 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT  6
10523 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK   0x1
10524 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT  7
10525         u8 flags9;
10526 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK  0x1
10527 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
10528 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK  0x1
10529 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
10530 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK  0x1
10531 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
10532 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK  0x1
10533 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
10534 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK  0x1
10535 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
10536 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK  0x1
10537 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
10538 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK  0x1
10539 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
10540 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK  0x1
10541 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
10542         u8 flags10;
10543 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK          0x1
10544 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT         0
10545 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK        0x1
10546 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT       1
10547 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK     0x1
10548 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT    2
10549 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK      0x1
10550 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT     3
10551 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK    0x1
10552 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT   4
10553 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK          0x1
10554 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT         5
10555 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK      0x1
10556 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT     6
10557 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK      0x1
10558 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT     7
10559         u8 flags11;
10560 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK              0x1
10561 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT             0
10562 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK              0x1
10563 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT             1
10564 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK              0x1
10565 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT             2
10566 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK                 0x1
10567 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT                3
10568 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK                 0x1
10569 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT                4
10570 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK                 0x1
10571 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT                5
10572 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK            0x1
10573 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT           6
10574 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK       0x1
10575 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT      7
10576         u8 flags12;
10577 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK  0x1
10578 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
10579 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK        0x1
10580 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT       1
10581 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK    0x1
10582 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT   2
10583 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK    0x1
10584 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT   3
10585 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK        0x1
10586 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT       4
10587 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK        0x1
10588 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT       5
10589 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK        0x1
10590 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT       6
10591 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK        0x1
10592 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT       7
10593         u8 flags13;
10594 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK       0x1
10595 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT      0
10596 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK                0x1
10597 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT               1
10598 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK            0x1
10599 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT           2
10600 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK            0x1
10601 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT           3
10602 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK            0x1
10603 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT           4
10604 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK            0x1
10605 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT           5
10606 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK            0x1
10607 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT           6
10608 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK            0x1
10609 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT           7
10610         u8 flags14;
10611 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK   0x1
10612 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT  0
10613 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK   0x1
10614 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT  1
10615 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK   0x1
10616 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT  2
10617 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK   0x1
10618 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT  3
10619 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK   0x1
10620 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT  4
10621 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK   0x1
10622 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT  5
10623 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK    0x3
10624 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT   6
10625         u8 byte2;
10626         __le16 physical_q0;
10627         __le16 word1;
10628         __le16 word2;
10629         __le16 sq_cons;
10630         __le16 sq_prod;
10631         __le16 xferq_prod;
10632         __le16 xferq_cons;
10633         u8 byte3;
10634         u8 byte4;
10635         u8 byte5;
10636         u8 byte6;
10637         __le32 remain_io;
10638         __le32 reg1;
10639         __le32 reg2;
10640         __le32 reg3;
10641         __le32 reg4;
10642         __le32 reg5;
10643         __le32 reg6;
10644         __le16 respq_prod;
10645         __le16 respq_cons;
10646         __le16 word9;
10647         __le16 word10;
10648         __le32 reg7;
10649         __le32 reg8;
10650 };
10651
10652 /* The fcoe storm context of Ustorm */
10653 struct ustorm_fcoe_conn_st_ctx {
10654         struct regpair respq_pbl_addr;
10655         __le16 num_pages_in_pbl;
10656         u8 ptu_log_page_size;
10657         u8 log_page_size;
10658         __le16 respq_prod;
10659         u8 reserved[2];
10660 };
10661
10662 struct e4_tstorm_fcoe_conn_ag_ctx {
10663         u8 reserved0;
10664         u8 state;
10665         u8 flags0;
10666 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK    0x1
10667 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT   0
10668 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK            0x1
10669 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT           1
10670 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK            0x1
10671 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT           2
10672 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK            0x1
10673 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT           3
10674 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK            0x1
10675 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT           4
10676 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK            0x1
10677 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT           5
10678 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK  0x3
10679 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
10680         u8 flags1;
10681 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK             0x3
10682 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT            0
10683 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK                     0x3
10684 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT                    2
10685 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK       0x3
10686 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT      4
10687 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK                     0x3
10688 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT                    6
10689         u8 flags2;
10690 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK     0x3
10691 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT    0
10692 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK     0x3
10693 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT    2
10694 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK     0x3
10695 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT    4
10696 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK     0x3
10697 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT    6
10698         u8 flags3;
10699 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK                     0x3
10700 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT                    0
10701 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK                    0x3
10702 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT                   2
10703 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK       0x1
10704 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT      4
10705 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK          0x1
10706 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT         5
10707 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK                   0x1
10708 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT                  6
10709 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK    0x1
10710 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT   7
10711         u8 flags4;
10712 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK           0x1
10713 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT          0
10714 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK           0x1
10715 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT          1
10716 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK           0x1
10717 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT          2
10718 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK           0x1
10719 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT          3
10720 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK           0x1
10721 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT          4
10722 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK           0x1
10723 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT          5
10724 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK          0x1
10725 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT         6
10726 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK         0x1
10727 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT        7
10728         u8 flags5;
10729 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK         0x1
10730 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT        0
10731 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK         0x1
10732 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT        1
10733 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK         0x1
10734 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT        2
10735 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK         0x1
10736 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT        3
10737 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK         0x1
10738 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT        4
10739 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK         0x1
10740 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT        5
10741 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK         0x1
10742 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT        6
10743 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK         0x1
10744 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT        7
10745         __le32 reg0;
10746         __le32 reg1;
10747 };
10748
10749 struct e4_ustorm_fcoe_conn_ag_ctx {
10750         u8 byte0;
10751         u8 byte1;
10752         u8 flags0;
10753 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK    0x1
10754 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT   0
10755 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK    0x1
10756 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT   1
10757 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK     0x3
10758 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT    2
10759 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK     0x3
10760 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT    4
10761 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK     0x3
10762 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT    6
10763         u8 flags1;
10764 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK     0x3
10765 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT    0
10766 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK     0x3
10767 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT    2
10768 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK     0x3
10769 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT    4
10770 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK     0x3
10771 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT    6
10772         u8 flags2;
10773 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK           0x1
10774 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT          0
10775 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK           0x1
10776 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT          1
10777 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK           0x1
10778 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT          2
10779 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK           0x1
10780 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT          3
10781 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK           0x1
10782 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT          4
10783 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK           0x1
10784 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT          5
10785 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK           0x1
10786 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT          6
10787 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK         0x1
10788 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT        7
10789         u8 flags3;
10790 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK         0x1
10791 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT        0
10792 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK         0x1
10793 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT        1
10794 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK         0x1
10795 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT        2
10796 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK         0x1
10797 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT        3
10798 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK         0x1
10799 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT        4
10800 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK         0x1
10801 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT        5
10802 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK         0x1
10803 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT        6
10804 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK         0x1
10805 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT        7
10806         u8 byte2;
10807         u8 byte3;
10808         __le16 word0;
10809         __le16 word1;
10810         __le32 reg0;
10811         __le32 reg1;
10812         __le32 reg2;
10813         __le32 reg3;
10814         __le16 word2;
10815         __le16 word3;
10816 };
10817
10818 /* The fcoe storm context of Tstorm */
10819 struct tstorm_fcoe_conn_st_ctx {
10820         __le16 stat_ram_addr;
10821         __le16 rx_max_fc_payload_len;
10822         __le16 e_d_tov_val;
10823         u8 flags;
10824 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK        0x1
10825 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT       0
10826 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK       0x1
10827 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT      1
10828 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK          0x3F
10829 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT         2
10830         u8 timers_cleanup_invocation_cnt;
10831         __le32 reserved1[2];
10832         __le32 dst_mac_address_bytes_0_to_3;
10833         __le16 dst_mac_address_bytes_4_to_5;
10834         __le16 ramrod_echo;
10835         u8 flags1;
10836 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK       0x3
10837 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT      0
10838 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK   0x3F
10839 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT  2
10840         u8 cq_relative_offset;
10841         u8 cmdq_relative_offset;
10842         u8 bdq_resource_id;
10843         u8 reserved0[4];
10844 };
10845
10846 struct e4_mstorm_fcoe_conn_ag_ctx {
10847         u8 byte0;
10848         u8 byte1;
10849         u8 flags0;
10850 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK    0x1
10851 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT   0
10852 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK    0x1
10853 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT   1
10854 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK     0x3
10855 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT    2
10856 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK     0x3
10857 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT    4
10858 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK     0x3
10859 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT    6
10860         u8 flags1;
10861 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK           0x1
10862 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT          0
10863 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK           0x1
10864 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT          1
10865 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK           0x1
10866 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT          2
10867 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK         0x1
10868 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT        3
10869 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK         0x1
10870 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT        4
10871 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK         0x1
10872 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT        5
10873 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK         0x1
10874 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT        6
10875 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK         0x1
10876 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT        7
10877         __le16 word0;
10878         __le16 word1;
10879         __le32 reg0;
10880         __le32 reg1;
10881 };
10882
10883 /* Fast path part of the fcoe storm context of Mstorm */
10884 struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
10885         __le16 xfer_prod;
10886         u8 num_cqs;
10887         u8 reserved1;
10888         u8 protection_info;
10889 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK  0x1
10890 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10891 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK               0x1
10892 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT              1
10893 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK           0x3F
10894 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT          2
10895         u8 q_relative_offset;
10896         u8 reserved2[2];
10897 };
10898
10899 /* Non fast path part of the fcoe storm context of Mstorm */
10900 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
10901         __le16 conn_id;
10902         __le16 stat_ram_addr;
10903         __le16 num_pages_in_pbl;
10904         u8 ptu_log_page_size;
10905         u8 log_page_size;
10906         __le16 unsolicited_cq_count;
10907         __le16 cmdq_count;
10908         u8 bdq_resource_id;
10909         u8 reserved0[3];
10910         struct regpair xferq_pbl_addr;
10911         struct regpair reserved1;
10912         struct regpair reserved2[3];
10913 };
10914
10915 /* The fcoe storm context of Mstorm */
10916 struct mstorm_fcoe_conn_st_ctx {
10917         struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
10918         struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
10919 };
10920
10921 /* fcoe connection context */
10922 struct e4_fcoe_conn_context {
10923         struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
10924         struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
10925         struct regpair pstorm_st_padding[2];
10926         struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
10927         struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
10928         struct regpair xstorm_ag_padding[6];
10929         struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
10930         struct regpair ustorm_st_padding[2];
10931         struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
10932         struct regpair tstorm_ag_padding[2];
10933         struct timers_context timer_context;
10934         struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
10935         struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
10936         struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
10937         struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
10938 };
10939
10940 /* FCoE connection offload params passed by driver to FW in FCoE offload
10941  * ramrod.
10942  */
10943 struct fcoe_conn_offload_ramrod_params {
10944         struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
10945 };
10946
10947 /* FCoE connection terminate params passed by driver to FW in FCoE terminate
10948  * conn ramrod.
10949  */
10950 struct fcoe_conn_terminate_ramrod_params {
10951         struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
10952 };
10953
10954 /* FCoE event type */
10955 enum fcoe_event_type {
10956         FCOE_EVENT_INIT_FUNC,
10957         FCOE_EVENT_DESTROY_FUNC,
10958         FCOE_EVENT_STAT_FUNC,
10959         FCOE_EVENT_OFFLOAD_CONN,
10960         FCOE_EVENT_TERMINATE_CONN,
10961         FCOE_EVENT_ERROR,
10962         MAX_FCOE_EVENT_TYPE
10963 };
10964
10965 /* FCoE init params passed by driver to FW in FCoE init ramrod */
10966 struct fcoe_init_ramrod_params {
10967         struct fcoe_init_func_ramrod_data init_ramrod_data;
10968 };
10969
10970 /* FCoE ramrod Command IDs */
10971 enum fcoe_ramrod_cmd_id {
10972         FCOE_RAMROD_CMD_ID_INIT_FUNC,
10973         FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
10974         FCOE_RAMROD_CMD_ID_STAT_FUNC,
10975         FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
10976         FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
10977         MAX_FCOE_RAMROD_CMD_ID
10978 };
10979
10980 /* FCoE statistics params buffer passed by driver to FW in FCoE statistics
10981  * ramrod.
10982  */
10983 struct fcoe_stat_ramrod_params {
10984         struct fcoe_stat_ramrod_data stat_ramrod_data;
10985 };
10986
10987 struct e4_ystorm_fcoe_conn_ag_ctx {
10988         u8 byte0;
10989         u8 byte1;
10990         u8 flags0;
10991 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK    0x1
10992 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT   0
10993 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK    0x1
10994 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT   1
10995 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK     0x3
10996 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT    2
10997 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK     0x3
10998 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT    4
10999 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK     0x3
11000 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT    6
11001         u8 flags1;
11002 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK           0x1
11003 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT          0
11004 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK           0x1
11005 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT          1
11006 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK           0x1
11007 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT          2
11008 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK         0x1
11009 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT        3
11010 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK         0x1
11011 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT        4
11012 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK         0x1
11013 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT        5
11014 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK         0x1
11015 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT        6
11016 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK         0x1
11017 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT        7
11018         u8 byte2;
11019         u8 byte3;
11020         __le16 word0;
11021         __le32 reg0;
11022         __le32 reg1;
11023         __le16 word1;
11024         __le16 word2;
11025         __le16 word3;
11026         __le16 word4;
11027         __le32 reg2;
11028         __le32 reg3;
11029 };
11030
11031 /* The iscsi storm connection context of Ystorm */
11032 struct ystorm_iscsi_conn_st_ctx {
11033         __le32 reserved[8];
11034 };
11035
11036 /* Combined iSCSI and TCP storm connection of Pstorm */
11037 struct pstorm_iscsi_tcp_conn_st_ctx {
11038         __le32 tcp[32];
11039         __le32 iscsi[4];
11040 };
11041
11042 /* The combined tcp and iscsi storm context of Xstorm */
11043 struct xstorm_iscsi_tcp_conn_st_ctx {
11044         __le32 reserved_tcp[4];
11045         __le32 reserved_iscsi[44];
11046 };
11047
11048 struct e4_xstorm_iscsi_conn_ag_ctx {
11049         u8 cdu_validation;
11050         u8 state;
11051         u8 flags0;
11052 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK   0x1
11053 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT  0
11054 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK   0x1
11055 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT  1
11056 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK      0x1
11057 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT     2
11058 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK   0x1
11059 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT  3
11060 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK           0x1
11061 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT          4
11062 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK      0x1
11063 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT     5
11064 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK           0x1
11065 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT          6
11066 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK           0x1
11067 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT          7
11068         u8 flags1;
11069 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK           0x1
11070 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT          0
11071 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK           0x1
11072 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT          1
11073 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK          0x1
11074 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT         2
11075 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK          0x1
11076 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT         3
11077 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK          0x1
11078 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT         4
11079 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK          0x1
11080 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT         5
11081 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK          0x1
11082 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT         6
11083 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK    0x1
11084 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT   7
11085         u8 flags2;
11086 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK                    0x3
11087 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT                   0
11088 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK                    0x3
11089 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT                   2
11090 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK                    0x3
11091 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT                   4
11092 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK         0x3
11093 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT        6
11094         u8 flags3;
11095 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK    0x3
11096 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT   0
11097 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK    0x3
11098 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT   2
11099 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK    0x3
11100 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT   4
11101 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK    0x3
11102 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT   6
11103         u8 flags4;
11104 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK    0x3
11105 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT   0
11106 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK    0x3
11107 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT   2
11108 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK   0x3
11109 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT  4
11110 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK   0x3
11111 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT  6
11112         u8 flags5;
11113 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK                           0x3
11114 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT                          0
11115 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK                           0x3
11116 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT                          2
11117 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK                           0x3
11118 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT                          4
11119 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK        0x3
11120 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT       6
11121         u8 flags6;
11122 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK           0x3
11123 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT          0
11124 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK           0x3
11125 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT          2
11126 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK           0x3
11127 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT          4
11128 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK       0x3
11129 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT      6
11130         u8 flags7;
11131 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK    0x3
11132 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT   0
11133 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK    0x3
11134 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT   2
11135 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK              0x3
11136 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT             4
11137 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK                  0x1
11138 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT                 6
11139 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK                  0x1
11140 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT                 7
11141         u8 flags8;
11142 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK                  0x1
11143 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT                 0
11144 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK      0x1
11145 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT     1
11146 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK                  0x1
11147 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT                 2
11148 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK                  0x1
11149 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT                 3
11150 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK                  0x1
11151 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT                 4
11152 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK                  0x1
11153 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT                 5
11154 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK                  0x1
11155 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT                 6
11156 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK                  0x1
11157 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT                 7
11158         u8 flags9;
11159 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK                         0x1
11160 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT                        0
11161 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK                         0x1
11162 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT                        1
11163 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK                         0x1
11164 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT                        2
11165 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK                         0x1
11166 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT                        3
11167 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK                         0x1
11168 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT                        4
11169 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK     0x1
11170 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT    5
11171 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK                         0x1
11172 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT                        6
11173 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK                         0x1
11174 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT                        7
11175         u8 flags10;
11176 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK                         0x1
11177 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT                        0
11178 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK                    0x1
11179 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT                   1
11180 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK         0x1
11181 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT        2
11182 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK         0x1
11183 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT        3
11184 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK                   0x1
11185 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT                  4
11186 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK           0x1
11187 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT          5
11188 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK                        0x1
11189 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT                       6
11190 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK       0x1
11191 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT      7
11192         u8 flags11;
11193 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK  0x1
11194 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
11195 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK        0x1
11196 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT       1
11197 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK      0x1
11198 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT     2
11199 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK        0x1
11200 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT       3
11201 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK        0x1
11202 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT       4
11203 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK        0x1
11204 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT       5
11205 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK   0x1
11206 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT  6
11207 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK        0x1
11208 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT       7
11209         u8 flags12;
11210 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK         0x1
11211 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT        0
11212 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK               0x1
11213 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT              1
11214 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK           0x1
11215 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT          2
11216 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK           0x1
11217 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT          3
11218 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK               0x1
11219 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT              4
11220 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK               0x1
11221 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT              5
11222 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK               0x1
11223 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT              6
11224 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK               0x1
11225 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT              7
11226         u8 flags13;
11227 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK       0x1
11228 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT      0
11229 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK         0x1
11230 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT        1
11231 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK           0x1
11232 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT          2
11233 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK           0x1
11234 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT          3
11235 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK           0x1
11236 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT          4
11237 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK           0x1
11238 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT          5
11239 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK           0x1
11240 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT          6
11241 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK           0x1
11242 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT          7
11243         u8 flags14;
11244 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK                  0x1
11245 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT                 0
11246 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK                  0x1
11247 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT                 1
11248 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK                  0x1
11249 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT                 2
11250 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK                  0x1
11251 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT                 3
11252 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK                  0x1
11253 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT                 4
11254 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK        0x1
11255 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT       5
11256 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK      0x3
11257 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT     6
11258         u8 byte2;
11259         __le16 physical_q0;
11260         __le16 physical_q1;
11261         __le16 dummy_dorq_var;
11262         __le16 sq_cons;
11263         __le16 sq_prod;
11264         __le16 word5;
11265         __le16 slow_io_total_data_tx_update;
11266         u8 byte3;
11267         u8 byte4;
11268         u8 byte5;
11269         u8 byte6;
11270         __le32 reg0;
11271         __le32 reg1;
11272         __le32 reg2;
11273         __le32 more_to_send_seq;
11274         __le32 reg4;
11275         __le32 reg5;
11276         __le32 hq_scan_next_relevant_ack;
11277         __le16 r2tq_prod;
11278         __le16 r2tq_cons;
11279         __le16 hq_prod;
11280         __le16 hq_cons;
11281         __le32 remain_seq;
11282         __le32 bytes_to_next_pdu;
11283         __le32 hq_tcp_seq;
11284         u8 byte7;
11285         u8 byte8;
11286         u8 byte9;
11287         u8 byte10;
11288         u8 byte11;
11289         u8 byte12;
11290         u8 byte13;
11291         u8 byte14;
11292         u8 byte15;
11293         u8 e5_reserved;
11294         __le16 word11;
11295         __le32 reg10;
11296         __le32 reg11;
11297         __le32 exp_stat_sn;
11298         __le32 ongoing_fast_rxmit_seq;
11299         __le32 reg14;
11300         __le32 reg15;
11301         __le32 reg16;
11302         __le32 reg17;
11303 };
11304
11305 struct e4_tstorm_iscsi_conn_ag_ctx {
11306         u8 reserved0;
11307         u8 state;
11308         u8 flags0;
11309 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK   0x1
11310 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT  0
11311 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK           0x1
11312 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT          1
11313 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK           0x1
11314 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT          2
11315 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK           0x1
11316 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT          3
11317 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK           0x1
11318 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT          4
11319 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK           0x1
11320 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT          5
11321 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK            0x3
11322 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT           6
11323         u8 flags1;
11324 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK           0x3
11325 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT          0
11326 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK           0x3
11327 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT          2
11328 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK         0x3
11329 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT        4
11330 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK                    0x3
11331 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT                   6
11332         u8 flags2;
11333 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK    0x3
11334 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT   0
11335 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK    0x3
11336 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT   2
11337 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK    0x3
11338 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT   4
11339 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK    0x3
11340 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT   6
11341         u8 flags3;
11342 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK               0x3
11343 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT              0
11344 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK                   0x3
11345 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT                  2
11346 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK                  0x1
11347 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT                 4
11348 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK        0x1
11349 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT       5
11350 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK        0x1
11351 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT       6
11352 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK      0x1
11353 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT     7
11354         u8 flags4;
11355 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK          0x1
11356 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT         0
11357 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK          0x1
11358 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT         1
11359 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK          0x1
11360 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT         2
11361 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK          0x1
11362 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT         3
11363 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK          0x1
11364 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT         4
11365 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK    0x1
11366 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT   5
11367 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK         0x1
11368 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT        6
11369 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK        0x1
11370 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT       7
11371         u8 flags5;
11372 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK        0x1
11373 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT       0
11374 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK        0x1
11375 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT       1
11376 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK        0x1
11377 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT       2
11378 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK        0x1
11379 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT       3
11380 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK        0x1
11381 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT       4
11382 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK        0x1
11383 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT       5
11384 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK        0x1
11385 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT       6
11386 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK        0x1
11387 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT       7
11388         __le32 reg0;
11389         __le32 reg1;
11390         __le32 rx_tcp_checksum_err_cnt;
11391         __le32 reg3;
11392         __le32 reg4;
11393         __le32 reg5;
11394         __le32 reg6;
11395         __le32 reg7;
11396         __le32 reg8;
11397         u8 cid_offload_cnt;
11398         u8 byte3;
11399         __le16 word0;
11400 };
11401
11402 struct e4_ustorm_iscsi_conn_ag_ctx {
11403         u8 byte0;
11404         u8 byte1;
11405         u8 flags0;
11406 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK   0x1
11407 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT  0
11408 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK   0x1
11409 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT  1
11410 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK    0x3
11411 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT   2
11412 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK    0x3
11413 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT   4
11414 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK    0x3
11415 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT   6
11416         u8 flags1;
11417 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK    0x3
11418 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT   0
11419 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK    0x3
11420 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT   2
11421 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK    0x3
11422 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT   4
11423 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK    0x3
11424 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT   6
11425         u8 flags2;
11426 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK          0x1
11427 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT         0
11428 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK          0x1
11429 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT         1
11430 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK          0x1
11431 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT         2
11432 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK          0x1
11433 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT         3
11434 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK          0x1
11435 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT         4
11436 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK          0x1
11437 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT         5
11438 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK          0x1
11439 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT         6
11440 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK        0x1
11441 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT       7
11442         u8 flags3;
11443 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK        0x1
11444 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT       0
11445 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK        0x1
11446 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT       1
11447 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK        0x1
11448 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT       2
11449 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK        0x1
11450 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT       3
11451 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK        0x1
11452 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT       4
11453 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK        0x1
11454 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT       5
11455 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK        0x1
11456 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT       6
11457 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK        0x1
11458 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT       7
11459         u8 byte2;
11460         u8 byte3;
11461         __le16 word0;
11462         __le16 word1;
11463         __le32 reg0;
11464         __le32 reg1;
11465         __le32 reg2;
11466         __le32 reg3;
11467         __le16 word2;
11468         __le16 word3;
11469 };
11470
11471 /* The iscsi storm connection context of Tstorm */
11472 struct tstorm_iscsi_conn_st_ctx {
11473         __le32 reserved[44];
11474 };
11475
11476 struct e4_mstorm_iscsi_conn_ag_ctx {
11477         u8 reserved;
11478         u8 state;
11479         u8 flags0;
11480 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK   0x1
11481 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT  0
11482 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK   0x1
11483 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT  1
11484 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK    0x3
11485 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT   2
11486 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK    0x3
11487 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT   4
11488 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK    0x3
11489 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT   6
11490         u8 flags1;
11491 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK          0x1
11492 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT         0
11493 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK          0x1
11494 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT         1
11495 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK          0x1
11496 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT         2
11497 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK        0x1
11498 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT       3
11499 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK        0x1
11500 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT       4
11501 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK        0x1
11502 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT       5
11503 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK        0x1
11504 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT       6
11505 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK        0x1
11506 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT       7
11507         __le16 word0;
11508         __le16 word1;
11509         __le32 reg0;
11510         __le32 reg1;
11511 };
11512
11513 /* Combined iSCSI and TCP storm connection of Mstorm */
11514 struct mstorm_iscsi_tcp_conn_st_ctx {
11515         __le32 reserved_tcp[20];
11516         __le32 reserved_iscsi[12];
11517 };
11518
11519 /* The iscsi storm context of Ustorm */
11520 struct ustorm_iscsi_conn_st_ctx {
11521         __le32 reserved[52];
11522 };
11523
11524 /* iscsi connection context */
11525 struct e4_iscsi_conn_context {
11526         struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
11527         struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
11528         struct regpair pstorm_st_padding[2];
11529         struct pb_context xpb2_context;
11530         struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
11531         struct regpair xstorm_st_padding[2];
11532         struct e4_xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
11533         struct e4_tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
11534         struct regpair tstorm_ag_padding[2];
11535         struct timers_context timer_context;
11536         struct e4_ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
11537         struct pb_context upb_context;
11538         struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
11539         struct regpair tstorm_st_padding[2];
11540         struct e4_mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
11541         struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
11542         struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
11543 };
11544
11545 /* iSCSI init params passed by driver to FW in iSCSI init ramrod */
11546 struct iscsi_init_ramrod_params {
11547         struct iscsi_spe_func_init iscsi_init_spe;
11548         struct tcp_init_params tcp_init;
11549 };
11550
11551 struct e4_ystorm_iscsi_conn_ag_ctx {
11552         u8 byte0;
11553         u8 byte1;
11554         u8 flags0;
11555 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK   0x1
11556 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT  0
11557 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK   0x1
11558 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT  1
11559 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK    0x3
11560 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT   2
11561 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK    0x3
11562 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT   4
11563 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK    0x3
11564 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT   6
11565         u8 flags1;
11566 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK          0x1
11567 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT         0
11568 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK          0x1
11569 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT         1
11570 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK          0x1
11571 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT         2
11572 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK        0x1
11573 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT       3
11574 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK        0x1
11575 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT       4
11576 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK        0x1
11577 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT       5
11578 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK        0x1
11579 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT       6
11580 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK        0x1
11581 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT       7
11582         u8 byte2;
11583         u8 byte3;
11584         __le16 word0;
11585         __le32 reg0;
11586         __le32 reg1;
11587         __le16 word1;
11588         __le16 word2;
11589         __le16 word3;
11590         __le16 word4;
11591         __le32 reg2;
11592         __le32 reg3;
11593 };
11594
11595 #define MFW_TRACE_SIGNATURE     0x25071946
11596
11597 /* The trace in the buffer */
11598 #define MFW_TRACE_EVENTID_MASK          0x00ffff
11599 #define MFW_TRACE_PRM_SIZE_MASK         0x0f0000
11600 #define MFW_TRACE_PRM_SIZE_SHIFT        16
11601 #define MFW_TRACE_ENTRY_SIZE            3
11602
11603 struct mcp_trace {
11604         u32 signature;          /* Help to identify that the trace is valid */
11605         u32 size;               /* the size of the trace buffer in bytes */
11606         u32 curr_level;         /* 2 - all will be written to the buffer
11607                                  * 1 - debug trace will not be written
11608                                  * 0 - just errors will be written to the buffer
11609                                  */
11610         u32 modules_mask[2];    /* a bit per module, 1 means write it, 0 means
11611                                  * mask it.
11612                                  */
11613
11614         /* Warning: the following pointers are assumed to be 32bits as they are
11615          * used only in the MFW.
11616          */
11617         u32 trace_prod; /* The next trace will be written to this offset */
11618         u32 trace_oldest; /* The oldest valid trace starts at this offset
11619                            * (usually very close after the current producer).
11620                            */
11621 };
11622
11623 #define VF_MAX_STATIC 192
11624
11625 #define MCP_GLOB_PATH_MAX       2
11626 #define MCP_PORT_MAX            2
11627 #define MCP_GLOB_PORT_MAX       4
11628 #define MCP_GLOB_FUNC_MAX       16
11629
11630 typedef u32 offsize_t;          /* In DWORDS !!! */
11631 /* Offset from the beginning of the MCP scratchpad */
11632 #define OFFSIZE_OFFSET_SHIFT    0
11633 #define OFFSIZE_OFFSET_MASK     0x0000ffff
11634 /* Size of specific element (not the whole array if any) */
11635 #define OFFSIZE_SIZE_SHIFT      16
11636 #define OFFSIZE_SIZE_MASK       0xffff0000
11637
11638 #define SECTION_OFFSET(_offsize) ((((_offsize &                 \
11639                                      OFFSIZE_OFFSET_MASK) >>    \
11640                                     OFFSIZE_OFFSET_SHIFT) << 2))
11641
11642 #define QED_SECTION_SIZE(_offsize) (((_offsize &                \
11643                                       OFFSIZE_SIZE_MASK) >>     \
11644                                      OFFSIZE_SIZE_SHIFT) << 2)
11645
11646 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH +                  \
11647                                      SECTION_OFFSET(_offsize) +         \
11648                                      (QED_SECTION_SIZE(_offsize) * idx))
11649
11650 #define SECTION_OFFSIZE_ADDR(_pub_base, _section)       \
11651         (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
11652
11653 /* PHY configuration */
11654 struct eth_phy_cfg {
11655         u32 speed;
11656 #define ETH_SPEED_AUTONEG       0
11657 #define ETH_SPEED_SMARTLINQ     0x8
11658
11659         u32 pause;
11660 #define ETH_PAUSE_NONE          0x0
11661 #define ETH_PAUSE_AUTONEG       0x1
11662 #define ETH_PAUSE_RX            0x2
11663 #define ETH_PAUSE_TX            0x4
11664
11665         u32 adv_speed;
11666         u32 loopback_mode;
11667 #define ETH_LOOPBACK_NONE               (0)
11668 #define ETH_LOOPBACK_INT_PHY            (1)
11669 #define ETH_LOOPBACK_EXT_PHY            (2)
11670 #define ETH_LOOPBACK_EXT                (3)
11671 #define ETH_LOOPBACK_MAC                (4)
11672
11673         u32 eee_cfg;
11674 #define EEE_CFG_EEE_ENABLED                     BIT(0)
11675 #define EEE_CFG_TX_LPI                          BIT(1)
11676 #define EEE_CFG_ADV_SPEED_1G                    BIT(2)
11677 #define EEE_CFG_ADV_SPEED_10G                   BIT(3)
11678 #define EEE_TX_TIMER_USEC_MASK                  (0xfffffff0)
11679 #define EEE_TX_TIMER_USEC_OFFSET                4
11680 #define EEE_TX_TIMER_USEC_BALANCED_TIME         (0xa00)
11681 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME       (0x100)
11682 #define EEE_TX_TIMER_USEC_LATENCY_TIME          (0x6000)
11683
11684         u32 feature_config_flags;
11685 #define ETH_EEE_MODE_ADV_LPI            (1 << 0)
11686 };
11687
11688 struct port_mf_cfg {
11689         u32 dynamic_cfg;
11690 #define PORT_MF_CFG_OV_TAG_MASK         0x0000ffff
11691 #define PORT_MF_CFG_OV_TAG_SHIFT        0
11692 #define PORT_MF_CFG_OV_TAG_DEFAULT      PORT_MF_CFG_OV_TAG_MASK
11693
11694         u32 reserved[1];
11695 };
11696
11697 struct eth_stats {
11698         u64 r64;
11699         u64 r127;
11700         u64 r255;
11701         u64 r511;
11702         u64 r1023;
11703         u64 r1518;
11704
11705         union {
11706                 struct {
11707                         u64 r1522;
11708                         u64 r2047;
11709                         u64 r4095;
11710                         u64 r9216;
11711                         u64 r16383;
11712                 } bb0;
11713                 struct {
11714                         u64 unused1;
11715                         u64 r1519_to_max;
11716                         u64 unused2;
11717                         u64 unused3;
11718                         u64 unused4;
11719                 } ah0;
11720         } u0;
11721
11722         u64 rfcs;
11723         u64 rxcf;
11724         u64 rxpf;
11725         u64 rxpp;
11726         u64 raln;
11727         u64 rfcr;
11728         u64 rovr;
11729         u64 rjbr;
11730         u64 rund;
11731         u64 rfrg;
11732         u64 t64;
11733         u64 t127;
11734         u64 t255;
11735         u64 t511;
11736         u64 t1023;
11737         u64 t1518;
11738
11739         union {
11740                 struct {
11741                         u64 t2047;
11742                         u64 t4095;
11743                         u64 t9216;
11744                         u64 t16383;
11745                 } bb1;
11746                 struct {
11747                         u64 t1519_to_max;
11748                         u64 unused6;
11749                         u64 unused7;
11750                         u64 unused8;
11751                 } ah1;
11752         } u1;
11753
11754         u64 txpf;
11755         u64 txpp;
11756
11757         union {
11758                 struct {
11759                         u64 tlpiec;
11760                         u64 tncl;
11761                 } bb2;
11762                 struct {
11763                         u64 unused9;
11764                         u64 unused10;
11765                 } ah2;
11766         } u2;
11767
11768         u64 rbyte;
11769         u64 rxuca;
11770         u64 rxmca;
11771         u64 rxbca;
11772         u64 rxpok;
11773         u64 tbyte;
11774         u64 txuca;
11775         u64 txmca;
11776         u64 txbca;
11777         u64 txcf;
11778 };
11779
11780 struct brb_stats {
11781         u64 brb_truncate[8];
11782         u64 brb_discard[8];
11783 };
11784
11785 struct port_stats {
11786         struct brb_stats brb;
11787         struct eth_stats eth;
11788 };
11789
11790 struct couple_mode_teaming {
11791         u8 port_cmt[MCP_GLOB_PORT_MAX];
11792 #define PORT_CMT_IN_TEAM        (1 << 0)
11793
11794 #define PORT_CMT_PORT_ROLE      (1 << 1)
11795 #define PORT_CMT_PORT_INACTIVE  (0 << 1)
11796 #define PORT_CMT_PORT_ACTIVE    (1 << 1)
11797
11798 #define PORT_CMT_TEAM_MASK      (1 << 2)
11799 #define PORT_CMT_TEAM0          (0 << 2)
11800 #define PORT_CMT_TEAM1          (1 << 2)
11801 };
11802
11803 #define LLDP_CHASSIS_ID_STAT_LEN        4
11804 #define LLDP_PORT_ID_STAT_LEN           4
11805 #define DCBX_MAX_APP_PROTOCOL           32
11806 #define MAX_SYSTEM_LLDP_TLV_DATA        32
11807
11808 enum _lldp_agent {
11809         LLDP_NEAREST_BRIDGE = 0,
11810         LLDP_NEAREST_NON_TPMR_BRIDGE,
11811         LLDP_NEAREST_CUSTOMER_BRIDGE,
11812         LLDP_MAX_LLDP_AGENTS
11813 };
11814
11815 struct lldp_config_params_s {
11816         u32 config;
11817 #define LLDP_CONFIG_TX_INTERVAL_MASK    0x000000ff
11818 #define LLDP_CONFIG_TX_INTERVAL_SHIFT   0
11819 #define LLDP_CONFIG_HOLD_MASK           0x00000f00
11820 #define LLDP_CONFIG_HOLD_SHIFT          8
11821 #define LLDP_CONFIG_MAX_CREDIT_MASK     0x0000f000
11822 #define LLDP_CONFIG_MAX_CREDIT_SHIFT    12
11823 #define LLDP_CONFIG_ENABLE_RX_MASK      0x40000000
11824 #define LLDP_CONFIG_ENABLE_RX_SHIFT     30
11825 #define LLDP_CONFIG_ENABLE_TX_MASK      0x80000000
11826 #define LLDP_CONFIG_ENABLE_TX_SHIFT     31
11827         u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11828         u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
11829 };
11830
11831 struct lldp_status_params_s {
11832         u32 prefix_seq_num;
11833         u32 status;
11834         u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11835         u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
11836         u32 suffix_seq_num;
11837 };
11838
11839 struct dcbx_ets_feature {
11840         u32 flags;
11841 #define DCBX_ETS_ENABLED_MASK   0x00000001
11842 #define DCBX_ETS_ENABLED_SHIFT  0
11843 #define DCBX_ETS_WILLING_MASK   0x00000002
11844 #define DCBX_ETS_WILLING_SHIFT  1
11845 #define DCBX_ETS_ERROR_MASK     0x00000004
11846 #define DCBX_ETS_ERROR_SHIFT    2
11847 #define DCBX_ETS_CBS_MASK       0x00000008
11848 #define DCBX_ETS_CBS_SHIFT      3
11849 #define DCBX_ETS_MAX_TCS_MASK   0x000000f0
11850 #define DCBX_ETS_MAX_TCS_SHIFT  4
11851 #define DCBX_OOO_TC_MASK        0x00000f00
11852 #define DCBX_OOO_TC_SHIFT       8
11853         u32 pri_tc_tbl[1];
11854 #define DCBX_TCP_OOO_TC         (4)
11855
11856 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1)
11857 #define DCBX_CEE_STRICT_PRIORITY        0xf
11858         u32 tc_bw_tbl[2];
11859         u32 tc_tsa_tbl[2];
11860 #define DCBX_ETS_TSA_STRICT     0
11861 #define DCBX_ETS_TSA_CBS        1
11862 #define DCBX_ETS_TSA_ETS        2
11863 };
11864
11865 #define DCBX_TCP_OOO_TC                 (4)
11866 #define DCBX_TCP_OOO_K2_4PORT_TC        (3)
11867
11868 struct dcbx_app_priority_entry {
11869         u32 entry;
11870 #define DCBX_APP_PRI_MAP_MASK           0x000000ff
11871 #define DCBX_APP_PRI_MAP_SHIFT          0
11872 #define DCBX_APP_PRI_0                  0x01
11873 #define DCBX_APP_PRI_1                  0x02
11874 #define DCBX_APP_PRI_2                  0x04
11875 #define DCBX_APP_PRI_3                  0x08
11876 #define DCBX_APP_PRI_4                  0x10
11877 #define DCBX_APP_PRI_5                  0x20
11878 #define DCBX_APP_PRI_6                  0x40
11879 #define DCBX_APP_PRI_7                  0x80
11880 #define DCBX_APP_SF_MASK                0x00000300
11881 #define DCBX_APP_SF_SHIFT               8
11882 #define DCBX_APP_SF_ETHTYPE             0
11883 #define DCBX_APP_SF_PORT                1
11884 #define DCBX_APP_SF_IEEE_MASK           0x0000f000
11885 #define DCBX_APP_SF_IEEE_SHIFT          12
11886 #define DCBX_APP_SF_IEEE_RESERVED       0
11887 #define DCBX_APP_SF_IEEE_ETHTYPE        1
11888 #define DCBX_APP_SF_IEEE_TCP_PORT       2
11889 #define DCBX_APP_SF_IEEE_UDP_PORT       3
11890 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT   4
11891
11892 #define DCBX_APP_PROTOCOL_ID_MASK       0xffff0000
11893 #define DCBX_APP_PROTOCOL_ID_SHIFT      16
11894 };
11895
11896 struct dcbx_app_priority_feature {
11897         u32 flags;
11898 #define DCBX_APP_ENABLED_MASK           0x00000001
11899 #define DCBX_APP_ENABLED_SHIFT          0
11900 #define DCBX_APP_WILLING_MASK           0x00000002
11901 #define DCBX_APP_WILLING_SHIFT          1
11902 #define DCBX_APP_ERROR_MASK             0x00000004
11903 #define DCBX_APP_ERROR_SHIFT            2
11904 #define DCBX_APP_MAX_TCS_MASK           0x0000f000
11905 #define DCBX_APP_MAX_TCS_SHIFT          12
11906 #define DCBX_APP_NUM_ENTRIES_MASK       0x00ff0000
11907 #define DCBX_APP_NUM_ENTRIES_SHIFT      16
11908         struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
11909 };
11910
11911 struct dcbx_features {
11912         struct dcbx_ets_feature ets;
11913         u32 pfc;
11914 #define DCBX_PFC_PRI_EN_BITMAP_MASK     0x000000ff
11915 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT    0
11916 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0    0x01
11917 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1    0x02
11918 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2    0x04
11919 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3    0x08
11920 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4    0x10
11921 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5    0x20
11922 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6    0x40
11923 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7    0x80
11924
11925 #define DCBX_PFC_FLAGS_MASK             0x0000ff00
11926 #define DCBX_PFC_FLAGS_SHIFT            8
11927 #define DCBX_PFC_CAPS_MASK              0x00000f00
11928 #define DCBX_PFC_CAPS_SHIFT             8
11929 #define DCBX_PFC_MBC_MASK               0x00004000
11930 #define DCBX_PFC_MBC_SHIFT              14
11931 #define DCBX_PFC_WILLING_MASK           0x00008000
11932 #define DCBX_PFC_WILLING_SHIFT          15
11933 #define DCBX_PFC_ENABLED_MASK           0x00010000
11934 #define DCBX_PFC_ENABLED_SHIFT          16
11935 #define DCBX_PFC_ERROR_MASK             0x00020000
11936 #define DCBX_PFC_ERROR_SHIFT            17
11937
11938         struct dcbx_app_priority_feature app;
11939 };
11940
11941 struct dcbx_local_params {
11942         u32 config;
11943 #define DCBX_CONFIG_VERSION_MASK        0x00000007
11944 #define DCBX_CONFIG_VERSION_SHIFT       0
11945 #define DCBX_CONFIG_VERSION_DISABLED    0
11946 #define DCBX_CONFIG_VERSION_IEEE        1
11947 #define DCBX_CONFIG_VERSION_CEE         2
11948 #define DCBX_CONFIG_VERSION_STATIC      4
11949
11950         u32 flags;
11951         struct dcbx_features features;
11952 };
11953
11954 struct dcbx_mib {
11955         u32 prefix_seq_num;
11956         u32 flags;
11957         struct dcbx_features features;
11958         u32 suffix_seq_num;
11959 };
11960
11961 struct lldp_system_tlvs_buffer_s {
11962         u16 valid;
11963         u16 length;
11964         u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
11965 };
11966
11967 struct dcb_dscp_map {
11968         u32 flags;
11969 #define DCB_DSCP_ENABLE_MASK    0x1
11970 #define DCB_DSCP_ENABLE_SHIFT   0
11971 #define DCB_DSCP_ENABLE 1
11972         u32 dscp_pri_map[8];
11973 };
11974
11975 struct public_global {
11976         u32 max_path;
11977         u32 max_ports;
11978 #define MODE_1P 1
11979 #define MODE_2P 2
11980 #define MODE_3P 3
11981 #define MODE_4P 4
11982         u32 debug_mb_offset;
11983         u32 phymod_dbg_mb_offset;
11984         struct couple_mode_teaming cmt;
11985         s32 internal_temperature;
11986         u32 mfw_ver;
11987         u32 running_bundle_id;
11988         s32 external_temperature;
11989         u32 mdump_reason;
11990         u64 reserved;
11991         u32 data_ptr;
11992         u32 data_size;
11993 };
11994
11995 struct fw_flr_mb {
11996         u32 aggint;
11997         u32 opgen_addr;
11998         u32 accum_ack;
11999 };
12000
12001 struct public_path {
12002         struct fw_flr_mb flr_mb;
12003         u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
12004
12005         u32 process_kill;
12006 #define PROCESS_KILL_COUNTER_MASK       0x0000ffff
12007 #define PROCESS_KILL_COUNTER_SHIFT      0
12008 #define PROCESS_KILL_GLOB_AEU_BIT_MASK  0xffff0000
12009 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
12010 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
12011 };
12012
12013 struct public_port {
12014         u32 validity_map;
12015
12016         u32 link_status;
12017 #define LINK_STATUS_LINK_UP                     0x00000001
12018 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK       0x0000001e
12019 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD    (1 << 1)
12020 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD    (2 << 1)
12021 #define LINK_STATUS_SPEED_AND_DUPLEX_10G        (3 << 1)
12022 #define LINK_STATUS_SPEED_AND_DUPLEX_20G        (4 << 1)
12023 #define LINK_STATUS_SPEED_AND_DUPLEX_40G        (5 << 1)
12024 #define LINK_STATUS_SPEED_AND_DUPLEX_50G        (6 << 1)
12025 #define LINK_STATUS_SPEED_AND_DUPLEX_100G       (7 << 1)
12026 #define LINK_STATUS_SPEED_AND_DUPLEX_25G        (8 << 1)
12027
12028 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED      0x00000020
12029
12030 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE     0x00000040
12031 #define LINK_STATUS_PARALLEL_DETECTION_USED     0x00000080
12032
12033 #define LINK_STATUS_PFC_ENABLED                         0x00000100
12034 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
12035 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
12036 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE            0x00000800
12037 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE            0x00001000
12038 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE            0x00002000
12039 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE            0x00004000
12040 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE           0x00008000
12041 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE            0x00010000
12042
12043 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
12044 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0 << 18)
12045 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1 << 18)
12046 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2 << 18)
12047 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3 << 18)
12048
12049 #define LINK_STATUS_SFP_TX_FAULT                        0x00100000
12050 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00200000
12051 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00400000
12052 #define LINK_STATUS_RX_SIGNAL_PRESENT                   0x00800000
12053 #define LINK_STATUS_MAC_LOCAL_FAULT                     0x01000000
12054 #define LINK_STATUS_MAC_REMOTE_FAULT                    0x02000000
12055 #define LINK_STATUS_UNSUPPORTED_SPD_REQ                 0x04000000
12056
12057         u32 link_status1;
12058         u32 ext_phy_fw_version;
12059         u32 drv_phy_cfg_addr;
12060
12061         u32 port_stx;
12062
12063         u32 stat_nig_timer;
12064
12065         struct port_mf_cfg port_mf_config;
12066         struct port_stats stats;
12067
12068         u32 media_type;
12069 #define MEDIA_UNSPECIFIED       0x0
12070 #define MEDIA_SFPP_10G_FIBER    0x1
12071 #define MEDIA_XFP_FIBER         0x2
12072 #define MEDIA_DA_TWINAX         0x3
12073 #define MEDIA_BASE_T            0x4
12074 #define MEDIA_SFP_1G_FIBER      0x5
12075 #define MEDIA_MODULE_FIBER      0x6
12076 #define MEDIA_KR                0xf0
12077 #define MEDIA_NOT_PRESENT       0xff
12078
12079         u32 lfa_status;
12080         u32 link_change_count;
12081
12082         struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
12083         struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
12084         struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
12085
12086         /* DCBX related MIB */
12087         struct dcbx_local_params local_admin_dcbx_mib;
12088         struct dcbx_mib remote_dcbx_mib;
12089         struct dcbx_mib operational_dcbx_mib;
12090
12091         u32 reserved[2];
12092         u32 transceiver_data;
12093 #define ETH_TRANSCEIVER_STATE_MASK      0x000000FF
12094 #define ETH_TRANSCEIVER_STATE_SHIFT     0x00000000
12095 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
12096 #define ETH_TRANSCEIVER_STATE_PRESENT   0x00000001
12097 #define ETH_TRANSCEIVER_STATE_VALID     0x00000003
12098 #define ETH_TRANSCEIVER_STATE_UPDATING  0x00000008
12099
12100         u32 wol_info;
12101         u32 wol_pkt_len;
12102         u32 wol_pkt_details;
12103         struct dcb_dscp_map dcb_dscp_map;
12104
12105         u32 eee_status;
12106 #define EEE_ACTIVE_BIT                  BIT(0)
12107 #define EEE_LD_ADV_STATUS_MASK          0x000000f0
12108 #define EEE_LD_ADV_STATUS_OFFSET        4
12109 #define EEE_1G_ADV                      BIT(1)
12110 #define EEE_10G_ADV                     BIT(2)
12111 #define EEE_LP_ADV_STATUS_MASK          0x00000f00
12112 #define EEE_LP_ADV_STATUS_OFFSET        8
12113 #define EEE_SUPPORTED_SPEED_MASK        0x0000f000
12114 #define EEE_SUPPORTED_SPEED_OFFSET      12
12115 #define EEE_1G_SUPPORTED                BIT(1)
12116 #define EEE_10G_SUPPORTED               BIT(2)
12117
12118         u32 eee_remote;
12119 #define EEE_REMOTE_TW_TX_MASK   0x0000ffff
12120 #define EEE_REMOTE_TW_TX_OFFSET 0
12121 #define EEE_REMOTE_TW_RX_MASK   0xffff0000
12122 #define EEE_REMOTE_TW_RX_OFFSET 16
12123
12124         u32 reserved1;
12125         u32 oem_cfg_port;
12126 #define OEM_CFG_CHANNEL_TYPE_MASK                       0x00000003
12127 #define OEM_CFG_CHANNEL_TYPE_OFFSET                     0
12128 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION             0x1
12129 #define OEM_CFG_CHANNEL_TYPE_STAGGED                    0x2
12130 #define OEM_CFG_SCHED_TYPE_MASK                         0x0000000C
12131 #define OEM_CFG_SCHED_TYPE_OFFSET                       2
12132 #define OEM_CFG_SCHED_TYPE_ETS                          0x1
12133 #define OEM_CFG_SCHED_TYPE_VNIC_BW                      0x2
12134 };
12135
12136 struct public_func {
12137         u32 reserved0[2];
12138
12139         u32 mtu_size;
12140
12141         u32 reserved[7];
12142
12143         u32 config;
12144 #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
12145 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING          0x00000002
12146 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT    0x00000001
12147
12148 #define FUNC_MF_CFG_PROTOCOL_MASK       0x000000f0
12149 #define FUNC_MF_CFG_PROTOCOL_SHIFT      4
12150 #define FUNC_MF_CFG_PROTOCOL_ETHERNET   0x00000000
12151 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
12152 #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000020
12153 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
12154 #define FUNC_MF_CFG_PROTOCOL_MAX        0x00000030
12155
12156 #define FUNC_MF_CFG_MIN_BW_MASK         0x0000ff00
12157 #define FUNC_MF_CFG_MIN_BW_SHIFT        8
12158 #define FUNC_MF_CFG_MIN_BW_DEFAULT      0x00000000
12159 #define FUNC_MF_CFG_MAX_BW_MASK         0x00ff0000
12160 #define FUNC_MF_CFG_MAX_BW_SHIFT        16
12161 #define FUNC_MF_CFG_MAX_BW_DEFAULT      0x00640000
12162
12163         u32 status;
12164 #define FUNC_STATUS_VLINK_DOWN          0x00000001
12165
12166         u32 mac_upper;
12167 #define FUNC_MF_CFG_UPPERMAC_MASK       0x0000ffff
12168 #define FUNC_MF_CFG_UPPERMAC_SHIFT      0
12169 #define FUNC_MF_CFG_UPPERMAC_DEFAULT    FUNC_MF_CFG_UPPERMAC_MASK
12170         u32 mac_lower;
12171 #define FUNC_MF_CFG_LOWERMAC_DEFAULT    0xffffffff
12172
12173         u32 fcoe_wwn_port_name_upper;
12174         u32 fcoe_wwn_port_name_lower;
12175
12176         u32 fcoe_wwn_node_name_upper;
12177         u32 fcoe_wwn_node_name_lower;
12178
12179         u32 ovlan_stag;
12180 #define FUNC_MF_CFG_OV_STAG_MASK        0x0000ffff
12181 #define FUNC_MF_CFG_OV_STAG_SHIFT       0
12182 #define FUNC_MF_CFG_OV_STAG_DEFAULT     FUNC_MF_CFG_OV_STAG_MASK
12183
12184         u32 pf_allocation;
12185
12186         u32 preserve_data;
12187
12188         u32 driver_last_activity_ts;
12189
12190         u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
12191
12192         u32 drv_id;
12193 #define DRV_ID_PDA_COMP_VER_MASK        0x0000ffff
12194 #define DRV_ID_PDA_COMP_VER_SHIFT       0
12195
12196 #define LOAD_REQ_HSI_VERSION            2
12197 #define DRV_ID_MCP_HSI_VER_MASK         0x00ff0000
12198 #define DRV_ID_MCP_HSI_VER_SHIFT        16
12199 #define DRV_ID_MCP_HSI_VER_CURRENT      (LOAD_REQ_HSI_VERSION << \
12200                                          DRV_ID_MCP_HSI_VER_SHIFT)
12201
12202 #define DRV_ID_DRV_TYPE_MASK            0x7f000000
12203 #define DRV_ID_DRV_TYPE_SHIFT           24
12204 #define DRV_ID_DRV_TYPE_UNKNOWN         (0 << DRV_ID_DRV_TYPE_SHIFT)
12205 #define DRV_ID_DRV_TYPE_LINUX           (1 << DRV_ID_DRV_TYPE_SHIFT)
12206
12207 #define DRV_ID_DRV_INIT_HW_MASK         0x80000000
12208 #define DRV_ID_DRV_INIT_HW_SHIFT        31
12209 #define DRV_ID_DRV_INIT_HW_FLAG         (1 << DRV_ID_DRV_INIT_HW_SHIFT)
12210
12211         u32 oem_cfg_func;
12212 #define OEM_CFG_FUNC_TC_MASK                    0x0000000F
12213 #define OEM_CFG_FUNC_TC_OFFSET                  0
12214 #define OEM_CFG_FUNC_TC_0                       0x0
12215 #define OEM_CFG_FUNC_TC_1                       0x1
12216 #define OEM_CFG_FUNC_TC_2                       0x2
12217 #define OEM_CFG_FUNC_TC_3                       0x3
12218 #define OEM_CFG_FUNC_TC_4                       0x4
12219 #define OEM_CFG_FUNC_TC_5                       0x5
12220 #define OEM_CFG_FUNC_TC_6                       0x6
12221 #define OEM_CFG_FUNC_TC_7                       0x7
12222
12223 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK         0x00000030
12224 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET       4
12225 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC         0x1
12226 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS           0x2
12227 };
12228
12229 struct mcp_mac {
12230         u32 mac_upper;
12231         u32 mac_lower;
12232 };
12233
12234 struct mcp_val64 {
12235         u32 lo;
12236         u32 hi;
12237 };
12238
12239 struct mcp_file_att {
12240         u32 nvm_start_addr;
12241         u32 len;
12242 };
12243
12244 struct bist_nvm_image_att {
12245         u32 return_code;
12246         u32 image_type;
12247         u32 nvm_start_addr;
12248         u32 len;
12249 };
12250
12251 #define MCP_DRV_VER_STR_SIZE 16
12252 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
12253 #define MCP_DRV_NVM_BUF_LEN 32
12254 struct drv_version_stc {
12255         u32 version;
12256         u8 name[MCP_DRV_VER_STR_SIZE - 4];
12257 };
12258
12259 struct lan_stats_stc {
12260         u64 ucast_rx_pkts;
12261         u64 ucast_tx_pkts;
12262         u32 fcs_err;
12263         u32 rserved;
12264 };
12265
12266 struct fcoe_stats_stc {
12267         u64 rx_pkts;
12268         u64 tx_pkts;
12269         u32 fcs_err;
12270         u32 login_failure;
12271 };
12272
12273 struct ocbb_data_stc {
12274         u32 ocbb_host_addr;
12275         u32 ocsd_host_addr;
12276         u32 ocsd_req_update_interval;
12277 };
12278
12279 #define MAX_NUM_OF_SENSORS 7
12280 struct temperature_status_stc {
12281         u32 num_of_sensors;
12282         u32 sensor[MAX_NUM_OF_SENSORS];
12283 };
12284
12285 /* crash dump configuration header */
12286 struct mdump_config_stc {
12287         u32 version;
12288         u32 config;
12289         u32 epoc;
12290         u32 num_of_logs;
12291         u32 valid_logs;
12292 };
12293
12294 enum resource_id_enum {
12295         RESOURCE_NUM_SB_E = 0,
12296         RESOURCE_NUM_L2_QUEUE_E = 1,
12297         RESOURCE_NUM_VPORT_E = 2,
12298         RESOURCE_NUM_VMQ_E = 3,
12299         RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
12300         RESOURCE_FACTOR_RSS_PER_VF_E = 5,
12301         RESOURCE_NUM_RL_E = 6,
12302         RESOURCE_NUM_PQ_E = 7,
12303         RESOURCE_NUM_VF_E = 8,
12304         RESOURCE_VFC_FILTER_E = 9,
12305         RESOURCE_ILT_E = 10,
12306         RESOURCE_CQS_E = 11,
12307         RESOURCE_GFT_PROFILES_E = 12,
12308         RESOURCE_NUM_TC_E = 13,
12309         RESOURCE_NUM_RSS_ENGINES_E = 14,
12310         RESOURCE_LL2_QUEUE_E = 15,
12311         RESOURCE_RDMA_STATS_QUEUE_E = 16,
12312         RESOURCE_BDQ_E = 17,
12313         RESOURCE_MAX_NUM,
12314         RESOURCE_NUM_INVALID = 0xFFFFFFFF
12315 };
12316
12317 /* Resource ID is to be filled by the driver in the MB request
12318  * Size, offset & flags to be filled by the MFW in the MB response
12319  */
12320 struct resource_info {
12321         enum resource_id_enum res_id;
12322         u32 size;               /* number of allocated resources */
12323         u32 offset;             /* Offset of the 1st resource */
12324         u32 vf_size;
12325         u32 vf_offset;
12326         u32 flags;
12327 #define RESOURCE_ELEMENT_STRICT (1 << 0)
12328 };
12329
12330 #define DRV_ROLE_NONE           0
12331 #define DRV_ROLE_PREBOOT        1
12332 #define DRV_ROLE_OS             2
12333 #define DRV_ROLE_KDUMP          3
12334
12335 struct load_req_stc {
12336         u32 drv_ver_0;
12337         u32 drv_ver_1;
12338         u32 fw_ver;
12339         u32 misc0;
12340 #define LOAD_REQ_ROLE_MASK              0x000000FF
12341 #define LOAD_REQ_ROLE_SHIFT             0
12342 #define LOAD_REQ_LOCK_TO_MASK           0x0000FF00
12343 #define LOAD_REQ_LOCK_TO_SHIFT          8
12344 #define LOAD_REQ_LOCK_TO_DEFAULT        0
12345 #define LOAD_REQ_LOCK_TO_NONE           255
12346 #define LOAD_REQ_FORCE_MASK             0x000F0000
12347 #define LOAD_REQ_FORCE_SHIFT            16
12348 #define LOAD_REQ_FORCE_NONE             0
12349 #define LOAD_REQ_FORCE_PF               1
12350 #define LOAD_REQ_FORCE_ALL              2
12351 #define LOAD_REQ_FLAGS0_MASK            0x00F00000
12352 #define LOAD_REQ_FLAGS0_SHIFT           20
12353 #define LOAD_REQ_FLAGS0_AVOID_RESET     (0x1 << 0)
12354 };
12355
12356 struct load_rsp_stc {
12357         u32 drv_ver_0;
12358         u32 drv_ver_1;
12359         u32 fw_ver;
12360         u32 misc0;
12361 #define LOAD_RSP_ROLE_MASK              0x000000FF
12362 #define LOAD_RSP_ROLE_SHIFT             0
12363 #define LOAD_RSP_HSI_MASK               0x0000FF00
12364 #define LOAD_RSP_HSI_SHIFT              8
12365 #define LOAD_RSP_FLAGS0_MASK            0x000F0000
12366 #define LOAD_RSP_FLAGS0_SHIFT           16
12367 #define LOAD_RSP_FLAGS0_DRV_EXISTS      (0x1 << 0)
12368 };
12369
12370 union drv_union_data {
12371         u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
12372         struct mcp_mac wol_mac;
12373
12374         struct eth_phy_cfg drv_phy_cfg;
12375
12376         struct mcp_val64 val64;
12377
12378         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
12379
12380         struct mcp_file_att file_att;
12381
12382         u32 ack_vf_disabled[VF_MAX_STATIC / 32];
12383
12384         struct drv_version_stc drv_version;
12385
12386         struct lan_stats_stc lan_stats;
12387         struct fcoe_stats_stc fcoe_stats;
12388         struct ocbb_data_stc ocbb_info;
12389         struct temperature_status_stc temp_info;
12390         struct resource_info resource;
12391         struct bist_nvm_image_att nvm_image_att;
12392         struct mdump_config_stc mdump_config;
12393 };
12394
12395 struct public_drv_mb {
12396         u32 drv_mb_header;
12397 #define DRV_MSG_CODE_MASK                       0xffff0000
12398 #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
12399 #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
12400 #define DRV_MSG_CODE_INIT_HW                    0x12000000
12401 #define DRV_MSG_CODE_CANCEL_LOAD_REQ            0x13000000
12402 #define DRV_MSG_CODE_UNLOAD_REQ                 0x20000000
12403 #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
12404 #define DRV_MSG_CODE_INIT_PHY                   0x22000000
12405 #define DRV_MSG_CODE_LINK_RESET                 0x23000000
12406 #define DRV_MSG_CODE_SET_DCBX                   0x25000000
12407 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG         0x26000000
12408 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM          0x27000000
12409 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS    0x28000000
12410 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER     0x29000000
12411 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE     0x31000000
12412 #define DRV_MSG_CODE_BW_UPDATE_ACK              0x32000000
12413 #define DRV_MSG_CODE_OV_UPDATE_MTU              0x33000000
12414 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG          0x34000000
12415 #define DRV_MSG_SET_RESOURCE_VALUE_MSG          0x35000000
12416 #define DRV_MSG_CODE_OV_UPDATE_WOL              0x38000000
12417 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE     0x39000000
12418 #define DRV_MSG_CODE_GET_OEM_UPDATES            0x41000000
12419
12420 #define DRV_MSG_CODE_BW_UPDATE_ACK              0x32000000
12421 #define DRV_MSG_CODE_NIG_DRAIN                  0x30000000
12422 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK           0x3b000000
12423 #define DRV_MSG_CODE_INITIATE_PF_FLR            0x02010000
12424 #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
12425 #define DRV_MSG_CODE_CFG_VF_MSIX                0xc0010000
12426 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX            0xc0020000
12427 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN         0x00010000
12428 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA          0x00020000
12429 #define DRV_MSG_CODE_NVM_GET_FILE_ATT           0x00030000
12430 #define DRV_MSG_CODE_NVM_READ_NVRAM             0x00050000
12431 #define DRV_MSG_CODE_NVM_WRITE_NVRAM            0x00060000
12432 #define DRV_MSG_CODE_MCP_RESET                  0x00090000
12433 #define DRV_MSG_CODE_SET_VERSION                0x000f0000
12434 #define DRV_MSG_CODE_MCP_HALT                   0x00100000
12435 #define DRV_MSG_CODE_SET_VMAC                   0x00110000
12436 #define DRV_MSG_CODE_GET_VMAC                   0x00120000
12437 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT            4
12438 #define DRV_MSG_CODE_VMAC_TYPE_MASK             0x30
12439 #define DRV_MSG_CODE_VMAC_TYPE_MAC              1
12440 #define DRV_MSG_CODE_VMAC_TYPE_WWNN             2
12441 #define DRV_MSG_CODE_VMAC_TYPE_WWPN             3
12442
12443 #define DRV_MSG_CODE_GET_STATS                  0x00130000
12444 #define DRV_MSG_CODE_STATS_TYPE_LAN             1
12445 #define DRV_MSG_CODE_STATS_TYPE_FCOE            2
12446 #define DRV_MSG_CODE_STATS_TYPE_ISCSI           3
12447 #define DRV_MSG_CODE_STATS_TYPE_RDMA            4
12448
12449 #define DRV_MSG_CODE_TRANSCEIVER_READ           0x00160000
12450
12451 #define DRV_MSG_CODE_MASK_PARITIES              0x001a0000
12452
12453 #define DRV_MSG_CODE_BIST_TEST                  0x001e0000
12454 #define DRV_MSG_CODE_SET_LED_MODE               0x00200000
12455 #define DRV_MSG_CODE_RESOURCE_CMD       0x00230000
12456 #define DRV_MSG_CODE_GET_TLV_DONE               0x002f0000
12457
12458 #define RESOURCE_CMD_REQ_RESC_MASK              0x0000001F
12459 #define RESOURCE_CMD_REQ_RESC_SHIFT             0
12460 #define RESOURCE_CMD_REQ_OPCODE_MASK            0x000000E0
12461 #define RESOURCE_CMD_REQ_OPCODE_SHIFT           5
12462 #define RESOURCE_OPCODE_REQ                     1
12463 #define RESOURCE_OPCODE_REQ_WO_AGING            2
12464 #define RESOURCE_OPCODE_REQ_W_AGING             3
12465 #define RESOURCE_OPCODE_RELEASE                 4
12466 #define RESOURCE_OPCODE_FORCE_RELEASE           5
12467 #define RESOURCE_CMD_REQ_AGE_MASK               0x0000FF00
12468 #define RESOURCE_CMD_REQ_AGE_SHIFT              8
12469
12470 #define RESOURCE_CMD_RSP_OWNER_MASK             0x000000FF
12471 #define RESOURCE_CMD_RSP_OWNER_SHIFT            0
12472 #define RESOURCE_CMD_RSP_OPCODE_MASK            0x00000700
12473 #define RESOURCE_CMD_RSP_OPCODE_SHIFT           8
12474 #define RESOURCE_OPCODE_GNT                     1
12475 #define RESOURCE_OPCODE_BUSY                    2
12476 #define RESOURCE_OPCODE_RELEASED                3
12477 #define RESOURCE_OPCODE_RELEASED_PREVIOUS       4
12478 #define RESOURCE_OPCODE_WRONG_OWNER             5
12479 #define RESOURCE_OPCODE_UNKNOWN_CMD             255
12480
12481 #define RESOURCE_DUMP                           0
12482
12483 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL       0x002b0000
12484 #define DRV_MSG_CODE_OS_WOL                     0x002e0000
12485
12486 #define DRV_MSG_CODE_FEATURE_SUPPORT            0x00300000
12487 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT    0x00310000
12488 #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
12489
12490         u32 drv_mb_param;
12491 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN         0x00000000
12492 #define DRV_MB_PARAM_UNLOAD_WOL_MCP             0x00000001
12493 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED        0x00000002
12494 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED         0x00000003
12495 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK           0x000000FF
12496 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT          3
12497
12498 #define DRV_MB_PARAM_NVM_LEN_OFFSET             24
12499
12500 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT    0
12501 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK     0x000000FF
12502 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT   8
12503 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK    0x0000FF00
12504 #define DRV_MB_PARAM_LLDP_SEND_MASK             0x00000001
12505 #define DRV_MB_PARAM_LLDP_SEND_SHIFT            0
12506
12507 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT          0
12508 #define DRV_MB_PARAM_OV_CURR_CFG_MASK           0x0000000F
12509 #define DRV_MB_PARAM_OV_CURR_CFG_NONE           0
12510 #define DRV_MB_PARAM_OV_CURR_CFG_OS             1
12511 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC    2
12512 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER          3
12513
12514 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT      0
12515 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK       0xFFFFFFFF
12516 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
12517 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
12518 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
12519 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK  0x000000FF
12520
12521 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT       0
12522 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK        0xF
12523 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN     0x1
12524 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED  0x2
12525 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING     0x3
12526 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED    0x4
12527 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE      0x5
12528
12529 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT  0
12530 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK   0xFFFFFFFF
12531
12532 #define DRV_MB_PARAM_WOL_MASK   (DRV_MB_PARAM_WOL_DEFAULT | \
12533                                  DRV_MB_PARAM_WOL_DISABLED | \
12534                                  DRV_MB_PARAM_WOL_ENABLED)
12535 #define DRV_MB_PARAM_WOL_DEFAULT        DRV_MB_PARAM_UNLOAD_WOL_MCP
12536 #define DRV_MB_PARAM_WOL_DISABLED       DRV_MB_PARAM_UNLOAD_WOL_DISABLED
12537 #define DRV_MB_PARAM_WOL_ENABLED        DRV_MB_PARAM_UNLOAD_WOL_ENABLED
12538
12539 #define DRV_MB_PARAM_ESWITCH_MODE_MASK  (DRV_MB_PARAM_ESWITCH_MODE_NONE | \
12540                                          DRV_MB_PARAM_ESWITCH_MODE_VEB | \
12541                                          DRV_MB_PARAM_ESWITCH_MODE_VEPA)
12542 #define DRV_MB_PARAM_ESWITCH_MODE_NONE  0x0
12543 #define DRV_MB_PARAM_ESWITCH_MODE_VEB   0x1
12544 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA  0x2
12545
12546 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK     0x1
12547 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET   0
12548
12549 #define DRV_MB_PARAM_SET_LED_MODE_OPER          0x0
12550 #define DRV_MB_PARAM_SET_LED_MODE_ON            0x1
12551 #define DRV_MB_PARAM_SET_LED_MODE_OFF           0x2
12552
12553 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET            0
12554 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK              0x00000003
12555 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET            2
12556 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK              0x000000FC
12557 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET     8
12558 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK       0x0000FF00
12559 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET          16
12560 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK            0xFFFF0000
12561
12562         /* Resource Allocation params - Driver version support */
12563 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK  0xFFFF0000
12564 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
12565 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK  0x0000FFFF
12566 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12567
12568 #define DRV_MB_PARAM_BIST_REGISTER_TEST         1
12569 #define DRV_MB_PARAM_BIST_CLOCK_TEST            2
12570 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES   3
12571 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX       4
12572
12573 #define DRV_MB_PARAM_BIST_RC_UNKNOWN            0
12574 #define DRV_MB_PARAM_BIST_RC_PASSED             1
12575 #define DRV_MB_PARAM_BIST_RC_FAILED             2
12576 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER  3
12577
12578 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT      0
12579 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK       0x000000FF
12580 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT        8
12581 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK         0x0000FF00
12582
12583 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK          0x0000FFFF
12584 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET        0
12585 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE           0x00000002
12586
12587         u32 fw_mb_header;
12588 #define FW_MSG_CODE_MASK                        0xffff0000
12589 #define FW_MSG_CODE_UNSUPPORTED                 0x00000000
12590 #define FW_MSG_CODE_DRV_LOAD_ENGINE             0x10100000
12591 #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
12592 #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
12593 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA        0x10200000
12594 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1      0x10210000
12595 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG       0x10220000
12596 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI        0x10230000
12597 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
12598 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT     0x10310000
12599 #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
12600 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE           0x20110000
12601 #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20120000
12602 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20130000
12603 #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
12604 #define FW_MSG_CODE_RESOURCE_ALLOC_OK           0x34000000
12605 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN      0x35000000
12606 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED   0x36000000
12607 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE       0x3b000000
12608 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE        0xb0010000
12609
12610 #define FW_MSG_CODE_NVM_OK                      0x00010000
12611 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK      0x00400000
12612 #define FW_MSG_CODE_PHY_OK                      0x00110000
12613 #define FW_MSG_CODE_OK                          0x00160000
12614 #define FW_MSG_CODE_ERROR                       0x00170000
12615 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK         0x00160000
12616 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR      0x00170000
12617 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT     0x00020000
12618
12619 #define FW_MSG_CODE_OS_WOL_SUPPORTED            0x00800000
12620 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED        0x00810000
12621 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE    0x00870000
12622 #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
12623
12624         u32 fw_mb_param;
12625 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK   0xFFFF0000
12626 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT  16
12627 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK   0x0000FFFF
12628 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT  0
12629
12630         /* get pf rdma protocol command responce */
12631 #define FW_MB_PARAM_GET_PF_RDMA_NONE            0x0
12632 #define FW_MB_PARAM_GET_PF_RDMA_ROCE            0x1
12633 #define FW_MB_PARAM_GET_PF_RDMA_IWARP           0x2
12634 #define FW_MB_PARAM_GET_PF_RDMA_BOTH            0x3
12635
12636 /* get MFW feature support response */
12637 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE         0x00000002
12638
12639 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR   (1 << 0)
12640
12641         u32 drv_pulse_mb;
12642 #define DRV_PULSE_SEQ_MASK                      0x00007fff
12643 #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
12644 #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
12645
12646         u32 mcp_pulse_mb;
12647 #define MCP_PULSE_SEQ_MASK                      0x00007fff
12648 #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
12649 #define MCP_EVENT_MASK                          0xffff0000
12650 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
12651
12652         union drv_union_data union_data;
12653 };
12654
12655 enum MFW_DRV_MSG_TYPE {
12656         MFW_DRV_MSG_LINK_CHANGE,
12657         MFW_DRV_MSG_FLR_FW_ACK_FAILED,
12658         MFW_DRV_MSG_VF_DISABLED,
12659         MFW_DRV_MSG_LLDP_DATA_UPDATED,
12660         MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
12661         MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
12662         MFW_DRV_MSG_RESERVED4,
12663         MFW_DRV_MSG_BW_UPDATE,
12664         MFW_DRV_MSG_S_TAG_UPDATE,
12665         MFW_DRV_MSG_GET_LAN_STATS,
12666         MFW_DRV_MSG_GET_FCOE_STATS,
12667         MFW_DRV_MSG_GET_ISCSI_STATS,
12668         MFW_DRV_MSG_GET_RDMA_STATS,
12669         MFW_DRV_MSG_BW_UPDATE10,
12670         MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
12671         MFW_DRV_MSG_BW_UPDATE11,
12672         MFW_DRV_MSG_RESERVED,
12673         MFW_DRV_MSG_GET_TLV_REQ,
12674         MFW_DRV_MSG_OEM_CFG_UPDATE,
12675         MFW_DRV_MSG_MAX
12676 };
12677
12678 #define MFW_DRV_MSG_MAX_DWORDS(msgs)    (((msgs - 1) >> 2) + 1)
12679 #define MFW_DRV_MSG_DWORD(msg_id)       (msg_id >> 2)
12680 #define MFW_DRV_MSG_OFFSET(msg_id)      ((msg_id & 0x3) << 3)
12681 #define MFW_DRV_MSG_MASK(msg_id)        (0xff << MFW_DRV_MSG_OFFSET(msg_id))
12682
12683 struct public_mfw_mb {
12684         u32 sup_msgs;
12685         u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
12686         u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
12687 };
12688
12689 enum public_sections {
12690         PUBLIC_DRV_MB,
12691         PUBLIC_MFW_MB,
12692         PUBLIC_GLOBAL,
12693         PUBLIC_PATH,
12694         PUBLIC_PORT,
12695         PUBLIC_FUNC,
12696         PUBLIC_MAX_SECTIONS
12697 };
12698
12699 struct mcp_public_data {
12700         u32 num_sections;
12701         u32 sections[PUBLIC_MAX_SECTIONS];
12702         struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
12703         struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
12704         struct public_global global;
12705         struct public_path path[MCP_GLOB_PATH_MAX];
12706         struct public_port port[MCP_GLOB_PORT_MAX];
12707         struct public_func func[MCP_GLOB_FUNC_MAX];
12708 };
12709
12710 #define MAX_I2C_TRANSACTION_SIZE        16
12711
12712 /* OCBB definitions */
12713 enum tlvs {
12714         /* Category 1: Device Properties */
12715         DRV_TLV_CLP_STR,
12716         DRV_TLV_CLP_STR_CTD,
12717         /* Category 6: Device Configuration */
12718         DRV_TLV_SCSI_TO,
12719         DRV_TLV_R_T_TOV,
12720         DRV_TLV_R_A_TOV,
12721         DRV_TLV_E_D_TOV,
12722         DRV_TLV_CR_TOV,
12723         DRV_TLV_BOOT_TYPE,
12724         /* Category 8: Port Configuration */
12725         DRV_TLV_NPIV_ENABLED,
12726         /* Category 10: Function Configuration */
12727         DRV_TLV_FEATURE_FLAGS,
12728         DRV_TLV_LOCAL_ADMIN_ADDR,
12729         DRV_TLV_ADDITIONAL_MAC_ADDR_1,
12730         DRV_TLV_ADDITIONAL_MAC_ADDR_2,
12731         DRV_TLV_LSO_MAX_OFFLOAD_SIZE,
12732         DRV_TLV_LSO_MIN_SEGMENT_COUNT,
12733         DRV_TLV_PROMISCUOUS_MODE,
12734         DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE,
12735         DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE,
12736         DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG,
12737         DRV_TLV_FLEX_NIC_OUTER_VLAN_ID,
12738         DRV_TLV_OS_DRIVER_STATES,
12739         DRV_TLV_PXE_BOOT_PROGRESS,
12740         /* Category 12: FC/FCoE Configuration */
12741         DRV_TLV_NPIV_STATE,
12742         DRV_TLV_NUM_OF_NPIV_IDS,
12743         DRV_TLV_SWITCH_NAME,
12744         DRV_TLV_SWITCH_PORT_NUM,
12745         DRV_TLV_SWITCH_PORT_ID,
12746         DRV_TLV_VENDOR_NAME,
12747         DRV_TLV_SWITCH_MODEL,
12748         DRV_TLV_SWITCH_FW_VER,
12749         DRV_TLV_QOS_PRIORITY_PER_802_1P,
12750         DRV_TLV_PORT_ALIAS,
12751         DRV_TLV_PORT_STATE,
12752         DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE,
12753         DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE,
12754         DRV_TLV_LINK_FAILURE_COUNT,
12755         DRV_TLV_FCOE_BOOT_PROGRESS,
12756         /* Category 13: iSCSI Configuration */
12757         DRV_TLV_TARGET_LLMNR_ENABLED,
12758         DRV_TLV_HEADER_DIGEST_FLAG_ENABLED,
12759         DRV_TLV_DATA_DIGEST_FLAG_ENABLED,
12760         DRV_TLV_AUTHENTICATION_METHOD,
12761         DRV_TLV_ISCSI_BOOT_TARGET_PORTAL,
12762         DRV_TLV_MAX_FRAME_SIZE,
12763         DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE,
12764         DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE,
12765         DRV_TLV_ISCSI_BOOT_PROGRESS,
12766         /* Category 20: Device Data */
12767         DRV_TLV_PCIE_BUS_RX_UTILIZATION,
12768         DRV_TLV_PCIE_BUS_TX_UTILIZATION,
12769         DRV_TLV_DEVICE_CPU_CORES_UTILIZATION,
12770         DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED,
12771         DRV_TLV_NCSI_RX_BYTES_RECEIVED,
12772         DRV_TLV_NCSI_TX_BYTES_SENT,
12773         /* Category 22: Base Port Data */
12774         DRV_TLV_RX_DISCARDS,
12775         DRV_TLV_RX_ERRORS,
12776         DRV_TLV_TX_ERRORS,
12777         DRV_TLV_TX_DISCARDS,
12778         DRV_TLV_RX_FRAMES_RECEIVED,
12779         DRV_TLV_TX_FRAMES_SENT,
12780         /* Category 23: FC/FCoE Port Data */
12781         DRV_TLV_RX_BROADCAST_PACKETS,
12782         DRV_TLV_TX_BROADCAST_PACKETS,
12783         /* Category 28: Base Function Data */
12784         DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4,
12785         DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6,
12786         DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
12787         DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
12788         DRV_TLV_PF_RX_FRAMES_RECEIVED,
12789         DRV_TLV_RX_BYTES_RECEIVED,
12790         DRV_TLV_PF_TX_FRAMES_SENT,
12791         DRV_TLV_TX_BYTES_SENT,
12792         DRV_TLV_IOV_OFFLOAD,
12793         DRV_TLV_PCI_ERRORS_CAP_ID,
12794         DRV_TLV_UNCORRECTABLE_ERROR_STATUS,
12795         DRV_TLV_UNCORRECTABLE_ERROR_MASK,
12796         DRV_TLV_CORRECTABLE_ERROR_STATUS,
12797         DRV_TLV_CORRECTABLE_ERROR_MASK,
12798         DRV_TLV_PCI_ERRORS_AECC_REGISTER,
12799         DRV_TLV_TX_QUEUES_EMPTY,
12800         DRV_TLV_RX_QUEUES_EMPTY,
12801         DRV_TLV_TX_QUEUES_FULL,
12802         DRV_TLV_RX_QUEUES_FULL,
12803         /* Category 29: FC/FCoE Function Data */
12804         DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
12805         DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
12806         DRV_TLV_FCOE_RX_FRAMES_RECEIVED,
12807         DRV_TLV_FCOE_RX_BYTES_RECEIVED,
12808         DRV_TLV_FCOE_TX_FRAMES_SENT,
12809         DRV_TLV_FCOE_TX_BYTES_SENT,
12810         DRV_TLV_CRC_ERROR_COUNT,
12811         DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID,
12812         DRV_TLV_CRC_ERROR_1_TIMESTAMP,
12813         DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID,
12814         DRV_TLV_CRC_ERROR_2_TIMESTAMP,
12815         DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID,
12816         DRV_TLV_CRC_ERROR_3_TIMESTAMP,
12817         DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID,
12818         DRV_TLV_CRC_ERROR_4_TIMESTAMP,
12819         DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID,
12820         DRV_TLV_CRC_ERROR_5_TIMESTAMP,
12821         DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT,
12822         DRV_TLV_LOSS_OF_SIGNAL_ERRORS,
12823         DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT,
12824         DRV_TLV_DISPARITY_ERROR_COUNT,
12825         DRV_TLV_CODE_VIOLATION_ERROR_COUNT,
12826         DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1,
12827         DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2,
12828         DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3,
12829         DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4,
12830         DRV_TLV_LAST_FLOGI_TIMESTAMP,
12831         DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1,
12832         DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2,
12833         DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3,
12834         DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4,
12835         DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP,
12836         DRV_TLV_LAST_FLOGI_RJT,
12837         DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP,
12838         DRV_TLV_FDISCS_SENT_COUNT,
12839         DRV_TLV_FDISC_ACCS_RECEIVED,
12840         DRV_TLV_FDISC_RJTS_RECEIVED,
12841         DRV_TLV_PLOGI_SENT_COUNT,
12842         DRV_TLV_PLOGI_ACCS_RECEIVED,
12843         DRV_TLV_PLOGI_RJTS_RECEIVED,
12844         DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID,
12845         DRV_TLV_PLOGI_1_TIMESTAMP,
12846         DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID,
12847         DRV_TLV_PLOGI_2_TIMESTAMP,
12848         DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID,
12849         DRV_TLV_PLOGI_3_TIMESTAMP,
12850         DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID,
12851         DRV_TLV_PLOGI_4_TIMESTAMP,
12852         DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID,
12853         DRV_TLV_PLOGI_5_TIMESTAMP,
12854         DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID,
12855         DRV_TLV_PLOGI_1_ACC_TIMESTAMP,
12856         DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID,
12857         DRV_TLV_PLOGI_2_ACC_TIMESTAMP,
12858         DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID,
12859         DRV_TLV_PLOGI_3_ACC_TIMESTAMP,
12860         DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID,
12861         DRV_TLV_PLOGI_4_ACC_TIMESTAMP,
12862         DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID,
12863         DRV_TLV_PLOGI_5_ACC_TIMESTAMP,
12864         DRV_TLV_LOGOS_ISSUED,
12865         DRV_TLV_LOGO_ACCS_RECEIVED,
12866         DRV_TLV_LOGO_RJTS_RECEIVED,
12867         DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID,
12868         DRV_TLV_LOGO_1_TIMESTAMP,
12869         DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID,
12870         DRV_TLV_LOGO_2_TIMESTAMP,
12871         DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID,
12872         DRV_TLV_LOGO_3_TIMESTAMP,
12873         DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID,
12874         DRV_TLV_LOGO_4_TIMESTAMP,
12875         DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID,
12876         DRV_TLV_LOGO_5_TIMESTAMP,
12877         DRV_TLV_LOGOS_RECEIVED,
12878         DRV_TLV_ACCS_ISSUED,
12879         DRV_TLV_PRLIS_ISSUED,
12880         DRV_TLV_ACCS_RECEIVED,
12881         DRV_TLV_ABTS_SENT_COUNT,
12882         DRV_TLV_ABTS_ACCS_RECEIVED,
12883         DRV_TLV_ABTS_RJTS_RECEIVED,
12884         DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID,
12885         DRV_TLV_ABTS_1_TIMESTAMP,
12886         DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID,
12887         DRV_TLV_ABTS_2_TIMESTAMP,
12888         DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID,
12889         DRV_TLV_ABTS_3_TIMESTAMP,
12890         DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID,
12891         DRV_TLV_ABTS_4_TIMESTAMP,
12892         DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID,
12893         DRV_TLV_ABTS_5_TIMESTAMP,
12894         DRV_TLV_RSCNS_RECEIVED,
12895         DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1,
12896         DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2,
12897         DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3,
12898         DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4,
12899         DRV_TLV_LUN_RESETS_ISSUED,
12900         DRV_TLV_ABORT_TASK_SETS_ISSUED,
12901         DRV_TLV_TPRLOS_SENT,
12902         DRV_TLV_NOS_SENT_COUNT,
12903         DRV_TLV_NOS_RECEIVED_COUNT,
12904         DRV_TLV_OLS_COUNT,
12905         DRV_TLV_LR_COUNT,
12906         DRV_TLV_LRR_COUNT,
12907         DRV_TLV_LIP_SENT_COUNT,
12908         DRV_TLV_LIP_RECEIVED_COUNT,
12909         DRV_TLV_EOFA_COUNT,
12910         DRV_TLV_EOFNI_COUNT,
12911         DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT,
12912         DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT,
12913         DRV_TLV_SCSI_STATUS_BUSY_COUNT,
12914         DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT,
12915         DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT,
12916         DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT,
12917         DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT,
12918         DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT,
12919         DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT,
12920         DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ,
12921         DRV_TLV_SCSI_CHECK_1_TIMESTAMP,
12922         DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ,
12923         DRV_TLV_SCSI_CHECK_2_TIMESTAMP,
12924         DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ,
12925         DRV_TLV_SCSI_CHECK_3_TIMESTAMP,
12926         DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ,
12927         DRV_TLV_SCSI_CHECK_4_TIMESTAMP,
12928         DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ,
12929         DRV_TLV_SCSI_CHECK_5_TIMESTAMP,
12930         /* Category 30: iSCSI Function Data */
12931         DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
12932         DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
12933         DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED,
12934         DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED,
12935         DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT,
12936         DRV_TLV_ISCSI_PDU_TX_BYTES_SENT
12937 };
12938
12939 struct nvm_cfg_mac_address {
12940         u32 mac_addr_hi;
12941 #define NVM_CFG_MAC_ADDRESS_HI_MASK     0x0000FFFF
12942 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET   0
12943         u32 mac_addr_lo;
12944 };
12945
12946 struct nvm_cfg1_glob {
12947         u32 generic_cont0;
12948 #define NVM_CFG1_GLOB_MF_MODE_MASK              0x00000FF0
12949 #define NVM_CFG1_GLOB_MF_MODE_OFFSET            4
12950 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED        0x0
12951 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT           0x1
12952 #define NVM_CFG1_GLOB_MF_MODE_SPIO4             0x2
12953 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0           0x3
12954 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5           0x4
12955 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0           0x5
12956 #define NVM_CFG1_GLOB_MF_MODE_BD                0x6
12957 #define NVM_CFG1_GLOB_MF_MODE_UFP               0x7
12958         u32 engineering_change[3];
12959         u32 manufacturing_id;
12960         u32 serial_number[4];
12961         u32 pcie_cfg;
12962         u32 mgmt_traffic;
12963         u32 core_cfg;
12964 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK            0x000000FF
12965 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET          0
12966 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G        0x0
12967 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G           0x1
12968 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G       0x2
12969 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F         0x3
12970 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E      0x4
12971 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G        0x5
12972 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G           0xB
12973 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G           0xC
12974 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G           0xD
12975 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G           0xE
12976 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G           0xF
12977
12978         u32 e_lane_cfg1;
12979         u32 e_lane_cfg2;
12980         u32 f_lane_cfg1;
12981         u32 f_lane_cfg2;
12982         u32 mps10_preemphasis;
12983         u32 mps10_driver_current;
12984         u32 mps25_preemphasis;
12985         u32 mps25_driver_current;
12986         u32 pci_id;
12987         u32 pci_subsys_id;
12988         u32 bar;
12989         u32 mps10_txfir_main;
12990         u32 mps10_txfir_post;
12991         u32 mps25_txfir_main;
12992         u32 mps25_txfir_post;
12993         u32 manufacture_ver;
12994         u32 manufacture_time;
12995         u32 led_global_settings;
12996         u32 generic_cont1;
12997         u32 mbi_version;
12998 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK                0x000000FF
12999 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET              0
13000 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK                0x0000FF00
13001 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET              8
13002 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK                0x00FF0000
13003 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET              16
13004         u32 mbi_date;
13005         u32 misc_sig;
13006         u32 device_capabilities;
13007 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET      0x1
13008 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE          0x2
13009 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI         0x4
13010 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE          0x8
13011         u32 power_dissipated;
13012         u32 power_consumed;
13013         u32 efi_version;
13014         u32 multi_network_modes_capability;
13015         u32 reserved[41];
13016 };
13017
13018 struct nvm_cfg1_path {
13019         u32 reserved[30];
13020 };
13021
13022 struct nvm_cfg1_port {
13023         u32 reserved__m_relocated_to_option_123;
13024         u32 reserved__m_relocated_to_option_124;
13025         u32 generic_cont0;
13026 #define NVM_CFG1_PORT_DCBX_MODE_MASK                            0x000F0000
13027 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET                          16
13028 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED                        0x0
13029 #define NVM_CFG1_PORT_DCBX_MODE_IEEE                            0x1
13030 #define NVM_CFG1_PORT_DCBX_MODE_CEE                             0x2
13031 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC                         0x3
13032 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK            0x00F00000
13033 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET          20
13034 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET        0x1
13035 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE            0x2
13036 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI           0x4
13037         u32 pcie_cfg;
13038         u32 features;
13039         u32 speed_cap_mask;
13040 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK            0x0000FFFF
13041 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET          0
13042 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G              0x1
13043 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G             0x2
13044 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G             0x8
13045 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G             0x10
13046 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G             0x20
13047 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G         0x40
13048         u32 link_settings;
13049 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK                       0x0000000F
13050 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET                     0
13051 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG                    0x0
13052 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G                         0x1
13053 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G                        0x2
13054 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G                        0x4
13055 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G                        0x5
13056 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G                        0x6
13057 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G                    0x7
13058 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ                  0x8
13059 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK                     0x00000070
13060 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET                   4
13061 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG                  0x1
13062 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX                       0x2
13063 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX                       0x4
13064         u32 phy_cfg;
13065         u32 mgmt_traffic;
13066
13067         u32 ext_phy;
13068         /* EEE power saving mode */
13069 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK                0x00FF0000
13070 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET              16
13071 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED            0x0
13072 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED            0x1
13073 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE          0x2
13074 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY         0x3
13075
13076         u32 mba_cfg1;
13077         u32 mba_cfg2;
13078         u32 vf_cfg;
13079         struct nvm_cfg_mac_address lldp_mac_address;
13080         u32 led_port_settings;
13081         u32 transceiver_00;
13082         u32 device_ids;
13083         u32 board_cfg;
13084         u32 mnm_10g_cap;
13085         u32 mnm_10g_ctrl;
13086         u32 mnm_10g_misc;
13087         u32 mnm_25g_cap;
13088         u32 mnm_25g_ctrl;
13089         u32 mnm_25g_misc;
13090         u32 mnm_40g_cap;
13091         u32 mnm_40g_ctrl;
13092         u32 mnm_40g_misc;
13093         u32 mnm_50g_cap;
13094         u32 mnm_50g_ctrl;
13095         u32 mnm_50g_misc;
13096         u32 mnm_100g_cap;
13097         u32 mnm_100g_ctrl;
13098         u32 mnm_100g_misc;
13099         u32 reserved[116];
13100 };
13101
13102 struct nvm_cfg1_func {
13103         struct nvm_cfg_mac_address mac_address;
13104         u32 rsrv1;
13105         u32 rsrv2;
13106         u32 device_id;
13107         u32 cmn_cfg;
13108         u32 pci_cfg;
13109         struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
13110         struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
13111         u32 preboot_generic_cfg;
13112         u32 reserved[8];
13113 };
13114
13115 struct nvm_cfg1 {
13116         struct nvm_cfg1_glob glob;
13117         struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
13118         struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
13119         struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
13120 };
13121
13122 enum spad_sections {
13123         SPAD_SECTION_TRACE,
13124         SPAD_SECTION_NVM_CFG,
13125         SPAD_SECTION_PUBLIC,
13126         SPAD_SECTION_PRIVATE,
13127         SPAD_SECTION_MAX
13128 };
13129
13130 #define MCP_TRACE_SIZE          2048    /* 2kb */
13131
13132 /* This section is located at a fixed location in the beginning of the
13133  * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
13134  * All the rest of data has a floating location which differs from version to
13135  * version, and is pointed by the mcp_meta_data below.
13136  * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
13137  * with it from nvram in order to clear this portion.
13138  */
13139 struct static_init {
13140         u32 num_sections;
13141         offsize_t sections[SPAD_SECTION_MAX];
13142 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
13143
13144         struct mcp_trace trace;
13145 #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
13146         u8 trace_buffer[MCP_TRACE_SIZE];
13147 #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
13148         /* running_mfw has the same definition as in nvm_map.h.
13149          * This bit indicate both the running dir, and the running bundle.
13150          * It is set once when the LIM is loaded.
13151          */
13152         u32 running_mfw;
13153 #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
13154         u32 build_time;
13155 #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
13156         u32 reset_type;
13157 #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
13158         u32 mfw_secure_mode;
13159 #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
13160         u16 pme_status_pf_bitmap;
13161 #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
13162         u16 pme_enable_pf_bitmap;
13163 #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
13164         u32 mim_nvm_addr;
13165         u32 mim_start_addr;
13166         u32 ah_pcie_link_params;
13167 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK     (0x000000ff)
13168 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT    (0)
13169 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK     (0x0000ff00)
13170 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT    (8)
13171 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK      (0x00ff0000)
13172 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT     (16)
13173 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK       (0xff000000)
13174 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT      (24)
13175 #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
13176
13177         u32 rsrv_persist[5];    /* Persist reserved for MFW upgrades */
13178 };
13179
13180 #define NVM_MAGIC_VALUE         0x669955aa
13181
13182 enum nvm_image_type {
13183         NVM_TYPE_TIM1 = 0x01,
13184         NVM_TYPE_TIM2 = 0x02,
13185         NVM_TYPE_MIM1 = 0x03,
13186         NVM_TYPE_MIM2 = 0x04,
13187         NVM_TYPE_MBA = 0x05,
13188         NVM_TYPE_MODULES_PN = 0x06,
13189         NVM_TYPE_VPD = 0x07,
13190         NVM_TYPE_MFW_TRACE1 = 0x08,
13191         NVM_TYPE_MFW_TRACE2 = 0x09,
13192         NVM_TYPE_NVM_CFG1 = 0x0a,
13193         NVM_TYPE_L2B = 0x0b,
13194         NVM_TYPE_DIR1 = 0x0c,
13195         NVM_TYPE_EAGLE_FW1 = 0x0d,
13196         NVM_TYPE_FALCON_FW1 = 0x0e,
13197         NVM_TYPE_PCIE_FW1 = 0x0f,
13198         NVM_TYPE_HW_SET = 0x10,
13199         NVM_TYPE_LIM = 0x11,
13200         NVM_TYPE_AVS_FW1 = 0x12,
13201         NVM_TYPE_DIR2 = 0x13,
13202         NVM_TYPE_CCM = 0x14,
13203         NVM_TYPE_EAGLE_FW2 = 0x15,
13204         NVM_TYPE_FALCON_FW2 = 0x16,
13205         NVM_TYPE_PCIE_FW2 = 0x17,
13206         NVM_TYPE_AVS_FW2 = 0x18,
13207         NVM_TYPE_INIT_HW = 0x19,
13208         NVM_TYPE_DEFAULT_CFG = 0x1a,
13209         NVM_TYPE_MDUMP = 0x1b,
13210         NVM_TYPE_META = 0x1c,
13211         NVM_TYPE_ISCSI_CFG = 0x1d,
13212         NVM_TYPE_FCOE_CFG = 0x1f,
13213         NVM_TYPE_ETH_PHY_FW1 = 0x20,
13214         NVM_TYPE_ETH_PHY_FW2 = 0x21,
13215         NVM_TYPE_MAX,
13216 };
13217
13218 #define DIR_ID_1    (0)
13219
13220 #endif