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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / stmicro / stmmac / dwmac1000_core.c
blobe4e9a7591efe92fb1b762dbca45c83b2c0fc4ff2
1 /*******************************************************************************
2 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
4 developing this code.
5
6 This only implements the mac core functions for this chip.
7
8 Copyright (C) 2007-2009 STMicroelectronics Ltd
9
10 This program is free software; you can redistribute it and/or modify it
11 under the terms and conditions of the GNU General Public License,
12 version 2, as published by the Free Software Foundation.
13
14 This program is distributed in the hope it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 more details.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
24
25 #include <linux/crc32.h>
26 #include <linux/slab.h>
27 #include <linux/ethtool.h>
28 #include <net/dsa.h>
29 #include <asm/io.h>
30 #include "stmmac.h"
31 #include "stmmac_pcs.h"
32 #include "dwmac1000.h"
33
34 static void dwmac1000_core_init(struct mac_device_info *hw,
35 struct net_device *dev)
36 {
37 struct stmmac_priv *priv = netdev_priv(dev);
38 void __iomem *ioaddr = hw->pcsr;
39 u32 value = readl(ioaddr + GMAC_CONTROL);
40 int mtu = dev->mtu;
41
42 /* Configure GMAC core */
43 value |= GMAC_CORE_INIT;
44
45 /* Clear ACS bit because Ethernet switch tagging formats such as
46 * Broadcom tags can look like invalid LLC/SNAP packets and cause the
47 * hardware to truncate packets on reception.
48 */
49 if (netdev_uses_dsa(dev) || !priv->plat->enh_desc)
50 value &= ~GMAC_CONTROL_ACS;
51
52 if (mtu > 1500)
53 value |= GMAC_CONTROL_2K;
54 if (mtu > 2000)
55 value |= GMAC_CONTROL_JE;
56
57 if (hw->ps) {
58 value |= GMAC_CONTROL_TE;
59
60 value &= ~hw->link.speed_mask;
61 switch (hw->ps) {
62 case SPEED_1000:
63 value |= hw->link.speed1000;
64 break;
65 case SPEED_100:
66 value |= hw->link.speed100;
67 break;
68 case SPEED_10:
69 value |= hw->link.speed10;
70 break;
71 }
72 }
73
74 writel(value, ioaddr + GMAC_CONTROL);
75
76 /* Mask GMAC interrupts */
77 value = GMAC_INT_DEFAULT_MASK;
78
79 if (hw->pcs)
80 value &= ~GMAC_INT_DISABLE_PCS;
81
82 writel(value, ioaddr + GMAC_INT_MASK);
83
84 #ifdef STMMAC_VLAN_TAG_USED
85 /* Tag detection without filtering */
86 writel(0x0, ioaddr + GMAC_VLAN_TAG);
87 #endif
88 }
89
90 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
91 {
92 void __iomem *ioaddr = hw->pcsr;
93 u32 value = readl(ioaddr + GMAC_CONTROL);
94
95 if (hw->rx_csum)
96 value |= GMAC_CONTROL_IPC;
97 else
98 value &= ~GMAC_CONTROL_IPC;
99
100 writel(value, ioaddr + GMAC_CONTROL);
101
102 value = readl(ioaddr + GMAC_CONTROL);
103
104 return !!(value & GMAC_CONTROL_IPC);
105 }
106
107 static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
108 {
109 void __iomem *ioaddr = hw->pcsr;
110 int i;
111
112 for (i = 0; i < 55; i++)
113 reg_space[i] = readl(ioaddr + i * 4);
114 }
115
116 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
117 unsigned char *addr,
118 unsigned int reg_n)
119 {
120 void __iomem *ioaddr = hw->pcsr;
121 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
122 GMAC_ADDR_LOW(reg_n));
123 }
124
125 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
126 unsigned char *addr,
127 unsigned int reg_n)
128 {
129 void __iomem *ioaddr = hw->pcsr;
130 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
131 GMAC_ADDR_LOW(reg_n));
132 }
133
134 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
135 int mcbitslog2)
136 {
137 int numhashregs, regs;
138
139 switch (mcbitslog2) {
140 case 6:
141 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
142 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
143 return;
144 break;
145 case 7:
146 numhashregs = 4;
147 break;
148 case 8:
149 numhashregs = 8;
150 break;
151 default:
152 pr_debug("STMMAC: err in setting multicast filter\n");
153 return;
154 break;
155 }
156 for (regs = 0; regs < numhashregs; regs++)
157 writel(mcfilterbits[regs],
158 ioaddr + GMAC_EXTHASH_BASE + regs * 4);
159 }
160
161 static void dwmac1000_set_filter(struct mac_device_info *hw,
162 struct net_device *dev)
163 {
164 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
165 unsigned int value = 0;
166 unsigned int perfect_addr_number = hw->unicast_filter_entries;
167 u32 mc_filter[8];
168 int mcbitslog2 = hw->mcast_bits_log2;
169
170 pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
171 netdev_mc_count(dev), netdev_uc_count(dev));
172
173 memset(mc_filter, 0, sizeof(mc_filter));
174
175 if (dev->flags & IFF_PROMISC) {
176 value = GMAC_FRAME_FILTER_PR;
177 } else if (dev->flags & IFF_ALLMULTI) {
178 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
179 } else if (!netdev_mc_empty(dev)) {
180 struct netdev_hw_addr *ha;
181
182 /* Hash filter for multicast */
183 value = GMAC_FRAME_FILTER_HMC;
184
185 netdev_for_each_mc_addr(ha, dev) {
186 /* The upper n bits of the calculated CRC are used to
187 * index the contents of the hash table. The number of
188 * bits used depends on the hardware configuration
189 * selected at core configuration time.
190 */
191 int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
192 ETH_ALEN)) >>
193 (32 - mcbitslog2);
194 /* The most significant bit determines the register to
195 * use (H/L) while the other 5 bits determine the bit
196 * within the register.
197 */
198 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
199 }
200 }
201
202 dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
203
204 /* Handle multiple unicast addresses (perfect filtering) */
205 if (netdev_uc_count(dev) > perfect_addr_number)
206 /* Switch to promiscuous mode if more than unicast
207 * addresses are requested than supported by hardware.
208 */
209 value |= GMAC_FRAME_FILTER_PR;
210 else {
211 int reg = 1;
212 struct netdev_hw_addr *ha;
213
214 netdev_for_each_uc_addr(ha, dev) {
215 stmmac_set_mac_addr(ioaddr, ha->addr,
216 GMAC_ADDR_HIGH(reg),
217 GMAC_ADDR_LOW(reg));
218 reg++;
219 }
220
221 while (reg < perfect_addr_number) {
222 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
223 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
224 reg++;
225 }
226 }
227
228 #ifdef FRAME_FILTER_DEBUG
229 /* Enable Receive all mode (to debug filtering_fail errors) */
230 value |= GMAC_FRAME_FILTER_RA;
231 #endif
232 writel(value, ioaddr + GMAC_FRAME_FILTER);
233 }
234
235
236 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
237 unsigned int fc, unsigned int pause_time,
238 u32 tx_cnt)
239 {
240 void __iomem *ioaddr = hw->pcsr;
241 /* Set flow such that DZPQ in Mac Register 6 is 0,
242 * and unicast pause detect is enabled.
243 */
244 unsigned int flow = GMAC_FLOW_CTRL_UP;
245
246 pr_debug("GMAC Flow-Control:\n");
247 if (fc & FLOW_RX) {
248 pr_debug("\tReceive Flow-Control ON\n");
249 flow |= GMAC_FLOW_CTRL_RFE;
250 }
251 if (fc & FLOW_TX) {
252 pr_debug("\tTransmit Flow-Control ON\n");
253 flow |= GMAC_FLOW_CTRL_TFE;
254 }
255
256 if (duplex) {
257 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
258 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
259 }
260
261 writel(flow, ioaddr + GMAC_FLOW_CTRL);
262 }
263
264 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
265 {
266 void __iomem *ioaddr = hw->pcsr;
267 unsigned int pmt = 0;
268
269 if (mode & WAKE_MAGIC) {
270 pr_debug("GMAC: WOL Magic frame\n");
271 pmt |= power_down | magic_pkt_en;
272 }
273 if (mode & WAKE_UCAST) {
274 pr_debug("GMAC: WOL on global unicast\n");
275 pmt |= power_down | global_unicast | wake_up_frame_en;
276 }
277
278 writel(pmt, ioaddr + GMAC_PMT);
279 }
280
281 /* RGMII or SMII interface */
282 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
283 {
284 u32 status;
285
286 status = readl(ioaddr + GMAC_RGSMIIIS);
287 x->irq_rgmii_n++;
288
289 /* Check the link status */
290 if (status & GMAC_RGSMIIIS_LNKSTS) {
291 int speed_value;
292
293 x->pcs_link = 1;
294
295 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
296 GMAC_RGSMIIIS_SPEED_SHIFT);
297 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
298 x->pcs_speed = SPEED_1000;
299 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
300 x->pcs_speed = SPEED_100;
301 else
302 x->pcs_speed = SPEED_10;
303
304 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
305
306 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
307 x->pcs_duplex ? "Full" : "Half");
308 } else {
309 x->pcs_link = 0;
310 pr_info("Link is Down\n");
311 }
312 }
313
314 static int dwmac1000_irq_status(struct mac_device_info *hw,
315 struct stmmac_extra_stats *x)
316 {
317 void __iomem *ioaddr = hw->pcsr;
318 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
319 u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
320 int ret = 0;
321
322 /* Discard masked bits */
323 intr_status &= ~intr_mask;
324
325 /* Not used events (e.g. MMC interrupts) are not handled. */
326 if ((intr_status & GMAC_INT_STATUS_MMCTIS))
327 x->mmc_tx_irq_n++;
328 if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
329 x->mmc_rx_irq_n++;
330 if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
331 x->mmc_rx_csum_offload_irq_n++;
332 if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
333 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
334 readl(ioaddr + GMAC_PMT);
335 x->irq_receive_pmt_irq_n++;
336 }
337
338 /* MAC tx/rx EEE LPI entry/exit interrupts */
339 if (intr_status & GMAC_INT_STATUS_LPIIS) {
340 /* Clean LPI interrupt by reading the Reg 12 */
341 ret = readl(ioaddr + LPI_CTRL_STATUS);
342
343 if (ret & LPI_CTRL_STATUS_TLPIEN)
344 x->irq_tx_path_in_lpi_mode_n++;
345 if (ret & LPI_CTRL_STATUS_TLPIEX)
346 x->irq_tx_path_exit_lpi_mode_n++;
347 if (ret & LPI_CTRL_STATUS_RLPIEN)
348 x->irq_rx_path_in_lpi_mode_n++;
349 if (ret & LPI_CTRL_STATUS_RLPIEX)
350 x->irq_rx_path_exit_lpi_mode_n++;
351 }
352
353 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
354
355 if (intr_status & PCS_RGSMIIIS_IRQ)
356 dwmac1000_rgsmii(ioaddr, x);
357
358 return ret;
359 }
360
361 static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
362 bool en_tx_lpi_clockgating)
363 {
364 void __iomem *ioaddr = hw->pcsr;
365 u32 value;
366
367 /*TODO - en_tx_lpi_clockgating treatment */
368
369 /* Enable the link status receive on RGMII, SGMII ore SMII
370 * receive path and instruct the transmit to enter in LPI
371 * state.
372 */
373 value = readl(ioaddr + LPI_CTRL_STATUS);
374 value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
375 writel(value, ioaddr + LPI_CTRL_STATUS);
376 }
377
378 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
379 {
380 void __iomem *ioaddr = hw->pcsr;
381 u32 value;
382
383 value = readl(ioaddr + LPI_CTRL_STATUS);
384 value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
385 writel(value, ioaddr + LPI_CTRL_STATUS);
386 }
387
388 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
389 {
390 void __iomem *ioaddr = hw->pcsr;
391 u32 value;
392
393 value = readl(ioaddr + LPI_CTRL_STATUS);
394
395 if (link)
396 value |= LPI_CTRL_STATUS_PLS;
397 else
398 value &= ~LPI_CTRL_STATUS_PLS;
399
400 writel(value, ioaddr + LPI_CTRL_STATUS);
401 }
402
403 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
404 {
405 void __iomem *ioaddr = hw->pcsr;
406 int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
407
408 /* Program the timers in the LPI timer control register:
409 * LS: minimum time (ms) for which the link
410 * status from PHY should be ok before transmitting
411 * the LPI pattern.
412 * TW: minimum time (us) for which the core waits
413 * after it has stopped transmitting the LPI pattern.
414 */
415 writel(value, ioaddr + LPI_TIMER_CTRL);
416 }
417
418 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
419 bool loopback)
420 {
421 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
422 }
423
424 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
425 {
426 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
427 }
428
429 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
430 {
431 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
432 }
433
434 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
435 u32 rx_queues, u32 tx_queues)
436 {
437 u32 value = readl(ioaddr + GMAC_DEBUG);
438
439 if (value & GMAC_DEBUG_TXSTSFSTS)
440 x->mtl_tx_status_fifo_full++;
441 if (value & GMAC_DEBUG_TXFSTS)
442 x->mtl_tx_fifo_not_empty++;
443 if (value & GMAC_DEBUG_TWCSTS)
444 x->mmtl_fifo_ctrl++;
445 if (value & GMAC_DEBUG_TRCSTS_MASK) {
446 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
447 >> GMAC_DEBUG_TRCSTS_SHIFT;
448 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
449 x->mtl_tx_fifo_read_ctrl_write++;
450 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
451 x->mtl_tx_fifo_read_ctrl_wait++;
452 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
453 x->mtl_tx_fifo_read_ctrl_read++;
454 else
455 x->mtl_tx_fifo_read_ctrl_idle++;
456 }
457 if (value & GMAC_DEBUG_TXPAUSED)
458 x->mac_tx_in_pause++;
459 if (value & GMAC_DEBUG_TFCSTS_MASK) {
460 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
461 >> GMAC_DEBUG_TFCSTS_SHIFT;
462
463 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
464 x->mac_tx_frame_ctrl_xfer++;
465 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
466 x->mac_tx_frame_ctrl_pause++;
467 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
468 x->mac_tx_frame_ctrl_wait++;
469 else
470 x->mac_tx_frame_ctrl_idle++;
471 }
472 if (value & GMAC_DEBUG_TPESTS)
473 x->mac_gmii_tx_proto_engine++;
474 if (value & GMAC_DEBUG_RXFSTS_MASK) {
475 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
476 >> GMAC_DEBUG_RRCSTS_SHIFT;
477
478 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
479 x->mtl_rx_fifo_fill_level_full++;
480 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
481 x->mtl_rx_fifo_fill_above_thresh++;
482 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
483 x->mtl_rx_fifo_fill_below_thresh++;
484 else
485 x->mtl_rx_fifo_fill_level_empty++;
486 }
487 if (value & GMAC_DEBUG_RRCSTS_MASK) {
488 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
489 GMAC_DEBUG_RRCSTS_SHIFT;
490
491 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
492 x->mtl_rx_fifo_read_ctrl_flush++;
493 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
494 x->mtl_rx_fifo_read_ctrl_read_data++;
495 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
496 x->mtl_rx_fifo_read_ctrl_status++;
497 else
498 x->mtl_rx_fifo_read_ctrl_idle++;
499 }
500 if (value & GMAC_DEBUG_RWCSTS)
501 x->mtl_rx_fifo_ctrl_active++;
502 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
503 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
504 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
505 if (value & GMAC_DEBUG_RPESTS)
506 x->mac_gmii_rx_proto_engine++;
507 }
508
509 const struct stmmac_ops dwmac1000_ops = {
510 .core_init = dwmac1000_core_init,
511 .set_mac = stmmac_set_mac,
512 .rx_ipc = dwmac1000_rx_ipc_enable,
513 .dump_regs = dwmac1000_dump_regs,
514 .host_irq_status = dwmac1000_irq_status,
515 .set_filter = dwmac1000_set_filter,
516 .flow_ctrl = dwmac1000_flow_ctrl,
517 .pmt = dwmac1000_pmt,
518 .set_umac_addr = dwmac1000_set_umac_addr,
519 .get_umac_addr = dwmac1000_get_umac_addr,
520 .set_eee_mode = dwmac1000_set_eee_mode,
521 .reset_eee_mode = dwmac1000_reset_eee_mode,
522 .set_eee_timer = dwmac1000_set_eee_timer,
523 .set_eee_pls = dwmac1000_set_eee_pls,
524 .debug = dwmac1000_debug,
525 .pcs_ctrl_ane = dwmac1000_ctrl_ane,
526 .pcs_rane = dwmac1000_rane,
527 .pcs_get_adv_lp = dwmac1000_get_adv_lp,
528 };
529
530 int dwmac1000_setup(struct stmmac_priv *priv)
531 {
532 struct mac_device_info *mac = priv->hw;
533
534 dev_info(priv->device, "\tDWMAC1000\n");
535
536 priv->dev->priv_flags |= IFF_UNICAST_FLT;
537 mac->pcsr = priv->ioaddr;
538 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
539 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
540 mac->mcast_bits_log2 = 0;
541
542 if (mac->multicast_filter_bins)
543 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
544
545 mac->link.duplex = GMAC_CONTROL_DM;
546 mac->link.speed10 = GMAC_CONTROL_PS;
547 mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
548 mac->link.speed1000 = 0;
549 mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
550 mac->mii.addr = GMAC_MII_ADDR;
551 mac->mii.data = GMAC_MII_DATA;
552 mac->mii.addr_shift = 11;
553 mac->mii.addr_mask = 0x0000F800;
554 mac->mii.reg_shift = 6;
555 mac->mii.reg_mask = 0x000007C0;
556 mac->mii.clk_csr_shift = 2;
557 mac->mii.clk_csr_mask = GENMASK(5, 2);
558
559 return 0;
560 }
Linux with added FPC-III support