drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h

   1 /*******************************************************************************
   2   DWMAC DMA Header file.
   3
   4   Copyright (C) 2007-2009  STMicroelectronics Ltd
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   The full GNU General Public License is included in this distribution in
  16   the file called "COPYING".
  17
  18   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  19 *******************************************************************************/
  20
  21 #ifndef __DWMAC_DMA_H__
  22 #define __DWMAC_DMA_H__
  23
  24 /* DMA CRS Control and Status Register Mapping */
  25 #define DMA_BUS_MODE            0x00001000      /* Bus Mode */
  26 #define DMA_XMT_POLL_DEMAND     0x00001004      /* Transmit Poll Demand */
  27 #define DMA_RCV_POLL_DEMAND     0x00001008      /* Received Poll Demand */
  28 #define DMA_RCV_BASE_ADDR       0x0000100c      /* Receive List Base */
  29 #define DMA_TX_BASE_ADDR        0x00001010      /* Transmit List Base */
  30 #define DMA_STATUS              0x00001014      /* Status Register */
  31 #define DMA_CONTROL             0x00001018      /* Ctrl (Operational Mode) */
  32 #define DMA_INTR_ENA            0x0000101c      /* Interrupt Enable */
  33 #define DMA_MISSED_FRAME_CTR    0x00001020      /* Missed Frame Counter */
  34
  35 /* SW Reset */
  36 #define DMA_BUS_MODE_SFT_RESET  0x00000001      /* Software Reset */
  37
  38 /* Rx watchdog register */
  39 #define DMA_RX_WATCHDOG         0x00001024
  40
  41 /* AXI Master Bus Mode */
  42 #define DMA_AXI_BUS_MODE        0x00001028
  43
  44 #define DMA_AXI_EN_LPI          BIT(31)
  45 #define DMA_AXI_LPI_XIT_FRM     BIT(30)
  46 #define DMA_AXI_WR_OSR_LMT      GENMASK(23, 20)
  47 #define DMA_AXI_WR_OSR_LMT_SHIFT        20
  48 #define DMA_AXI_WR_OSR_LMT_MASK 0xf
  49 #define DMA_AXI_RD_OSR_LMT      GENMASK(19, 16)
  50 #define DMA_AXI_RD_OSR_LMT_SHIFT        16
  51 #define DMA_AXI_RD_OSR_LMT_MASK 0xf
  52
  53 #define DMA_AXI_OSR_MAX         0xf
  54 #define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
  55                                (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
  56 #define DMA_AXI_1KBBE           BIT(13)
  57 #define DMA_AXI_AAL             BIT(12)
  58 #define DMA_AXI_BLEN256         BIT(7)
  59 #define DMA_AXI_BLEN128         BIT(6)
  60 #define DMA_AXI_BLEN64          BIT(5)
  61 #define DMA_AXI_BLEN32          BIT(4)
  62 #define DMA_AXI_BLEN16          BIT(3)
  63 #define DMA_AXI_BLEN8           BIT(2)
  64 #define DMA_AXI_BLEN4           BIT(1)
  65 #define DMA_BURST_LEN_DEFAULT   (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
  66                                  DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
  67                                  DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
  68                                  DMA_AXI_BLEN4)
  69
  70 #define DMA_AXI_UNDEF           BIT(0)
  71
  72 #define DMA_AXI_BURST_LEN_MASK  0x000000FE
  73
  74 #define DMA_CUR_TX_BUF_ADDR     0x00001050      /* Current Host Tx Buffer */
  75 #define DMA_CUR_RX_BUF_ADDR     0x00001054      /* Current Host Rx Buffer */
  76 #define DMA_HW_FEATURE          0x00001058      /* HW Feature Register */
  77
  78 /* DMA Control register defines */
  79 #define DMA_CONTROL_ST          0x00002000      /* Start/Stop Transmission */
  80 #define DMA_CONTROL_SR          0x00000002      /* Start/Stop Receive */
  81
  82 /* DMA Normal interrupt */
  83 #define DMA_INTR_ENA_NIE 0x00010000     /* Normal Summary */
  84 #define DMA_INTR_ENA_TIE 0x00000001     /* Transmit Interrupt */
  85 #define DMA_INTR_ENA_TUE 0x00000004     /* Transmit Buffer Unavailable */
  86 #define DMA_INTR_ENA_RIE 0x00000040     /* Receive Interrupt */
  87 #define DMA_INTR_ENA_ERE 0x00004000     /* Early Receive */
  88
  89 #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
  90                         DMA_INTR_ENA_TIE)
  91
  92 /* DMA Abnormal interrupt */
  93 #define DMA_INTR_ENA_AIE 0x00008000     /* Abnormal Summary */
  94 #define DMA_INTR_ENA_FBE 0x00002000     /* Fatal Bus Error */
  95 #define DMA_INTR_ENA_ETE 0x00000400     /* Early Transmit */
  96 #define DMA_INTR_ENA_RWE 0x00000200     /* Receive Watchdog */
  97 #define DMA_INTR_ENA_RSE 0x00000100     /* Receive Stopped */
  98 #define DMA_INTR_ENA_RUE 0x00000080     /* Receive Buffer Unavailable */
  99 #define DMA_INTR_ENA_UNE 0x00000020     /* Tx Underflow */
 100 #define DMA_INTR_ENA_OVE 0x00000010     /* Receive Overflow */
 101 #define DMA_INTR_ENA_TJE 0x00000008     /* Transmit Jabber */
 102 #define DMA_INTR_ENA_TSE 0x00000002     /* Transmit Stopped */
 103
 104 #define DMA_INTR_ABNORMAL       (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
 105                                 DMA_INTR_ENA_UNE)
 106
 107 /* DMA default interrupt mask */
 108 #define DMA_INTR_DEFAULT_MASK   (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
 109
 110 /* DMA Status register defines */
 111 #define DMA_STATUS_GLPII        0x40000000      /* GMAC LPI interrupt */
 112 #define DMA_STATUS_GPI          0x10000000      /* PMT interrupt */
 113 #define DMA_STATUS_GMI          0x08000000      /* MMC interrupt */
 114 #define DMA_STATUS_GLI          0x04000000      /* GMAC Line interface int */
 115 #define DMA_STATUS_EB_MASK      0x00380000      /* Error Bits Mask */
 116 #define DMA_STATUS_EB_TX_ABORT  0x00080000      /* Error Bits - TX Abort */
 117 #define DMA_STATUS_EB_RX_ABORT  0x00100000      /* Error Bits - RX Abort */
 118 #define DMA_STATUS_TS_MASK      0x00700000      /* Transmit Process State */
 119 #define DMA_STATUS_TS_SHIFT     20
 120 #define DMA_STATUS_RS_MASK      0x000e0000      /* Receive Process State */
 121 #define DMA_STATUS_RS_SHIFT     17
 122 #define DMA_STATUS_NIS  0x00010000      /* Normal Interrupt Summary */
 123 #define DMA_STATUS_AIS  0x00008000      /* Abnormal Interrupt Summary */
 124 #define DMA_STATUS_ERI  0x00004000      /* Early Receive Interrupt */
 125 #define DMA_STATUS_FBI  0x00002000      /* Fatal Bus Error Interrupt */
 126 #define DMA_STATUS_ETI  0x00000400      /* Early Transmit Interrupt */
 127 #define DMA_STATUS_RWT  0x00000200      /* Receive Watchdog Timeout */
 128 #define DMA_STATUS_RPS  0x00000100      /* Receive Process Stopped */
 129 #define DMA_STATUS_RU   0x00000080      /* Receive Buffer Unavailable */
 130 #define DMA_STATUS_RI   0x00000040      /* Receive Interrupt */
 131 #define DMA_STATUS_UNF  0x00000020      /* Transmit Underflow */
 132 #define DMA_STATUS_OVF  0x00000010      /* Receive Overflow */
 133 #define DMA_STATUS_TJT  0x00000008      /* Transmit Jabber Timeout */
 134 #define DMA_STATUS_TU   0x00000004      /* Transmit Buffer Unavailable */
 135 #define DMA_STATUS_TPS  0x00000002      /* Transmit Process Stopped */
 136 #define DMA_STATUS_TI   0x00000001      /* Transmit Interrupt */
 137 #define DMA_CONTROL_FTF         0x00100000      /* Flush transmit FIFO */
 138
 139 #define NUM_DWMAC100_DMA_REGS   9
 140 #define NUM_DWMAC1000_DMA_REGS  23
 141
 142 void dwmac_enable_dma_transmission(void __iomem *ioaddr);
 143 void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan);
 144 void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan);
 145 void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan);
 146 void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan);
 147 void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan);
 148 void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan);
 149 int dwmac_dma_interrupt(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 150                         u32 chan);
 151 int dwmac_dma_reset(void __iomem *ioaddr);
 152
 153 #endif /* __DWMAC_DMA_H__ */