drivers/net/phy/mdio-mux-bcm-iproc.c

   1 /*
   2  * Copyright 2016 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License, version 2, as
   6  * published by the Free Software Foundation (the "GPL").
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License version 2 (GPLv2) for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * version 2 (GPLv2) along with this source code.
  15  */
  16 #include <linux/clk.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/device.h>
  19 #include <linux/of_mdio.h>
  20 #include <linux/module.h>
  21 #include <linux/phy.h>
  22 #include <linux/mdio-mux.h>
  23 #include <linux/delay.h>
  24
  25 #define MDIO_RATE_ADJ_EXT_OFFSET        0x000
  26 #define MDIO_RATE_ADJ_INT_OFFSET        0x004
  27 #define MDIO_RATE_ADJ_DIVIDENT_SHIFT    16
  28
  29 #define MDIO_SCAN_CTRL_OFFSET           0x008
  30 #define MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR  28
  31
  32 #define MDIO_PARAM_OFFSET               0x23c
  33 #define MDIO_PARAM_MIIM_CYCLE           29
  34 #define MDIO_PARAM_INTERNAL_SEL         25
  35 #define MDIO_PARAM_BUS_ID               22
  36 #define MDIO_PARAM_C45_SEL              21
  37 #define MDIO_PARAM_PHY_ID               16
  38 #define MDIO_PARAM_PHY_DATA             0
  39
  40 #define MDIO_READ_OFFSET                0x240
  41 #define MDIO_READ_DATA_MASK             0xffff
  42 #define MDIO_ADDR_OFFSET                0x244
  43
  44 #define MDIO_CTRL_OFFSET                0x248
  45 #define MDIO_CTRL_WRITE_OP              0x1
  46 #define MDIO_CTRL_READ_OP               0x2
  47
  48 #define MDIO_STAT_OFFSET                0x24c
  49 #define MDIO_STAT_DONE                  1
  50
  51 #define BUS_MAX_ADDR                    32
  52 #define EXT_BUS_START_ADDR              16
  53
  54 #define MDIO_REG_ADDR_SPACE_SIZE        0x250
  55
  56 #define MDIO_OPERATING_FREQUENCY        11000000
  57 #define MDIO_RATE_ADJ_DIVIDENT          1
  58
  59 struct iproc_mdiomux_desc {
  60         void *mux_handle;
  61         void __iomem *base;
  62         struct device *dev;
  63         struct mii_bus *mii_bus;
  64         struct clk *core_clk;
  65 };
  66
  67 static void mdio_mux_iproc_config(struct iproc_mdiomux_desc *md)
  68 {
  69         u32 divisor;
  70         u32 val;
  71
  72         /* Disable external mdio master access */
  73         val = readl(md->base + MDIO_SCAN_CTRL_OFFSET);
  74         val |= BIT(MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR);
  75         writel(val, md->base + MDIO_SCAN_CTRL_OFFSET);
  76
  77         if (md->core_clk) {
  78                 /* use rate adjust regs to derrive the mdio's operating
  79                  * frequency from the specified core clock
  80                  */
  81                 divisor = clk_get_rate(md->core_clk) / MDIO_OPERATING_FREQUENCY;
  82                 divisor = divisor / (MDIO_RATE_ADJ_DIVIDENT + 1);
  83                 val = divisor;
  84                 val |= MDIO_RATE_ADJ_DIVIDENT << MDIO_RATE_ADJ_DIVIDENT_SHIFT;
  85                 writel(val, md->base + MDIO_RATE_ADJ_EXT_OFFSET);
  86                 writel(val, md->base + MDIO_RATE_ADJ_INT_OFFSET);
  87         }
  88 }
  89
  90 static int iproc_mdio_wait_for_idle(void __iomem *base, bool result)
  91 {
  92         unsigned int timeout = 1000; /* loop for 1s */
  93         u32 val;
  94
  95         do {
  96                 val = readl(base + MDIO_STAT_OFFSET);
  97                 if ((val & MDIO_STAT_DONE) == result)
  98                         return 0;
  99
 100                 usleep_range(1000, 2000);
 101         } while (timeout--);
 102
 103         return -ETIMEDOUT;
 104 }
 105
 106 /* start_miim_ops- Program and start MDIO transaction over mdio bus.
 107  * @base: Base address
 108  * @phyid: phyid of the selected bus.
 109  * @reg: register offset to be read/written.
 110  * @val :0 if read op else value to be written in @reg;
 111  * @op: Operation that need to be carried out.
 112  *      MDIO_CTRL_READ_OP: Read transaction.
 113  *      MDIO_CTRL_WRITE_OP: Write transaction.
 114  *
 115  * Return value: Successful Read operation returns read reg values and write
 116  *      operation returns 0. Failure operation returns negative error code.
 117  */
 118 static int start_miim_ops(void __iomem *base,
 119                           u16 phyid, u32 reg, u16 val, u32 op)
 120 {
 121         u32 param;
 122         int ret;
 123
 124         writel(0, base + MDIO_CTRL_OFFSET);
 125         ret = iproc_mdio_wait_for_idle(base, 0);
 126         if (ret)
 127                 goto err;
 128
 129         param = readl(base + MDIO_PARAM_OFFSET);
 130         param |= phyid << MDIO_PARAM_PHY_ID;
 131         param |= val << MDIO_PARAM_PHY_DATA;
 132         if (reg & MII_ADDR_C45)
 133                 param |= BIT(MDIO_PARAM_C45_SEL);
 134
 135         writel(param, base + MDIO_PARAM_OFFSET);
 136
 137         writel(reg, base + MDIO_ADDR_OFFSET);
 138
 139         writel(op, base + MDIO_CTRL_OFFSET);
 140
 141         ret = iproc_mdio_wait_for_idle(base, 1);
 142         if (ret)
 143                 goto err;
 144
 145         if (op == MDIO_CTRL_READ_OP)
 146                 ret = readl(base + MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK;
 147 err:
 148         return ret;
 149 }
 150
 151 static int iproc_mdiomux_read(struct mii_bus *bus, int phyid, int reg)
 152 {
 153         struct iproc_mdiomux_desc *md = bus->priv;
 154         int ret;
 155
 156         ret = start_miim_ops(md->base, phyid, reg, 0, MDIO_CTRL_READ_OP);
 157         if (ret < 0)
 158                 dev_err(&bus->dev, "mdiomux read operation failed!!!");
 159
 160         return ret;
 161 }
 162
 163 static int iproc_mdiomux_write(struct mii_bus *bus,
 164                                int phyid, int reg, u16 val)
 165 {
 166         struct iproc_mdiomux_desc *md = bus->priv;
 167         int ret;
 168
 169         /* Write val at reg offset */
 170         ret = start_miim_ops(md->base, phyid, reg, val, MDIO_CTRL_WRITE_OP);
 171         if (ret < 0)
 172                 dev_err(&bus->dev, "mdiomux write operation failed!!!");
 173
 174         return ret;
 175 }
 176
 177 static int mdio_mux_iproc_switch_fn(int current_child, int desired_child,
 178                                     void *data)
 179 {
 180         struct iproc_mdiomux_desc *md = data;
 181         u32 param, bus_id;
 182         bool bus_dir;
 183
 184         /* select bus and its properties */
 185         bus_dir = (desired_child < EXT_BUS_START_ADDR);
 186         bus_id = bus_dir ? desired_child : (desired_child - EXT_BUS_START_ADDR);
 187
 188         param = (bus_dir ? 1 : 0) << MDIO_PARAM_INTERNAL_SEL;
 189         param |= (bus_id << MDIO_PARAM_BUS_ID);
 190
 191         writel(param, md->base + MDIO_PARAM_OFFSET);
 192         return 0;
 193 }
 194
 195 static int mdio_mux_iproc_probe(struct platform_device *pdev)
 196 {
 197         struct iproc_mdiomux_desc *md;
 198         struct mii_bus *bus;
 199         struct resource *res;
 200         int rc;
 201
 202         md = devm_kzalloc(&pdev->dev, sizeof(*md), GFP_KERNEL);
 203         if (!md)
 204                 return -ENOMEM;
 205         md->dev = &pdev->dev;
 206
 207         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 208         if (res->start & 0xfff) {
 209                 /* For backward compatibility in case the
 210                  * base address is specified with an offset.
 211                  */
 212                 dev_info(&pdev->dev, "fix base address in dt-blob\n");
 213                 res->start &= ~0xfff;
 214                 res->end = res->start + MDIO_REG_ADDR_SPACE_SIZE - 1;
 215         }
 216         md->base = devm_ioremap_resource(&pdev->dev, res);
 217         if (IS_ERR(md->base)) {
 218                 dev_err(&pdev->dev, "failed to ioremap register\n");
 219                 return PTR_ERR(md->base);
 220         }
 221
 222         md->mii_bus = devm_mdiobus_alloc(&pdev->dev);
 223         if (!md->mii_bus) {
 224                 dev_err(&pdev->dev, "mdiomux bus alloc failed\n");
 225                 return -ENOMEM;
 226         }
 227
 228         md->core_clk = devm_clk_get(&pdev->dev, NULL);
 229         if (md->core_clk == ERR_PTR(-ENOENT) ||
 230             md->core_clk == ERR_PTR(-EINVAL))
 231                 md->core_clk = NULL;
 232         else if (IS_ERR(md->core_clk))
 233                 return PTR_ERR(md->core_clk);
 234
 235         rc = clk_prepare_enable(md->core_clk);
 236         if (rc) {
 237                 dev_err(&pdev->dev, "failed to enable core clk\n");
 238                 return rc;
 239         }
 240
 241         bus = md->mii_bus;
 242         bus->priv = md;
 243         bus->name = "iProc MDIO mux bus";
 244         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id);
 245         bus->parent = &pdev->dev;
 246         bus->read = iproc_mdiomux_read;
 247         bus->write = iproc_mdiomux_write;
 248
 249         bus->phy_mask = ~0;
 250         bus->dev.of_node = pdev->dev.of_node;
 251         rc = mdiobus_register(bus);
 252         if (rc) {
 253                 dev_err(&pdev->dev, "mdiomux registration failed\n");
 254                 goto out_clk;
 255         }
 256
 257         platform_set_drvdata(pdev, md);
 258
 259         rc = mdio_mux_init(md->dev, md->dev->of_node, mdio_mux_iproc_switch_fn,
 260                            &md->mux_handle, md, md->mii_bus);
 261         if (rc) {
 262                 dev_info(md->dev, "mdiomux initialization failed\n");
 263                 goto out_register;
 264         }
 265
 266         mdio_mux_iproc_config(md);
 267
 268         dev_info(md->dev, "iProc mdiomux registered\n");
 269         return 0;
 270
 271 out_register:
 272         mdiobus_unregister(bus);
 273 out_clk:
 274         clk_disable_unprepare(md->core_clk);
 275         return rc;
 276 }
 277
 278 static int mdio_mux_iproc_remove(struct platform_device *pdev)
 279 {
 280         struct iproc_mdiomux_desc *md = platform_get_drvdata(pdev);
 281
 282         mdio_mux_uninit(md->mux_handle);
 283         mdiobus_unregister(md->mii_bus);
 284         clk_disable_unprepare(md->core_clk);
 285
 286         return 0;
 287 }
 288
 289 #ifdef CONFIG_PM_SLEEP
 290 static int mdio_mux_iproc_suspend(struct device *dev)
 291 {
 292         struct platform_device *pdev = to_platform_device(dev);
 293         struct iproc_mdiomux_desc *md = platform_get_drvdata(pdev);
 294
 295         clk_disable_unprepare(md->core_clk);
 296
 297         return 0;
 298 }
 299
 300 static int mdio_mux_iproc_resume(struct device *dev)
 301 {
 302         struct platform_device *pdev = to_platform_device(dev);
 303         struct iproc_mdiomux_desc *md = platform_get_drvdata(pdev);
 304         int rc;
 305
 306         rc = clk_prepare_enable(md->core_clk);
 307         if (rc) {
 308                 dev_err(md->dev, "failed to enable core clk\n");
 309                 return rc;
 310         }
 311         mdio_mux_iproc_config(md);
 312
 313         return 0;
 314 }
 315 #endif
 316
 317 static SIMPLE_DEV_PM_OPS(mdio_mux_iproc_pm_ops,
 318                          mdio_mux_iproc_suspend, mdio_mux_iproc_resume);
 319
 320 static const struct of_device_id mdio_mux_iproc_match[] = {
 321         {
 322                 .compatible = "brcm,mdio-mux-iproc",
 323         },
 324         {},
 325 };
 326 MODULE_DEVICE_TABLE(of, mdio_mux_iproc_match);
 327
 328 static struct platform_driver mdiomux_iproc_driver = {
 329         .driver = {
 330                 .name           = "mdio-mux-iproc",
 331                 .of_match_table = mdio_mux_iproc_match,
 332                 .pm             = &mdio_mux_iproc_pm_ops,
 333         },
 334         .probe          = mdio_mux_iproc_probe,
 335         .remove         = mdio_mux_iproc_remove,
 336 };
 337
 338 module_platform_driver(mdiomux_iproc_driver);
 339
 340 MODULE_DESCRIPTION("iProc MDIO Mux Bus Driver");
 341 MODULE_AUTHOR("Pramod Kumar <pramod.kumar@broadcom.com>");
 342 MODULE_LICENSE("GPL v2");