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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / phy / micrel.c
blob55caaaf969da5dee6c30a28110c0aac77b0275f0
1 /*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
20 * ksz8081, ksz8091,
21 * ksz8061,
22 * Switch : ksz8873, ksz886x
23 * ksz9477
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/phy.h>
29 #include <linux/micrel_phy.h>
30 #include <linux/of.h>
31 #include <linux/clk.h>
32 #include <linux/delay.h>
33
34 /* Operation Mode Strap Override */
35 #define MII_KSZPHY_OMSO 0x16
36 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
37 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
38 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
39 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
40
41 /* general Interrupt control/status reg in vendor specific block. */
42 #define MII_KSZPHY_INTCS 0x1B
43 #define KSZPHY_INTCS_JABBER BIT(15)
44 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
45 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
46 #define KSZPHY_INTCS_PARELLEL BIT(12)
47 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
48 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
49 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
50 #define KSZPHY_INTCS_LINK_UP BIT(8)
51 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
52 KSZPHY_INTCS_LINK_DOWN)
53
54 /* PHY Control 1 */
55 #define MII_KSZPHY_CTRL_1 0x1e
56
57 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
58 #define MII_KSZPHY_CTRL_2 0x1f
59 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
60 /* bitmap of PHY register to set interrupt mode */
61 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
62 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
63
64 /* Write/read to/from extended registers */
65 #define MII_KSZPHY_EXTREG 0x0b
66 #define KSZPHY_EXTREG_WRITE 0x8000
67
68 #define MII_KSZPHY_EXTREG_WRITE 0x0c
69 #define MII_KSZPHY_EXTREG_READ 0x0d
70
71 /* Extended registers */
72 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
73 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
74 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
75
76 #define PS_TO_REG 200
77
78 struct kszphy_hw_stat {
79 const char *string;
80 u8 reg;
81 u8 bits;
82 };
83
84 static struct kszphy_hw_stat kszphy_hw_stats[] = {
85 { "phy_receive_errors", 21, 16},
86 { "phy_idle_errors", 10, 8 },
87 };
88
89 struct kszphy_type {
90 u32 led_mode_reg;
91 u16 interrupt_level_mask;
92 bool has_broadcast_disable;
93 bool has_nand_tree_disable;
94 bool has_rmii_ref_clk_sel;
95 };
96
97 struct kszphy_priv {
98 const struct kszphy_type *type;
99 int led_mode;
100 bool rmii_ref_clk_sel;
101 bool rmii_ref_clk_sel_val;
102 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
103 };
104
105 static const struct kszphy_type ksz8021_type = {
106 .led_mode_reg = MII_KSZPHY_CTRL_2,
107 .has_broadcast_disable = true,
108 .has_nand_tree_disable = true,
109 .has_rmii_ref_clk_sel = true,
110 };
111
112 static const struct kszphy_type ksz8041_type = {
113 .led_mode_reg = MII_KSZPHY_CTRL_1,
114 };
115
116 static const struct kszphy_type ksz8051_type = {
117 .led_mode_reg = MII_KSZPHY_CTRL_2,
118 .has_nand_tree_disable = true,
119 };
120
121 static const struct kszphy_type ksz8081_type = {
122 .led_mode_reg = MII_KSZPHY_CTRL_2,
123 .has_broadcast_disable = true,
124 .has_nand_tree_disable = true,
125 .has_rmii_ref_clk_sel = true,
126 };
127
128 static const struct kszphy_type ks8737_type = {
129 .interrupt_level_mask = BIT(14),
130 };
131
132 static const struct kszphy_type ksz9021_type = {
133 .interrupt_level_mask = BIT(14),
134 };
135
136 static int kszphy_extended_write(struct phy_device *phydev,
137 u32 regnum, u16 val)
138 {
139 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
140 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
141 }
142
143 static int kszphy_extended_read(struct phy_device *phydev,
144 u32 regnum)
145 {
146 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
147 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
148 }
149
150 static int kszphy_ack_interrupt(struct phy_device *phydev)
151 {
152 /* bit[7..0] int status, which is a read and clear register. */
153 int rc;
154
155 rc = phy_read(phydev, MII_KSZPHY_INTCS);
156
157 return (rc < 0) ? rc : 0;
158 }
159
160 static int kszphy_config_intr(struct phy_device *phydev)
161 {
162 const struct kszphy_type *type = phydev->drv->driver_data;
163 int temp;
164 u16 mask;
165
166 if (type && type->interrupt_level_mask)
167 mask = type->interrupt_level_mask;
168 else
169 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
170
171 /* set the interrupt pin active low */
172 temp = phy_read(phydev, MII_KSZPHY_CTRL);
173 if (temp < 0)
174 return temp;
175 temp &= ~mask;
176 phy_write(phydev, MII_KSZPHY_CTRL, temp);
177
178 /* enable / disable interrupts */
179 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
180 temp = KSZPHY_INTCS_ALL;
181 else
182 temp = 0;
183
184 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
185 }
186
187 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
188 {
189 int ctrl;
190
191 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
192 if (ctrl < 0)
193 return ctrl;
194
195 if (val)
196 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
197 else
198 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
199
200 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
201 }
202
203 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
204 {
205 int rc, temp, shift;
206
207 switch (reg) {
208 case MII_KSZPHY_CTRL_1:
209 shift = 14;
210 break;
211 case MII_KSZPHY_CTRL_2:
212 shift = 4;
213 break;
214 default:
215 return -EINVAL;
216 }
217
218 temp = phy_read(phydev, reg);
219 if (temp < 0) {
220 rc = temp;
221 goto out;
222 }
223
224 temp &= ~(3 << shift);
225 temp |= val << shift;
226 rc = phy_write(phydev, reg, temp);
227 out:
228 if (rc < 0)
229 phydev_err(phydev, "failed to set led mode\n");
230
231 return rc;
232 }
233
234 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
235 * unique (non-broadcast) address on a shared bus.
236 */
237 static int kszphy_broadcast_disable(struct phy_device *phydev)
238 {
239 int ret;
240
241 ret = phy_read(phydev, MII_KSZPHY_OMSO);
242 if (ret < 0)
243 goto out;
244
245 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
246 out:
247 if (ret)
248 phydev_err(phydev, "failed to disable broadcast address\n");
249
250 return ret;
251 }
252
253 static int kszphy_nand_tree_disable(struct phy_device *phydev)
254 {
255 int ret;
256
257 ret = phy_read(phydev, MII_KSZPHY_OMSO);
258 if (ret < 0)
259 goto out;
260
261 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
262 return 0;
263
264 ret = phy_write(phydev, MII_KSZPHY_OMSO,
265 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
266 out:
267 if (ret)
268 phydev_err(phydev, "failed to disable NAND tree mode\n");
269
270 return ret;
271 }
272
273 /* Some config bits need to be set again on resume, handle them here. */
274 static int kszphy_config_reset(struct phy_device *phydev)
275 {
276 struct kszphy_priv *priv = phydev->priv;
277 int ret;
278
279 if (priv->rmii_ref_clk_sel) {
280 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
281 if (ret) {
282 phydev_err(phydev,
283 "failed to set rmii reference clock\n");
284 return ret;
285 }
286 }
287
288 if (priv->led_mode >= 0)
289 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
290
291 return 0;
292 }
293
294 static int kszphy_config_init(struct phy_device *phydev)
295 {
296 struct kszphy_priv *priv = phydev->priv;
297 const struct kszphy_type *type;
298
299 if (!priv)
300 return 0;
301
302 type = priv->type;
303
304 if (type->has_broadcast_disable)
305 kszphy_broadcast_disable(phydev);
306
307 if (type->has_nand_tree_disable)
308 kszphy_nand_tree_disable(phydev);
309
310 return kszphy_config_reset(phydev);
311 }
312
313 static int ksz8041_config_init(struct phy_device *phydev)
314 {
315 struct device_node *of_node = phydev->mdio.dev.of_node;
316
317 /* Limit supported and advertised modes in fiber mode */
318 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
319 phydev->dev_flags |= MICREL_PHY_FXEN;
320 phydev->supported &= SUPPORTED_100baseT_Full |
321 SUPPORTED_100baseT_Half;
322 phydev->supported |= SUPPORTED_FIBRE;
323 phydev->advertising &= ADVERTISED_100baseT_Full |
324 ADVERTISED_100baseT_Half;
325 phydev->advertising |= ADVERTISED_FIBRE;
326 phydev->autoneg = AUTONEG_DISABLE;
327 }
328
329 return kszphy_config_init(phydev);
330 }
331
332 static int ksz8041_config_aneg(struct phy_device *phydev)
333 {
334 /* Skip auto-negotiation in fiber mode */
335 if (phydev->dev_flags & MICREL_PHY_FXEN) {
336 phydev->speed = SPEED_100;
337 return 0;
338 }
339
340 return genphy_config_aneg(phydev);
341 }
342
343 static int ksz8061_config_init(struct phy_device *phydev)
344 {
345 int ret;
346
347 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
348 if (ret)
349 return ret;
350
351 return kszphy_config_init(phydev);
352 }
353
354 static int ksz9021_load_values_from_of(struct phy_device *phydev,
355 const struct device_node *of_node,
356 u16 reg,
357 const char *field1, const char *field2,
358 const char *field3, const char *field4)
359 {
360 int val1 = -1;
361 int val2 = -2;
362 int val3 = -3;
363 int val4 = -4;
364 int newval;
365 int matches = 0;
366
367 if (!of_property_read_u32(of_node, field1, &val1))
368 matches++;
369
370 if (!of_property_read_u32(of_node, field2, &val2))
371 matches++;
372
373 if (!of_property_read_u32(of_node, field3, &val3))
374 matches++;
375
376 if (!of_property_read_u32(of_node, field4, &val4))
377 matches++;
378
379 if (!matches)
380 return 0;
381
382 if (matches < 4)
383 newval = kszphy_extended_read(phydev, reg);
384 else
385 newval = 0;
386
387 if (val1 != -1)
388 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
389
390 if (val2 != -2)
391 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
392
393 if (val3 != -3)
394 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
395
396 if (val4 != -4)
397 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
398
399 return kszphy_extended_write(phydev, reg, newval);
400 }
401
402 static int ksz9021_config_init(struct phy_device *phydev)
403 {
404 const struct device *dev = &phydev->mdio.dev;
405 const struct device_node *of_node = dev->of_node;
406 const struct device *dev_walker;
407
408 /* The Micrel driver has a deprecated option to place phy OF
409 * properties in the MAC node. Walk up the tree of devices to
410 * find a device with an OF node.
411 */
412 dev_walker = &phydev->mdio.dev;
413 do {
414 of_node = dev_walker->of_node;
415 dev_walker = dev_walker->parent;
416
417 } while (!of_node && dev_walker);
418
419 if (of_node) {
420 ksz9021_load_values_from_of(phydev, of_node,
421 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
422 "txen-skew-ps", "txc-skew-ps",
423 "rxdv-skew-ps", "rxc-skew-ps");
424 ksz9021_load_values_from_of(phydev, of_node,
425 MII_KSZPHY_RX_DATA_PAD_SKEW,
426 "rxd0-skew-ps", "rxd1-skew-ps",
427 "rxd2-skew-ps", "rxd3-skew-ps");
428 ksz9021_load_values_from_of(phydev, of_node,
429 MII_KSZPHY_TX_DATA_PAD_SKEW,
430 "txd0-skew-ps", "txd1-skew-ps",
431 "txd2-skew-ps", "txd3-skew-ps");
432 }
433 return 0;
434 }
435
436 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
437 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
438 #define OP_DATA 1
439 #define KSZ9031_PS_TO_REG 60
440
441 /* Extended registers */
442 /* MMD Address 0x0 */
443 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
444 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
445
446 /* MMD Address 0x2 */
447 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
448 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
449 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
450 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
451
452 /* MMD Address 0x1C */
453 #define MII_KSZ9031RN_EDPD 0x23
454 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
455
456 static int ksz9031_extended_write(struct phy_device *phydev,
457 u8 mode, u32 dev_addr, u32 regnum, u16 val)
458 {
459 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
460 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
461 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
462 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
463 }
464
465 static int ksz9031_extended_read(struct phy_device *phydev,
466 u8 mode, u32 dev_addr, u32 regnum)
467 {
468 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
469 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
470 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
471 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
472 }
473
474 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
475 const struct device_node *of_node,
476 u16 reg, size_t field_sz,
477 const char *field[], u8 numfields)
478 {
479 int val[4] = {-1, -2, -3, -4};
480 int matches = 0;
481 u16 mask;
482 u16 maxval;
483 u16 newval;
484 int i;
485
486 for (i = 0; i < numfields; i++)
487 if (!of_property_read_u32(of_node, field[i], val + i))
488 matches++;
489
490 if (!matches)
491 return 0;
492
493 if (matches < numfields)
494 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
495 else
496 newval = 0;
497
498 maxval = (field_sz == 4) ? 0xf : 0x1f;
499 for (i = 0; i < numfields; i++)
500 if (val[i] != -(i + 1)) {
501 mask = 0xffff;
502 mask ^= maxval << (field_sz * i);
503 newval = (newval & mask) |
504 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
505 << (field_sz * i));
506 }
507
508 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
509 }
510
511 /* Center KSZ9031RNX FLP timing at 16ms. */
512 static int ksz9031_center_flp_timing(struct phy_device *phydev)
513 {
514 int result;
515
516 result = ksz9031_extended_write(phydev, OP_DATA, 0,
517 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
518 if (result)
519 return result;
520
521 result = ksz9031_extended_write(phydev, OP_DATA, 0,
522 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
523 if (result)
524 return result;
525
526 return genphy_restart_aneg(phydev);
527 }
528
529 /* Enable energy-detect power-down mode */
530 static int ksz9031_enable_edpd(struct phy_device *phydev)
531 {
532 int reg;
533
534 reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
535 if (reg < 0)
536 return reg;
537 return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
538 reg | MII_KSZ9031RN_EDPD_ENABLE);
539 }
540
541 static int ksz9031_config_init(struct phy_device *phydev)
542 {
543 const struct device *dev = &phydev->mdio.dev;
544 const struct device_node *of_node = dev->of_node;
545 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
546 static const char *rx_data_skews[4] = {
547 "rxd0-skew-ps", "rxd1-skew-ps",
548 "rxd2-skew-ps", "rxd3-skew-ps"
549 };
550 static const char *tx_data_skews[4] = {
551 "txd0-skew-ps", "txd1-skew-ps",
552 "txd2-skew-ps", "txd3-skew-ps"
553 };
554 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
555 const struct device *dev_walker;
556 int result;
557
558 result = ksz9031_enable_edpd(phydev);
559 if (result < 0)
560 return result;
561
562 /* The Micrel driver has a deprecated option to place phy OF
563 * properties in the MAC node. Walk up the tree of devices to
564 * find a device with an OF node.
565 */
566 dev_walker = &phydev->mdio.dev;
567 do {
568 of_node = dev_walker->of_node;
569 dev_walker = dev_walker->parent;
570 } while (!of_node && dev_walker);
571
572 if (of_node) {
573 ksz9031_of_load_skew_values(phydev, of_node,
574 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
575 clk_skews, 2);
576
577 ksz9031_of_load_skew_values(phydev, of_node,
578 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
579 control_skews, 2);
580
581 ksz9031_of_load_skew_values(phydev, of_node,
582 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
583 rx_data_skews, 4);
584
585 ksz9031_of_load_skew_values(phydev, of_node,
586 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
587 tx_data_skews, 4);
588
589 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
590 * When the device links in the 1000BASE-T slave mode only,
591 * the optional 125MHz reference output clock (CLK125_NDO)
592 * has wide duty cycle variation.
593 *
594 * The optional CLK125_NDO clock does not meet the RGMII
595 * 45/55 percent (min/max) duty cycle requirement and therefore
596 * cannot be used directly by the MAC side for clocking
597 * applications that have setup/hold time requirements on
598 * rising and falling clock edges.
599 *
600 * Workaround:
601 * Force the phy to be the master to receive a stable clock
602 * which meets the duty cycle requirement.
603 */
604 if (of_property_read_bool(of_node, "micrel,force-master")) {
605 result = phy_read(phydev, MII_CTRL1000);
606 if (result < 0)
607 goto err_force_master;
608
609 /* enable master mode, config & prefer master */
610 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
611 result = phy_write(phydev, MII_CTRL1000, result);
612 if (result < 0)
613 goto err_force_master;
614 }
615 }
616
617 return ksz9031_center_flp_timing(phydev);
618
619 err_force_master:
620 phydev_err(phydev, "failed to force the phy to master mode\n");
621 return result;
622 }
623
624 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
625 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
626 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
627 static int ksz8873mll_read_status(struct phy_device *phydev)
628 {
629 int regval;
630
631 /* dummy read */
632 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
633
634 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
635
636 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
637 phydev->duplex = DUPLEX_HALF;
638 else
639 phydev->duplex = DUPLEX_FULL;
640
641 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
642 phydev->speed = SPEED_10;
643 else
644 phydev->speed = SPEED_100;
645
646 phydev->link = 1;
647 phydev->pause = phydev->asym_pause = 0;
648
649 return 0;
650 }
651
652 static int ksz9031_read_status(struct phy_device *phydev)
653 {
654 int err;
655 int regval;
656
657 err = genphy_read_status(phydev);
658 if (err)
659 return err;
660
661 /* Make sure the PHY is not broken. Read idle error count,
662 * and reset the PHY if it is maxed out.
663 */
664 regval = phy_read(phydev, MII_STAT1000);
665 if ((regval & 0xFF) == 0xFF) {
666 phy_init_hw(phydev);
667 phydev->link = 0;
668 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
669 phydev->drv->config_intr(phydev);
670 return genphy_config_aneg(phydev);
671 }
672
673 return 0;
674 }
675
676 static int ksz8873mll_config_aneg(struct phy_device *phydev)
677 {
678 return 0;
679 }
680
681 static int kszphy_get_sset_count(struct phy_device *phydev)
682 {
683 return ARRAY_SIZE(kszphy_hw_stats);
684 }
685
686 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
687 {
688 int i;
689
690 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
691 strlcpy(data + i * ETH_GSTRING_LEN,
692 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
693 }
694 }
695
696 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
697 {
698 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
699 struct kszphy_priv *priv = phydev->priv;
700 int val;
701 u64 ret;
702
703 val = phy_read(phydev, stat.reg);
704 if (val < 0) {
705 ret = U64_MAX;
706 } else {
707 val = val & ((1 << stat.bits) - 1);
708 priv->stats[i] += val;
709 ret = priv->stats[i];
710 }
711
712 return ret;
713 }
714
715 static void kszphy_get_stats(struct phy_device *phydev,
716 struct ethtool_stats *stats, u64 *data)
717 {
718 int i;
719
720 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
721 data[i] = kszphy_get_stat(phydev, i);
722 }
723
724 static int kszphy_suspend(struct phy_device *phydev)
725 {
726 /* Disable PHY Interrupts */
727 if (phy_interrupt_is_valid(phydev)) {
728 phydev->interrupts = PHY_INTERRUPT_DISABLED;
729 if (phydev->drv->config_intr)
730 phydev->drv->config_intr(phydev);
731 }
732
733 return genphy_suspend(phydev);
734 }
735
736 static int kszphy_resume(struct phy_device *phydev)
737 {
738 int ret;
739
740 genphy_resume(phydev);
741
742 /* After switching from power-down to normal mode, an internal global
743 * reset is automatically generated. Wait a minimum of 1 ms before
744 * read/write access to the PHY registers.
745 */
746 usleep_range(1000, 2000);
747
748 ret = kszphy_config_reset(phydev);
749 if (ret)
750 return ret;
751
752 /* Enable PHY Interrupts */
753 if (phy_interrupt_is_valid(phydev)) {
754 phydev->interrupts = PHY_INTERRUPT_ENABLED;
755 if (phydev->drv->config_intr)
756 phydev->drv->config_intr(phydev);
757 }
758
759 return 0;
760 }
761
762 static int kszphy_probe(struct phy_device *phydev)
763 {
764 const struct kszphy_type *type = phydev->drv->driver_data;
765 const struct device_node *np = phydev->mdio.dev.of_node;
766 struct kszphy_priv *priv;
767 struct clk *clk;
768 int ret;
769
770 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
771 if (!priv)
772 return -ENOMEM;
773
774 phydev->priv = priv;
775
776 priv->type = type;
777
778 if (type->led_mode_reg) {
779 ret = of_property_read_u32(np, "micrel,led-mode",
780 &priv->led_mode);
781 if (ret)
782 priv->led_mode = -1;
783
784 if (priv->led_mode > 3) {
785 phydev_err(phydev, "invalid led mode: 0x%02x\n",
786 priv->led_mode);
787 priv->led_mode = -1;
788 }
789 } else {
790 priv->led_mode = -1;
791 }
792
793 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
794 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
795 if (!IS_ERR_OR_NULL(clk)) {
796 unsigned long rate = clk_get_rate(clk);
797 bool rmii_ref_clk_sel_25_mhz;
798
799 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
800 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
801 "micrel,rmii-reference-clock-select-25-mhz");
802
803 if (rate > 24500000 && rate < 25500000) {
804 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
805 } else if (rate > 49500000 && rate < 50500000) {
806 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
807 } else {
808 phydev_err(phydev, "Clock rate out of range: %ld\n",
809 rate);
810 return -EINVAL;
811 }
812 }
813
814 /* Support legacy board-file configuration */
815 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
816 priv->rmii_ref_clk_sel = true;
817 priv->rmii_ref_clk_sel_val = true;
818 }
819
820 return 0;
821 }
822
823 static struct phy_driver ksphy_driver[] = {
824 {
825 .phy_id = PHY_ID_KS8737,
826 .phy_id_mask = MICREL_PHY_ID_MASK,
827 .name = "Micrel KS8737",
828 .features = PHY_BASIC_FEATURES,
829 .flags = PHY_HAS_INTERRUPT,
830 .driver_data = &ks8737_type,
831 .config_init = kszphy_config_init,
832 .ack_interrupt = kszphy_ack_interrupt,
833 .config_intr = kszphy_config_intr,
834 .suspend = genphy_suspend,
835 .resume = genphy_resume,
836 }, {
837 .phy_id = PHY_ID_KSZ8021,
838 .phy_id_mask = 0x00ffffff,
839 .name = "Micrel KSZ8021 or KSZ8031",
840 .features = PHY_BASIC_FEATURES,
841 .flags = PHY_HAS_INTERRUPT,
842 .driver_data = &ksz8021_type,
843 .probe = kszphy_probe,
844 .config_init = kszphy_config_init,
845 .ack_interrupt = kszphy_ack_interrupt,
846 .config_intr = kszphy_config_intr,
847 .get_sset_count = kszphy_get_sset_count,
848 .get_strings = kszphy_get_strings,
849 .get_stats = kszphy_get_stats,
850 .suspend = genphy_suspend,
851 .resume = genphy_resume,
852 }, {
853 .phy_id = PHY_ID_KSZ8031,
854 .phy_id_mask = 0x00ffffff,
855 .name = "Micrel KSZ8031",
856 .features = PHY_BASIC_FEATURES,
857 .flags = PHY_HAS_INTERRUPT,
858 .driver_data = &ksz8021_type,
859 .probe = kszphy_probe,
860 .config_init = kszphy_config_init,
861 .ack_interrupt = kszphy_ack_interrupt,
862 .config_intr = kszphy_config_intr,
863 .get_sset_count = kszphy_get_sset_count,
864 .get_strings = kszphy_get_strings,
865 .get_stats = kszphy_get_stats,
866 .suspend = genphy_suspend,
867 .resume = genphy_resume,
868 }, {
869 .phy_id = PHY_ID_KSZ8041,
870 .phy_id_mask = MICREL_PHY_ID_MASK,
871 .name = "Micrel KSZ8041",
872 .features = PHY_BASIC_FEATURES,
873 .flags = PHY_HAS_INTERRUPT,
874 .driver_data = &ksz8041_type,
875 .probe = kszphy_probe,
876 .config_init = ksz8041_config_init,
877 .config_aneg = ksz8041_config_aneg,
878 .ack_interrupt = kszphy_ack_interrupt,
879 .config_intr = kszphy_config_intr,
880 .get_sset_count = kszphy_get_sset_count,
881 .get_strings = kszphy_get_strings,
882 .get_stats = kszphy_get_stats,
883 .suspend = genphy_suspend,
884 .resume = genphy_resume,
885 }, {
886 .phy_id = PHY_ID_KSZ8041RNLI,
887 .phy_id_mask = MICREL_PHY_ID_MASK,
888 .name = "Micrel KSZ8041RNLI",
889 .features = PHY_BASIC_FEATURES,
890 .flags = PHY_HAS_INTERRUPT,
891 .driver_data = &ksz8041_type,
892 .probe = kszphy_probe,
893 .config_init = kszphy_config_init,
894 .ack_interrupt = kszphy_ack_interrupt,
895 .config_intr = kszphy_config_intr,
896 .get_sset_count = kszphy_get_sset_count,
897 .get_strings = kszphy_get_strings,
898 .get_stats = kszphy_get_stats,
899 .suspend = genphy_suspend,
900 .resume = genphy_resume,
901 }, {
902 .phy_id = PHY_ID_KSZ8051,
903 .phy_id_mask = MICREL_PHY_ID_MASK,
904 .name = "Micrel KSZ8051",
905 .features = PHY_BASIC_FEATURES,
906 .flags = PHY_HAS_INTERRUPT,
907 .driver_data = &ksz8051_type,
908 .probe = kszphy_probe,
909 .config_init = kszphy_config_init,
910 .ack_interrupt = kszphy_ack_interrupt,
911 .config_intr = kszphy_config_intr,
912 .get_sset_count = kszphy_get_sset_count,
913 .get_strings = kszphy_get_strings,
914 .get_stats = kszphy_get_stats,
915 .suspend = genphy_suspend,
916 .resume = genphy_resume,
917 }, {
918 .phy_id = PHY_ID_KSZ8001,
919 .name = "Micrel KSZ8001 or KS8721",
920 .phy_id_mask = 0x00fffffc,
921 .features = PHY_BASIC_FEATURES,
922 .flags = PHY_HAS_INTERRUPT,
923 .driver_data = &ksz8041_type,
924 .probe = kszphy_probe,
925 .config_init = kszphy_config_init,
926 .ack_interrupt = kszphy_ack_interrupt,
927 .config_intr = kszphy_config_intr,
928 .get_sset_count = kszphy_get_sset_count,
929 .get_strings = kszphy_get_strings,
930 .get_stats = kszphy_get_stats,
931 .suspend = genphy_suspend,
932 .resume = genphy_resume,
933 }, {
934 .phy_id = PHY_ID_KSZ8081,
935 .name = "Micrel KSZ8081 or KSZ8091",
936 .phy_id_mask = MICREL_PHY_ID_MASK,
937 .features = PHY_BASIC_FEATURES,
938 .flags = PHY_HAS_INTERRUPT,
939 .driver_data = &ksz8081_type,
940 .probe = kszphy_probe,
941 .config_init = kszphy_config_init,
942 .ack_interrupt = kszphy_ack_interrupt,
943 .config_intr = kszphy_config_intr,
944 .get_sset_count = kszphy_get_sset_count,
945 .get_strings = kszphy_get_strings,
946 .get_stats = kszphy_get_stats,
947 .suspend = kszphy_suspend,
948 .resume = kszphy_resume,
949 }, {
950 .phy_id = PHY_ID_KSZ8061,
951 .name = "Micrel KSZ8061",
952 .phy_id_mask = MICREL_PHY_ID_MASK,
953 .features = PHY_BASIC_FEATURES,
954 .flags = PHY_HAS_INTERRUPT,
955 .config_init = ksz8061_config_init,
956 .ack_interrupt = kszphy_ack_interrupt,
957 .config_intr = kszphy_config_intr,
958 .suspend = genphy_suspend,
959 .resume = genphy_resume,
960 }, {
961 .phy_id = PHY_ID_KSZ9021,
962 .phy_id_mask = 0x000ffffe,
963 .name = "Micrel KSZ9021 Gigabit PHY",
964 .features = PHY_GBIT_FEATURES,
965 .flags = PHY_HAS_INTERRUPT,
966 .driver_data = &ksz9021_type,
967 .probe = kszphy_probe,
968 .config_init = ksz9021_config_init,
969 .ack_interrupt = kszphy_ack_interrupt,
970 .config_intr = kszphy_config_intr,
971 .get_sset_count = kszphy_get_sset_count,
972 .get_strings = kszphy_get_strings,
973 .get_stats = kszphy_get_stats,
974 .suspend = genphy_suspend,
975 .resume = genphy_resume,
976 .read_mmd = genphy_read_mmd_unsupported,
977 .write_mmd = genphy_write_mmd_unsupported,
978 }, {
979 .phy_id = PHY_ID_KSZ9031,
980 .phy_id_mask = MICREL_PHY_ID_MASK,
981 .name = "Micrel KSZ9031 Gigabit PHY",
982 .features = PHY_GBIT_FEATURES,
983 .flags = PHY_HAS_INTERRUPT,
984 .driver_data = &ksz9021_type,
985 .probe = kszphy_probe,
986 .config_init = ksz9031_config_init,
987 .soft_reset = genphy_soft_reset,
988 .read_status = ksz9031_read_status,
989 .ack_interrupt = kszphy_ack_interrupt,
990 .config_intr = kszphy_config_intr,
991 .get_sset_count = kszphy_get_sset_count,
992 .get_strings = kszphy_get_strings,
993 .get_stats = kszphy_get_stats,
994 .suspend = genphy_suspend,
995 .resume = kszphy_resume,
996 }, {
997 .phy_id = PHY_ID_KSZ8873MLL,
998 .phy_id_mask = MICREL_PHY_ID_MASK,
999 .name = "Micrel KSZ8873MLL Switch",
1000 .config_init = kszphy_config_init,
1001 .config_aneg = ksz8873mll_config_aneg,
1002 .read_status = ksz8873mll_read_status,
1003 .suspend = genphy_suspend,
1004 .resume = genphy_resume,
1005 }, {
1006 .phy_id = PHY_ID_KSZ886X,
1007 .phy_id_mask = MICREL_PHY_ID_MASK,
1008 .name = "Micrel KSZ886X Switch",
1009 .features = PHY_BASIC_FEATURES,
1010 .flags = PHY_HAS_INTERRUPT,
1011 .config_init = kszphy_config_init,
1012 .suspend = genphy_suspend,
1013 .resume = genphy_resume,
1014 }, {
1015 .phy_id = PHY_ID_KSZ8795,
1016 .phy_id_mask = MICREL_PHY_ID_MASK,
1017 .name = "Micrel KSZ8795",
1018 .features = PHY_BASIC_FEATURES,
1019 .flags = PHY_HAS_INTERRUPT,
1020 .config_init = kszphy_config_init,
1021 .config_aneg = ksz8873mll_config_aneg,
1022 .read_status = ksz8873mll_read_status,
1023 .suspend = genphy_suspend,
1024 .resume = genphy_resume,
1025 }, {
1026 .phy_id = PHY_ID_KSZ9477,
1027 .phy_id_mask = MICREL_PHY_ID_MASK,
1028 .name = "Microchip KSZ9477",
1029 .features = PHY_GBIT_FEATURES,
1030 .config_init = kszphy_config_init,
1031 .suspend = genphy_suspend,
1032 .resume = genphy_resume,
1033 } };
1034
1035 module_phy_driver(ksphy_driver);
1036
1037 MODULE_DESCRIPTION("Micrel PHY driver");
1038 MODULE_AUTHOR("David J. Choi");
1039 MODULE_LICENSE("GPL");
1040
1041 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1042 { PHY_ID_KSZ9021, 0x000ffffe },
1043 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1044 { PHY_ID_KSZ8001, 0x00fffffc },
1045 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1046 { PHY_ID_KSZ8021, 0x00ffffff },
1047 { PHY_ID_KSZ8031, 0x00ffffff },
1048 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1049 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1050 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1051 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1052 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1053 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1054 { }
1055 };
1056
1057 MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Linux with added FPC-III support