Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / usb / r8152.c
blob1b1ec4197830040b1ddd688544e8f8488d1fee1d
1 /*
2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
8 */
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
31 /* Information for net-next */
32 #define NETNEXT_VERSION "09"
34 /* Information for net */
35 #define NET_VERSION "9"
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
42 #define R8152_PHY_ID 32
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_TEREDO_WAKE_BASE 0xc0c4
55 #define PLA_MAR 0xcd00
56 #define PLA_BACKUP 0xd000
57 #define PAL_BDC_CR 0xd1a0
58 #define PLA_TEREDO_TIMER 0xd2cc
59 #define PLA_REALWOW_TIMER 0xd2e8
60 #define PLA_EFUSE_DATA 0xdd00
61 #define PLA_EFUSE_CMD 0xdd02
62 #define PLA_LEDSEL 0xdd90
63 #define PLA_LED_FEATURE 0xdd92
64 #define PLA_PHYAR 0xde00
65 #define PLA_BOOT_CTRL 0xe004
66 #define PLA_GPHY_INTR_IMR 0xe022
67 #define PLA_EEE_CR 0xe040
68 #define PLA_EEEP_CR 0xe080
69 #define PLA_MAC_PWR_CTRL 0xe0c0
70 #define PLA_MAC_PWR_CTRL2 0xe0ca
71 #define PLA_MAC_PWR_CTRL3 0xe0cc
72 #define PLA_MAC_PWR_CTRL4 0xe0ce
73 #define PLA_WDT6_CTRL 0xe428
74 #define PLA_TCR0 0xe610
75 #define PLA_TCR1 0xe612
76 #define PLA_MTPS 0xe615
77 #define PLA_TXFIFO_CTRL 0xe618
78 #define PLA_RSTTALLY 0xe800
79 #define PLA_CR 0xe813
80 #define PLA_CRWECR 0xe81c
81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5 0xe822
84 #define PLA_PHY_PWR 0xe84c
85 #define PLA_OOB_CTRL 0xe84f
86 #define PLA_CPCR 0xe854
87 #define PLA_MISC_0 0xe858
88 #define PLA_MISC_1 0xe85a
89 #define PLA_OCP_GPHY_BASE 0xe86c
90 #define PLA_TALLYCNT 0xe890
91 #define PLA_SFF_STS_7 0xe8de
92 #define PLA_PHYSTATUS 0xe908
93 #define PLA_BP_BA 0xfc26
94 #define PLA_BP_0 0xfc28
95 #define PLA_BP_1 0xfc2a
96 #define PLA_BP_2 0xfc2c
97 #define PLA_BP_3 0xfc2e
98 #define PLA_BP_4 0xfc30
99 #define PLA_BP_5 0xfc32
100 #define PLA_BP_6 0xfc34
101 #define PLA_BP_7 0xfc36
102 #define PLA_BP_EN 0xfc38
104 #define USB_USB2PHY 0xb41e
105 #define USB_SSPHYLINK2 0xb428
106 #define USB_U2P3_CTRL 0xb460
107 #define USB_CSR_DUMMY1 0xb464
108 #define USB_CSR_DUMMY2 0xb466
109 #define USB_DEV_STAT 0xb808
110 #define USB_CONNECT_TIMER 0xcbf8
111 #define USB_MSC_TIMER 0xcbfc
112 #define USB_BURST_SIZE 0xcfc0
113 #define USB_LPM_CONFIG 0xcfd8
114 #define USB_USB_CTRL 0xd406
115 #define USB_PHY_CTRL 0xd408
116 #define USB_TX_AGG 0xd40a
117 #define USB_RX_BUF_TH 0xd40c
118 #define USB_USB_TIMER 0xd428
119 #define USB_RX_EARLY_TIMEOUT 0xd42c
120 #define USB_RX_EARLY_SIZE 0xd42e
121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
123 #define USB_TX_DMA 0xd434
124 #define USB_UPT_RXDMA_OWN 0xd437
125 #define USB_TOLERANCE 0xd490
126 #define USB_LPM_CTRL 0xd41a
127 #define USB_BMU_RESET 0xd4b0
128 #define USB_U1U2_TIMER 0xd4da
129 #define USB_UPS_CTRL 0xd800
130 #define USB_POWER_CUT 0xd80a
131 #define USB_MISC_0 0xd81a
132 #define USB_AFE_CTRL2 0xd824
133 #define USB_UPS_CFG 0xd842
134 #define USB_UPS_FLAGS 0xd848
135 #define USB_WDT11_CTRL 0xe43c
136 #define USB_BP_BA 0xfc26
137 #define USB_BP_0 0xfc28
138 #define USB_BP_1 0xfc2a
139 #define USB_BP_2 0xfc2c
140 #define USB_BP_3 0xfc2e
141 #define USB_BP_4 0xfc30
142 #define USB_BP_5 0xfc32
143 #define USB_BP_6 0xfc34
144 #define USB_BP_7 0xfc36
145 #define USB_BP_EN 0xfc38
146 #define USB_BP_8 0xfc38
147 #define USB_BP_9 0xfc3a
148 #define USB_BP_10 0xfc3c
149 #define USB_BP_11 0xfc3e
150 #define USB_BP_12 0xfc40
151 #define USB_BP_13 0xfc42
152 #define USB_BP_14 0xfc44
153 #define USB_BP_15 0xfc46
154 #define USB_BP2_EN 0xfc48
156 /* OCP Registers */
157 #define OCP_ALDPS_CONFIG 0x2010
158 #define OCP_EEE_CONFIG1 0x2080
159 #define OCP_EEE_CONFIG2 0x2092
160 #define OCP_EEE_CONFIG3 0x2094
161 #define OCP_BASE_MII 0xa400
162 #define OCP_EEE_AR 0xa41a
163 #define OCP_EEE_DATA 0xa41c
164 #define OCP_PHY_STATUS 0xa420
165 #define OCP_NCTL_CFG 0xa42c
166 #define OCP_POWER_CFG 0xa430
167 #define OCP_EEE_CFG 0xa432
168 #define OCP_SRAM_ADDR 0xa436
169 #define OCP_SRAM_DATA 0xa438
170 #define OCP_DOWN_SPEED 0xa442
171 #define OCP_EEE_ABLE 0xa5c4
172 #define OCP_EEE_ADV 0xa5d0
173 #define OCP_EEE_LPABLE 0xa5d2
174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
175 #define OCP_PHY_PATCH_STAT 0xb800
176 #define OCP_PHY_PATCH_CMD 0xb820
177 #define OCP_ADC_IOFFSET 0xbcfc
178 #define OCP_ADC_CFG 0xbc06
179 #define OCP_SYSCLK_CFG 0xc416
181 /* SRAM Register */
182 #define SRAM_GREEN_CFG 0x8011
183 #define SRAM_LPF_CFG 0x8012
184 #define SRAM_10M_AMP1 0x8080
185 #define SRAM_10M_AMP2 0x8082
186 #define SRAM_IMPEDANCE 0x8084
188 /* PLA_RCR */
189 #define RCR_AAP 0x00000001
190 #define RCR_APM 0x00000002
191 #define RCR_AM 0x00000004
192 #define RCR_AB 0x00000008
193 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
195 /* PLA_RXFIFO_CTRL0 */
196 #define RXFIFO_THR1_NORMAL 0x00080002
197 #define RXFIFO_THR1_OOB 0x01800003
199 /* PLA_RXFIFO_CTRL1 */
200 #define RXFIFO_THR2_FULL 0x00000060
201 #define RXFIFO_THR2_HIGH 0x00000038
202 #define RXFIFO_THR2_OOB 0x0000004a
203 #define RXFIFO_THR2_NORMAL 0x00a0
205 /* PLA_RXFIFO_CTRL2 */
206 #define RXFIFO_THR3_FULL 0x00000078
207 #define RXFIFO_THR3_HIGH 0x00000048
208 #define RXFIFO_THR3_OOB 0x0000005a
209 #define RXFIFO_THR3_NORMAL 0x0110
211 /* PLA_TXFIFO_CTRL */
212 #define TXFIFO_THR_NORMAL 0x00400008
213 #define TXFIFO_THR_NORMAL2 0x01000008
215 /* PLA_DMY_REG0 */
216 #define ECM_ALDPS 0x0002
218 /* PLA_FMC */
219 #define FMC_FCR_MCU_EN 0x0001
221 /* PLA_EEEP_CR */
222 #define EEEP_CR_EEEP_TX 0x0002
224 /* PLA_WDT6_CTRL */
225 #define WDT6_SET_MODE 0x0010
227 /* PLA_TCR0 */
228 #define TCR0_TX_EMPTY 0x0800
229 #define TCR0_AUTO_FIFO 0x0080
231 /* PLA_TCR1 */
232 #define VERSION_MASK 0x7cf0
234 /* PLA_MTPS */
235 #define MTPS_JUMBO (12 * 1024 / 64)
236 #define MTPS_DEFAULT (6 * 1024 / 64)
238 /* PLA_RSTTALLY */
239 #define TALLY_RESET 0x0001
241 /* PLA_CR */
242 #define CR_RST 0x10
243 #define CR_RE 0x08
244 #define CR_TE 0x04
246 /* PLA_CRWECR */
247 #define CRWECR_NORAML 0x00
248 #define CRWECR_CONFIG 0xc0
250 /* PLA_OOB_CTRL */
251 #define NOW_IS_OOB 0x80
252 #define TXFIFO_EMPTY 0x20
253 #define RXFIFO_EMPTY 0x10
254 #define LINK_LIST_READY 0x02
255 #define DIS_MCU_CLROOB 0x01
256 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
258 /* PLA_MISC_1 */
259 #define RXDY_GATED_EN 0x0008
261 /* PLA_SFF_STS_7 */
262 #define RE_INIT_LL 0x8000
263 #define MCU_BORW_EN 0x4000
265 /* PLA_CPCR */
266 #define CPCR_RX_VLAN 0x0040
268 /* PLA_CFG_WOL */
269 #define MAGIC_EN 0x0001
271 /* PLA_TEREDO_CFG */
272 #define TEREDO_SEL 0x8000
273 #define TEREDO_WAKE_MASK 0x7f00
274 #define TEREDO_RS_EVENT_MASK 0x00fe
275 #define OOB_TEREDO_EN 0x0001
277 /* PAL_BDC_CR */
278 #define ALDPS_PROXY_MODE 0x0001
280 /* PLA_EFUSE_CMD */
281 #define EFUSE_READ_CMD BIT(15)
282 #define EFUSE_DATA_BIT16 BIT(7)
284 /* PLA_CONFIG34 */
285 #define LINK_ON_WAKE_EN 0x0010
286 #define LINK_OFF_WAKE_EN 0x0008
288 /* PLA_CONFIG5 */
289 #define BWF_EN 0x0040
290 #define MWF_EN 0x0020
291 #define UWF_EN 0x0010
292 #define LAN_WAKE_EN 0x0002
294 /* PLA_LED_FEATURE */
295 #define LED_MODE_MASK 0x0700
297 /* PLA_PHY_PWR */
298 #define TX_10M_IDLE_EN 0x0080
299 #define PFM_PWM_SWITCH 0x0040
301 /* PLA_MAC_PWR_CTRL */
302 #define D3_CLK_GATED_EN 0x00004000
303 #define MCU_CLK_RATIO 0x07010f07
304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
305 #define ALDPS_SPDWN_RATIO 0x0f87
307 /* PLA_MAC_PWR_CTRL2 */
308 #define EEE_SPDWN_RATIO 0x8007
309 #define MAC_CLK_SPDWN_EN BIT(15)
311 /* PLA_MAC_PWR_CTRL3 */
312 #define PKT_AVAIL_SPDWN_EN 0x0100
313 #define SUSPEND_SPDWN_EN 0x0004
314 #define U1U2_SPDWN_EN 0x0002
315 #define L1_SPDWN_EN 0x0001
317 /* PLA_MAC_PWR_CTRL4 */
318 #define PWRSAVE_SPDWN_EN 0x1000
319 #define RXDV_SPDWN_EN 0x0800
320 #define TX10MIDLE_EN 0x0100
321 #define TP100_SPDWN_EN 0x0020
322 #define TP500_SPDWN_EN 0x0010
323 #define TP1000_SPDWN_EN 0x0008
324 #define EEE_SPDWN_EN 0x0001
326 /* PLA_GPHY_INTR_IMR */
327 #define GPHY_STS_MSK 0x0001
328 #define SPEED_DOWN_MSK 0x0002
329 #define SPDWN_RXDV_MSK 0x0004
330 #define SPDWN_LINKCHG_MSK 0x0008
332 /* PLA_PHYAR */
333 #define PHYAR_FLAG 0x80000000
335 /* PLA_EEE_CR */
336 #define EEE_RX_EN 0x0001
337 #define EEE_TX_EN 0x0002
339 /* PLA_BOOT_CTRL */
340 #define AUTOLOAD_DONE 0x0002
342 /* USB_USB2PHY */
343 #define USB2PHY_SUSPEND 0x0001
344 #define USB2PHY_L1 0x0002
346 /* USB_SSPHYLINK2 */
347 #define pwd_dn_scale_mask 0x3ffe
348 #define pwd_dn_scale(x) ((x) << 1)
350 /* USB_CSR_DUMMY1 */
351 #define DYNAMIC_BURST 0x0001
353 /* USB_CSR_DUMMY2 */
354 #define EP4_FULL_FC 0x0001
356 /* USB_DEV_STAT */
357 #define STAT_SPEED_MASK 0x0006
358 #define STAT_SPEED_HIGH 0x0000
359 #define STAT_SPEED_FULL 0x0002
361 /* USB_LPM_CONFIG */
362 #define LPM_U1U2_EN BIT(0)
364 /* USB_TX_AGG */
365 #define TX_AGG_MAX_THRESHOLD 0x03
367 /* USB_RX_BUF_TH */
368 #define RX_THR_SUPPER 0x0c350180
369 #define RX_THR_HIGH 0x7a120180
370 #define RX_THR_SLOW 0xffff0180
371 #define RX_THR_B 0x00010001
373 /* USB_TX_DMA */
374 #define TEST_MODE_DISABLE 0x00000001
375 #define TX_SIZE_ADJUST1 0x00000100
377 /* USB_BMU_RESET */
378 #define BMU_RESET_EP_IN 0x01
379 #define BMU_RESET_EP_OUT 0x02
381 /* USB_UPT_RXDMA_OWN */
382 #define OWN_UPDATE BIT(0)
383 #define OWN_CLEAR BIT(1)
385 /* USB_UPS_CTRL */
386 #define POWER_CUT 0x0100
388 /* USB_PM_CTRL_STATUS */
389 #define RESUME_INDICATE 0x0001
391 /* USB_USB_CTRL */
392 #define RX_AGG_DISABLE 0x0010
393 #define RX_ZERO_EN 0x0080
395 /* USB_U2P3_CTRL */
396 #define U2P3_ENABLE 0x0001
398 /* USB_POWER_CUT */
399 #define PWR_EN 0x0001
400 #define PHASE2_EN 0x0008
401 #define UPS_EN BIT(4)
402 #define USP_PREWAKE BIT(5)
404 /* USB_MISC_0 */
405 #define PCUT_STATUS 0x0001
407 /* USB_RX_EARLY_TIMEOUT */
408 #define COALESCE_SUPER 85000U
409 #define COALESCE_HIGH 250000U
410 #define COALESCE_SLOW 524280U
412 /* USB_WDT11_CTRL */
413 #define TIMER11_EN 0x0001
415 /* USB_LPM_CTRL */
416 /* bit 4 ~ 5: fifo empty boundary */
417 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
418 /* bit 2 ~ 3: LMP timer */
419 #define LPM_TIMER_MASK 0x0c
420 #define LPM_TIMER_500MS 0x04 /* 500 ms */
421 #define LPM_TIMER_500US 0x0c /* 500 us */
422 #define ROK_EXIT_LPM 0x02
424 /* USB_AFE_CTRL2 */
425 #define SEN_VAL_MASK 0xf800
426 #define SEN_VAL_NORMAL 0xa000
427 #define SEL_RXIDLE 0x0100
429 /* USB_UPS_CFG */
430 #define SAW_CNT_1MS_MASK 0x0fff
432 /* USB_UPS_FLAGS */
433 #define UPS_FLAGS_R_TUNE BIT(0)
434 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
435 #define UPS_FLAGS_250M_CKDIV BIT(2)
436 #define UPS_FLAGS_EN_ALDPS BIT(3)
437 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
438 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
439 #define ups_flags_speed(x) ((x) << 16)
440 #define UPS_FLAGS_EN_EEE BIT(20)
441 #define UPS_FLAGS_EN_500M_EEE BIT(21)
442 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
443 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
444 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
445 #define UPS_FLAGS_EN_GREEN BIT(26)
446 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
448 enum spd_duplex {
449 NWAY_10M_HALF = 1,
450 NWAY_10M_FULL,
451 NWAY_100M_HALF,
452 NWAY_100M_FULL,
453 NWAY_1000M_FULL,
454 FORCE_10M_HALF,
455 FORCE_10M_FULL,
456 FORCE_100M_HALF,
457 FORCE_100M_FULL,
460 /* OCP_ALDPS_CONFIG */
461 #define ENPWRSAVE 0x8000
462 #define ENPDNPS 0x0200
463 #define LINKENA 0x0100
464 #define DIS_SDSAVE 0x0010
466 /* OCP_PHY_STATUS */
467 #define PHY_STAT_MASK 0x0007
468 #define PHY_STAT_EXT_INIT 2
469 #define PHY_STAT_LAN_ON 3
470 #define PHY_STAT_PWRDN 5
472 /* OCP_NCTL_CFG */
473 #define PGA_RETURN_EN BIT(1)
475 /* OCP_POWER_CFG */
476 #define EEE_CLKDIV_EN 0x8000
477 #define EN_ALDPS 0x0004
478 #define EN_10M_PLLOFF 0x0001
480 /* OCP_EEE_CONFIG1 */
481 #define RG_TXLPI_MSK_HFDUP 0x8000
482 #define RG_MATCLR_EN 0x4000
483 #define EEE_10_CAP 0x2000
484 #define EEE_NWAY_EN 0x1000
485 #define TX_QUIET_EN 0x0200
486 #define RX_QUIET_EN 0x0100
487 #define sd_rise_time_mask 0x0070
488 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
489 #define RG_RXLPI_MSK_HFDUP 0x0008
490 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
492 /* OCP_EEE_CONFIG2 */
493 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
494 #define RG_DACQUIET_EN 0x0400
495 #define RG_LDVQUIET_EN 0x0200
496 #define RG_CKRSEL 0x0020
497 #define RG_EEEPRG_EN 0x0010
499 /* OCP_EEE_CONFIG3 */
500 #define fast_snr_mask 0xff80
501 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
502 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
503 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
505 /* OCP_EEE_AR */
506 /* bit[15:14] function */
507 #define FUN_ADDR 0x0000
508 #define FUN_DATA 0x4000
509 /* bit[4:0] device addr */
511 /* OCP_EEE_CFG */
512 #define CTAP_SHORT_EN 0x0040
513 #define EEE10_EN 0x0010
515 /* OCP_DOWN_SPEED */
516 #define EN_EEE_CMODE BIT(14)
517 #define EN_EEE_1000 BIT(13)
518 #define EN_EEE_100 BIT(12)
519 #define EN_10M_CLKDIV BIT(11)
520 #define EN_10M_BGOFF 0x0080
522 /* OCP_PHY_STATE */
523 #define TXDIS_STATE 0x01
524 #define ABD_STATE 0x02
526 /* OCP_PHY_PATCH_STAT */
527 #define PATCH_READY BIT(6)
529 /* OCP_PHY_PATCH_CMD */
530 #define PATCH_REQUEST BIT(4)
532 /* OCP_ADC_CFG */
533 #define CKADSEL_L 0x0100
534 #define ADC_EN 0x0080
535 #define EN_EMI_L 0x0040
537 /* OCP_SYSCLK_CFG */
538 #define clk_div_expo(x) (min(x, 5) << 8)
540 /* SRAM_GREEN_CFG */
541 #define GREEN_ETH_EN BIT(15)
542 #define R_TUNE_EN BIT(11)
544 /* SRAM_LPF_CFG */
545 #define LPF_AUTO_TUNE 0x8000
547 /* SRAM_10M_AMP1 */
548 #define GDAC_IB_UPALL 0x0008
550 /* SRAM_10M_AMP2 */
551 #define AMP_DN 0x0200
553 /* SRAM_IMPEDANCE */
554 #define RX_DRIVING_MASK 0x6000
556 /* MAC PASSTHRU */
557 #define AD_MASK 0xfee0
558 #define EFUSE 0xcfdb
559 #define PASS_THRU_MASK 0x1
561 enum rtl_register_content {
562 _1000bps = 0x10,
563 _100bps = 0x08,
564 _10bps = 0x04,
565 LINK_STATUS = 0x02,
566 FULL_DUP = 0x01,
569 #define RTL8152_MAX_TX 4
570 #define RTL8152_MAX_RX 10
571 #define INTBUFSIZE 2
572 #define TX_ALIGN 4
573 #define RX_ALIGN 8
575 #define INTR_LINK 0x0004
577 #define RTL8152_REQT_READ 0xc0
578 #define RTL8152_REQT_WRITE 0x40
579 #define RTL8152_REQ_GET_REGS 0x05
580 #define RTL8152_REQ_SET_REGS 0x05
582 #define BYTE_EN_DWORD 0xff
583 #define BYTE_EN_WORD 0x33
584 #define BYTE_EN_BYTE 0x11
585 #define BYTE_EN_SIX_BYTES 0x3f
586 #define BYTE_EN_START_MASK 0x0f
587 #define BYTE_EN_END_MASK 0xf0
589 #define RTL8153_MAX_PACKET 9216 /* 9K */
590 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
591 ETH_FCS_LEN)
592 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
593 #define RTL8153_RMS RTL8153_MAX_PACKET
594 #define RTL8152_TX_TIMEOUT (5 * HZ)
595 #define RTL8152_NAPI_WEIGHT 64
596 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
597 sizeof(struct rx_desc) + RX_ALIGN)
599 /* rtl8152 flags */
600 enum rtl8152_flags {
601 RTL8152_UNPLUG = 0,
602 RTL8152_SET_RX_MODE,
603 WORK_ENABLE,
604 RTL8152_LINK_CHG,
605 SELECTIVE_SUSPEND,
606 PHY_RESET,
607 SCHEDULE_NAPI,
608 GREEN_ETHERNET,
609 DELL_TB_RX_AGG_BUG,
612 /* Define these values to match your device */
613 #define VENDOR_ID_REALTEK 0x0bda
614 #define VENDOR_ID_MICROSOFT 0x045e
615 #define VENDOR_ID_SAMSUNG 0x04e8
616 #define VENDOR_ID_LENOVO 0x17ef
617 #define VENDOR_ID_LINKSYS 0x13b1
618 #define VENDOR_ID_NVIDIA 0x0955
619 #define VENDOR_ID_TPLINK 0x2357
621 #define MCU_TYPE_PLA 0x0100
622 #define MCU_TYPE_USB 0x0000
624 struct tally_counter {
625 __le64 tx_packets;
626 __le64 rx_packets;
627 __le64 tx_errors;
628 __le32 rx_errors;
629 __le16 rx_missed;
630 __le16 align_errors;
631 __le32 tx_one_collision;
632 __le32 tx_multi_collision;
633 __le64 rx_unicast;
634 __le64 rx_broadcast;
635 __le32 rx_multicast;
636 __le16 tx_aborted;
637 __le16 tx_underrun;
640 struct rx_desc {
641 __le32 opts1;
642 #define RX_LEN_MASK 0x7fff
644 __le32 opts2;
645 #define RD_UDP_CS BIT(23)
646 #define RD_TCP_CS BIT(22)
647 #define RD_IPV6_CS BIT(20)
648 #define RD_IPV4_CS BIT(19)
650 __le32 opts3;
651 #define IPF BIT(23) /* IP checksum fail */
652 #define UDPF BIT(22) /* UDP checksum fail */
653 #define TCPF BIT(21) /* TCP checksum fail */
654 #define RX_VLAN_TAG BIT(16)
656 __le32 opts4;
657 __le32 opts5;
658 __le32 opts6;
661 struct tx_desc {
662 __le32 opts1;
663 #define TX_FS BIT(31) /* First segment of a packet */
664 #define TX_LS BIT(30) /* Final segment of a packet */
665 #define GTSENDV4 BIT(28)
666 #define GTSENDV6 BIT(27)
667 #define GTTCPHO_SHIFT 18
668 #define GTTCPHO_MAX 0x7fU
669 #define TX_LEN_MAX 0x3ffffU
671 __le32 opts2;
672 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
673 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
674 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
675 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
676 #define MSS_SHIFT 17
677 #define MSS_MAX 0x7ffU
678 #define TCPHO_SHIFT 17
679 #define TCPHO_MAX 0x7ffU
680 #define TX_VLAN_TAG BIT(16)
683 struct r8152;
685 struct rx_agg {
686 struct list_head list;
687 struct urb *urb;
688 struct r8152 *context;
689 void *buffer;
690 void *head;
693 struct tx_agg {
694 struct list_head list;
695 struct urb *urb;
696 struct r8152 *context;
697 void *buffer;
698 void *head;
699 u32 skb_num;
700 u32 skb_len;
703 struct r8152 {
704 unsigned long flags;
705 struct usb_device *udev;
706 struct napi_struct napi;
707 struct usb_interface *intf;
708 struct net_device *netdev;
709 struct urb *intr_urb;
710 struct tx_agg tx_info[RTL8152_MAX_TX];
711 struct rx_agg rx_info[RTL8152_MAX_RX];
712 struct list_head rx_done, tx_free;
713 struct sk_buff_head tx_queue, rx_queue;
714 spinlock_t rx_lock, tx_lock;
715 struct delayed_work schedule, hw_phy_work;
716 struct mii_if_info mii;
717 struct mutex control; /* use for hw setting */
718 #ifdef CONFIG_PM_SLEEP
719 struct notifier_block pm_notifier;
720 #endif
722 struct rtl_ops {
723 void (*init)(struct r8152 *);
724 int (*enable)(struct r8152 *);
725 void (*disable)(struct r8152 *);
726 void (*up)(struct r8152 *);
727 void (*down)(struct r8152 *);
728 void (*unload)(struct r8152 *);
729 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
730 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
731 bool (*in_nway)(struct r8152 *);
732 void (*hw_phy_cfg)(struct r8152 *);
733 void (*autosuspend_en)(struct r8152 *tp, bool enable);
734 } rtl_ops;
736 int intr_interval;
737 u32 saved_wolopts;
738 u32 msg_enable;
739 u32 tx_qlen;
740 u32 coalesce;
741 u16 ocp_base;
742 u16 speed;
743 u8 *intr_buff;
744 u8 version;
745 u8 duplex;
746 u8 autoneg;
749 enum rtl_version {
750 RTL_VER_UNKNOWN = 0,
751 RTL_VER_01,
752 RTL_VER_02,
753 RTL_VER_03,
754 RTL_VER_04,
755 RTL_VER_05,
756 RTL_VER_06,
757 RTL_VER_07,
758 RTL_VER_08,
759 RTL_VER_09,
760 RTL_VER_MAX
763 enum tx_csum_stat {
764 TX_CSUM_SUCCESS = 0,
765 TX_CSUM_TSO,
766 TX_CSUM_NONE
769 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
770 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
772 static const int multicast_filter_limit = 32;
773 static unsigned int agg_buf_sz = 16384;
775 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
776 VLAN_ETH_HLEN - ETH_FCS_LEN)
778 static
779 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
781 int ret;
782 void *tmp;
784 tmp = kmalloc(size, GFP_KERNEL);
785 if (!tmp)
786 return -ENOMEM;
788 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
789 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
790 value, index, tmp, size, 500);
791 if (ret < 0)
792 memset(data, 0xff, size);
793 else
794 memcpy(data, tmp, size);
796 kfree(tmp);
798 return ret;
801 static
802 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
804 int ret;
805 void *tmp;
807 tmp = kmemdup(data, size, GFP_KERNEL);
808 if (!tmp)
809 return -ENOMEM;
811 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
812 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
813 value, index, tmp, size, 500);
815 kfree(tmp);
817 return ret;
820 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
821 void *data, u16 type)
823 u16 limit = 64;
824 int ret = 0;
826 if (test_bit(RTL8152_UNPLUG, &tp->flags))
827 return -ENODEV;
829 /* both size and indix must be 4 bytes align */
830 if ((size & 3) || !size || (index & 3) || !data)
831 return -EPERM;
833 if ((u32)index + (u32)size > 0xffff)
834 return -EPERM;
836 while (size) {
837 if (size > limit) {
838 ret = get_registers(tp, index, type, limit, data);
839 if (ret < 0)
840 break;
842 index += limit;
843 data += limit;
844 size -= limit;
845 } else {
846 ret = get_registers(tp, index, type, size, data);
847 if (ret < 0)
848 break;
850 index += size;
851 data += size;
852 size = 0;
853 break;
857 if (ret == -ENODEV)
858 set_bit(RTL8152_UNPLUG, &tp->flags);
860 return ret;
863 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
864 u16 size, void *data, u16 type)
866 int ret;
867 u16 byteen_start, byteen_end, byen;
868 u16 limit = 512;
870 if (test_bit(RTL8152_UNPLUG, &tp->flags))
871 return -ENODEV;
873 /* both size and indix must be 4 bytes align */
874 if ((size & 3) || !size || (index & 3) || !data)
875 return -EPERM;
877 if ((u32)index + (u32)size > 0xffff)
878 return -EPERM;
880 byteen_start = byteen & BYTE_EN_START_MASK;
881 byteen_end = byteen & BYTE_EN_END_MASK;
883 byen = byteen_start | (byteen_start << 4);
884 ret = set_registers(tp, index, type | byen, 4, data);
885 if (ret < 0)
886 goto error1;
888 index += 4;
889 data += 4;
890 size -= 4;
892 if (size) {
893 size -= 4;
895 while (size) {
896 if (size > limit) {
897 ret = set_registers(tp, index,
898 type | BYTE_EN_DWORD,
899 limit, data);
900 if (ret < 0)
901 goto error1;
903 index += limit;
904 data += limit;
905 size -= limit;
906 } else {
907 ret = set_registers(tp, index,
908 type | BYTE_EN_DWORD,
909 size, data);
910 if (ret < 0)
911 goto error1;
913 index += size;
914 data += size;
915 size = 0;
916 break;
920 byen = byteen_end | (byteen_end >> 4);
921 ret = set_registers(tp, index, type | byen, 4, data);
922 if (ret < 0)
923 goto error1;
926 error1:
927 if (ret == -ENODEV)
928 set_bit(RTL8152_UNPLUG, &tp->flags);
930 return ret;
933 static inline
934 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
936 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
939 static inline
940 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
942 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
945 static inline
946 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
948 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
951 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
953 __le32 data;
955 generic_ocp_read(tp, index, sizeof(data), &data, type);
957 return __le32_to_cpu(data);
960 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
962 __le32 tmp = __cpu_to_le32(data);
964 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
967 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
969 u32 data;
970 __le32 tmp;
971 u16 byen = BYTE_EN_WORD;
972 u8 shift = index & 2;
974 index &= ~3;
975 byen <<= shift;
977 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
979 data = __le32_to_cpu(tmp);
980 data >>= (shift * 8);
981 data &= 0xffff;
983 return (u16)data;
986 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
988 u32 mask = 0xffff;
989 __le32 tmp;
990 u16 byen = BYTE_EN_WORD;
991 u8 shift = index & 2;
993 data &= mask;
995 if (index & 2) {
996 byen <<= shift;
997 mask <<= (shift * 8);
998 data <<= (shift * 8);
999 index &= ~3;
1002 tmp = __cpu_to_le32(data);
1004 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1007 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1009 u32 data;
1010 __le32 tmp;
1011 u8 shift = index & 3;
1013 index &= ~3;
1015 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1017 data = __le32_to_cpu(tmp);
1018 data >>= (shift * 8);
1019 data &= 0xff;
1021 return (u8)data;
1024 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1026 u32 mask = 0xff;
1027 __le32 tmp;
1028 u16 byen = BYTE_EN_BYTE;
1029 u8 shift = index & 3;
1031 data &= mask;
1033 if (index & 3) {
1034 byen <<= shift;
1035 mask <<= (shift * 8);
1036 data <<= (shift * 8);
1037 index &= ~3;
1040 tmp = __cpu_to_le32(data);
1042 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1045 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1047 u16 ocp_base, ocp_index;
1049 ocp_base = addr & 0xf000;
1050 if (ocp_base != tp->ocp_base) {
1051 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1052 tp->ocp_base = ocp_base;
1055 ocp_index = (addr & 0x0fff) | 0xb000;
1056 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1059 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1061 u16 ocp_base, ocp_index;
1063 ocp_base = addr & 0xf000;
1064 if (ocp_base != tp->ocp_base) {
1065 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1066 tp->ocp_base = ocp_base;
1069 ocp_index = (addr & 0x0fff) | 0xb000;
1070 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1073 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1075 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1078 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1080 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1083 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1085 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1086 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1089 static u16 sram_read(struct r8152 *tp, u16 addr)
1091 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1092 return ocp_reg_read(tp, OCP_SRAM_DATA);
1095 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1097 struct r8152 *tp = netdev_priv(netdev);
1098 int ret;
1100 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1101 return -ENODEV;
1103 if (phy_id != R8152_PHY_ID)
1104 return -EINVAL;
1106 ret = r8152_mdio_read(tp, reg);
1108 return ret;
1111 static
1112 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1114 struct r8152 *tp = netdev_priv(netdev);
1116 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1117 return;
1119 if (phy_id != R8152_PHY_ID)
1120 return;
1122 r8152_mdio_write(tp, reg, val);
1125 static int
1126 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1128 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1130 struct r8152 *tp = netdev_priv(netdev);
1131 struct sockaddr *addr = p;
1132 int ret = -EADDRNOTAVAIL;
1134 if (!is_valid_ether_addr(addr->sa_data))
1135 goto out1;
1137 ret = usb_autopm_get_interface(tp->intf);
1138 if (ret < 0)
1139 goto out1;
1141 mutex_lock(&tp->control);
1143 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1145 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1146 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1147 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1149 mutex_unlock(&tp->control);
1151 usb_autopm_put_interface(tp->intf);
1152 out1:
1153 return ret;
1156 /* Devices containing RTL8153-AD can support a persistent
1157 * host system provided MAC address.
1158 * Examples of this are Dell TB15 and Dell WD15 docks
1160 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1162 acpi_status status;
1163 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1164 union acpi_object *obj;
1165 int ret = -EINVAL;
1166 u32 ocp_data;
1167 unsigned char buf[6];
1169 /* test for -AD variant of RTL8153 */
1170 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1171 if ((ocp_data & AD_MASK) != 0x1000)
1172 return -ENODEV;
1174 /* test for MAC address pass-through bit */
1175 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1176 if ((ocp_data & PASS_THRU_MASK) != 1)
1177 return -ENODEV;
1179 /* returns _AUXMAC_#AABBCCDDEEFF# */
1180 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1181 obj = (union acpi_object *)buffer.pointer;
1182 if (!ACPI_SUCCESS(status))
1183 return -ENODEV;
1184 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1185 netif_warn(tp, probe, tp->netdev,
1186 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1187 obj->type, obj->string.length);
1188 goto amacout;
1190 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1191 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1192 netif_warn(tp, probe, tp->netdev,
1193 "Invalid header when reading pass-thru MAC addr\n");
1194 goto amacout;
1196 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1197 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1198 netif_warn(tp, probe, tp->netdev,
1199 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1200 ret, buf);
1201 ret = -EINVAL;
1202 goto amacout;
1204 memcpy(sa->sa_data, buf, 6);
1205 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1206 netif_info(tp, probe, tp->netdev,
1207 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1209 amacout:
1210 kfree(obj);
1211 return ret;
1214 static int set_ethernet_addr(struct r8152 *tp)
1216 struct net_device *dev = tp->netdev;
1217 struct sockaddr sa;
1218 int ret;
1220 if (tp->version == RTL_VER_01) {
1221 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1222 } else {
1223 /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1224 * or system doesn't provide valid _SB.AMAC this will be
1225 * be expected to non-zero
1227 ret = vendor_mac_passthru_addr_read(tp, &sa);
1228 if (ret < 0)
1229 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1232 if (ret < 0) {
1233 netif_err(tp, probe, dev, "Get ether addr fail\n");
1234 } else if (!is_valid_ether_addr(sa.sa_data)) {
1235 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1236 sa.sa_data);
1237 eth_hw_addr_random(dev);
1238 ether_addr_copy(sa.sa_data, dev->dev_addr);
1239 ret = rtl8152_set_mac_address(dev, &sa);
1240 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1241 sa.sa_data);
1242 } else {
1243 if (tp->version == RTL_VER_01)
1244 ether_addr_copy(dev->dev_addr, sa.sa_data);
1245 else
1246 ret = rtl8152_set_mac_address(dev, &sa);
1249 return ret;
1252 static void read_bulk_callback(struct urb *urb)
1254 struct net_device *netdev;
1255 int status = urb->status;
1256 struct rx_agg *agg;
1257 struct r8152 *tp;
1258 unsigned long flags;
1260 agg = urb->context;
1261 if (!agg)
1262 return;
1264 tp = agg->context;
1265 if (!tp)
1266 return;
1268 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1269 return;
1271 if (!test_bit(WORK_ENABLE, &tp->flags))
1272 return;
1274 netdev = tp->netdev;
1276 /* When link down, the driver would cancel all bulks. */
1277 /* This avoid the re-submitting bulk */
1278 if (!netif_carrier_ok(netdev))
1279 return;
1281 usb_mark_last_busy(tp->udev);
1283 switch (status) {
1284 case 0:
1285 if (urb->actual_length < ETH_ZLEN)
1286 break;
1288 spin_lock_irqsave(&tp->rx_lock, flags);
1289 list_add_tail(&agg->list, &tp->rx_done);
1290 spin_unlock_irqrestore(&tp->rx_lock, flags);
1291 napi_schedule(&tp->napi);
1292 return;
1293 case -ESHUTDOWN:
1294 set_bit(RTL8152_UNPLUG, &tp->flags);
1295 netif_device_detach(tp->netdev);
1296 return;
1297 case -ENOENT:
1298 return; /* the urb is in unlink state */
1299 case -ETIME:
1300 if (net_ratelimit())
1301 netdev_warn(netdev, "maybe reset is needed?\n");
1302 break;
1303 default:
1304 if (net_ratelimit())
1305 netdev_warn(netdev, "Rx status %d\n", status);
1306 break;
1309 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1312 static void write_bulk_callback(struct urb *urb)
1314 struct net_device_stats *stats;
1315 struct net_device *netdev;
1316 struct tx_agg *agg;
1317 struct r8152 *tp;
1318 unsigned long flags;
1319 int status = urb->status;
1321 agg = urb->context;
1322 if (!agg)
1323 return;
1325 tp = agg->context;
1326 if (!tp)
1327 return;
1329 netdev = tp->netdev;
1330 stats = &netdev->stats;
1331 if (status) {
1332 if (net_ratelimit())
1333 netdev_warn(netdev, "Tx status %d\n", status);
1334 stats->tx_errors += agg->skb_num;
1335 } else {
1336 stats->tx_packets += agg->skb_num;
1337 stats->tx_bytes += agg->skb_len;
1340 spin_lock_irqsave(&tp->tx_lock, flags);
1341 list_add_tail(&agg->list, &tp->tx_free);
1342 spin_unlock_irqrestore(&tp->tx_lock, flags);
1344 usb_autopm_put_interface_async(tp->intf);
1346 if (!netif_carrier_ok(netdev))
1347 return;
1349 if (!test_bit(WORK_ENABLE, &tp->flags))
1350 return;
1352 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1353 return;
1355 if (!skb_queue_empty(&tp->tx_queue))
1356 napi_schedule(&tp->napi);
1359 static void intr_callback(struct urb *urb)
1361 struct r8152 *tp;
1362 __le16 *d;
1363 int status = urb->status;
1364 int res;
1366 tp = urb->context;
1367 if (!tp)
1368 return;
1370 if (!test_bit(WORK_ENABLE, &tp->flags))
1371 return;
1373 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1374 return;
1376 switch (status) {
1377 case 0: /* success */
1378 break;
1379 case -ECONNRESET: /* unlink */
1380 case -ESHUTDOWN:
1381 netif_device_detach(tp->netdev);
1382 /* fall through */
1383 case -ENOENT:
1384 case -EPROTO:
1385 netif_info(tp, intr, tp->netdev,
1386 "Stop submitting intr, status %d\n", status);
1387 return;
1388 case -EOVERFLOW:
1389 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1390 goto resubmit;
1391 /* -EPIPE: should clear the halt */
1392 default:
1393 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1394 goto resubmit;
1397 d = urb->transfer_buffer;
1398 if (INTR_LINK & __le16_to_cpu(d[0])) {
1399 if (!netif_carrier_ok(tp->netdev)) {
1400 set_bit(RTL8152_LINK_CHG, &tp->flags);
1401 schedule_delayed_work(&tp->schedule, 0);
1403 } else {
1404 if (netif_carrier_ok(tp->netdev)) {
1405 netif_stop_queue(tp->netdev);
1406 set_bit(RTL8152_LINK_CHG, &tp->flags);
1407 schedule_delayed_work(&tp->schedule, 0);
1411 resubmit:
1412 res = usb_submit_urb(urb, GFP_ATOMIC);
1413 if (res == -ENODEV) {
1414 set_bit(RTL8152_UNPLUG, &tp->flags);
1415 netif_device_detach(tp->netdev);
1416 } else if (res) {
1417 netif_err(tp, intr, tp->netdev,
1418 "can't resubmit intr, status %d\n", res);
1422 static inline void *rx_agg_align(void *data)
1424 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1427 static inline void *tx_agg_align(void *data)
1429 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1432 static void free_all_mem(struct r8152 *tp)
1434 int i;
1436 for (i = 0; i < RTL8152_MAX_RX; i++) {
1437 usb_free_urb(tp->rx_info[i].urb);
1438 tp->rx_info[i].urb = NULL;
1440 kfree(tp->rx_info[i].buffer);
1441 tp->rx_info[i].buffer = NULL;
1442 tp->rx_info[i].head = NULL;
1445 for (i = 0; i < RTL8152_MAX_TX; i++) {
1446 usb_free_urb(tp->tx_info[i].urb);
1447 tp->tx_info[i].urb = NULL;
1449 kfree(tp->tx_info[i].buffer);
1450 tp->tx_info[i].buffer = NULL;
1451 tp->tx_info[i].head = NULL;
1454 usb_free_urb(tp->intr_urb);
1455 tp->intr_urb = NULL;
1457 kfree(tp->intr_buff);
1458 tp->intr_buff = NULL;
1461 static int alloc_all_mem(struct r8152 *tp)
1463 struct net_device *netdev = tp->netdev;
1464 struct usb_interface *intf = tp->intf;
1465 struct usb_host_interface *alt = intf->cur_altsetting;
1466 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1467 struct urb *urb;
1468 int node, i;
1469 u8 *buf;
1471 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1473 spin_lock_init(&tp->rx_lock);
1474 spin_lock_init(&tp->tx_lock);
1475 INIT_LIST_HEAD(&tp->tx_free);
1476 INIT_LIST_HEAD(&tp->rx_done);
1477 skb_queue_head_init(&tp->tx_queue);
1478 skb_queue_head_init(&tp->rx_queue);
1480 for (i = 0; i < RTL8152_MAX_RX; i++) {
1481 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1482 if (!buf)
1483 goto err1;
1485 if (buf != rx_agg_align(buf)) {
1486 kfree(buf);
1487 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1488 node);
1489 if (!buf)
1490 goto err1;
1493 urb = usb_alloc_urb(0, GFP_KERNEL);
1494 if (!urb) {
1495 kfree(buf);
1496 goto err1;
1499 INIT_LIST_HEAD(&tp->rx_info[i].list);
1500 tp->rx_info[i].context = tp;
1501 tp->rx_info[i].urb = urb;
1502 tp->rx_info[i].buffer = buf;
1503 tp->rx_info[i].head = rx_agg_align(buf);
1506 for (i = 0; i < RTL8152_MAX_TX; i++) {
1507 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1508 if (!buf)
1509 goto err1;
1511 if (buf != tx_agg_align(buf)) {
1512 kfree(buf);
1513 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1514 node);
1515 if (!buf)
1516 goto err1;
1519 urb = usb_alloc_urb(0, GFP_KERNEL);
1520 if (!urb) {
1521 kfree(buf);
1522 goto err1;
1525 INIT_LIST_HEAD(&tp->tx_info[i].list);
1526 tp->tx_info[i].context = tp;
1527 tp->tx_info[i].urb = urb;
1528 tp->tx_info[i].buffer = buf;
1529 tp->tx_info[i].head = tx_agg_align(buf);
1531 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1534 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1535 if (!tp->intr_urb)
1536 goto err1;
1538 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1539 if (!tp->intr_buff)
1540 goto err1;
1542 tp->intr_interval = (int)ep_intr->desc.bInterval;
1543 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1544 tp->intr_buff, INTBUFSIZE, intr_callback,
1545 tp, tp->intr_interval);
1547 return 0;
1549 err1:
1550 free_all_mem(tp);
1551 return -ENOMEM;
1554 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1556 struct tx_agg *agg = NULL;
1557 unsigned long flags;
1559 if (list_empty(&tp->tx_free))
1560 return NULL;
1562 spin_lock_irqsave(&tp->tx_lock, flags);
1563 if (!list_empty(&tp->tx_free)) {
1564 struct list_head *cursor;
1566 cursor = tp->tx_free.next;
1567 list_del_init(cursor);
1568 agg = list_entry(cursor, struct tx_agg, list);
1570 spin_unlock_irqrestore(&tp->tx_lock, flags);
1572 return agg;
1575 /* r8152_csum_workaround()
1576 * The hw limites the value the transport offset. When the offset is out of the
1577 * range, calculate the checksum by sw.
1579 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1580 struct sk_buff_head *list)
1582 if (skb_shinfo(skb)->gso_size) {
1583 netdev_features_t features = tp->netdev->features;
1584 struct sk_buff_head seg_list;
1585 struct sk_buff *segs, *nskb;
1587 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1588 segs = skb_gso_segment(skb, features);
1589 if (IS_ERR(segs) || !segs)
1590 goto drop;
1592 __skb_queue_head_init(&seg_list);
1594 do {
1595 nskb = segs;
1596 segs = segs->next;
1597 nskb->next = NULL;
1598 __skb_queue_tail(&seg_list, nskb);
1599 } while (segs);
1601 skb_queue_splice(&seg_list, list);
1602 dev_kfree_skb(skb);
1603 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1604 if (skb_checksum_help(skb) < 0)
1605 goto drop;
1607 __skb_queue_head(list, skb);
1608 } else {
1609 struct net_device_stats *stats;
1611 drop:
1612 stats = &tp->netdev->stats;
1613 stats->tx_dropped++;
1614 dev_kfree_skb(skb);
1618 /* msdn_giant_send_check()
1619 * According to the document of microsoft, the TCP Pseudo Header excludes the
1620 * packet length for IPv6 TCP large packets.
1622 static int msdn_giant_send_check(struct sk_buff *skb)
1624 const struct ipv6hdr *ipv6h;
1625 struct tcphdr *th;
1626 int ret;
1628 ret = skb_cow_head(skb, 0);
1629 if (ret)
1630 return ret;
1632 ipv6h = ipv6_hdr(skb);
1633 th = tcp_hdr(skb);
1635 th->check = 0;
1636 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1638 return ret;
1641 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1643 if (skb_vlan_tag_present(skb)) {
1644 u32 opts2;
1646 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1647 desc->opts2 |= cpu_to_le32(opts2);
1651 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1653 u32 opts2 = le32_to_cpu(desc->opts2);
1655 if (opts2 & RX_VLAN_TAG)
1656 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1657 swab16(opts2 & 0xffff));
1660 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1661 struct sk_buff *skb, u32 len, u32 transport_offset)
1663 u32 mss = skb_shinfo(skb)->gso_size;
1664 u32 opts1, opts2 = 0;
1665 int ret = TX_CSUM_SUCCESS;
1667 WARN_ON_ONCE(len > TX_LEN_MAX);
1669 opts1 = len | TX_FS | TX_LS;
1671 if (mss) {
1672 if (transport_offset > GTTCPHO_MAX) {
1673 netif_warn(tp, tx_err, tp->netdev,
1674 "Invalid transport offset 0x%x for TSO\n",
1675 transport_offset);
1676 ret = TX_CSUM_TSO;
1677 goto unavailable;
1680 switch (vlan_get_protocol(skb)) {
1681 case htons(ETH_P_IP):
1682 opts1 |= GTSENDV4;
1683 break;
1685 case htons(ETH_P_IPV6):
1686 if (msdn_giant_send_check(skb)) {
1687 ret = TX_CSUM_TSO;
1688 goto unavailable;
1690 opts1 |= GTSENDV6;
1691 break;
1693 default:
1694 WARN_ON_ONCE(1);
1695 break;
1698 opts1 |= transport_offset << GTTCPHO_SHIFT;
1699 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1700 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1701 u8 ip_protocol;
1703 if (transport_offset > TCPHO_MAX) {
1704 netif_warn(tp, tx_err, tp->netdev,
1705 "Invalid transport offset 0x%x\n",
1706 transport_offset);
1707 ret = TX_CSUM_NONE;
1708 goto unavailable;
1711 switch (vlan_get_protocol(skb)) {
1712 case htons(ETH_P_IP):
1713 opts2 |= IPV4_CS;
1714 ip_protocol = ip_hdr(skb)->protocol;
1715 break;
1717 case htons(ETH_P_IPV6):
1718 opts2 |= IPV6_CS;
1719 ip_protocol = ipv6_hdr(skb)->nexthdr;
1720 break;
1722 default:
1723 ip_protocol = IPPROTO_RAW;
1724 break;
1727 if (ip_protocol == IPPROTO_TCP)
1728 opts2 |= TCP_CS;
1729 else if (ip_protocol == IPPROTO_UDP)
1730 opts2 |= UDP_CS;
1731 else
1732 WARN_ON_ONCE(1);
1734 opts2 |= transport_offset << TCPHO_SHIFT;
1737 desc->opts2 = cpu_to_le32(opts2);
1738 desc->opts1 = cpu_to_le32(opts1);
1740 unavailable:
1741 return ret;
1744 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1746 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1747 int remain, ret;
1748 u8 *tx_data;
1750 __skb_queue_head_init(&skb_head);
1751 spin_lock(&tx_queue->lock);
1752 skb_queue_splice_init(tx_queue, &skb_head);
1753 spin_unlock(&tx_queue->lock);
1755 tx_data = agg->head;
1756 agg->skb_num = 0;
1757 agg->skb_len = 0;
1758 remain = agg_buf_sz;
1760 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1761 struct tx_desc *tx_desc;
1762 struct sk_buff *skb;
1763 unsigned int len;
1764 u32 offset;
1766 skb = __skb_dequeue(&skb_head);
1767 if (!skb)
1768 break;
1770 len = skb->len + sizeof(*tx_desc);
1772 if (len > remain) {
1773 __skb_queue_head(&skb_head, skb);
1774 break;
1777 tx_data = tx_agg_align(tx_data);
1778 tx_desc = (struct tx_desc *)tx_data;
1780 offset = (u32)skb_transport_offset(skb);
1782 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1783 r8152_csum_workaround(tp, skb, &skb_head);
1784 continue;
1787 rtl_tx_vlan_tag(tx_desc, skb);
1789 tx_data += sizeof(*tx_desc);
1791 len = skb->len;
1792 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1793 struct net_device_stats *stats = &tp->netdev->stats;
1795 stats->tx_dropped++;
1796 dev_kfree_skb_any(skb);
1797 tx_data -= sizeof(*tx_desc);
1798 continue;
1801 tx_data += len;
1802 agg->skb_len += len;
1803 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1805 dev_kfree_skb_any(skb);
1807 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1809 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
1810 break;
1813 if (!skb_queue_empty(&skb_head)) {
1814 spin_lock(&tx_queue->lock);
1815 skb_queue_splice(&skb_head, tx_queue);
1816 spin_unlock(&tx_queue->lock);
1819 netif_tx_lock(tp->netdev);
1821 if (netif_queue_stopped(tp->netdev) &&
1822 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1823 netif_wake_queue(tp->netdev);
1825 netif_tx_unlock(tp->netdev);
1827 ret = usb_autopm_get_interface_async(tp->intf);
1828 if (ret < 0)
1829 goto out_tx_fill;
1831 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1832 agg->head, (int)(tx_data - (u8 *)agg->head),
1833 (usb_complete_t)write_bulk_callback, agg);
1835 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1836 if (ret < 0)
1837 usb_autopm_put_interface_async(tp->intf);
1839 out_tx_fill:
1840 return ret;
1843 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1845 u8 checksum = CHECKSUM_NONE;
1846 u32 opts2, opts3;
1848 if (!(tp->netdev->features & NETIF_F_RXCSUM))
1849 goto return_result;
1851 opts2 = le32_to_cpu(rx_desc->opts2);
1852 opts3 = le32_to_cpu(rx_desc->opts3);
1854 if (opts2 & RD_IPV4_CS) {
1855 if (opts3 & IPF)
1856 checksum = CHECKSUM_NONE;
1857 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1858 checksum = CHECKSUM_UNNECESSARY;
1859 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1860 checksum = CHECKSUM_UNNECESSARY;
1861 } else if (opts2 & RD_IPV6_CS) {
1862 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1863 checksum = CHECKSUM_UNNECESSARY;
1864 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1865 checksum = CHECKSUM_UNNECESSARY;
1868 return_result:
1869 return checksum;
1872 static int rx_bottom(struct r8152 *tp, int budget)
1874 unsigned long flags;
1875 struct list_head *cursor, *next, rx_queue;
1876 int ret = 0, work_done = 0;
1877 struct napi_struct *napi = &tp->napi;
1879 if (!skb_queue_empty(&tp->rx_queue)) {
1880 while (work_done < budget) {
1881 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1882 struct net_device *netdev = tp->netdev;
1883 struct net_device_stats *stats = &netdev->stats;
1884 unsigned int pkt_len;
1886 if (!skb)
1887 break;
1889 pkt_len = skb->len;
1890 napi_gro_receive(napi, skb);
1891 work_done++;
1892 stats->rx_packets++;
1893 stats->rx_bytes += pkt_len;
1897 if (list_empty(&tp->rx_done))
1898 goto out1;
1900 INIT_LIST_HEAD(&rx_queue);
1901 spin_lock_irqsave(&tp->rx_lock, flags);
1902 list_splice_init(&tp->rx_done, &rx_queue);
1903 spin_unlock_irqrestore(&tp->rx_lock, flags);
1905 list_for_each_safe(cursor, next, &rx_queue) {
1906 struct rx_desc *rx_desc;
1907 struct rx_agg *agg;
1908 int len_used = 0;
1909 struct urb *urb;
1910 u8 *rx_data;
1912 list_del_init(cursor);
1914 agg = list_entry(cursor, struct rx_agg, list);
1915 urb = agg->urb;
1916 if (urb->actual_length < ETH_ZLEN)
1917 goto submit;
1919 rx_desc = agg->head;
1920 rx_data = agg->head;
1921 len_used += sizeof(struct rx_desc);
1923 while (urb->actual_length > len_used) {
1924 struct net_device *netdev = tp->netdev;
1925 struct net_device_stats *stats = &netdev->stats;
1926 unsigned int pkt_len;
1927 struct sk_buff *skb;
1929 /* limite the skb numbers for rx_queue */
1930 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1931 break;
1933 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1934 if (pkt_len < ETH_ZLEN)
1935 break;
1937 len_used += pkt_len;
1938 if (urb->actual_length < len_used)
1939 break;
1941 pkt_len -= ETH_FCS_LEN;
1942 rx_data += sizeof(struct rx_desc);
1944 skb = napi_alloc_skb(napi, pkt_len);
1945 if (!skb) {
1946 stats->rx_dropped++;
1947 goto find_next_rx;
1950 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1951 memcpy(skb->data, rx_data, pkt_len);
1952 skb_put(skb, pkt_len);
1953 skb->protocol = eth_type_trans(skb, netdev);
1954 rtl_rx_vlan_tag(rx_desc, skb);
1955 if (work_done < budget) {
1956 napi_gro_receive(napi, skb);
1957 work_done++;
1958 stats->rx_packets++;
1959 stats->rx_bytes += pkt_len;
1960 } else {
1961 __skb_queue_tail(&tp->rx_queue, skb);
1964 find_next_rx:
1965 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1966 rx_desc = (struct rx_desc *)rx_data;
1967 len_used = (int)(rx_data - (u8 *)agg->head);
1968 len_used += sizeof(struct rx_desc);
1971 submit:
1972 if (!ret) {
1973 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1974 } else {
1975 urb->actual_length = 0;
1976 list_add_tail(&agg->list, next);
1980 if (!list_empty(&rx_queue)) {
1981 spin_lock_irqsave(&tp->rx_lock, flags);
1982 list_splice_tail(&rx_queue, &tp->rx_done);
1983 spin_unlock_irqrestore(&tp->rx_lock, flags);
1986 out1:
1987 return work_done;
1990 static void tx_bottom(struct r8152 *tp)
1992 int res;
1994 do {
1995 struct tx_agg *agg;
1997 if (skb_queue_empty(&tp->tx_queue))
1998 break;
2000 agg = r8152_get_tx_agg(tp);
2001 if (!agg)
2002 break;
2004 res = r8152_tx_agg_fill(tp, agg);
2005 if (res) {
2006 struct net_device *netdev = tp->netdev;
2008 if (res == -ENODEV) {
2009 set_bit(RTL8152_UNPLUG, &tp->flags);
2010 netif_device_detach(netdev);
2011 } else {
2012 struct net_device_stats *stats = &netdev->stats;
2013 unsigned long flags;
2015 netif_warn(tp, tx_err, netdev,
2016 "failed tx_urb %d\n", res);
2017 stats->tx_dropped += agg->skb_num;
2019 spin_lock_irqsave(&tp->tx_lock, flags);
2020 list_add_tail(&agg->list, &tp->tx_free);
2021 spin_unlock_irqrestore(&tp->tx_lock, flags);
2024 } while (res == 0);
2027 static void bottom_half(struct r8152 *tp)
2029 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2030 return;
2032 if (!test_bit(WORK_ENABLE, &tp->flags))
2033 return;
2035 /* When link down, the driver would cancel all bulks. */
2036 /* This avoid the re-submitting bulk */
2037 if (!netif_carrier_ok(tp->netdev))
2038 return;
2040 clear_bit(SCHEDULE_NAPI, &tp->flags);
2042 tx_bottom(tp);
2045 static int r8152_poll(struct napi_struct *napi, int budget)
2047 struct r8152 *tp = container_of(napi, struct r8152, napi);
2048 int work_done;
2050 work_done = rx_bottom(tp, budget);
2051 bottom_half(tp);
2053 if (work_done < budget) {
2054 if (!napi_complete_done(napi, work_done))
2055 goto out;
2056 if (!list_empty(&tp->rx_done))
2057 napi_schedule(napi);
2058 else if (!skb_queue_empty(&tp->tx_queue) &&
2059 !list_empty(&tp->tx_free))
2060 napi_schedule(napi);
2063 out:
2064 return work_done;
2067 static
2068 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2070 int ret;
2072 /* The rx would be stopped, so skip submitting */
2073 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2074 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2075 return 0;
2077 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2078 agg->head, agg_buf_sz,
2079 (usb_complete_t)read_bulk_callback, agg);
2081 ret = usb_submit_urb(agg->urb, mem_flags);
2082 if (ret == -ENODEV) {
2083 set_bit(RTL8152_UNPLUG, &tp->flags);
2084 netif_device_detach(tp->netdev);
2085 } else if (ret) {
2086 struct urb *urb = agg->urb;
2087 unsigned long flags;
2089 urb->actual_length = 0;
2090 spin_lock_irqsave(&tp->rx_lock, flags);
2091 list_add_tail(&agg->list, &tp->rx_done);
2092 spin_unlock_irqrestore(&tp->rx_lock, flags);
2094 netif_err(tp, rx_err, tp->netdev,
2095 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2097 napi_schedule(&tp->napi);
2100 return ret;
2103 static void rtl_drop_queued_tx(struct r8152 *tp)
2105 struct net_device_stats *stats = &tp->netdev->stats;
2106 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2107 struct sk_buff *skb;
2109 if (skb_queue_empty(tx_queue))
2110 return;
2112 __skb_queue_head_init(&skb_head);
2113 spin_lock_bh(&tx_queue->lock);
2114 skb_queue_splice_init(tx_queue, &skb_head);
2115 spin_unlock_bh(&tx_queue->lock);
2117 while ((skb = __skb_dequeue(&skb_head))) {
2118 dev_kfree_skb(skb);
2119 stats->tx_dropped++;
2123 static void rtl8152_tx_timeout(struct net_device *netdev)
2125 struct r8152 *tp = netdev_priv(netdev);
2127 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2129 usb_queue_reset_device(tp->intf);
2132 static void rtl8152_set_rx_mode(struct net_device *netdev)
2134 struct r8152 *tp = netdev_priv(netdev);
2136 if (netif_carrier_ok(netdev)) {
2137 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2138 schedule_delayed_work(&tp->schedule, 0);
2142 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2144 struct r8152 *tp = netdev_priv(netdev);
2145 u32 mc_filter[2]; /* Multicast hash filter */
2146 __le32 tmp[2];
2147 u32 ocp_data;
2149 netif_stop_queue(netdev);
2150 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2151 ocp_data &= ~RCR_ACPT_ALL;
2152 ocp_data |= RCR_AB | RCR_APM;
2154 if (netdev->flags & IFF_PROMISC) {
2155 /* Unconditionally log net taps. */
2156 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2157 ocp_data |= RCR_AM | RCR_AAP;
2158 mc_filter[1] = 0xffffffff;
2159 mc_filter[0] = 0xffffffff;
2160 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2161 (netdev->flags & IFF_ALLMULTI)) {
2162 /* Too many to filter perfectly -- accept all multicasts. */
2163 ocp_data |= RCR_AM;
2164 mc_filter[1] = 0xffffffff;
2165 mc_filter[0] = 0xffffffff;
2166 } else {
2167 struct netdev_hw_addr *ha;
2169 mc_filter[1] = 0;
2170 mc_filter[0] = 0;
2171 netdev_for_each_mc_addr(ha, netdev) {
2172 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2174 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2175 ocp_data |= RCR_AM;
2179 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2180 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2182 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2183 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2184 netif_wake_queue(netdev);
2187 static netdev_features_t
2188 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2189 netdev_features_t features)
2191 u32 mss = skb_shinfo(skb)->gso_size;
2192 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2193 int offset = skb_transport_offset(skb);
2195 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2196 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2197 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2198 features &= ~NETIF_F_GSO_MASK;
2200 return features;
2203 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2204 struct net_device *netdev)
2206 struct r8152 *tp = netdev_priv(netdev);
2208 skb_tx_timestamp(skb);
2210 skb_queue_tail(&tp->tx_queue, skb);
2212 if (!list_empty(&tp->tx_free)) {
2213 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2214 set_bit(SCHEDULE_NAPI, &tp->flags);
2215 schedule_delayed_work(&tp->schedule, 0);
2216 } else {
2217 usb_mark_last_busy(tp->udev);
2218 napi_schedule(&tp->napi);
2220 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2221 netif_stop_queue(netdev);
2224 return NETDEV_TX_OK;
2227 static void r8152b_reset_packet_filter(struct r8152 *tp)
2229 u32 ocp_data;
2231 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2232 ocp_data &= ~FMC_FCR_MCU_EN;
2233 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2234 ocp_data |= FMC_FCR_MCU_EN;
2235 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2238 static void rtl8152_nic_reset(struct r8152 *tp)
2240 int i;
2242 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2244 for (i = 0; i < 1000; i++) {
2245 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2246 break;
2247 usleep_range(100, 400);
2251 static void set_tx_qlen(struct r8152 *tp)
2253 struct net_device *netdev = tp->netdev;
2255 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2256 sizeof(struct tx_desc));
2259 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2261 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2264 static void rtl_set_eee_plus(struct r8152 *tp)
2266 u32 ocp_data;
2267 u8 speed;
2269 speed = rtl8152_get_speed(tp);
2270 if (speed & _10bps) {
2271 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2272 ocp_data |= EEEP_CR_EEEP_TX;
2273 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2274 } else {
2275 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2276 ocp_data &= ~EEEP_CR_EEEP_TX;
2277 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2281 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2283 u32 ocp_data;
2285 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2286 if (enable)
2287 ocp_data |= RXDY_GATED_EN;
2288 else
2289 ocp_data &= ~RXDY_GATED_EN;
2290 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2293 static int rtl_start_rx(struct r8152 *tp)
2295 int i, ret = 0;
2297 INIT_LIST_HEAD(&tp->rx_done);
2298 for (i = 0; i < RTL8152_MAX_RX; i++) {
2299 INIT_LIST_HEAD(&tp->rx_info[i].list);
2300 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2301 if (ret)
2302 break;
2305 if (ret && ++i < RTL8152_MAX_RX) {
2306 struct list_head rx_queue;
2307 unsigned long flags;
2309 INIT_LIST_HEAD(&rx_queue);
2311 do {
2312 struct rx_agg *agg = &tp->rx_info[i++];
2313 struct urb *urb = agg->urb;
2315 urb->actual_length = 0;
2316 list_add_tail(&agg->list, &rx_queue);
2317 } while (i < RTL8152_MAX_RX);
2319 spin_lock_irqsave(&tp->rx_lock, flags);
2320 list_splice_tail(&rx_queue, &tp->rx_done);
2321 spin_unlock_irqrestore(&tp->rx_lock, flags);
2324 return ret;
2327 static int rtl_stop_rx(struct r8152 *tp)
2329 int i;
2331 for (i = 0; i < RTL8152_MAX_RX; i++)
2332 usb_kill_urb(tp->rx_info[i].urb);
2334 while (!skb_queue_empty(&tp->rx_queue))
2335 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2337 return 0;
2340 static int rtl_enable(struct r8152 *tp)
2342 u32 ocp_data;
2344 r8152b_reset_packet_filter(tp);
2346 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2347 ocp_data |= CR_RE | CR_TE;
2348 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2350 rxdy_gated_en(tp, false);
2352 return 0;
2355 static int rtl8152_enable(struct r8152 *tp)
2357 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2358 return -ENODEV;
2360 set_tx_qlen(tp);
2361 rtl_set_eee_plus(tp);
2363 return rtl_enable(tp);
2366 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2368 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2369 OWN_UPDATE | OWN_CLEAR);
2372 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2374 u32 ocp_data = tp->coalesce / 8;
2376 switch (tp->version) {
2377 case RTL_VER_03:
2378 case RTL_VER_04:
2379 case RTL_VER_05:
2380 case RTL_VER_06:
2381 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2382 ocp_data);
2383 break;
2385 case RTL_VER_08:
2386 case RTL_VER_09:
2387 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2388 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2390 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2391 128 / 8);
2392 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2393 ocp_data);
2394 r8153b_rx_agg_chg_indicate(tp);
2395 break;
2397 default:
2398 break;
2402 static void r8153_set_rx_early_size(struct r8152 *tp)
2404 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2406 switch (tp->version) {
2407 case RTL_VER_03:
2408 case RTL_VER_04:
2409 case RTL_VER_05:
2410 case RTL_VER_06:
2411 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2412 ocp_data / 4);
2413 break;
2414 case RTL_VER_08:
2415 case RTL_VER_09:
2416 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2417 ocp_data / 8);
2418 r8153b_rx_agg_chg_indicate(tp);
2419 break;
2420 default:
2421 WARN_ON_ONCE(1);
2422 break;
2426 static int rtl8153_enable(struct r8152 *tp)
2428 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2429 return -ENODEV;
2431 set_tx_qlen(tp);
2432 rtl_set_eee_plus(tp);
2433 r8153_set_rx_early_timeout(tp);
2434 r8153_set_rx_early_size(tp);
2436 return rtl_enable(tp);
2439 static void rtl_disable(struct r8152 *tp)
2441 u32 ocp_data;
2442 int i;
2444 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2445 rtl_drop_queued_tx(tp);
2446 return;
2449 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2450 ocp_data &= ~RCR_ACPT_ALL;
2451 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2453 rtl_drop_queued_tx(tp);
2455 for (i = 0; i < RTL8152_MAX_TX; i++)
2456 usb_kill_urb(tp->tx_info[i].urb);
2458 rxdy_gated_en(tp, true);
2460 for (i = 0; i < 1000; i++) {
2461 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2462 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2463 break;
2464 usleep_range(1000, 2000);
2467 for (i = 0; i < 1000; i++) {
2468 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2469 break;
2470 usleep_range(1000, 2000);
2473 rtl_stop_rx(tp);
2475 rtl8152_nic_reset(tp);
2478 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2480 u32 ocp_data;
2482 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2483 if (enable)
2484 ocp_data |= POWER_CUT;
2485 else
2486 ocp_data &= ~POWER_CUT;
2487 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2489 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2490 ocp_data &= ~RESUME_INDICATE;
2491 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2494 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2496 u32 ocp_data;
2498 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2499 if (enable)
2500 ocp_data |= CPCR_RX_VLAN;
2501 else
2502 ocp_data &= ~CPCR_RX_VLAN;
2503 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2506 static int rtl8152_set_features(struct net_device *dev,
2507 netdev_features_t features)
2509 netdev_features_t changed = features ^ dev->features;
2510 struct r8152 *tp = netdev_priv(dev);
2511 int ret;
2513 ret = usb_autopm_get_interface(tp->intf);
2514 if (ret < 0)
2515 goto out;
2517 mutex_lock(&tp->control);
2519 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2520 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2521 rtl_rx_vlan_en(tp, true);
2522 else
2523 rtl_rx_vlan_en(tp, false);
2526 mutex_unlock(&tp->control);
2528 usb_autopm_put_interface(tp->intf);
2530 out:
2531 return ret;
2534 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2536 static u32 __rtl_get_wol(struct r8152 *tp)
2538 u32 ocp_data;
2539 u32 wolopts = 0;
2541 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2542 if (ocp_data & LINK_ON_WAKE_EN)
2543 wolopts |= WAKE_PHY;
2545 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2546 if (ocp_data & UWF_EN)
2547 wolopts |= WAKE_UCAST;
2548 if (ocp_data & BWF_EN)
2549 wolopts |= WAKE_BCAST;
2550 if (ocp_data & MWF_EN)
2551 wolopts |= WAKE_MCAST;
2553 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2554 if (ocp_data & MAGIC_EN)
2555 wolopts |= WAKE_MAGIC;
2557 return wolopts;
2560 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2562 u32 ocp_data;
2564 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2566 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2567 ocp_data &= ~LINK_ON_WAKE_EN;
2568 if (wolopts & WAKE_PHY)
2569 ocp_data |= LINK_ON_WAKE_EN;
2570 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2572 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2573 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2574 if (wolopts & WAKE_UCAST)
2575 ocp_data |= UWF_EN;
2576 if (wolopts & WAKE_BCAST)
2577 ocp_data |= BWF_EN;
2578 if (wolopts & WAKE_MCAST)
2579 ocp_data |= MWF_EN;
2580 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2582 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2584 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2585 ocp_data &= ~MAGIC_EN;
2586 if (wolopts & WAKE_MAGIC)
2587 ocp_data |= MAGIC_EN;
2588 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2590 if (wolopts & WAKE_ANY)
2591 device_set_wakeup_enable(&tp->udev->dev, true);
2592 else
2593 device_set_wakeup_enable(&tp->udev->dev, false);
2596 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2598 /* MAC clock speed down */
2599 if (enable) {
2600 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2601 ALDPS_SPDWN_RATIO);
2602 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2603 EEE_SPDWN_RATIO);
2604 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2605 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2606 U1U2_SPDWN_EN | L1_SPDWN_EN);
2607 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2608 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2609 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2610 TP1000_SPDWN_EN);
2611 } else {
2612 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2613 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2614 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2615 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2619 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2621 u8 u1u2[8];
2623 if (enable)
2624 memset(u1u2, 0xff, sizeof(u1u2));
2625 else
2626 memset(u1u2, 0x00, sizeof(u1u2));
2628 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2631 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2633 u32 ocp_data;
2635 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2636 if (enable)
2637 ocp_data |= LPM_U1U2_EN;
2638 else
2639 ocp_data &= ~LPM_U1U2_EN;
2641 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2644 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2646 u32 ocp_data;
2648 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2649 if (enable)
2650 ocp_data |= U2P3_ENABLE;
2651 else
2652 ocp_data &= ~U2P3_ENABLE;
2653 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2656 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2658 u32 ocp_data;
2660 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2661 ocp_data &= ~clear;
2662 ocp_data |= set;
2663 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2666 static void r8153b_green_en(struct r8152 *tp, bool enable)
2668 u16 data;
2670 if (enable) {
2671 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
2672 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2673 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2674 } else {
2675 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2676 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2677 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2680 data = sram_read(tp, SRAM_GREEN_CFG);
2681 data |= GREEN_ETH_EN;
2682 sram_write(tp, SRAM_GREEN_CFG, data);
2684 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2687 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2689 u16 data;
2690 int i;
2692 for (i = 0; i < 500; i++) {
2693 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2694 data &= PHY_STAT_MASK;
2695 if (desired) {
2696 if (data == desired)
2697 break;
2698 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2699 data == PHY_STAT_EXT_INIT) {
2700 break;
2703 msleep(20);
2704 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2705 break;
2708 return data;
2711 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2713 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2715 if (enable) {
2716 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2717 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2719 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2720 ocp_data |= BIT(0);
2721 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2722 } else {
2723 u16 data;
2725 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2726 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2728 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2729 ocp_data &= ~BIT(0);
2730 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2732 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2733 ocp_data &= ~PCUT_STATUS;
2734 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2736 data = r8153_phy_status(tp, 0);
2738 switch (data) {
2739 case PHY_STAT_PWRDN:
2740 case PHY_STAT_EXT_INIT:
2741 r8153b_green_en(tp,
2742 test_bit(GREEN_ETHERNET, &tp->flags));
2744 data = r8152_mdio_read(tp, MII_BMCR);
2745 data &= ~BMCR_PDOWN;
2746 data |= BMCR_RESET;
2747 r8152_mdio_write(tp, MII_BMCR, data);
2749 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2750 /* fall through */
2752 default:
2753 if (data != PHY_STAT_LAN_ON)
2754 netif_warn(tp, link, tp->netdev,
2755 "PHY not ready");
2756 break;
2761 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2763 u32 ocp_data;
2765 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2766 if (enable)
2767 ocp_data |= PWR_EN | PHASE2_EN;
2768 else
2769 ocp_data &= ~(PWR_EN | PHASE2_EN);
2770 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2772 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2773 ocp_data &= ~PCUT_STATUS;
2774 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2777 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2779 u32 ocp_data;
2781 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2782 if (enable)
2783 ocp_data |= PWR_EN | PHASE2_EN;
2784 else
2785 ocp_data &= ~PWR_EN;
2786 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2788 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2789 ocp_data &= ~PCUT_STATUS;
2790 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2793 static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2795 u32 ocp_data;
2797 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2798 if (enable)
2799 ocp_data |= BIT(0);
2800 else
2801 ocp_data &= ~BIT(0);
2802 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2804 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2805 ocp_data &= ~BIT(0);
2806 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
2809 static bool rtl_can_wakeup(struct r8152 *tp)
2811 struct usb_device *udev = tp->udev;
2813 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2816 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2818 if (enable) {
2819 u32 ocp_data;
2821 __rtl_set_wol(tp, WAKE_ANY);
2823 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2825 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2826 ocp_data |= LINK_OFF_WAKE_EN;
2827 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2829 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2830 } else {
2831 u32 ocp_data;
2833 __rtl_set_wol(tp, tp->saved_wolopts);
2835 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2837 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2838 ocp_data &= ~LINK_OFF_WAKE_EN;
2839 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2841 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2845 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2847 if (enable) {
2848 r8153_u1u2en(tp, false);
2849 r8153_u2p3en(tp, false);
2850 r8153_mac_clk_spd(tp, true);
2851 rtl_runtime_suspend_enable(tp, true);
2852 } else {
2853 rtl_runtime_suspend_enable(tp, false);
2854 r8153_mac_clk_spd(tp, false);
2856 switch (tp->version) {
2857 case RTL_VER_03:
2858 case RTL_VER_04:
2859 break;
2860 case RTL_VER_05:
2861 case RTL_VER_06:
2862 default:
2863 r8153_u2p3en(tp, true);
2864 break;
2867 r8153_u1u2en(tp, true);
2871 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2873 if (enable) {
2874 r8153b_queue_wake(tp, true);
2875 r8153b_u1u2en(tp, false);
2876 r8153_u2p3en(tp, false);
2877 rtl_runtime_suspend_enable(tp, true);
2878 r8153b_ups_en(tp, true);
2879 } else {
2880 r8153b_ups_en(tp, false);
2881 r8153b_queue_wake(tp, false);
2882 rtl_runtime_suspend_enable(tp, false);
2883 r8153_u2p3en(tp, true);
2884 r8153b_u1u2en(tp, true);
2888 static void r8153_teredo_off(struct r8152 *tp)
2890 u32 ocp_data;
2892 switch (tp->version) {
2893 case RTL_VER_01:
2894 case RTL_VER_02:
2895 case RTL_VER_03:
2896 case RTL_VER_04:
2897 case RTL_VER_05:
2898 case RTL_VER_06:
2899 case RTL_VER_07:
2900 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2901 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2902 OOB_TEREDO_EN);
2903 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2904 break;
2906 case RTL_VER_08:
2907 case RTL_VER_09:
2908 /* The bit 0 ~ 7 are relative with teredo settings. They are
2909 * W1C (write 1 to clear), so set all 1 to disable it.
2911 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2912 break;
2914 default:
2915 break;
2918 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2919 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2920 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2923 static void rtl_reset_bmu(struct r8152 *tp)
2925 u32 ocp_data;
2927 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2928 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2929 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2930 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2931 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2934 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2936 if (enable) {
2937 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2938 LINKENA | DIS_SDSAVE);
2939 } else {
2940 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2941 DIS_SDSAVE);
2942 msleep(20);
2946 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2948 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2949 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2950 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2953 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2955 u16 data;
2957 r8152_mmd_indirect(tp, dev, reg);
2958 data = ocp_reg_read(tp, OCP_EEE_DATA);
2959 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2961 return data;
2964 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2966 r8152_mmd_indirect(tp, dev, reg);
2967 ocp_reg_write(tp, OCP_EEE_DATA, data);
2968 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2971 static void r8152_eee_en(struct r8152 *tp, bool enable)
2973 u16 config1, config2, config3;
2974 u32 ocp_data;
2976 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2977 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2978 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2979 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2981 if (enable) {
2982 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2983 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2984 config1 |= sd_rise_time(1);
2985 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2986 config3 |= fast_snr(42);
2987 } else {
2988 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2989 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2990 RX_QUIET_EN);
2991 config1 |= sd_rise_time(7);
2992 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2993 config3 |= fast_snr(511);
2996 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2997 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
2998 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
2999 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3002 static void r8152b_enable_eee(struct r8152 *tp)
3004 r8152_eee_en(tp, true);
3005 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3008 static void r8152b_enable_fc(struct r8152 *tp)
3010 u16 anar;
3012 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3013 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3014 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3017 static void rtl8152_disable(struct r8152 *tp)
3019 r8152_aldps_en(tp, false);
3020 rtl_disable(tp);
3021 r8152_aldps_en(tp, true);
3024 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3026 r8152b_enable_eee(tp);
3027 r8152_aldps_en(tp, true);
3028 r8152b_enable_fc(tp);
3030 set_bit(PHY_RESET, &tp->flags);
3033 static void r8152b_exit_oob(struct r8152 *tp)
3035 u32 ocp_data;
3036 int i;
3038 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3039 ocp_data &= ~RCR_ACPT_ALL;
3040 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3042 rxdy_gated_en(tp, true);
3043 r8153_teredo_off(tp);
3044 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3045 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3047 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3048 ocp_data &= ~NOW_IS_OOB;
3049 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3051 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3052 ocp_data &= ~MCU_BORW_EN;
3053 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3055 for (i = 0; i < 1000; i++) {
3056 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3057 if (ocp_data & LINK_LIST_READY)
3058 break;
3059 usleep_range(1000, 2000);
3062 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3063 ocp_data |= RE_INIT_LL;
3064 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3066 for (i = 0; i < 1000; i++) {
3067 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3068 if (ocp_data & LINK_LIST_READY)
3069 break;
3070 usleep_range(1000, 2000);
3073 rtl8152_nic_reset(tp);
3075 /* rx share fifo credit full threshold */
3076 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3078 if (tp->udev->speed == USB_SPEED_FULL ||
3079 tp->udev->speed == USB_SPEED_LOW) {
3080 /* rx share fifo credit near full threshold */
3081 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3082 RXFIFO_THR2_FULL);
3083 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3084 RXFIFO_THR3_FULL);
3085 } else {
3086 /* rx share fifo credit near full threshold */
3087 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3088 RXFIFO_THR2_HIGH);
3089 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3090 RXFIFO_THR3_HIGH);
3093 /* TX share fifo free credit full threshold */
3094 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3096 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3097 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3098 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3099 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3101 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3103 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3105 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3106 ocp_data |= TCR0_AUTO_FIFO;
3107 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3110 static void r8152b_enter_oob(struct r8152 *tp)
3112 u32 ocp_data;
3113 int i;
3115 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3116 ocp_data &= ~NOW_IS_OOB;
3117 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3119 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3120 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3121 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3123 rtl_disable(tp);
3125 for (i = 0; i < 1000; i++) {
3126 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3127 if (ocp_data & LINK_LIST_READY)
3128 break;
3129 usleep_range(1000, 2000);
3132 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3133 ocp_data |= RE_INIT_LL;
3134 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3136 for (i = 0; i < 1000; i++) {
3137 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3138 if (ocp_data & LINK_LIST_READY)
3139 break;
3140 usleep_range(1000, 2000);
3143 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3145 rtl_rx_vlan_en(tp, true);
3147 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3148 ocp_data |= ALDPS_PROXY_MODE;
3149 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3151 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3152 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3153 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3155 rxdy_gated_en(tp, false);
3157 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3158 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3159 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3162 static int r8153_patch_request(struct r8152 *tp, bool request)
3164 u16 data;
3165 int i;
3167 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3168 if (request)
3169 data |= PATCH_REQUEST;
3170 else
3171 data &= ~PATCH_REQUEST;
3172 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3174 for (i = 0; request && i < 5000; i++) {
3175 usleep_range(1000, 2000);
3176 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3177 break;
3180 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3181 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3182 r8153_patch_request(tp, false);
3183 return -ETIME;
3184 } else {
3185 return 0;
3189 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3191 u16 data;
3193 data = ocp_reg_read(tp, OCP_POWER_CFG);
3194 if (enable) {
3195 data |= EN_ALDPS;
3196 ocp_reg_write(tp, OCP_POWER_CFG, data);
3197 } else {
3198 int i;
3200 data &= ~EN_ALDPS;
3201 ocp_reg_write(tp, OCP_POWER_CFG, data);
3202 for (i = 0; i < 20; i++) {
3203 usleep_range(1000, 2000);
3204 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3205 break;
3210 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3212 r8153_aldps_en(tp, enable);
3214 if (enable)
3215 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3216 else
3217 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3220 static void r8153_eee_en(struct r8152 *tp, bool enable)
3222 u32 ocp_data;
3223 u16 config;
3225 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3226 config = ocp_reg_read(tp, OCP_EEE_CFG);
3228 if (enable) {
3229 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3230 config |= EEE10_EN;
3231 } else {
3232 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3233 config &= ~EEE10_EN;
3236 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3237 ocp_reg_write(tp, OCP_EEE_CFG, config);
3240 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3242 r8153_eee_en(tp, enable);
3244 if (enable)
3245 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3246 else
3247 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3250 static void r8153b_enable_fc(struct r8152 *tp)
3252 r8152b_enable_fc(tp);
3253 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3256 static void r8153_hw_phy_cfg(struct r8152 *tp)
3258 u32 ocp_data;
3259 u16 data;
3261 /* disable ALDPS before updating the PHY parameters */
3262 r8153_aldps_en(tp, false);
3264 /* disable EEE before updating the PHY parameters */
3265 r8153_eee_en(tp, false);
3266 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3268 if (tp->version == RTL_VER_03) {
3269 data = ocp_reg_read(tp, OCP_EEE_CFG);
3270 data &= ~CTAP_SHORT_EN;
3271 ocp_reg_write(tp, OCP_EEE_CFG, data);
3274 data = ocp_reg_read(tp, OCP_POWER_CFG);
3275 data |= EEE_CLKDIV_EN;
3276 ocp_reg_write(tp, OCP_POWER_CFG, data);
3278 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3279 data |= EN_10M_BGOFF;
3280 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3281 data = ocp_reg_read(tp, OCP_POWER_CFG);
3282 data |= EN_10M_PLLOFF;
3283 ocp_reg_write(tp, OCP_POWER_CFG, data);
3284 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3286 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3287 ocp_data |= PFM_PWM_SWITCH;
3288 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3290 /* Enable LPF corner auto tune */
3291 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3293 /* Adjust 10M Amplitude */
3294 sram_write(tp, SRAM_10M_AMP1, 0x00af);
3295 sram_write(tp, SRAM_10M_AMP2, 0x0208);
3297 r8153_eee_en(tp, true);
3298 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3300 r8153_aldps_en(tp, true);
3301 r8152b_enable_fc(tp);
3303 switch (tp->version) {
3304 case RTL_VER_03:
3305 case RTL_VER_04:
3306 break;
3307 case RTL_VER_05:
3308 case RTL_VER_06:
3309 default:
3310 r8153_u2p3en(tp, true);
3311 break;
3314 set_bit(PHY_RESET, &tp->flags);
3317 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3319 u32 ocp_data;
3321 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3322 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3323 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
3324 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3326 return ocp_data;
3329 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3331 u32 ocp_data, ups_flags = 0;
3332 u16 data;
3334 /* disable ALDPS before updating the PHY parameters */
3335 r8153b_aldps_en(tp, false);
3337 /* disable EEE before updating the PHY parameters */
3338 r8153b_eee_en(tp, false);
3339 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3341 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3343 data = sram_read(tp, SRAM_GREEN_CFG);
3344 data |= R_TUNE_EN;
3345 sram_write(tp, SRAM_GREEN_CFG, data);
3346 data = ocp_reg_read(tp, OCP_NCTL_CFG);
3347 data |= PGA_RETURN_EN;
3348 ocp_reg_write(tp, OCP_NCTL_CFG, data);
3350 /* ADC Bias Calibration:
3351 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3352 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3353 * ADC ioffset.
3355 ocp_data = r8152_efuse_read(tp, 0x7d);
3356 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3357 if (data != 0xffff)
3358 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3360 /* ups mode tx-link-pulse timing adjustment:
3361 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3362 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3364 ocp_data = ocp_reg_read(tp, 0xc426);
3365 ocp_data &= 0x3fff;
3366 if (ocp_data) {
3367 u32 swr_cnt_1ms_ini;
3369 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3370 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3371 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3372 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3375 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3376 ocp_data |= PFM_PWM_SWITCH;
3377 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3379 /* Advnace EEE */
3380 if (!r8153_patch_request(tp, true)) {
3381 data = ocp_reg_read(tp, OCP_POWER_CFG);
3382 data |= EEE_CLKDIV_EN;
3383 ocp_reg_write(tp, OCP_POWER_CFG, data);
3385 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3386 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3387 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3389 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3390 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3392 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3393 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3394 UPS_FLAGS_EEE_PLLOFF_GIGA;
3396 r8153_patch_request(tp, false);
3399 r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3401 r8153b_eee_en(tp, true);
3402 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3404 r8153b_aldps_en(tp, true);
3405 r8153b_enable_fc(tp);
3406 r8153_u2p3en(tp, true);
3408 set_bit(PHY_RESET, &tp->flags);
3411 static void r8153_first_init(struct r8152 *tp)
3413 u32 ocp_data;
3414 int i;
3416 r8153_mac_clk_spd(tp, false);
3417 rxdy_gated_en(tp, true);
3418 r8153_teredo_off(tp);
3420 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3421 ocp_data &= ~RCR_ACPT_ALL;
3422 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3424 rtl8152_nic_reset(tp);
3425 rtl_reset_bmu(tp);
3427 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3428 ocp_data &= ~NOW_IS_OOB;
3429 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3431 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3432 ocp_data &= ~MCU_BORW_EN;
3433 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3435 for (i = 0; i < 1000; i++) {
3436 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3437 if (ocp_data & LINK_LIST_READY)
3438 break;
3439 usleep_range(1000, 2000);
3442 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3443 ocp_data |= RE_INIT_LL;
3444 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3446 for (i = 0; i < 1000; i++) {
3447 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3448 if (ocp_data & LINK_LIST_READY)
3449 break;
3450 usleep_range(1000, 2000);
3453 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3455 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3457 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3459 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3460 ocp_data |= TCR0_AUTO_FIFO;
3461 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3463 rtl8152_nic_reset(tp);
3465 /* rx share fifo credit full threshold */
3466 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3467 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3468 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3469 /* TX share fifo free credit full threshold */
3470 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3473 static void r8153_enter_oob(struct r8152 *tp)
3475 u32 ocp_data;
3476 int i;
3478 r8153_mac_clk_spd(tp, true);
3480 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3481 ocp_data &= ~NOW_IS_OOB;
3482 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3484 rtl_disable(tp);
3485 rtl_reset_bmu(tp);
3487 for (i = 0; i < 1000; i++) {
3488 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3489 if (ocp_data & LINK_LIST_READY)
3490 break;
3491 usleep_range(1000, 2000);
3494 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3495 ocp_data |= RE_INIT_LL;
3496 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3498 for (i = 0; i < 1000; i++) {
3499 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3500 if (ocp_data & LINK_LIST_READY)
3501 break;
3502 usleep_range(1000, 2000);
3505 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3506 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3508 switch (tp->version) {
3509 case RTL_VER_03:
3510 case RTL_VER_04:
3511 case RTL_VER_05:
3512 case RTL_VER_06:
3513 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3514 ocp_data &= ~TEREDO_WAKE_MASK;
3515 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3516 break;
3518 case RTL_VER_08:
3519 case RTL_VER_09:
3520 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3521 * type. Set it to zero. bits[7:0] are the W1C bits about
3522 * the events. Set them to all 1 to clear them.
3524 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3525 break;
3527 default:
3528 break;
3531 rtl_rx_vlan_en(tp, true);
3533 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3534 ocp_data |= ALDPS_PROXY_MODE;
3535 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3537 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3538 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3539 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3541 rxdy_gated_en(tp, false);
3543 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3544 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3545 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3548 static void rtl8153_disable(struct r8152 *tp)
3550 r8153_aldps_en(tp, false);
3551 rtl_disable(tp);
3552 rtl_reset_bmu(tp);
3553 r8153_aldps_en(tp, true);
3556 static void rtl8153b_disable(struct r8152 *tp)
3558 r8153b_aldps_en(tp, false);
3559 rtl_disable(tp);
3560 rtl_reset_bmu(tp);
3561 r8153b_aldps_en(tp, true);
3564 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3566 u16 bmcr, anar, gbcr;
3567 enum spd_duplex speed_duplex;
3568 int ret = 0;
3570 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3571 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3572 ADVERTISE_100HALF | ADVERTISE_100FULL);
3573 if (tp->mii.supports_gmii) {
3574 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3575 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3576 } else {
3577 gbcr = 0;
3580 if (autoneg == AUTONEG_DISABLE) {
3581 if (speed == SPEED_10) {
3582 bmcr = 0;
3583 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3584 speed_duplex = FORCE_10M_HALF;
3585 } else if (speed == SPEED_100) {
3586 bmcr = BMCR_SPEED100;
3587 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3588 speed_duplex = FORCE_100M_HALF;
3589 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3590 bmcr = BMCR_SPEED1000;
3591 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3592 speed_duplex = NWAY_1000M_FULL;
3593 } else {
3594 ret = -EINVAL;
3595 goto out;
3598 if (duplex == DUPLEX_FULL) {
3599 bmcr |= BMCR_FULLDPLX;
3600 if (speed != SPEED_1000)
3601 speed_duplex++;
3603 } else {
3604 if (speed == SPEED_10) {
3605 if (duplex == DUPLEX_FULL) {
3606 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3607 speed_duplex = NWAY_10M_FULL;
3608 } else {
3609 anar |= ADVERTISE_10HALF;
3610 speed_duplex = NWAY_10M_HALF;
3612 } else if (speed == SPEED_100) {
3613 if (duplex == DUPLEX_FULL) {
3614 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3615 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3616 speed_duplex = NWAY_100M_FULL;
3617 } else {
3618 anar |= ADVERTISE_10HALF;
3619 anar |= ADVERTISE_100HALF;
3620 speed_duplex = NWAY_100M_HALF;
3622 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3623 if (duplex == DUPLEX_FULL) {
3624 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3625 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3626 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3627 } else {
3628 anar |= ADVERTISE_10HALF;
3629 anar |= ADVERTISE_100HALF;
3630 gbcr |= ADVERTISE_1000HALF;
3632 speed_duplex = NWAY_1000M_FULL;
3633 } else {
3634 ret = -EINVAL;
3635 goto out;
3638 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3641 if (test_and_clear_bit(PHY_RESET, &tp->flags))
3642 bmcr |= BMCR_RESET;
3644 if (tp->mii.supports_gmii)
3645 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3647 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3648 r8152_mdio_write(tp, MII_BMCR, bmcr);
3650 switch (tp->version) {
3651 case RTL_VER_08:
3652 case RTL_VER_09:
3653 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3654 UPS_FLAGS_SPEED_MASK);
3655 break;
3657 default:
3658 break;
3661 if (bmcr & BMCR_RESET) {
3662 int i;
3664 for (i = 0; i < 50; i++) {
3665 msleep(20);
3666 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3667 break;
3671 out:
3672 return ret;
3675 static void rtl8152_up(struct r8152 *tp)
3677 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3678 return;
3680 r8152_aldps_en(tp, false);
3681 r8152b_exit_oob(tp);
3682 r8152_aldps_en(tp, true);
3685 static void rtl8152_down(struct r8152 *tp)
3687 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3688 rtl_drop_queued_tx(tp);
3689 return;
3692 r8152_power_cut_en(tp, false);
3693 r8152_aldps_en(tp, false);
3694 r8152b_enter_oob(tp);
3695 r8152_aldps_en(tp, true);
3698 static void rtl8153_up(struct r8152 *tp)
3700 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3701 return;
3703 r8153_u1u2en(tp, false);
3704 r8153_u2p3en(tp, false);
3705 r8153_aldps_en(tp, false);
3706 r8153_first_init(tp);
3707 r8153_aldps_en(tp, true);
3709 switch (tp->version) {
3710 case RTL_VER_03:
3711 case RTL_VER_04:
3712 break;
3713 case RTL_VER_05:
3714 case RTL_VER_06:
3715 default:
3716 r8153_u2p3en(tp, true);
3717 break;
3720 r8153_u1u2en(tp, true);
3723 static void rtl8153_down(struct r8152 *tp)
3725 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3726 rtl_drop_queued_tx(tp);
3727 return;
3730 r8153_u1u2en(tp, false);
3731 r8153_u2p3en(tp, false);
3732 r8153_power_cut_en(tp, false);
3733 r8153_aldps_en(tp, false);
3734 r8153_enter_oob(tp);
3735 r8153_aldps_en(tp, true);
3738 static void rtl8153b_up(struct r8152 *tp)
3740 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3741 return;
3743 r8153b_u1u2en(tp, false);
3744 r8153_u2p3en(tp, false);
3745 r8153b_aldps_en(tp, false);
3747 r8153_first_init(tp);
3748 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3750 r8153b_aldps_en(tp, true);
3751 r8153_u2p3en(tp, true);
3752 r8153b_u1u2en(tp, true);
3755 static void rtl8153b_down(struct r8152 *tp)
3757 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3758 rtl_drop_queued_tx(tp);
3759 return;
3762 r8153b_u1u2en(tp, false);
3763 r8153_u2p3en(tp, false);
3764 r8153b_power_cut_en(tp, false);
3765 r8153b_aldps_en(tp, false);
3766 r8153_enter_oob(tp);
3767 r8153b_aldps_en(tp, true);
3770 static bool rtl8152_in_nway(struct r8152 *tp)
3772 u16 nway_state;
3774 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3775 tp->ocp_base = 0x2000;
3776 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3777 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3779 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3780 if (nway_state & 0xc000)
3781 return false;
3782 else
3783 return true;
3786 static bool rtl8153_in_nway(struct r8152 *tp)
3788 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3790 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3791 return false;
3792 else
3793 return true;
3796 static void set_carrier(struct r8152 *tp)
3798 struct net_device *netdev = tp->netdev;
3799 struct napi_struct *napi = &tp->napi;
3800 u8 speed;
3802 speed = rtl8152_get_speed(tp);
3804 if (speed & LINK_STATUS) {
3805 if (!netif_carrier_ok(netdev)) {
3806 tp->rtl_ops.enable(tp);
3807 netif_stop_queue(netdev);
3808 napi_disable(napi);
3809 netif_carrier_on(netdev);
3810 rtl_start_rx(tp);
3811 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
3812 _rtl8152_set_rx_mode(netdev);
3813 napi_enable(&tp->napi);
3814 netif_wake_queue(netdev);
3815 netif_info(tp, link, netdev, "carrier on\n");
3816 } else if (netif_queue_stopped(netdev) &&
3817 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3818 netif_wake_queue(netdev);
3820 } else {
3821 if (netif_carrier_ok(netdev)) {
3822 netif_carrier_off(netdev);
3823 napi_disable(napi);
3824 tp->rtl_ops.disable(tp);
3825 napi_enable(napi);
3826 netif_info(tp, link, netdev, "carrier off\n");
3831 static void rtl_work_func_t(struct work_struct *work)
3833 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3835 /* If the device is unplugged or !netif_running(), the workqueue
3836 * doesn't need to wake the device, and could return directly.
3838 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3839 return;
3841 if (usb_autopm_get_interface(tp->intf) < 0)
3842 return;
3844 if (!test_bit(WORK_ENABLE, &tp->flags))
3845 goto out1;
3847 if (!mutex_trylock(&tp->control)) {
3848 schedule_delayed_work(&tp->schedule, 0);
3849 goto out1;
3852 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3853 set_carrier(tp);
3855 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3856 _rtl8152_set_rx_mode(tp->netdev);
3858 /* don't schedule napi before linking */
3859 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3860 netif_carrier_ok(tp->netdev))
3861 napi_schedule(&tp->napi);
3863 mutex_unlock(&tp->control);
3865 out1:
3866 usb_autopm_put_interface(tp->intf);
3869 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3871 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3873 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3874 return;
3876 if (usb_autopm_get_interface(tp->intf) < 0)
3877 return;
3879 mutex_lock(&tp->control);
3881 tp->rtl_ops.hw_phy_cfg(tp);
3883 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3885 mutex_unlock(&tp->control);
3887 usb_autopm_put_interface(tp->intf);
3890 #ifdef CONFIG_PM_SLEEP
3891 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3892 void *data)
3894 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3896 switch (action) {
3897 case PM_HIBERNATION_PREPARE:
3898 case PM_SUSPEND_PREPARE:
3899 usb_autopm_get_interface(tp->intf);
3900 break;
3902 case PM_POST_HIBERNATION:
3903 case PM_POST_SUSPEND:
3904 usb_autopm_put_interface(tp->intf);
3905 break;
3907 case PM_POST_RESTORE:
3908 case PM_RESTORE_PREPARE:
3909 default:
3910 break;
3913 return NOTIFY_DONE;
3915 #endif
3917 static int rtl8152_open(struct net_device *netdev)
3919 struct r8152 *tp = netdev_priv(netdev);
3920 int res = 0;
3922 res = alloc_all_mem(tp);
3923 if (res)
3924 goto out;
3926 res = usb_autopm_get_interface(tp->intf);
3927 if (res < 0)
3928 goto out_free;
3930 mutex_lock(&tp->control);
3932 tp->rtl_ops.up(tp);
3934 netif_carrier_off(netdev);
3935 netif_start_queue(netdev);
3936 set_bit(WORK_ENABLE, &tp->flags);
3938 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3939 if (res) {
3940 if (res == -ENODEV)
3941 netif_device_detach(tp->netdev);
3942 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3943 res);
3944 goto out_unlock;
3946 napi_enable(&tp->napi);
3948 mutex_unlock(&tp->control);
3950 usb_autopm_put_interface(tp->intf);
3951 #ifdef CONFIG_PM_SLEEP
3952 tp->pm_notifier.notifier_call = rtl_notifier;
3953 register_pm_notifier(&tp->pm_notifier);
3954 #endif
3955 return 0;
3957 out_unlock:
3958 mutex_unlock(&tp->control);
3959 usb_autopm_put_interface(tp->intf);
3960 out_free:
3961 free_all_mem(tp);
3962 out:
3963 return res;
3966 static int rtl8152_close(struct net_device *netdev)
3968 struct r8152 *tp = netdev_priv(netdev);
3969 int res = 0;
3971 #ifdef CONFIG_PM_SLEEP
3972 unregister_pm_notifier(&tp->pm_notifier);
3973 #endif
3974 if (!test_bit(RTL8152_UNPLUG, &tp->flags))
3975 napi_disable(&tp->napi);
3976 clear_bit(WORK_ENABLE, &tp->flags);
3977 usb_kill_urb(tp->intr_urb);
3978 cancel_delayed_work_sync(&tp->schedule);
3979 netif_stop_queue(netdev);
3981 res = usb_autopm_get_interface(tp->intf);
3982 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3983 rtl_drop_queued_tx(tp);
3984 rtl_stop_rx(tp);
3985 } else {
3986 mutex_lock(&tp->control);
3988 tp->rtl_ops.down(tp);
3990 mutex_unlock(&tp->control);
3992 usb_autopm_put_interface(tp->intf);
3995 free_all_mem(tp);
3997 return res;
4000 static void rtl_tally_reset(struct r8152 *tp)
4002 u32 ocp_data;
4004 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
4005 ocp_data |= TALLY_RESET;
4006 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
4009 static void r8152b_init(struct r8152 *tp)
4011 u32 ocp_data;
4012 u16 data;
4014 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4015 return;
4017 data = r8152_mdio_read(tp, MII_BMCR);
4018 if (data & BMCR_PDOWN) {
4019 data &= ~BMCR_PDOWN;
4020 r8152_mdio_write(tp, MII_BMCR, data);
4023 r8152_aldps_en(tp, false);
4025 if (tp->version == RTL_VER_01) {
4026 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4027 ocp_data &= ~LED_MODE_MASK;
4028 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4031 r8152_power_cut_en(tp, false);
4033 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4034 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4035 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4036 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4037 ocp_data &= ~MCU_CLK_RATIO_MASK;
4038 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4039 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4040 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4041 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4042 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4044 rtl_tally_reset(tp);
4046 /* enable rx aggregation */
4047 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4048 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4049 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4052 static void r8153_init(struct r8152 *tp)
4054 u32 ocp_data;
4055 u16 data;
4056 int i;
4058 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4059 return;
4061 r8153_u1u2en(tp, false);
4063 for (i = 0; i < 500; i++) {
4064 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4065 AUTOLOAD_DONE)
4066 break;
4068 msleep(20);
4069 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4070 break;
4073 data = r8153_phy_status(tp, 0);
4075 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4076 tp->version == RTL_VER_05)
4077 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4079 data = r8152_mdio_read(tp, MII_BMCR);
4080 if (data & BMCR_PDOWN) {
4081 data &= ~BMCR_PDOWN;
4082 r8152_mdio_write(tp, MII_BMCR, data);
4085 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4087 r8153_u2p3en(tp, false);
4089 if (tp->version == RTL_VER_04) {
4090 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4091 ocp_data &= ~pwd_dn_scale_mask;
4092 ocp_data |= pwd_dn_scale(96);
4093 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4095 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4096 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4097 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4098 } else if (tp->version == RTL_VER_05) {
4099 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4100 ocp_data &= ~ECM_ALDPS;
4101 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4103 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4104 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4105 ocp_data &= ~DYNAMIC_BURST;
4106 else
4107 ocp_data |= DYNAMIC_BURST;
4108 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4109 } else if (tp->version == RTL_VER_06) {
4110 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4111 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4112 ocp_data &= ~DYNAMIC_BURST;
4113 else
4114 ocp_data |= DYNAMIC_BURST;
4115 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4118 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4119 ocp_data |= EP4_FULL_FC;
4120 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4122 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4123 ocp_data &= ~TIMER11_EN;
4124 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4126 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4127 ocp_data &= ~LED_MODE_MASK;
4128 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4130 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4131 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4132 ocp_data |= LPM_TIMER_500MS;
4133 else
4134 ocp_data |= LPM_TIMER_500US;
4135 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4137 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4138 ocp_data &= ~SEN_VAL_MASK;
4139 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4140 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4142 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4144 r8153_power_cut_en(tp, false);
4145 r8153_u1u2en(tp, true);
4146 r8153_mac_clk_spd(tp, false);
4147 usb_enable_lpm(tp->udev);
4149 /* rx aggregation */
4150 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4151 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4152 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
4153 ocp_data |= RX_AGG_DISABLE;
4155 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4157 rtl_tally_reset(tp);
4159 switch (tp->udev->speed) {
4160 case USB_SPEED_SUPER:
4161 case USB_SPEED_SUPER_PLUS:
4162 tp->coalesce = COALESCE_SUPER;
4163 break;
4164 case USB_SPEED_HIGH:
4165 tp->coalesce = COALESCE_HIGH;
4166 break;
4167 default:
4168 tp->coalesce = COALESCE_SLOW;
4169 break;
4173 static void r8153b_init(struct r8152 *tp)
4175 u32 ocp_data;
4176 u16 data;
4177 int i;
4179 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4180 return;
4182 r8153b_u1u2en(tp, false);
4184 for (i = 0; i < 500; i++) {
4185 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4186 AUTOLOAD_DONE)
4187 break;
4189 msleep(20);
4190 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4191 break;
4194 data = r8153_phy_status(tp, 0);
4196 data = r8152_mdio_read(tp, MII_BMCR);
4197 if (data & BMCR_PDOWN) {
4198 data &= ~BMCR_PDOWN;
4199 r8152_mdio_write(tp, MII_BMCR, data);
4202 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4204 r8153_u2p3en(tp, false);
4206 /* MSC timer = 0xfff * 8ms = 32760 ms */
4207 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4209 /* U1/U2/L1 idle timer. 500 us */
4210 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4212 r8153b_power_cut_en(tp, false);
4213 r8153b_ups_en(tp, false);
4214 r8153b_queue_wake(tp, false);
4215 rtl_runtime_suspend_enable(tp, false);
4216 r8153b_u1u2en(tp, true);
4217 usb_enable_lpm(tp->udev);
4219 /* MAC clock speed down */
4220 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4221 ocp_data |= MAC_CLK_SPDWN_EN;
4222 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4224 set_bit(GREEN_ETHERNET, &tp->flags);
4226 /* rx aggregation */
4227 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4228 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4229 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4231 rtl_tally_reset(tp);
4233 tp->coalesce = 15000; /* 15 us */
4236 static int rtl8152_pre_reset(struct usb_interface *intf)
4238 struct r8152 *tp = usb_get_intfdata(intf);
4239 struct net_device *netdev;
4241 if (!tp)
4242 return 0;
4244 netdev = tp->netdev;
4245 if (!netif_running(netdev))
4246 return 0;
4248 netif_stop_queue(netdev);
4249 napi_disable(&tp->napi);
4250 clear_bit(WORK_ENABLE, &tp->flags);
4251 usb_kill_urb(tp->intr_urb);
4252 cancel_delayed_work_sync(&tp->schedule);
4253 if (netif_carrier_ok(netdev)) {
4254 mutex_lock(&tp->control);
4255 tp->rtl_ops.disable(tp);
4256 mutex_unlock(&tp->control);
4259 return 0;
4262 static int rtl8152_post_reset(struct usb_interface *intf)
4264 struct r8152 *tp = usb_get_intfdata(intf);
4265 struct net_device *netdev;
4267 if (!tp)
4268 return 0;
4270 netdev = tp->netdev;
4271 if (!netif_running(netdev))
4272 return 0;
4274 set_bit(WORK_ENABLE, &tp->flags);
4275 if (netif_carrier_ok(netdev)) {
4276 mutex_lock(&tp->control);
4277 tp->rtl_ops.enable(tp);
4278 rtl_start_rx(tp);
4279 _rtl8152_set_rx_mode(netdev);
4280 mutex_unlock(&tp->control);
4283 napi_enable(&tp->napi);
4284 netif_wake_queue(netdev);
4285 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4287 if (!list_empty(&tp->rx_done))
4288 napi_schedule(&tp->napi);
4290 return 0;
4293 static bool delay_autosuspend(struct r8152 *tp)
4295 bool sw_linking = !!netif_carrier_ok(tp->netdev);
4296 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4298 /* This means a linking change occurs and the driver doesn't detect it,
4299 * yet. If the driver has disabled tx/rx and hw is linking on, the
4300 * device wouldn't wake up by receiving any packet.
4302 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4303 return true;
4305 /* If the linking down is occurred by nway, the device may miss the
4306 * linking change event. And it wouldn't wake when linking on.
4308 if (!sw_linking && tp->rtl_ops.in_nway(tp))
4309 return true;
4310 else if (!skb_queue_empty(&tp->tx_queue))
4311 return true;
4312 else
4313 return false;
4316 static int rtl8152_runtime_resume(struct r8152 *tp)
4318 struct net_device *netdev = tp->netdev;
4320 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4321 struct napi_struct *napi = &tp->napi;
4323 tp->rtl_ops.autosuspend_en(tp, false);
4324 napi_disable(napi);
4325 set_bit(WORK_ENABLE, &tp->flags);
4327 if (netif_carrier_ok(netdev)) {
4328 if (rtl8152_get_speed(tp) & LINK_STATUS) {
4329 rtl_start_rx(tp);
4330 } else {
4331 netif_carrier_off(netdev);
4332 tp->rtl_ops.disable(tp);
4333 netif_info(tp, link, netdev, "linking down\n");
4337 napi_enable(napi);
4338 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4339 smp_mb__after_atomic();
4341 if (!list_empty(&tp->rx_done))
4342 napi_schedule(&tp->napi);
4344 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4345 } else {
4346 if (netdev->flags & IFF_UP)
4347 tp->rtl_ops.autosuspend_en(tp, false);
4349 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4352 return 0;
4355 static int rtl8152_system_resume(struct r8152 *tp)
4357 struct net_device *netdev = tp->netdev;
4359 netif_device_attach(netdev);
4361 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4362 tp->rtl_ops.up(tp);
4363 netif_carrier_off(netdev);
4364 set_bit(WORK_ENABLE, &tp->flags);
4365 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4368 return 0;
4371 static int rtl8152_runtime_suspend(struct r8152 *tp)
4373 struct net_device *netdev = tp->netdev;
4374 int ret = 0;
4376 set_bit(SELECTIVE_SUSPEND, &tp->flags);
4377 smp_mb__after_atomic();
4379 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4380 u32 rcr = 0;
4382 if (netif_carrier_ok(netdev)) {
4383 u32 ocp_data;
4385 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4386 ocp_data = rcr & ~RCR_ACPT_ALL;
4387 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4388 rxdy_gated_en(tp, true);
4389 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4390 PLA_OOB_CTRL);
4391 if (!(ocp_data & RXFIFO_EMPTY)) {
4392 rxdy_gated_en(tp, false);
4393 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4394 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4395 smp_mb__after_atomic();
4396 ret = -EBUSY;
4397 goto out1;
4401 clear_bit(WORK_ENABLE, &tp->flags);
4402 usb_kill_urb(tp->intr_urb);
4404 tp->rtl_ops.autosuspend_en(tp, true);
4406 if (netif_carrier_ok(netdev)) {
4407 struct napi_struct *napi = &tp->napi;
4409 napi_disable(napi);
4410 rtl_stop_rx(tp);
4411 rxdy_gated_en(tp, false);
4412 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4413 napi_enable(napi);
4416 if (delay_autosuspend(tp)) {
4417 rtl8152_runtime_resume(tp);
4418 ret = -EBUSY;
4422 out1:
4423 return ret;
4426 static int rtl8152_system_suspend(struct r8152 *tp)
4428 struct net_device *netdev = tp->netdev;
4430 netif_device_detach(netdev);
4432 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4433 struct napi_struct *napi = &tp->napi;
4435 clear_bit(WORK_ENABLE, &tp->flags);
4436 usb_kill_urb(tp->intr_urb);
4437 napi_disable(napi);
4438 cancel_delayed_work_sync(&tp->schedule);
4439 tp->rtl_ops.down(tp);
4440 napi_enable(napi);
4443 return 0;
4446 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4448 struct r8152 *tp = usb_get_intfdata(intf);
4449 int ret;
4451 mutex_lock(&tp->control);
4453 if (PMSG_IS_AUTO(message))
4454 ret = rtl8152_runtime_suspend(tp);
4455 else
4456 ret = rtl8152_system_suspend(tp);
4458 mutex_unlock(&tp->control);
4460 return ret;
4463 static int rtl8152_resume(struct usb_interface *intf)
4465 struct r8152 *tp = usb_get_intfdata(intf);
4466 int ret;
4468 mutex_lock(&tp->control);
4470 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4471 ret = rtl8152_runtime_resume(tp);
4472 else
4473 ret = rtl8152_system_resume(tp);
4475 mutex_unlock(&tp->control);
4477 return ret;
4480 static int rtl8152_reset_resume(struct usb_interface *intf)
4482 struct r8152 *tp = usb_get_intfdata(intf);
4484 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4485 tp->rtl_ops.init(tp);
4486 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4487 set_ethernet_addr(tp);
4488 return rtl8152_resume(intf);
4491 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4493 struct r8152 *tp = netdev_priv(dev);
4495 if (usb_autopm_get_interface(tp->intf) < 0)
4496 return;
4498 if (!rtl_can_wakeup(tp)) {
4499 wol->supported = 0;
4500 wol->wolopts = 0;
4501 } else {
4502 mutex_lock(&tp->control);
4503 wol->supported = WAKE_ANY;
4504 wol->wolopts = __rtl_get_wol(tp);
4505 mutex_unlock(&tp->control);
4508 usb_autopm_put_interface(tp->intf);
4511 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4513 struct r8152 *tp = netdev_priv(dev);
4514 int ret;
4516 if (!rtl_can_wakeup(tp))
4517 return -EOPNOTSUPP;
4519 if (wol->wolopts & ~WAKE_ANY)
4520 return -EINVAL;
4522 ret = usb_autopm_get_interface(tp->intf);
4523 if (ret < 0)
4524 goto out_set_wol;
4526 mutex_lock(&tp->control);
4528 __rtl_set_wol(tp, wol->wolopts);
4529 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4531 mutex_unlock(&tp->control);
4533 usb_autopm_put_interface(tp->intf);
4535 out_set_wol:
4536 return ret;
4539 static u32 rtl8152_get_msglevel(struct net_device *dev)
4541 struct r8152 *tp = netdev_priv(dev);
4543 return tp->msg_enable;
4546 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4548 struct r8152 *tp = netdev_priv(dev);
4550 tp->msg_enable = value;
4553 static void rtl8152_get_drvinfo(struct net_device *netdev,
4554 struct ethtool_drvinfo *info)
4556 struct r8152 *tp = netdev_priv(netdev);
4558 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4559 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4560 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4563 static
4564 int rtl8152_get_link_ksettings(struct net_device *netdev,
4565 struct ethtool_link_ksettings *cmd)
4567 struct r8152 *tp = netdev_priv(netdev);
4568 int ret;
4570 if (!tp->mii.mdio_read)
4571 return -EOPNOTSUPP;
4573 ret = usb_autopm_get_interface(tp->intf);
4574 if (ret < 0)
4575 goto out;
4577 mutex_lock(&tp->control);
4579 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4581 mutex_unlock(&tp->control);
4583 usb_autopm_put_interface(tp->intf);
4585 out:
4586 return ret;
4589 static int rtl8152_set_link_ksettings(struct net_device *dev,
4590 const struct ethtool_link_ksettings *cmd)
4592 struct r8152 *tp = netdev_priv(dev);
4593 int ret;
4595 ret = usb_autopm_get_interface(tp->intf);
4596 if (ret < 0)
4597 goto out;
4599 mutex_lock(&tp->control);
4601 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4602 cmd->base.duplex);
4603 if (!ret) {
4604 tp->autoneg = cmd->base.autoneg;
4605 tp->speed = cmd->base.speed;
4606 tp->duplex = cmd->base.duplex;
4609 mutex_unlock(&tp->control);
4611 usb_autopm_put_interface(tp->intf);
4613 out:
4614 return ret;
4617 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4618 "tx_packets",
4619 "rx_packets",
4620 "tx_errors",
4621 "rx_errors",
4622 "rx_missed",
4623 "align_errors",
4624 "tx_single_collisions",
4625 "tx_multi_collisions",
4626 "rx_unicast",
4627 "rx_broadcast",
4628 "rx_multicast",
4629 "tx_aborted",
4630 "tx_underrun",
4633 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4635 switch (sset) {
4636 case ETH_SS_STATS:
4637 return ARRAY_SIZE(rtl8152_gstrings);
4638 default:
4639 return -EOPNOTSUPP;
4643 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4644 struct ethtool_stats *stats, u64 *data)
4646 struct r8152 *tp = netdev_priv(dev);
4647 struct tally_counter tally;
4649 if (usb_autopm_get_interface(tp->intf) < 0)
4650 return;
4652 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4654 usb_autopm_put_interface(tp->intf);
4656 data[0] = le64_to_cpu(tally.tx_packets);
4657 data[1] = le64_to_cpu(tally.rx_packets);
4658 data[2] = le64_to_cpu(tally.tx_errors);
4659 data[3] = le32_to_cpu(tally.rx_errors);
4660 data[4] = le16_to_cpu(tally.rx_missed);
4661 data[5] = le16_to_cpu(tally.align_errors);
4662 data[6] = le32_to_cpu(tally.tx_one_collision);
4663 data[7] = le32_to_cpu(tally.tx_multi_collision);
4664 data[8] = le64_to_cpu(tally.rx_unicast);
4665 data[9] = le64_to_cpu(tally.rx_broadcast);
4666 data[10] = le32_to_cpu(tally.rx_multicast);
4667 data[11] = le16_to_cpu(tally.tx_aborted);
4668 data[12] = le16_to_cpu(tally.tx_underrun);
4671 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4673 switch (stringset) {
4674 case ETH_SS_STATS:
4675 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4676 break;
4680 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4682 u32 ocp_data, lp, adv, supported = 0;
4683 u16 val;
4685 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4686 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4688 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4689 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4691 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4692 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4694 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4695 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4697 eee->eee_enabled = !!ocp_data;
4698 eee->eee_active = !!(supported & adv & lp);
4699 eee->supported = supported;
4700 eee->advertised = adv;
4701 eee->lp_advertised = lp;
4703 return 0;
4706 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4708 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4710 r8152_eee_en(tp, eee->eee_enabled);
4712 if (!eee->eee_enabled)
4713 val = 0;
4715 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4717 return 0;
4720 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4722 u32 ocp_data, lp, adv, supported = 0;
4723 u16 val;
4725 val = ocp_reg_read(tp, OCP_EEE_ABLE);
4726 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4728 val = ocp_reg_read(tp, OCP_EEE_ADV);
4729 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4731 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4732 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4734 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4735 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4737 eee->eee_enabled = !!ocp_data;
4738 eee->eee_active = !!(supported & adv & lp);
4739 eee->supported = supported;
4740 eee->advertised = adv;
4741 eee->lp_advertised = lp;
4743 return 0;
4746 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4748 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4750 r8153_eee_en(tp, eee->eee_enabled);
4752 if (!eee->eee_enabled)
4753 val = 0;
4755 ocp_reg_write(tp, OCP_EEE_ADV, val);
4757 return 0;
4760 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4762 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4764 r8153b_eee_en(tp, eee->eee_enabled);
4766 if (!eee->eee_enabled)
4767 val = 0;
4769 ocp_reg_write(tp, OCP_EEE_ADV, val);
4771 return 0;
4774 static int
4775 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4777 struct r8152 *tp = netdev_priv(net);
4778 int ret;
4780 ret = usb_autopm_get_interface(tp->intf);
4781 if (ret < 0)
4782 goto out;
4784 mutex_lock(&tp->control);
4786 ret = tp->rtl_ops.eee_get(tp, edata);
4788 mutex_unlock(&tp->control);
4790 usb_autopm_put_interface(tp->intf);
4792 out:
4793 return ret;
4796 static int
4797 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4799 struct r8152 *tp = netdev_priv(net);
4800 int ret;
4802 ret = usb_autopm_get_interface(tp->intf);
4803 if (ret < 0)
4804 goto out;
4806 mutex_lock(&tp->control);
4808 ret = tp->rtl_ops.eee_set(tp, edata);
4809 if (!ret)
4810 ret = mii_nway_restart(&tp->mii);
4812 mutex_unlock(&tp->control);
4814 usb_autopm_put_interface(tp->intf);
4816 out:
4817 return ret;
4820 static int rtl8152_nway_reset(struct net_device *dev)
4822 struct r8152 *tp = netdev_priv(dev);
4823 int ret;
4825 ret = usb_autopm_get_interface(tp->intf);
4826 if (ret < 0)
4827 goto out;
4829 mutex_lock(&tp->control);
4831 ret = mii_nway_restart(&tp->mii);
4833 mutex_unlock(&tp->control);
4835 usb_autopm_put_interface(tp->intf);
4837 out:
4838 return ret;
4841 static int rtl8152_get_coalesce(struct net_device *netdev,
4842 struct ethtool_coalesce *coalesce)
4844 struct r8152 *tp = netdev_priv(netdev);
4846 switch (tp->version) {
4847 case RTL_VER_01:
4848 case RTL_VER_02:
4849 case RTL_VER_07:
4850 return -EOPNOTSUPP;
4851 default:
4852 break;
4855 coalesce->rx_coalesce_usecs = tp->coalesce;
4857 return 0;
4860 static int rtl8152_set_coalesce(struct net_device *netdev,
4861 struct ethtool_coalesce *coalesce)
4863 struct r8152 *tp = netdev_priv(netdev);
4864 int ret;
4866 switch (tp->version) {
4867 case RTL_VER_01:
4868 case RTL_VER_02:
4869 case RTL_VER_07:
4870 return -EOPNOTSUPP;
4871 default:
4872 break;
4875 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4876 return -EINVAL;
4878 ret = usb_autopm_get_interface(tp->intf);
4879 if (ret < 0)
4880 return ret;
4882 mutex_lock(&tp->control);
4884 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4885 tp->coalesce = coalesce->rx_coalesce_usecs;
4887 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4888 r8153_set_rx_early_timeout(tp);
4891 mutex_unlock(&tp->control);
4893 usb_autopm_put_interface(tp->intf);
4895 return ret;
4898 static const struct ethtool_ops ops = {
4899 .get_drvinfo = rtl8152_get_drvinfo,
4900 .get_link = ethtool_op_get_link,
4901 .nway_reset = rtl8152_nway_reset,
4902 .get_msglevel = rtl8152_get_msglevel,
4903 .set_msglevel = rtl8152_set_msglevel,
4904 .get_wol = rtl8152_get_wol,
4905 .set_wol = rtl8152_set_wol,
4906 .get_strings = rtl8152_get_strings,
4907 .get_sset_count = rtl8152_get_sset_count,
4908 .get_ethtool_stats = rtl8152_get_ethtool_stats,
4909 .get_coalesce = rtl8152_get_coalesce,
4910 .set_coalesce = rtl8152_set_coalesce,
4911 .get_eee = rtl_ethtool_get_eee,
4912 .set_eee = rtl_ethtool_set_eee,
4913 .get_link_ksettings = rtl8152_get_link_ksettings,
4914 .set_link_ksettings = rtl8152_set_link_ksettings,
4917 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4919 struct r8152 *tp = netdev_priv(netdev);
4920 struct mii_ioctl_data *data = if_mii(rq);
4921 int res;
4923 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4924 return -ENODEV;
4926 res = usb_autopm_get_interface(tp->intf);
4927 if (res < 0)
4928 goto out;
4930 switch (cmd) {
4931 case SIOCGMIIPHY:
4932 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4933 break;
4935 case SIOCGMIIREG:
4936 mutex_lock(&tp->control);
4937 data->val_out = r8152_mdio_read(tp, data->reg_num);
4938 mutex_unlock(&tp->control);
4939 break;
4941 case SIOCSMIIREG:
4942 if (!capable(CAP_NET_ADMIN)) {
4943 res = -EPERM;
4944 break;
4946 mutex_lock(&tp->control);
4947 r8152_mdio_write(tp, data->reg_num, data->val_in);
4948 mutex_unlock(&tp->control);
4949 break;
4951 default:
4952 res = -EOPNOTSUPP;
4955 usb_autopm_put_interface(tp->intf);
4957 out:
4958 return res;
4961 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4963 struct r8152 *tp = netdev_priv(dev);
4964 int ret;
4966 switch (tp->version) {
4967 case RTL_VER_01:
4968 case RTL_VER_02:
4969 case RTL_VER_07:
4970 dev->mtu = new_mtu;
4971 return 0;
4972 default:
4973 break;
4976 ret = usb_autopm_get_interface(tp->intf);
4977 if (ret < 0)
4978 return ret;
4980 mutex_lock(&tp->control);
4982 dev->mtu = new_mtu;
4984 if (netif_running(dev)) {
4985 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4987 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4989 if (netif_carrier_ok(dev))
4990 r8153_set_rx_early_size(tp);
4993 mutex_unlock(&tp->control);
4995 usb_autopm_put_interface(tp->intf);
4997 return ret;
5000 static const struct net_device_ops rtl8152_netdev_ops = {
5001 .ndo_open = rtl8152_open,
5002 .ndo_stop = rtl8152_close,
5003 .ndo_do_ioctl = rtl8152_ioctl,
5004 .ndo_start_xmit = rtl8152_start_xmit,
5005 .ndo_tx_timeout = rtl8152_tx_timeout,
5006 .ndo_set_features = rtl8152_set_features,
5007 .ndo_set_rx_mode = rtl8152_set_rx_mode,
5008 .ndo_set_mac_address = rtl8152_set_mac_address,
5009 .ndo_change_mtu = rtl8152_change_mtu,
5010 .ndo_validate_addr = eth_validate_addr,
5011 .ndo_features_check = rtl8152_features_check,
5014 static void rtl8152_unload(struct r8152 *tp)
5016 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5017 return;
5019 if (tp->version != RTL_VER_01)
5020 r8152_power_cut_en(tp, true);
5023 static void rtl8153_unload(struct r8152 *tp)
5025 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5026 return;
5028 r8153_power_cut_en(tp, false);
5031 static void rtl8153b_unload(struct r8152 *tp)
5033 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5034 return;
5036 r8153b_power_cut_en(tp, false);
5039 static int rtl_ops_init(struct r8152 *tp)
5041 struct rtl_ops *ops = &tp->rtl_ops;
5042 int ret = 0;
5044 switch (tp->version) {
5045 case RTL_VER_01:
5046 case RTL_VER_02:
5047 case RTL_VER_07:
5048 ops->init = r8152b_init;
5049 ops->enable = rtl8152_enable;
5050 ops->disable = rtl8152_disable;
5051 ops->up = rtl8152_up;
5052 ops->down = rtl8152_down;
5053 ops->unload = rtl8152_unload;
5054 ops->eee_get = r8152_get_eee;
5055 ops->eee_set = r8152_set_eee;
5056 ops->in_nway = rtl8152_in_nway;
5057 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
5058 ops->autosuspend_en = rtl_runtime_suspend_enable;
5059 break;
5061 case RTL_VER_03:
5062 case RTL_VER_04:
5063 case RTL_VER_05:
5064 case RTL_VER_06:
5065 ops->init = r8153_init;
5066 ops->enable = rtl8153_enable;
5067 ops->disable = rtl8153_disable;
5068 ops->up = rtl8153_up;
5069 ops->down = rtl8153_down;
5070 ops->unload = rtl8153_unload;
5071 ops->eee_get = r8153_get_eee;
5072 ops->eee_set = r8153_set_eee;
5073 ops->in_nway = rtl8153_in_nway;
5074 ops->hw_phy_cfg = r8153_hw_phy_cfg;
5075 ops->autosuspend_en = rtl8153_runtime_enable;
5076 break;
5078 case RTL_VER_08:
5079 case RTL_VER_09:
5080 ops->init = r8153b_init;
5081 ops->enable = rtl8153_enable;
5082 ops->disable = rtl8153b_disable;
5083 ops->up = rtl8153b_up;
5084 ops->down = rtl8153b_down;
5085 ops->unload = rtl8153b_unload;
5086 ops->eee_get = r8153_get_eee;
5087 ops->eee_set = r8153b_set_eee;
5088 ops->in_nway = rtl8153_in_nway;
5089 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
5090 ops->autosuspend_en = rtl8153b_runtime_enable;
5091 break;
5093 default:
5094 ret = -ENODEV;
5095 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5096 break;
5099 return ret;
5102 static u8 rtl_get_version(struct usb_interface *intf)
5104 struct usb_device *udev = interface_to_usbdev(intf);
5105 u32 ocp_data = 0;
5106 __le32 *tmp;
5107 u8 version;
5108 int ret;
5110 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5111 if (!tmp)
5112 return 0;
5114 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5115 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5116 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5117 if (ret > 0)
5118 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5120 kfree(tmp);
5122 switch (ocp_data) {
5123 case 0x4c00:
5124 version = RTL_VER_01;
5125 break;
5126 case 0x4c10:
5127 version = RTL_VER_02;
5128 break;
5129 case 0x5c00:
5130 version = RTL_VER_03;
5131 break;
5132 case 0x5c10:
5133 version = RTL_VER_04;
5134 break;
5135 case 0x5c20:
5136 version = RTL_VER_05;
5137 break;
5138 case 0x5c30:
5139 version = RTL_VER_06;
5140 break;
5141 case 0x4800:
5142 version = RTL_VER_07;
5143 break;
5144 case 0x6000:
5145 version = RTL_VER_08;
5146 break;
5147 case 0x6010:
5148 version = RTL_VER_09;
5149 break;
5150 default:
5151 version = RTL_VER_UNKNOWN;
5152 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5153 break;
5156 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5158 return version;
5161 static int rtl8152_probe(struct usb_interface *intf,
5162 const struct usb_device_id *id)
5164 struct usb_device *udev = interface_to_usbdev(intf);
5165 u8 version = rtl_get_version(intf);
5166 struct r8152 *tp;
5167 struct net_device *netdev;
5168 int ret;
5170 if (version == RTL_VER_UNKNOWN)
5171 return -ENODEV;
5173 if (udev->actconfig->desc.bConfigurationValue != 1) {
5174 usb_driver_set_configuration(udev, 1);
5175 return -ENODEV;
5178 if (intf->cur_altsetting->desc.bNumEndpoints < 3)
5179 return -ENODEV;
5181 usb_reset_device(udev);
5182 netdev = alloc_etherdev(sizeof(struct r8152));
5183 if (!netdev) {
5184 dev_err(&intf->dev, "Out of memory\n");
5185 return -ENOMEM;
5188 SET_NETDEV_DEV(netdev, &intf->dev);
5189 tp = netdev_priv(netdev);
5190 tp->msg_enable = 0x7FFF;
5192 tp->udev = udev;
5193 tp->netdev = netdev;
5194 tp->intf = intf;
5195 tp->version = version;
5197 switch (version) {
5198 case RTL_VER_01:
5199 case RTL_VER_02:
5200 case RTL_VER_07:
5201 tp->mii.supports_gmii = 0;
5202 break;
5203 default:
5204 tp->mii.supports_gmii = 1;
5205 break;
5208 ret = rtl_ops_init(tp);
5209 if (ret)
5210 goto out;
5212 mutex_init(&tp->control);
5213 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5214 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5216 netdev->netdev_ops = &rtl8152_netdev_ops;
5217 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5219 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5220 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5221 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5222 NETIF_F_HW_VLAN_CTAG_TX;
5223 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5224 NETIF_F_TSO | NETIF_F_FRAGLIST |
5225 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5226 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5227 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5228 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5229 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5231 if (tp->version == RTL_VER_01) {
5232 netdev->features &= ~NETIF_F_RXCSUM;
5233 netdev->hw_features &= ~NETIF_F_RXCSUM;
5236 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
5237 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) {
5238 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
5239 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
5242 netdev->ethtool_ops = &ops;
5243 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5245 /* MTU range: 68 - 1500 or 9194 */
5246 netdev->min_mtu = ETH_MIN_MTU;
5247 switch (tp->version) {
5248 case RTL_VER_01:
5249 case RTL_VER_02:
5250 netdev->max_mtu = ETH_DATA_LEN;
5251 break;
5252 default:
5253 netdev->max_mtu = RTL8153_MAX_MTU;
5254 break;
5257 tp->mii.dev = netdev;
5258 tp->mii.mdio_read = read_mii_word;
5259 tp->mii.mdio_write = write_mii_word;
5260 tp->mii.phy_id_mask = 0x3f;
5261 tp->mii.reg_num_mask = 0x1f;
5262 tp->mii.phy_id = R8152_PHY_ID;
5264 tp->autoneg = AUTONEG_ENABLE;
5265 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5266 tp->duplex = DUPLEX_FULL;
5268 intf->needs_remote_wakeup = 1;
5270 if (!rtl_can_wakeup(tp))
5271 __rtl_set_wol(tp, 0);
5272 else
5273 tp->saved_wolopts = __rtl_get_wol(tp);
5275 tp->rtl_ops.init(tp);
5276 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5277 set_ethernet_addr(tp);
5279 usb_set_intfdata(intf, tp);
5280 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5282 ret = register_netdev(netdev);
5283 if (ret != 0) {
5284 netif_err(tp, probe, netdev, "couldn't register the device\n");
5285 goto out1;
5288 if (tp->saved_wolopts)
5289 device_set_wakeup_enable(&udev->dev, true);
5290 else
5291 device_set_wakeup_enable(&udev->dev, false);
5293 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5295 return 0;
5297 out1:
5298 netif_napi_del(&tp->napi);
5299 usb_set_intfdata(intf, NULL);
5300 out:
5301 free_netdev(netdev);
5302 return ret;
5305 static void rtl8152_disconnect(struct usb_interface *intf)
5307 struct r8152 *tp = usb_get_intfdata(intf);
5309 usb_set_intfdata(intf, NULL);
5310 if (tp) {
5311 struct usb_device *udev = tp->udev;
5313 if (udev->state == USB_STATE_NOTATTACHED)
5314 set_bit(RTL8152_UNPLUG, &tp->flags);
5316 netif_napi_del(&tp->napi);
5317 unregister_netdev(tp->netdev);
5318 cancel_delayed_work_sync(&tp->hw_phy_work);
5319 tp->rtl_ops.unload(tp);
5320 free_netdev(tp->netdev);
5324 #define REALTEK_USB_DEVICE(vend, prod) \
5325 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5326 USB_DEVICE_ID_MATCH_INT_CLASS, \
5327 .idVendor = (vend), \
5328 .idProduct = (prod), \
5329 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5330 }, \
5332 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5333 USB_DEVICE_ID_MATCH_DEVICE, \
5334 .idVendor = (vend), \
5335 .idProduct = (prod), \
5336 .bInterfaceClass = USB_CLASS_COMM, \
5337 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5338 .bInterfaceProtocol = USB_CDC_PROTO_NONE
5340 /* table of devices that work with this driver */
5341 static const struct usb_device_id rtl8152_table[] = {
5342 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5343 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5344 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5345 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5346 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5347 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
5348 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5349 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
5350 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
5351 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
5352 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
5353 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
5354 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
5355 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
5356 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5357 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
5358 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
5362 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5364 static struct usb_driver rtl8152_driver = {
5365 .name = MODULENAME,
5366 .id_table = rtl8152_table,
5367 .probe = rtl8152_probe,
5368 .disconnect = rtl8152_disconnect,
5369 .suspend = rtl8152_suspend,
5370 .resume = rtl8152_resume,
5371 .reset_resume = rtl8152_reset_resume,
5372 .pre_reset = rtl8152_pre_reset,
5373 .post_reset = rtl8152_post_reset,
5374 .supports_autosuspend = 1,
5375 .disable_hub_initiated_lpm = 1,
5378 module_usb_driver(rtl8152_driver);
5380 MODULE_AUTHOR(DRIVER_AUTHOR);
5381 MODULE_DESCRIPTION(DRIVER_DESC);
5382 MODULE_LICENSE("GPL");
5383 MODULE_VERSION(DRIVER_VERSION);