drivers/pci/controller/dwc/pcie-qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Qualcomm PCIe root complex driver
   4  *
   5  * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   6  * Copyright 2015 Linaro Limited.
   7  *
   8  * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/of_device.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/pci.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/phy/phy.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/reset.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29
  30 #include "pcie-designware.h"
  31
  32 #define PCIE20_PARF_SYS_CTRL                    0x00
  33 #define MST_WAKEUP_EN                           BIT(13)
  34 #define SLV_WAKEUP_EN                           BIT(12)
  35 #define MSTR_ACLK_CGC_DIS                       BIT(10)
  36 #define SLV_ACLK_CGC_DIS                        BIT(9)
  37 #define CORE_CLK_CGC_DIS                        BIT(6)
  38 #define AUX_PWR_DET                             BIT(4)
  39 #define L23_CLK_RMV_DIS                         BIT(2)
  40 #define L1_CLK_RMV_DIS                          BIT(1)
  41
  42 #define PCIE20_COMMAND_STATUS                   0x04
  43 #define CMD_BME_VAL                             0x4
  44 #define PCIE20_DEVICE_CONTROL2_STATUS2          0x98
  45 #define PCIE_CAP_CPL_TIMEOUT_DISABLE            0x10
  46
  47 #define PCIE20_PARF_PHY_CTRL                    0x40
  48 #define PCIE20_PARF_PHY_REFCLK                  0x4C
  49 #define PCIE20_PARF_DBI_BASE_ADDR               0x168
  50 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE         0x16C
  51 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL        0x174
  52 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT       0x178
  53 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2    0x1A8
  54 #define PCIE20_PARF_LTSSM                       0x1B0
  55 #define PCIE20_PARF_SID_OFFSET                  0x234
  56 #define PCIE20_PARF_BDF_TRANSLATE_CFG           0x24C
  57
  58 #define PCIE20_ELBI_SYS_CTRL                    0x04
  59 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE          BIT(0)
  60
  61 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL0         0x818
  62 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K        0x4
  63 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K        0x5
  64 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1         0x81c
  65 #define CFG_BRIDGE_SB_INIT                      BIT(0)
  66
  67 #define PCIE20_CAP                              0x70
  68 #define PCIE20_CAP_LINK_CAPABILITIES            (PCIE20_CAP + 0xC)
  69 #define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11))
  70 #define PCIE20_CAP_LINK_1                       (PCIE20_CAP + 0x14)
  71 #define PCIE_CAP_LINK1_VAL                      0x2FD7F
  72
  73 #define PCIE20_PARF_Q2A_FLUSH                   0x1AC
  74
  75 #define PCIE20_MISC_CONTROL_1_REG               0x8BC
  76 #define DBI_RO_WR_EN                            1
  77
  78 #define PERST_DELAY_US                          1000
  79
  80 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE      0x358
  81 #define SLV_ADDR_SPACE_SZ                       0x10000000
  82
  83 #define QCOM_PCIE_2_1_0_MAX_SUPPLY      3
  84 struct qcom_pcie_resources_2_1_0 {
  85         struct clk *iface_clk;
  86         struct clk *core_clk;
  87         struct clk *phy_clk;
  88         struct reset_control *pci_reset;
  89         struct reset_control *axi_reset;
  90         struct reset_control *ahb_reset;
  91         struct reset_control *por_reset;
  92         struct reset_control *phy_reset;
  93         struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
  94 };
  95
  96 struct qcom_pcie_resources_1_0_0 {
  97         struct clk *iface;
  98         struct clk *aux;
  99         struct clk *master_bus;
 100         struct clk *slave_bus;
 101         struct reset_control *core;
 102         struct regulator *vdda;
 103 };
 104
 105 #define QCOM_PCIE_2_3_2_MAX_SUPPLY      2
 106 struct qcom_pcie_resources_2_3_2 {
 107         struct clk *aux_clk;
 108         struct clk *master_clk;
 109         struct clk *slave_clk;
 110         struct clk *cfg_clk;
 111         struct clk *pipe_clk;
 112         struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
 113 };
 114
 115 struct qcom_pcie_resources_2_4_0 {
 116         struct clk *aux_clk;
 117         struct clk *master_clk;
 118         struct clk *slave_clk;
 119         struct reset_control *axi_m_reset;
 120         struct reset_control *axi_s_reset;
 121         struct reset_control *pipe_reset;
 122         struct reset_control *axi_m_vmid_reset;
 123         struct reset_control *axi_s_xpu_reset;
 124         struct reset_control *parf_reset;
 125         struct reset_control *phy_reset;
 126         struct reset_control *axi_m_sticky_reset;
 127         struct reset_control *pipe_sticky_reset;
 128         struct reset_control *pwr_reset;
 129         struct reset_control *ahb_reset;
 130         struct reset_control *phy_ahb_reset;
 131 };
 132
 133 struct qcom_pcie_resources_2_3_3 {
 134         struct clk *iface;
 135         struct clk *axi_m_clk;
 136         struct clk *axi_s_clk;
 137         struct clk *ahb_clk;
 138         struct clk *aux_clk;
 139         struct reset_control *rst[7];
 140 };
 141
 142 union qcom_pcie_resources {
 143         struct qcom_pcie_resources_1_0_0 v1_0_0;
 144         struct qcom_pcie_resources_2_1_0 v2_1_0;
 145         struct qcom_pcie_resources_2_3_2 v2_3_2;
 146         struct qcom_pcie_resources_2_3_3 v2_3_3;
 147         struct qcom_pcie_resources_2_4_0 v2_4_0;
 148 };
 149
 150 struct qcom_pcie;
 151
 152 struct qcom_pcie_ops {
 153         int (*get_resources)(struct qcom_pcie *pcie);
 154         int (*init)(struct qcom_pcie *pcie);
 155         int (*post_init)(struct qcom_pcie *pcie);
 156         void (*deinit)(struct qcom_pcie *pcie);
 157         void (*post_deinit)(struct qcom_pcie *pcie);
 158         void (*ltssm_enable)(struct qcom_pcie *pcie);
 159 };
 160
 161 struct qcom_pcie {
 162         struct dw_pcie *pci;
 163         void __iomem *parf;                     /* DT parf */
 164         void __iomem *elbi;                     /* DT elbi */
 165         union qcom_pcie_resources res;
 166         struct phy *phy;
 167         struct gpio_desc *reset;
 168         const struct qcom_pcie_ops *ops;
 169 };
 170
 171 #define to_qcom_pcie(x)         dev_get_drvdata((x)->dev)
 172
 173 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
 174 {
 175         gpiod_set_value_cansleep(pcie->reset, 1);
 176         usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
 177 }
 178
 179 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
 180 {
 181         /* Ensure that PERST has been asserted for at least 100 ms */
 182         msleep(100);
 183         gpiod_set_value_cansleep(pcie->reset, 0);
 184         usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
 185 }
 186
 187 static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
 188 {
 189         struct dw_pcie *pci = pcie->pci;
 190
 191         if (dw_pcie_link_up(pci))
 192                 return 0;
 193
 194         /* Enable Link Training state machine */
 195         if (pcie->ops->ltssm_enable)
 196                 pcie->ops->ltssm_enable(pcie);
 197
 198         return dw_pcie_wait_for_link(pci);
 199 }
 200
 201 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
 202 {
 203         u32 val;
 204
 205         /* enable link training */
 206         val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
 207         val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
 208         writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
 209 }
 210
 211 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
 212 {
 213         struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 214         struct dw_pcie *pci = pcie->pci;
 215         struct device *dev = pci->dev;
 216         int ret;
 217
 218         res->supplies[0].supply = "vdda";
 219         res->supplies[1].supply = "vdda_phy";
 220         res->supplies[2].supply = "vdda_refclk";
 221         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
 222                                       res->supplies);
 223         if (ret)
 224                 return ret;
 225
 226         res->iface_clk = devm_clk_get(dev, "iface");
 227         if (IS_ERR(res->iface_clk))
 228                 return PTR_ERR(res->iface_clk);
 229
 230         res->core_clk = devm_clk_get(dev, "core");
 231         if (IS_ERR(res->core_clk))
 232                 return PTR_ERR(res->core_clk);
 233
 234         res->phy_clk = devm_clk_get(dev, "phy");
 235         if (IS_ERR(res->phy_clk))
 236                 return PTR_ERR(res->phy_clk);
 237
 238         res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
 239         if (IS_ERR(res->pci_reset))
 240                 return PTR_ERR(res->pci_reset);
 241
 242         res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
 243         if (IS_ERR(res->axi_reset))
 244                 return PTR_ERR(res->axi_reset);
 245
 246         res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
 247         if (IS_ERR(res->ahb_reset))
 248                 return PTR_ERR(res->ahb_reset);
 249
 250         res->por_reset = devm_reset_control_get_exclusive(dev, "por");
 251         if (IS_ERR(res->por_reset))
 252                 return PTR_ERR(res->por_reset);
 253
 254         res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
 255         return PTR_ERR_OR_ZERO(res->phy_reset);
 256 }
 257
 258 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
 259 {
 260         struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 261
 262         reset_control_assert(res->pci_reset);
 263         reset_control_assert(res->axi_reset);
 264         reset_control_assert(res->ahb_reset);
 265         reset_control_assert(res->por_reset);
 266         reset_control_assert(res->pci_reset);
 267         clk_disable_unprepare(res->iface_clk);
 268         clk_disable_unprepare(res->core_clk);
 269         clk_disable_unprepare(res->phy_clk);
 270         regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
 271 }
 272
 273 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 274 {
 275         struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 276         struct dw_pcie *pci = pcie->pci;
 277         struct device *dev = pci->dev;
 278         u32 val;
 279         int ret;
 280
 281         ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
 282         if (ret < 0) {
 283                 dev_err(dev, "cannot enable regulators\n");
 284                 return ret;
 285         }
 286
 287         ret = reset_control_assert(res->ahb_reset);
 288         if (ret) {
 289                 dev_err(dev, "cannot assert ahb reset\n");
 290                 goto err_assert_ahb;
 291         }
 292
 293         ret = clk_prepare_enable(res->iface_clk);
 294         if (ret) {
 295                 dev_err(dev, "cannot prepare/enable iface clock\n");
 296                 goto err_assert_ahb;
 297         }
 298
 299         ret = clk_prepare_enable(res->phy_clk);
 300         if (ret) {
 301                 dev_err(dev, "cannot prepare/enable phy clock\n");
 302                 goto err_clk_phy;
 303         }
 304
 305         ret = clk_prepare_enable(res->core_clk);
 306         if (ret) {
 307                 dev_err(dev, "cannot prepare/enable core clock\n");
 308                 goto err_clk_core;
 309         }
 310
 311         ret = reset_control_deassert(res->ahb_reset);
 312         if (ret) {
 313                 dev_err(dev, "cannot deassert ahb reset\n");
 314                 goto err_deassert_ahb;
 315         }
 316
 317         /* enable PCIe clocks and resets */
 318         val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
 319         val &= ~BIT(0);
 320         writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
 321
 322         /* enable external reference clock */
 323         val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
 324         val |= BIT(16);
 325         writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
 326
 327         ret = reset_control_deassert(res->phy_reset);
 328         if (ret) {
 329                 dev_err(dev, "cannot deassert phy reset\n");
 330                 return ret;
 331         }
 332
 333         ret = reset_control_deassert(res->pci_reset);
 334         if (ret) {
 335                 dev_err(dev, "cannot deassert pci reset\n");
 336                 return ret;
 337         }
 338
 339         ret = reset_control_deassert(res->por_reset);
 340         if (ret) {
 341                 dev_err(dev, "cannot deassert por reset\n");
 342                 return ret;
 343         }
 344
 345         ret = reset_control_deassert(res->axi_reset);
 346         if (ret) {
 347                 dev_err(dev, "cannot deassert axi reset\n");
 348                 return ret;
 349         }
 350
 351         /* wait for clock acquisition */
 352         usleep_range(1000, 1500);
 353
 354
 355         /* Set the Max TLP size to 2K, instead of using default of 4K */
 356         writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
 357                pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
 358         writel(CFG_BRIDGE_SB_INIT,
 359                pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
 360
 361         return 0;
 362
 363 err_deassert_ahb:
 364         clk_disable_unprepare(res->core_clk);
 365 err_clk_core:
 366         clk_disable_unprepare(res->phy_clk);
 367 err_clk_phy:
 368         clk_disable_unprepare(res->iface_clk);
 369 err_assert_ahb:
 370         regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
 371
 372         return ret;
 373 }
 374
 375 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
 376 {
 377         struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
 378         struct dw_pcie *pci = pcie->pci;
 379         struct device *dev = pci->dev;
 380
 381         res->vdda = devm_regulator_get(dev, "vdda");
 382         if (IS_ERR(res->vdda))
 383                 return PTR_ERR(res->vdda);
 384
 385         res->iface = devm_clk_get(dev, "iface");
 386         if (IS_ERR(res->iface))
 387                 return PTR_ERR(res->iface);
 388
 389         res->aux = devm_clk_get(dev, "aux");
 390         if (IS_ERR(res->aux))
 391                 return PTR_ERR(res->aux);
 392
 393         res->master_bus = devm_clk_get(dev, "master_bus");
 394         if (IS_ERR(res->master_bus))
 395                 return PTR_ERR(res->master_bus);
 396
 397         res->slave_bus = devm_clk_get(dev, "slave_bus");
 398         if (IS_ERR(res->slave_bus))
 399                 return PTR_ERR(res->slave_bus);
 400
 401         res->core = devm_reset_control_get_exclusive(dev, "core");
 402         return PTR_ERR_OR_ZERO(res->core);
 403 }
 404
 405 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
 406 {
 407         struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
 408
 409         reset_control_assert(res->core);
 410         clk_disable_unprepare(res->slave_bus);
 411         clk_disable_unprepare(res->master_bus);
 412         clk_disable_unprepare(res->iface);
 413         clk_disable_unprepare(res->aux);
 414         regulator_disable(res->vdda);
 415 }
 416
 417 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
 418 {
 419         struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
 420         struct dw_pcie *pci = pcie->pci;
 421         struct device *dev = pci->dev;
 422         int ret;
 423
 424         ret = reset_control_deassert(res->core);
 425         if (ret) {
 426                 dev_err(dev, "cannot deassert core reset\n");
 427                 return ret;
 428         }
 429
 430         ret = clk_prepare_enable(res->aux);
 431         if (ret) {
 432                 dev_err(dev, "cannot prepare/enable aux clock\n");
 433                 goto err_res;
 434         }
 435
 436         ret = clk_prepare_enable(res->iface);
 437         if (ret) {
 438                 dev_err(dev, "cannot prepare/enable iface clock\n");
 439                 goto err_aux;
 440         }
 441
 442         ret = clk_prepare_enable(res->master_bus);
 443         if (ret) {
 444                 dev_err(dev, "cannot prepare/enable master_bus clock\n");
 445                 goto err_iface;
 446         }
 447
 448         ret = clk_prepare_enable(res->slave_bus);
 449         if (ret) {
 450                 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
 451                 goto err_master;
 452         }
 453
 454         ret = regulator_enable(res->vdda);
 455         if (ret) {
 456                 dev_err(dev, "cannot enable vdda regulator\n");
 457                 goto err_slave;
 458         }
 459
 460         /* change DBI base address */
 461         writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
 462
 463         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 464                 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
 465
 466                 val |= BIT(31);
 467                 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
 468         }
 469
 470         return 0;
 471 err_slave:
 472         clk_disable_unprepare(res->slave_bus);
 473 err_master:
 474         clk_disable_unprepare(res->master_bus);
 475 err_iface:
 476         clk_disable_unprepare(res->iface);
 477 err_aux:
 478         clk_disable_unprepare(res->aux);
 479 err_res:
 480         reset_control_assert(res->core);
 481
 482         return ret;
 483 }
 484
 485 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
 486 {
 487         u32 val;
 488
 489         /* enable link training */
 490         val = readl(pcie->parf + PCIE20_PARF_LTSSM);
 491         val |= BIT(8);
 492         writel(val, pcie->parf + PCIE20_PARF_LTSSM);
 493 }
 494
 495 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
 496 {
 497         struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
 498         struct dw_pcie *pci = pcie->pci;
 499         struct device *dev = pci->dev;
 500         int ret;
 501
 502         res->supplies[0].supply = "vdda";
 503         res->supplies[1].supply = "vddpe-3v3";
 504         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
 505                                       res->supplies);
 506         if (ret)
 507                 return ret;
 508
 509         res->aux_clk = devm_clk_get(dev, "aux");
 510         if (IS_ERR(res->aux_clk))
 511                 return PTR_ERR(res->aux_clk);
 512
 513         res->cfg_clk = devm_clk_get(dev, "cfg");
 514         if (IS_ERR(res->cfg_clk))
 515                 return PTR_ERR(res->cfg_clk);
 516
 517         res->master_clk = devm_clk_get(dev, "bus_master");
 518         if (IS_ERR(res->master_clk))
 519                 return PTR_ERR(res->master_clk);
 520
 521         res->slave_clk = devm_clk_get(dev, "bus_slave");
 522         if (IS_ERR(res->slave_clk))
 523                 return PTR_ERR(res->slave_clk);
 524
 525         res->pipe_clk = devm_clk_get(dev, "pipe");
 526         return PTR_ERR_OR_ZERO(res->pipe_clk);
 527 }
 528
 529 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
 530 {
 531         struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
 532
 533         clk_disable_unprepare(res->slave_clk);
 534         clk_disable_unprepare(res->master_clk);
 535         clk_disable_unprepare(res->cfg_clk);
 536         clk_disable_unprepare(res->aux_clk);
 537
 538         regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
 539 }
 540
 541 static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
 542 {
 543         struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
 544
 545         clk_disable_unprepare(res->pipe_clk);
 546 }
 547
 548 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
 549 {
 550         struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
 551         struct dw_pcie *pci = pcie->pci;
 552         struct device *dev = pci->dev;
 553         u32 val;
 554         int ret;
 555
 556         ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
 557         if (ret < 0) {
 558                 dev_err(dev, "cannot enable regulators\n");
 559                 return ret;
 560         }
 561
 562         ret = clk_prepare_enable(res->aux_clk);
 563         if (ret) {
 564                 dev_err(dev, "cannot prepare/enable aux clock\n");
 565                 goto err_aux_clk;
 566         }
 567
 568         ret = clk_prepare_enable(res->cfg_clk);
 569         if (ret) {
 570                 dev_err(dev, "cannot prepare/enable cfg clock\n");
 571                 goto err_cfg_clk;
 572         }
 573
 574         ret = clk_prepare_enable(res->master_clk);
 575         if (ret) {
 576                 dev_err(dev, "cannot prepare/enable master clock\n");
 577                 goto err_master_clk;
 578         }
 579
 580         ret = clk_prepare_enable(res->slave_clk);
 581         if (ret) {
 582                 dev_err(dev, "cannot prepare/enable slave clock\n");
 583                 goto err_slave_clk;
 584         }
 585
 586         /* enable PCIe clocks and resets */
 587         val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
 588         val &= ~BIT(0);
 589         writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
 590
 591         /* change DBI base address */
 592         writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
 593
 594         /* MAC PHY_POWERDOWN MUX DISABLE  */
 595         val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
 596         val &= ~BIT(29);
 597         writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
 598
 599         val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
 600         val |= BIT(4);
 601         writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
 602
 603         val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 604         val |= BIT(31);
 605         writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 606
 607         return 0;
 608
 609 err_slave_clk:
 610         clk_disable_unprepare(res->master_clk);
 611 err_master_clk:
 612         clk_disable_unprepare(res->cfg_clk);
 613 err_cfg_clk:
 614         clk_disable_unprepare(res->aux_clk);
 615
 616 err_aux_clk:
 617         regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
 618
 619         return ret;
 620 }
 621
 622 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
 623 {
 624         struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
 625         struct dw_pcie *pci = pcie->pci;
 626         struct device *dev = pci->dev;
 627         int ret;
 628
 629         ret = clk_prepare_enable(res->pipe_clk);
 630         if (ret) {
 631                 dev_err(dev, "cannot prepare/enable pipe clock\n");
 632                 return ret;
 633         }
 634
 635         return 0;
 636 }
 637
 638 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
 639 {
 640         struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
 641         struct dw_pcie *pci = pcie->pci;
 642         struct device *dev = pci->dev;
 643
 644         res->aux_clk = devm_clk_get(dev, "aux");
 645         if (IS_ERR(res->aux_clk))
 646                 return PTR_ERR(res->aux_clk);
 647
 648         res->master_clk = devm_clk_get(dev, "master_bus");
 649         if (IS_ERR(res->master_clk))
 650                 return PTR_ERR(res->master_clk);
 651
 652         res->slave_clk = devm_clk_get(dev, "slave_bus");
 653         if (IS_ERR(res->slave_clk))
 654                 return PTR_ERR(res->slave_clk);
 655
 656         res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
 657         if (IS_ERR(res->axi_m_reset))
 658                 return PTR_ERR(res->axi_m_reset);
 659
 660         res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
 661         if (IS_ERR(res->axi_s_reset))
 662                 return PTR_ERR(res->axi_s_reset);
 663
 664         res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
 665         if (IS_ERR(res->pipe_reset))
 666                 return PTR_ERR(res->pipe_reset);
 667
 668         res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
 669                                                                  "axi_m_vmid");
 670         if (IS_ERR(res->axi_m_vmid_reset))
 671                 return PTR_ERR(res->axi_m_vmid_reset);
 672
 673         res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
 674                                                                 "axi_s_xpu");
 675         if (IS_ERR(res->axi_s_xpu_reset))
 676                 return PTR_ERR(res->axi_s_xpu_reset);
 677
 678         res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
 679         if (IS_ERR(res->parf_reset))
 680                 return PTR_ERR(res->parf_reset);
 681
 682         res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
 683         if (IS_ERR(res->phy_reset))
 684                 return PTR_ERR(res->phy_reset);
 685
 686         res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
 687                                                                    "axi_m_sticky");
 688         if (IS_ERR(res->axi_m_sticky_reset))
 689                 return PTR_ERR(res->axi_m_sticky_reset);
 690
 691         res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
 692                                                                   "pipe_sticky");
 693         if (IS_ERR(res->pipe_sticky_reset))
 694                 return PTR_ERR(res->pipe_sticky_reset);
 695
 696         res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
 697         if (IS_ERR(res->pwr_reset))
 698                 return PTR_ERR(res->pwr_reset);
 699
 700         res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
 701         if (IS_ERR(res->ahb_reset))
 702                 return PTR_ERR(res->ahb_reset);
 703
 704         res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
 705         if (IS_ERR(res->phy_ahb_reset))
 706                 return PTR_ERR(res->phy_ahb_reset);
 707
 708         return 0;
 709 }
 710
 711 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
 712 {
 713         struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
 714
 715         reset_control_assert(res->axi_m_reset);
 716         reset_control_assert(res->axi_s_reset);
 717         reset_control_assert(res->pipe_reset);
 718         reset_control_assert(res->pipe_sticky_reset);
 719         reset_control_assert(res->phy_reset);
 720         reset_control_assert(res->phy_ahb_reset);
 721         reset_control_assert(res->axi_m_sticky_reset);
 722         reset_control_assert(res->pwr_reset);
 723         reset_control_assert(res->ahb_reset);
 724         clk_disable_unprepare(res->aux_clk);
 725         clk_disable_unprepare(res->master_clk);
 726         clk_disable_unprepare(res->slave_clk);
 727 }
 728
 729 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
 730 {
 731         struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
 732         struct dw_pcie *pci = pcie->pci;
 733         struct device *dev = pci->dev;
 734         u32 val;
 735         int ret;
 736
 737         ret = reset_control_assert(res->axi_m_reset);
 738         if (ret) {
 739                 dev_err(dev, "cannot assert axi master reset\n");
 740                 return ret;
 741         }
 742
 743         ret = reset_control_assert(res->axi_s_reset);
 744         if (ret) {
 745                 dev_err(dev, "cannot assert axi slave reset\n");
 746                 return ret;
 747         }
 748
 749         usleep_range(10000, 12000);
 750
 751         ret = reset_control_assert(res->pipe_reset);
 752         if (ret) {
 753                 dev_err(dev, "cannot assert pipe reset\n");
 754                 return ret;
 755         }
 756
 757         ret = reset_control_assert(res->pipe_sticky_reset);
 758         if (ret) {
 759                 dev_err(dev, "cannot assert pipe sticky reset\n");
 760                 return ret;
 761         }
 762
 763         ret = reset_control_assert(res->phy_reset);
 764         if (ret) {
 765                 dev_err(dev, "cannot assert phy reset\n");
 766                 return ret;
 767         }
 768
 769         ret = reset_control_assert(res->phy_ahb_reset);
 770         if (ret) {
 771                 dev_err(dev, "cannot assert phy ahb reset\n");
 772                 return ret;
 773         }
 774
 775         usleep_range(10000, 12000);
 776
 777         ret = reset_control_assert(res->axi_m_sticky_reset);
 778         if (ret) {
 779                 dev_err(dev, "cannot assert axi master sticky reset\n");
 780                 return ret;
 781         }
 782
 783         ret = reset_control_assert(res->pwr_reset);
 784         if (ret) {
 785                 dev_err(dev, "cannot assert power reset\n");
 786                 return ret;
 787         }
 788
 789         ret = reset_control_assert(res->ahb_reset);
 790         if (ret) {
 791                 dev_err(dev, "cannot assert ahb reset\n");
 792                 return ret;
 793         }
 794
 795         usleep_range(10000, 12000);
 796
 797         ret = reset_control_deassert(res->phy_ahb_reset);
 798         if (ret) {
 799                 dev_err(dev, "cannot deassert phy ahb reset\n");
 800                 return ret;
 801         }
 802
 803         ret = reset_control_deassert(res->phy_reset);
 804         if (ret) {
 805                 dev_err(dev, "cannot deassert phy reset\n");
 806                 goto err_rst_phy;
 807         }
 808
 809         ret = reset_control_deassert(res->pipe_reset);
 810         if (ret) {
 811                 dev_err(dev, "cannot deassert pipe reset\n");
 812                 goto err_rst_pipe;
 813         }
 814
 815         ret = reset_control_deassert(res->pipe_sticky_reset);
 816         if (ret) {
 817                 dev_err(dev, "cannot deassert pipe sticky reset\n");
 818                 goto err_rst_pipe_sticky;
 819         }
 820
 821         usleep_range(10000, 12000);
 822
 823         ret = reset_control_deassert(res->axi_m_reset);
 824         if (ret) {
 825                 dev_err(dev, "cannot deassert axi master reset\n");
 826                 goto err_rst_axi_m;
 827         }
 828
 829         ret = reset_control_deassert(res->axi_m_sticky_reset);
 830         if (ret) {
 831                 dev_err(dev, "cannot deassert axi master sticky reset\n");
 832                 goto err_rst_axi_m_sticky;
 833         }
 834
 835         ret = reset_control_deassert(res->axi_s_reset);
 836         if (ret) {
 837                 dev_err(dev, "cannot deassert axi slave reset\n");
 838                 goto err_rst_axi_s;
 839         }
 840
 841         ret = reset_control_deassert(res->pwr_reset);
 842         if (ret) {
 843                 dev_err(dev, "cannot deassert power reset\n");
 844                 goto err_rst_pwr;
 845         }
 846
 847         ret = reset_control_deassert(res->ahb_reset);
 848         if (ret) {
 849                 dev_err(dev, "cannot deassert ahb reset\n");
 850                 goto err_rst_ahb;
 851         }
 852
 853         usleep_range(10000, 12000);
 854
 855         ret = clk_prepare_enable(res->aux_clk);
 856         if (ret) {
 857                 dev_err(dev, "cannot prepare/enable iface clock\n");
 858                 goto err_clk_aux;
 859         }
 860
 861         ret = clk_prepare_enable(res->master_clk);
 862         if (ret) {
 863                 dev_err(dev, "cannot prepare/enable core clock\n");
 864                 goto err_clk_axi_m;
 865         }
 866
 867         ret = clk_prepare_enable(res->slave_clk);
 868         if (ret) {
 869                 dev_err(dev, "cannot prepare/enable phy clock\n");
 870                 goto err_clk_axi_s;
 871         }
 872
 873         /* enable PCIe clocks and resets */
 874         val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
 875         val &= ~BIT(0);
 876         writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
 877
 878         /* change DBI base address */
 879         writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
 880
 881         /* MAC PHY_POWERDOWN MUX DISABLE  */
 882         val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
 883         val &= ~BIT(29);
 884         writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
 885
 886         val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
 887         val |= BIT(4);
 888         writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
 889
 890         val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 891         val |= BIT(31);
 892         writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 893
 894         return 0;
 895
 896 err_clk_axi_s:
 897         clk_disable_unprepare(res->master_clk);
 898 err_clk_axi_m:
 899         clk_disable_unprepare(res->aux_clk);
 900 err_clk_aux:
 901         reset_control_assert(res->ahb_reset);
 902 err_rst_ahb:
 903         reset_control_assert(res->pwr_reset);
 904 err_rst_pwr:
 905         reset_control_assert(res->axi_s_reset);
 906 err_rst_axi_s:
 907         reset_control_assert(res->axi_m_sticky_reset);
 908 err_rst_axi_m_sticky:
 909         reset_control_assert(res->axi_m_reset);
 910 err_rst_axi_m:
 911         reset_control_assert(res->pipe_sticky_reset);
 912 err_rst_pipe_sticky:
 913         reset_control_assert(res->pipe_reset);
 914 err_rst_pipe:
 915         reset_control_assert(res->phy_reset);
 916 err_rst_phy:
 917         reset_control_assert(res->phy_ahb_reset);
 918         return ret;
 919 }
 920
 921 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
 922 {
 923         struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
 924         struct dw_pcie *pci = pcie->pci;
 925         struct device *dev = pci->dev;
 926         int i;
 927         const char *rst_names[] = { "axi_m", "axi_s", "pipe",
 928                                     "axi_m_sticky", "sticky",
 929                                     "ahb", "sleep", };
 930
 931         res->iface = devm_clk_get(dev, "iface");
 932         if (IS_ERR(res->iface))
 933                 return PTR_ERR(res->iface);
 934
 935         res->axi_m_clk = devm_clk_get(dev, "axi_m");
 936         if (IS_ERR(res->axi_m_clk))
 937                 return PTR_ERR(res->axi_m_clk);
 938
 939         res->axi_s_clk = devm_clk_get(dev, "axi_s");
 940         if (IS_ERR(res->axi_s_clk))
 941                 return PTR_ERR(res->axi_s_clk);
 942
 943         res->ahb_clk = devm_clk_get(dev, "ahb");
 944         if (IS_ERR(res->ahb_clk))
 945                 return PTR_ERR(res->ahb_clk);
 946
 947         res->aux_clk = devm_clk_get(dev, "aux");
 948         if (IS_ERR(res->aux_clk))
 949                 return PTR_ERR(res->aux_clk);
 950
 951         for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
 952                 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
 953                 if (IS_ERR(res->rst[i]))
 954                         return PTR_ERR(res->rst[i]);
 955         }
 956
 957         return 0;
 958 }
 959
 960 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
 961 {
 962         struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
 963
 964         clk_disable_unprepare(res->iface);
 965         clk_disable_unprepare(res->axi_m_clk);
 966         clk_disable_unprepare(res->axi_s_clk);
 967         clk_disable_unprepare(res->ahb_clk);
 968         clk_disable_unprepare(res->aux_clk);
 969 }
 970
 971 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
 972 {
 973         struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
 974         struct dw_pcie *pci = pcie->pci;
 975         struct device *dev = pci->dev;
 976         int i, ret;
 977         u32 val;
 978
 979         for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
 980                 ret = reset_control_assert(res->rst[i]);
 981                 if (ret) {
 982                         dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
 983                         return ret;
 984                 }
 985         }
 986
 987         usleep_range(2000, 2500);
 988
 989         for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
 990                 ret = reset_control_deassert(res->rst[i]);
 991                 if (ret) {
 992                         dev_err(dev, "reset #%d deassert failed (%d)\n", i,
 993                                 ret);
 994                         return ret;
 995                 }
 996         }
 997
 998         /*
 999          * Don't have a way to see if the reset has completed.
1000          * Wait for some time.
1001          */
1002         usleep_range(2000, 2500);
1003
1004         ret = clk_prepare_enable(res->iface);
1005         if (ret) {
1006                 dev_err(dev, "cannot prepare/enable core clock\n");
1007                 goto err_clk_iface;
1008         }
1009
1010         ret = clk_prepare_enable(res->axi_m_clk);
1011         if (ret) {
1012                 dev_err(dev, "cannot prepare/enable core clock\n");
1013                 goto err_clk_axi_m;
1014         }
1015
1016         ret = clk_prepare_enable(res->axi_s_clk);
1017         if (ret) {
1018                 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1019                 goto err_clk_axi_s;
1020         }
1021
1022         ret = clk_prepare_enable(res->ahb_clk);
1023         if (ret) {
1024                 dev_err(dev, "cannot prepare/enable ahb clock\n");
1025                 goto err_clk_ahb;
1026         }
1027
1028         ret = clk_prepare_enable(res->aux_clk);
1029         if (ret) {
1030                 dev_err(dev, "cannot prepare/enable aux clock\n");
1031                 goto err_clk_aux;
1032         }
1033
1034         writel(SLV_ADDR_SPACE_SZ,
1035                 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1036
1037         val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1038         val &= ~BIT(0);
1039         writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1040
1041         writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1042
1043         writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1044                 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1045                 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1046                 pcie->parf + PCIE20_PARF_SYS_CTRL);
1047         writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1048
1049         writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);
1050         writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1051         writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
1052
1053         val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1054         val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT;
1055         writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1056
1057         writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base +
1058                 PCIE20_DEVICE_CONTROL2_STATUS2);
1059
1060         return 0;
1061
1062 err_clk_aux:
1063         clk_disable_unprepare(res->ahb_clk);
1064 err_clk_ahb:
1065         clk_disable_unprepare(res->axi_s_clk);
1066 err_clk_axi_s:
1067         clk_disable_unprepare(res->axi_m_clk);
1068 err_clk_axi_m:
1069         clk_disable_unprepare(res->iface);
1070 err_clk_iface:
1071         /*
1072          * Not checking for failure, will anyway return
1073          * the original failure in 'ret'.
1074          */
1075         for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1076                 reset_control_assert(res->rst[i]);
1077
1078         return ret;
1079 }
1080
1081 static int qcom_pcie_link_up(struct dw_pcie *pci)
1082 {
1083         u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
1084
1085         return !!(val & PCI_EXP_LNKSTA_DLLLA);
1086 }
1087
1088 static int qcom_pcie_host_init(struct pcie_port *pp)
1089 {
1090         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1091         struct qcom_pcie *pcie = to_qcom_pcie(pci);
1092         int ret;
1093
1094         qcom_ep_reset_assert(pcie);
1095
1096         ret = pcie->ops->init(pcie);
1097         if (ret)
1098                 return ret;
1099
1100         ret = phy_power_on(pcie->phy);
1101         if (ret)
1102                 goto err_deinit;
1103
1104         if (pcie->ops->post_init) {
1105                 ret = pcie->ops->post_init(pcie);
1106                 if (ret)
1107                         goto err_disable_phy;
1108         }
1109
1110         dw_pcie_setup_rc(pp);
1111
1112         if (IS_ENABLED(CONFIG_PCI_MSI))
1113                 dw_pcie_msi_init(pp);
1114
1115         qcom_ep_reset_deassert(pcie);
1116
1117         ret = qcom_pcie_establish_link(pcie);
1118         if (ret)
1119                 goto err;
1120
1121         return 0;
1122 err:
1123         qcom_ep_reset_assert(pcie);
1124         if (pcie->ops->post_deinit)
1125                 pcie->ops->post_deinit(pcie);
1126 err_disable_phy:
1127         phy_power_off(pcie->phy);
1128 err_deinit:
1129         pcie->ops->deinit(pcie);
1130
1131         return ret;
1132 }
1133
1134 static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
1135                                  u32 *val)
1136 {
1137         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1138
1139         /* the device class is not reported correctly from the register */
1140         if (where == PCI_CLASS_REVISION && size == 4) {
1141                 *val = readl(pci->dbi_base + PCI_CLASS_REVISION);
1142                 *val &= 0xff;   /* keep revision id */
1143                 *val |= PCI_CLASS_BRIDGE_PCI << 16;
1144                 return PCIBIOS_SUCCESSFUL;
1145         }
1146
1147         return dw_pcie_read(pci->dbi_base + where, size, val);
1148 }
1149
1150 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1151         .host_init = qcom_pcie_host_init,
1152         .rd_own_conf = qcom_pcie_rd_own_conf,
1153 };
1154
1155 /* Qcom IP rev.: 2.1.0  Synopsys IP rev.: 4.01a */
1156 static const struct qcom_pcie_ops ops_2_1_0 = {
1157         .get_resources = qcom_pcie_get_resources_2_1_0,
1158         .init = qcom_pcie_init_2_1_0,
1159         .deinit = qcom_pcie_deinit_2_1_0,
1160         .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1161 };
1162
1163 /* Qcom IP rev.: 1.0.0  Synopsys IP rev.: 4.11a */
1164 static const struct qcom_pcie_ops ops_1_0_0 = {
1165         .get_resources = qcom_pcie_get_resources_1_0_0,
1166         .init = qcom_pcie_init_1_0_0,
1167         .deinit = qcom_pcie_deinit_1_0_0,
1168         .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1169 };
1170
1171 /* Qcom IP rev.: 2.3.2  Synopsys IP rev.: 4.21a */
1172 static const struct qcom_pcie_ops ops_2_3_2 = {
1173         .get_resources = qcom_pcie_get_resources_2_3_2,
1174         .init = qcom_pcie_init_2_3_2,
1175         .post_init = qcom_pcie_post_init_2_3_2,
1176         .deinit = qcom_pcie_deinit_2_3_2,
1177         .post_deinit = qcom_pcie_post_deinit_2_3_2,
1178         .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1179 };
1180
1181 /* Qcom IP rev.: 2.4.0  Synopsys IP rev.: 4.20a */
1182 static const struct qcom_pcie_ops ops_2_4_0 = {
1183         .get_resources = qcom_pcie_get_resources_2_4_0,
1184         .init = qcom_pcie_init_2_4_0,
1185         .deinit = qcom_pcie_deinit_2_4_0,
1186         .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1187 };
1188
1189 /* Qcom IP rev.: 2.3.3  Synopsys IP rev.: 4.30a */
1190 static const struct qcom_pcie_ops ops_2_3_3 = {
1191         .get_resources = qcom_pcie_get_resources_2_3_3,
1192         .init = qcom_pcie_init_2_3_3,
1193         .deinit = qcom_pcie_deinit_2_3_3,
1194         .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1195 };
1196
1197 static const struct dw_pcie_ops dw_pcie_ops = {
1198         .link_up = qcom_pcie_link_up,
1199 };
1200
1201 static int qcom_pcie_probe(struct platform_device *pdev)
1202 {
1203         struct device *dev = &pdev->dev;
1204         struct resource *res;
1205         struct pcie_port *pp;
1206         struct dw_pcie *pci;
1207         struct qcom_pcie *pcie;
1208         int ret;
1209
1210         pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1211         if (!pcie)
1212                 return -ENOMEM;
1213
1214         pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1215         if (!pci)
1216                 return -ENOMEM;
1217
1218         pm_runtime_enable(dev);
1219         ret = pm_runtime_get_sync(dev);
1220         if (ret < 0) {
1221                 pm_runtime_disable(dev);
1222                 return ret;
1223         }
1224
1225         pci->dev = dev;
1226         pci->ops = &dw_pcie_ops;
1227         pp = &pci->pp;
1228
1229         pcie->pci = pci;
1230
1231         pcie->ops = of_device_get_match_data(dev);
1232
1233         pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1234         if (IS_ERR(pcie->reset)) {
1235                 ret = PTR_ERR(pcie->reset);
1236                 goto err_pm_runtime_put;
1237         }
1238
1239         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
1240         pcie->parf = devm_ioremap_resource(dev, res);
1241         if (IS_ERR(pcie->parf)) {
1242                 ret = PTR_ERR(pcie->parf);
1243                 goto err_pm_runtime_put;
1244         }
1245
1246         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1247         pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
1248         if (IS_ERR(pci->dbi_base)) {
1249                 ret = PTR_ERR(pci->dbi_base);
1250                 goto err_pm_runtime_put;
1251         }
1252
1253         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
1254         pcie->elbi = devm_ioremap_resource(dev, res);
1255         if (IS_ERR(pcie->elbi)) {
1256                 ret = PTR_ERR(pcie->elbi);
1257                 goto err_pm_runtime_put;
1258         }
1259
1260         pcie->phy = devm_phy_optional_get(dev, "pciephy");
1261         if (IS_ERR(pcie->phy)) {
1262                 ret = PTR_ERR(pcie->phy);
1263                 goto err_pm_runtime_put;
1264         }
1265
1266         ret = pcie->ops->get_resources(pcie);
1267         if (ret)
1268                 goto err_pm_runtime_put;
1269
1270         pp->ops = &qcom_pcie_dw_ops;
1271
1272         if (IS_ENABLED(CONFIG_PCI_MSI)) {
1273                 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
1274                 if (pp->msi_irq < 0) {
1275                         ret = pp->msi_irq;
1276                         goto err_pm_runtime_put;
1277                 }
1278         }
1279
1280         ret = phy_init(pcie->phy);
1281         if (ret) {
1282                 pm_runtime_disable(&pdev->dev);
1283                 goto err_pm_runtime_put;
1284         }
1285
1286         platform_set_drvdata(pdev, pcie);
1287
1288         ret = dw_pcie_host_init(pp);
1289         if (ret) {
1290                 dev_err(dev, "cannot initialize host\n");
1291                 pm_runtime_disable(&pdev->dev);
1292                 goto err_pm_runtime_put;
1293         }
1294
1295         return 0;
1296
1297 err_pm_runtime_put:
1298         pm_runtime_put(dev);
1299         pm_runtime_disable(dev);
1300
1301         return ret;
1302 }
1303
1304 static const struct of_device_id qcom_pcie_match[] = {
1305         { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
1306         { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
1307         { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
1308         { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
1309         { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
1310         { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
1311         { }
1312 };
1313
1314 static struct platform_driver qcom_pcie_driver = {
1315         .probe = qcom_pcie_probe,
1316         .driver = {
1317                 .name = "qcom-pcie",
1318                 .suppress_bind_attrs = true,
1319                 .of_match_table = qcom_pcie_match,
1320         },
1321 };
1322 builtin_platform_driver(qcom_pcie_driver);