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Linux 4.19.133
[linux/fpc-iii.git] / drivers / pci / controller / pci-aardvark.c
blob0235b6e7dcd13efe4fbe166a2db23d73da56382a
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
4 * 3700.
5 *
6 * Copyright (C) 2016 Marvell
7 *
8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
9 */
10
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21
22 #include "../pci.h"
23
24 /* PCIe core registers */
25 #define PCIE_CORE_CMD_STATUS_REG 0x4
26 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
27 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
28 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
29 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
30 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
31 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
32 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
33 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
34 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
35 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
36 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
37 #define PCIE_CORE_LINK_TRAINING BIT(5)
38 #define PCIE_CORE_LINK_WIDTH_SHIFT 20
39 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
41 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
42 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
43 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
44
45 /* PIO registers base address and register offsets */
46 #define PIO_BASE_ADDR 0x4000
47 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
48 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
49 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
50 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
51 #define PIO_COMPLETION_STATUS_SHIFT 7
52 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
53 #define PIO_COMPLETION_STATUS_OK 0
54 #define PIO_COMPLETION_STATUS_UR 1
55 #define PIO_COMPLETION_STATUS_CRS 2
56 #define PIO_COMPLETION_STATUS_CA 4
57 #define PIO_NON_POSTED_REQ BIT(0)
58 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
59 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
60 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
61 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
62 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
63 #define PIO_START (PIO_BASE_ADDR + 0x1c)
64 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
65 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
66
67 /* Aardvark Control registers */
68 #define CONTROL_BASE_ADDR 0x4800
69 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
70 #define PCIE_GEN_SEL_MSK 0x3
71 #define PCIE_GEN_SEL_SHIFT 0x0
72 #define SPEED_GEN_1 0
73 #define SPEED_GEN_2 1
74 #define SPEED_GEN_3 2
75 #define IS_RC_MSK 1
76 #define IS_RC_SHIFT 2
77 #define LANE_CNT_MSK 0x18
78 #define LANE_CNT_SHIFT 0x3
79 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
80 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
81 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
82 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
83 #define LINK_TRAINING_EN BIT(6)
84 #define LEGACY_INTA BIT(28)
85 #define LEGACY_INTB BIT(29)
86 #define LEGACY_INTC BIT(30)
87 #define LEGACY_INTD BIT(31)
88 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
89 #define HOT_RESET_GEN BIT(0)
90 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
91 #define PCIE_CORE_CTRL2_RESERVED 0x7
92 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
93 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
94 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
95 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
96 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
97 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
98 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
99 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
100 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
101 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
102 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
103 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
104 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
105 #define PCIE_ISR1_FLUSH BIT(5)
106 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
107 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
108 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
109 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
110 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
111 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
112 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
113
114 /* LMI registers base address and register offsets */
115 #define LMI_BASE_ADDR 0x6000
116 #define CFG_REG (LMI_BASE_ADDR + 0x0)
117 #define LTSSM_SHIFT 24
118 #define LTSSM_MASK 0x3f
119 #define LTSSM_L0 0x10
120 #define RC_BAR_CONFIG 0x300
121
122 /* PCIe core controller registers */
123 #define CTRL_CORE_BASE_ADDR 0x18000
124 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
125 #define CTRL_MODE_SHIFT 0x0
126 #define CTRL_MODE_MASK 0x1
127 #define PCIE_CORE_MODE_DIRECT 0x0
128 #define PCIE_CORE_MODE_COMMAND 0x1
129
130 /* PCIe Central Interrupts Registers */
131 #define CENTRAL_INT_BASE_ADDR 0x1b000
132 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
133 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
134 #define PCIE_IRQ_CMDQ_INT BIT(0)
135 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
136 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
137 #define PCIE_IRQ_DMA_INT BIT(4)
138 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
139 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
140 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
141 #define PCIE_IRQ_COMPQ_INT BIT(12)
142 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
143 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
144 #define PCIE_IRQ_CORE_INT BIT(16)
145 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
146 #define PCIE_IRQ_DPMU_INT BIT(18)
147 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
148 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
149 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
150 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
151 #define PCIE_IRQ_EP_STATUS BIT(23)
152 #define PCIE_IRQ_ALL_MASK 0xfff0fb
153 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
154
155 /* Transaction types */
156 #define PCIE_CONFIG_RD_TYPE0 0x8
157 #define PCIE_CONFIG_RD_TYPE1 0x9
158 #define PCIE_CONFIG_WR_TYPE0 0xa
159 #define PCIE_CONFIG_WR_TYPE1 0xb
160
161 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
162 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
163 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
164 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
165 #define PCIE_CONF_ADDR(bus, devfn, where) \
166 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
167 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
168
169 #define PIO_TIMEOUT_MS 1
170
171 #define LINK_WAIT_MAX_RETRIES 10
172 #define LINK_WAIT_USLEEP_MIN 90000
173 #define LINK_WAIT_USLEEP_MAX 100000
174
175 #define MSI_IRQ_NUM 32
176
177 struct advk_pcie {
178 struct platform_device *pdev;
179 void __iomem *base;
180 struct list_head resources;
181 struct irq_domain *irq_domain;
182 struct irq_chip irq_chip;
183 struct irq_domain *msi_domain;
184 struct irq_domain *msi_inner_domain;
185 struct irq_chip msi_bottom_irq_chip;
186 struct irq_chip msi_irq_chip;
187 struct msi_domain_info msi_domain_info;
188 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
189 struct mutex msi_used_lock;
190 u16 msi_msg;
191 int root_bus_nr;
192 };
193
194 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
195 {
196 writel(val, pcie->base + reg);
197 }
198
199 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
200 {
201 return readl(pcie->base + reg);
202 }
203
204 static int advk_pcie_link_up(struct advk_pcie *pcie)
205 {
206 u32 val, ltssm_state;
207
208 val = advk_readl(pcie, CFG_REG);
209 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
210 return ltssm_state >= LTSSM_L0;
211 }
212
213 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
214 {
215 struct device *dev = &pcie->pdev->dev;
216 int retries;
217
218 /* check if the link is up or not */
219 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
220 if (advk_pcie_link_up(pcie)) {
221 dev_info(dev, "link up\n");
222 return 0;
223 }
224
225 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
226 }
227
228 dev_err(dev, "link never came up\n");
229 return -ETIMEDOUT;
230 }
231
232 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
233 {
234 u32 reg;
235
236 /* Set to Direct mode */
237 reg = advk_readl(pcie, CTRL_CONFIG_REG);
238 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
239 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
240 advk_writel(pcie, reg, CTRL_CONFIG_REG);
241
242 /* Set PCI global control register to RC mode */
243 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
244 reg |= (IS_RC_MSK << IS_RC_SHIFT);
245 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
246
247 /* Set Advanced Error Capabilities and Control PF0 register */
248 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
249 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
250 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
251 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
252 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
253
254 /* Set PCIe Device Control and Status 1 PF0 register */
255 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
256 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
257 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
258 (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
259 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
260 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
261
262 /* Program PCIe Control 2 to disable strict ordering */
263 reg = PCIE_CORE_CTRL2_RESERVED |
264 PCIE_CORE_CTRL2_TD_ENABLE;
265 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
266
267 /* Set GEN2 */
268 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
269 reg &= ~PCIE_GEN_SEL_MSK;
270 reg |= SPEED_GEN_2;
271 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
272
273 /* Set lane X1 */
274 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
275 reg &= ~LANE_CNT_MSK;
276 reg |= LANE_COUNT_1;
277 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
278
279 /* Enable link training */
280 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
281 reg |= LINK_TRAINING_EN;
282 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
283
284 /* Enable MSI */
285 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
286 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
287 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
288
289 /* Clear all interrupts */
290 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
291 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
292 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
293
294 /* Disable All ISR0/1 Sources */
295 reg = PCIE_ISR0_ALL_MASK;
296 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
297 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
298
299 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
300
301 /* Unmask all MSI's */
302 advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
303
304 /* Enable summary interrupt for GIC SPI source */
305 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
306 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
307
308 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
309 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
310 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
311
312 /* Bypass the address window mapping for PIO */
313 reg = advk_readl(pcie, PIO_CTRL);
314 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
315 advk_writel(pcie, reg, PIO_CTRL);
316
317 /* Start link training */
318 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
319 reg |= PCIE_CORE_LINK_TRAINING;
320 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
321
322 advk_pcie_wait_for_link(pcie);
323
324 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
325 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
326 PCIE_CORE_CMD_IO_ACCESS_EN |
327 PCIE_CORE_CMD_MEM_IO_REQ_EN;
328 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
329 }
330
331 static void advk_pcie_check_pio_status(struct advk_pcie *pcie)
332 {
333 struct device *dev = &pcie->pdev->dev;
334 u32 reg;
335 unsigned int status;
336 char *strcomp_status, *str_posted;
337
338 reg = advk_readl(pcie, PIO_STAT);
339 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
340 PIO_COMPLETION_STATUS_SHIFT;
341
342 if (!status)
343 return;
344
345 switch (status) {
346 case PIO_COMPLETION_STATUS_UR:
347 strcomp_status = "UR";
348 break;
349 case PIO_COMPLETION_STATUS_CRS:
350 strcomp_status = "CRS";
351 break;
352 case PIO_COMPLETION_STATUS_CA:
353 strcomp_status = "CA";
354 break;
355 default:
356 strcomp_status = "Unknown";
357 break;
358 }
359
360 if (reg & PIO_NON_POSTED_REQ)
361 str_posted = "Non-posted";
362 else
363 str_posted = "Posted";
364
365 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
366 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
367 }
368
369 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
370 {
371 struct device *dev = &pcie->pdev->dev;
372 unsigned long timeout;
373
374 timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS);
375
376 while (time_before(jiffies, timeout)) {
377 u32 start, isr;
378
379 start = advk_readl(pcie, PIO_START);
380 isr = advk_readl(pcie, PIO_ISR);
381 if (!start && isr)
382 return 0;
383 }
384
385 dev_err(dev, "config read/write timed out\n");
386 return -ETIMEDOUT;
387 }
388
389 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
390 int devfn)
391 {
392 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
393 return false;
394
395 return true;
396 }
397
398 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
399 int where, int size, u32 *val)
400 {
401 struct advk_pcie *pcie = bus->sysdata;
402 u32 reg;
403 int ret;
404
405 if (!advk_pcie_valid_device(pcie, bus, devfn)) {
406 *val = 0xffffffff;
407 return PCIBIOS_DEVICE_NOT_FOUND;
408 }
409
410 /* Start PIO */
411 advk_writel(pcie, 0, PIO_START);
412 advk_writel(pcie, 1, PIO_ISR);
413
414 /* Program the control register */
415 reg = advk_readl(pcie, PIO_CTRL);
416 reg &= ~PIO_CTRL_TYPE_MASK;
417 if (bus->number == pcie->root_bus_nr)
418 reg |= PCIE_CONFIG_RD_TYPE0;
419 else
420 reg |= PCIE_CONFIG_RD_TYPE1;
421 advk_writel(pcie, reg, PIO_CTRL);
422
423 /* Program the address registers */
424 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
425 advk_writel(pcie, reg, PIO_ADDR_LS);
426 advk_writel(pcie, 0, PIO_ADDR_MS);
427
428 /* Program the data strobe */
429 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
430
431 /* Start the transfer */
432 advk_writel(pcie, 1, PIO_START);
433
434 ret = advk_pcie_wait_pio(pcie);
435 if (ret < 0)
436 return PCIBIOS_SET_FAILED;
437
438 advk_pcie_check_pio_status(pcie);
439
440 /* Get the read result */
441 *val = advk_readl(pcie, PIO_RD_DATA);
442 if (size == 1)
443 *val = (*val >> (8 * (where & 3))) & 0xff;
444 else if (size == 2)
445 *val = (*val >> (8 * (where & 3))) & 0xffff;
446
447 return PCIBIOS_SUCCESSFUL;
448 }
449
450 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
451 int where, int size, u32 val)
452 {
453 struct advk_pcie *pcie = bus->sysdata;
454 u32 reg;
455 u32 data_strobe = 0x0;
456 int offset;
457 int ret;
458
459 if (!advk_pcie_valid_device(pcie, bus, devfn))
460 return PCIBIOS_DEVICE_NOT_FOUND;
461
462 if (where % size)
463 return PCIBIOS_SET_FAILED;
464
465 /* Start PIO */
466 advk_writel(pcie, 0, PIO_START);
467 advk_writel(pcie, 1, PIO_ISR);
468
469 /* Program the control register */
470 reg = advk_readl(pcie, PIO_CTRL);
471 reg &= ~PIO_CTRL_TYPE_MASK;
472 if (bus->number == pcie->root_bus_nr)
473 reg |= PCIE_CONFIG_WR_TYPE0;
474 else
475 reg |= PCIE_CONFIG_WR_TYPE1;
476 advk_writel(pcie, reg, PIO_CTRL);
477
478 /* Program the address registers */
479 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
480 advk_writel(pcie, reg, PIO_ADDR_LS);
481 advk_writel(pcie, 0, PIO_ADDR_MS);
482
483 /* Calculate the write strobe */
484 offset = where & 0x3;
485 reg = val << (8 * offset);
486 data_strobe = GENMASK(size - 1, 0) << offset;
487
488 /* Program the data register */
489 advk_writel(pcie, reg, PIO_WR_DATA);
490
491 /* Program the data strobe */
492 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
493
494 /* Start the transfer */
495 advk_writel(pcie, 1, PIO_START);
496
497 ret = advk_pcie_wait_pio(pcie);
498 if (ret < 0)
499 return PCIBIOS_SET_FAILED;
500
501 advk_pcie_check_pio_status(pcie);
502
503 return PCIBIOS_SUCCESSFUL;
504 }
505
506 static struct pci_ops advk_pcie_ops = {
507 .read = advk_pcie_rd_conf,
508 .write = advk_pcie_wr_conf,
509 };
510
511 static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
512 struct msi_msg *msg)
513 {
514 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
515 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
516
517 msg->address_lo = lower_32_bits(msi_msg);
518 msg->address_hi = upper_32_bits(msi_msg);
519 msg->data = data->irq;
520 }
521
522 static int advk_msi_set_affinity(struct irq_data *irq_data,
523 const struct cpumask *mask, bool force)
524 {
525 return -EINVAL;
526 }
527
528 static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
529 unsigned int virq,
530 unsigned int nr_irqs, void *args)
531 {
532 struct advk_pcie *pcie = domain->host_data;
533 int hwirq, i;
534
535 mutex_lock(&pcie->msi_used_lock);
536 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM,
537 0, nr_irqs, 0);
538 if (hwirq >= MSI_IRQ_NUM) {
539 mutex_unlock(&pcie->msi_used_lock);
540 return -ENOSPC;
541 }
542
543 bitmap_set(pcie->msi_used, hwirq, nr_irqs);
544 mutex_unlock(&pcie->msi_used_lock);
545
546 for (i = 0; i < nr_irqs; i++)
547 irq_domain_set_info(domain, virq + i, hwirq + i,
548 &pcie->msi_bottom_irq_chip,
549 domain->host_data, handle_simple_irq,
550 NULL, NULL);
551
552 return hwirq;
553 }
554
555 static void advk_msi_irq_domain_free(struct irq_domain *domain,
556 unsigned int virq, unsigned int nr_irqs)
557 {
558 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
559 struct advk_pcie *pcie = domain->host_data;
560
561 mutex_lock(&pcie->msi_used_lock);
562 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs);
563 mutex_unlock(&pcie->msi_used_lock);
564 }
565
566 static const struct irq_domain_ops advk_msi_domain_ops = {
567 .alloc = advk_msi_irq_domain_alloc,
568 .free = advk_msi_irq_domain_free,
569 };
570
571 static void advk_pcie_irq_mask(struct irq_data *d)
572 {
573 struct advk_pcie *pcie = d->domain->host_data;
574 irq_hw_number_t hwirq = irqd_to_hwirq(d);
575 u32 mask;
576
577 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
578 mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
579 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
580 }
581
582 static void advk_pcie_irq_unmask(struct irq_data *d)
583 {
584 struct advk_pcie *pcie = d->domain->host_data;
585 irq_hw_number_t hwirq = irqd_to_hwirq(d);
586 u32 mask;
587
588 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
589 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
590 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
591 }
592
593 static int advk_pcie_irq_map(struct irq_domain *h,
594 unsigned int virq, irq_hw_number_t hwirq)
595 {
596 struct advk_pcie *pcie = h->host_data;
597
598 advk_pcie_irq_mask(irq_get_irq_data(virq));
599 irq_set_status_flags(virq, IRQ_LEVEL);
600 irq_set_chip_and_handler(virq, &pcie->irq_chip,
601 handle_level_irq);
602 irq_set_chip_data(virq, pcie);
603
604 return 0;
605 }
606
607 static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
608 .map = advk_pcie_irq_map,
609 .xlate = irq_domain_xlate_onecell,
610 };
611
612 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
613 {
614 struct device *dev = &pcie->pdev->dev;
615 struct device_node *node = dev->of_node;
616 struct irq_chip *bottom_ic, *msi_ic;
617 struct msi_domain_info *msi_di;
618 phys_addr_t msi_msg_phys;
619
620 mutex_init(&pcie->msi_used_lock);
621
622 bottom_ic = &pcie->msi_bottom_irq_chip;
623
624 bottom_ic->name = "MSI";
625 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
626 bottom_ic->irq_set_affinity = advk_msi_set_affinity;
627
628 msi_ic = &pcie->msi_irq_chip;
629 msi_ic->name = "advk-MSI";
630
631 msi_di = &pcie->msi_domain_info;
632 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
633 MSI_FLAG_MULTI_PCI_MSI;
634 msi_di->chip = msi_ic;
635
636 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
637
638 advk_writel(pcie, lower_32_bits(msi_msg_phys),
639 PCIE_MSI_ADDR_LOW_REG);
640 advk_writel(pcie, upper_32_bits(msi_msg_phys),
641 PCIE_MSI_ADDR_HIGH_REG);
642
643 pcie->msi_inner_domain =
644 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
645 &advk_msi_domain_ops, pcie);
646 if (!pcie->msi_inner_domain)
647 return -ENOMEM;
648
649 pcie->msi_domain =
650 pci_msi_create_irq_domain(of_node_to_fwnode(node),
651 msi_di, pcie->msi_inner_domain);
652 if (!pcie->msi_domain) {
653 irq_domain_remove(pcie->msi_inner_domain);
654 return -ENOMEM;
655 }
656
657 return 0;
658 }
659
660 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
661 {
662 irq_domain_remove(pcie->msi_domain);
663 irq_domain_remove(pcie->msi_inner_domain);
664 }
665
666 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
667 {
668 struct device *dev = &pcie->pdev->dev;
669 struct device_node *node = dev->of_node;
670 struct device_node *pcie_intc_node;
671 struct irq_chip *irq_chip;
672
673 pcie_intc_node = of_get_next_child(node, NULL);
674 if (!pcie_intc_node) {
675 dev_err(dev, "No PCIe Intc node found\n");
676 return -ENODEV;
677 }
678
679 irq_chip = &pcie->irq_chip;
680
681 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
682 dev_name(dev));
683 if (!irq_chip->name) {
684 of_node_put(pcie_intc_node);
685 return -ENOMEM;
686 }
687
688 irq_chip->irq_mask = advk_pcie_irq_mask;
689 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
690 irq_chip->irq_unmask = advk_pcie_irq_unmask;
691
692 pcie->irq_domain =
693 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
694 &advk_pcie_irq_domain_ops, pcie);
695 if (!pcie->irq_domain) {
696 dev_err(dev, "Failed to get a INTx IRQ domain\n");
697 of_node_put(pcie_intc_node);
698 return -ENOMEM;
699 }
700
701 return 0;
702 }
703
704 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
705 {
706 irq_domain_remove(pcie->irq_domain);
707 }
708
709 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
710 {
711 u32 msi_val, msi_mask, msi_status, msi_idx;
712 u16 msi_data;
713
714 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
715 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
716 msi_status = msi_val & ~msi_mask;
717
718 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
719 if (!(BIT(msi_idx) & msi_status))
720 continue;
721
722 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
723 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF;
724 generic_handle_irq(msi_data);
725 }
726
727 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
728 PCIE_ISR0_REG);
729 }
730
731 static void advk_pcie_handle_int(struct advk_pcie *pcie)
732 {
733 u32 isr0_val, isr0_mask, isr0_status;
734 u32 isr1_val, isr1_mask, isr1_status;
735 int i, virq;
736
737 isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
738 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
739 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
740
741 isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
742 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
743 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
744
745 if (!isr0_status && !isr1_status) {
746 advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
747 advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
748 return;
749 }
750
751 /* Process MSI interrupts */
752 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
753 advk_pcie_handle_msi(pcie);
754
755 /* Process legacy interrupts */
756 for (i = 0; i < PCI_NUM_INTX; i++) {
757 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
758 continue;
759
760 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
761 PCIE_ISR1_REG);
762
763 virq = irq_find_mapping(pcie->irq_domain, i);
764 generic_handle_irq(virq);
765 }
766 }
767
768 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
769 {
770 struct advk_pcie *pcie = arg;
771 u32 status;
772
773 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
774 if (!(status & PCIE_IRQ_CORE_INT))
775 return IRQ_NONE;
776
777 advk_pcie_handle_int(pcie);
778
779 /* Clear interrupt */
780 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
781
782 return IRQ_HANDLED;
783 }
784
785 static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
786 {
787 int err, res_valid = 0;
788 struct device *dev = &pcie->pdev->dev;
789 struct resource_entry *win, *tmp;
790 resource_size_t iobase;
791
792 INIT_LIST_HEAD(&pcie->resources);
793
794 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
795 &pcie->resources, &iobase);
796 if (err)
797 return err;
798
799 err = devm_request_pci_bus_resources(dev, &pcie->resources);
800 if (err)
801 goto out_release_res;
802
803 resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
804 struct resource *res = win->res;
805
806 switch (resource_type(res)) {
807 case IORESOURCE_IO:
808 err = devm_pci_remap_iospace(dev, res, iobase);
809 if (err) {
810 dev_warn(dev, "error %d: failed to map resource %pR\n",
811 err, res);
812 resource_list_destroy_entry(win);
813 }
814 break;
815 case IORESOURCE_MEM:
816 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
817 break;
818 case IORESOURCE_BUS:
819 pcie->root_bus_nr = res->start;
820 break;
821 }
822 }
823
824 if (!res_valid) {
825 dev_err(dev, "non-prefetchable memory resource required\n");
826 err = -EINVAL;
827 goto out_release_res;
828 }
829
830 return 0;
831
832 out_release_res:
833 pci_free_resource_list(&pcie->resources);
834 return err;
835 }
836
837 static int advk_pcie_probe(struct platform_device *pdev)
838 {
839 struct device *dev = &pdev->dev;
840 struct advk_pcie *pcie;
841 struct resource *res;
842 struct pci_host_bridge *bridge;
843 int ret, irq;
844
845 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
846 if (!bridge)
847 return -ENOMEM;
848
849 pcie = pci_host_bridge_priv(bridge);
850 pcie->pdev = pdev;
851
852 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
853 pcie->base = devm_ioremap_resource(dev, res);
854 if (IS_ERR(pcie->base))
855 return PTR_ERR(pcie->base);
856
857 irq = platform_get_irq(pdev, 0);
858 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
859 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
860 pcie);
861 if (ret) {
862 dev_err(dev, "Failed to register interrupt\n");
863 return ret;
864 }
865
866 ret = advk_pcie_parse_request_of_pci_ranges(pcie);
867 if (ret) {
868 dev_err(dev, "Failed to parse resources\n");
869 return ret;
870 }
871
872 advk_pcie_setup_hw(pcie);
873
874 ret = advk_pcie_init_irq_domain(pcie);
875 if (ret) {
876 dev_err(dev, "Failed to initialize irq\n");
877 return ret;
878 }
879
880 ret = advk_pcie_init_msi_irq_domain(pcie);
881 if (ret) {
882 dev_err(dev, "Failed to initialize irq\n");
883 advk_pcie_remove_irq_domain(pcie);
884 return ret;
885 }
886
887 list_splice_init(&pcie->resources, &bridge->windows);
888 bridge->dev.parent = dev;
889 bridge->sysdata = pcie;
890 bridge->busnr = 0;
891 bridge->ops = &advk_pcie_ops;
892 bridge->map_irq = of_irq_parse_and_map_pci;
893 bridge->swizzle_irq = pci_common_swizzle;
894
895 ret = pci_host_probe(bridge);
896 if (ret < 0) {
897 advk_pcie_remove_msi_irq_domain(pcie);
898 advk_pcie_remove_irq_domain(pcie);
899 return ret;
900 }
901
902 return 0;
903 }
904
905 static const struct of_device_id advk_pcie_of_match_table[] = {
906 { .compatible = "marvell,armada-3700-pcie", },
907 {},
908 };
909
910 static struct platform_driver advk_pcie_driver = {
911 .driver = {
912 .name = "advk-pcie",
913 .of_match_table = advk_pcie_of_match_table,
914 /* Driver unloading/unbinding currently not supported */
915 .suppress_bind_attrs = true,
916 },
917 .probe = advk_pcie_probe,
918 };
919 builtin_platform_driver(advk_pcie_driver);
Linux with added FPC-III support