?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / pci / controller / pcie-mediatek.c
blobca06d8bc01e7404efda4731b79183f86d672655c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2017 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/msi.h>
18 #include <linux/of_address.h>
19 #include <linux/of_pci.h>
20 #include <linux/of_platform.h>
21 #include <linux/pci.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/reset.h>
26
27 #include "../pci.h"
28
29 /* PCIe shared registers */
30 #define PCIE_SYS_CFG 0x00
31 #define PCIE_INT_ENABLE 0x0c
32 #define PCIE_CFG_ADDR 0x20
33 #define PCIE_CFG_DATA 0x24
34
35 /* PCIe per port registers */
36 #define PCIE_BAR0_SETUP 0x10
37 #define PCIE_CLASS 0x34
38 #define PCIE_LINK_STATUS 0x50
39
40 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
41 #define PCIE_PORT_PERST(x) BIT(1 + (x))
42 #define PCIE_PORT_LINKUP BIT(0)
43 #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
44
45 #define PCIE_BAR_ENABLE BIT(0)
46 #define PCIE_REVISION_ID BIT(0)
47 #define PCIE_CLASS_CODE (0x60400 << 8)
48 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
49 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
50 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
51 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
52 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
53 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
54 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
55 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
56
57 /* MediaTek specific configuration registers */
58 #define PCIE_FTS_NUM 0x70c
59 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
60 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
61
62 #define PCIE_FC_CREDIT 0x73c
63 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
64 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
65
66 /* PCIe V2 share registers */
67 #define PCIE_SYS_CFG_V2 0x0
68 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
69 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
70
71 /* PCIe V2 per-port registers */
72 #define PCIE_MSI_VECTOR 0x0c0
73
74 #define PCIE_CONF_VEND_ID 0x100
75 #define PCIE_CONF_DEVICE_ID 0x102
76 #define PCIE_CONF_CLASS_ID 0x106
77
78 #define PCIE_INT_MASK 0x420
79 #define INTX_MASK GENMASK(19, 16)
80 #define INTX_SHIFT 16
81 #define PCIE_INT_STATUS 0x424
82 #define MSI_STATUS BIT(23)
83 #define PCIE_IMSI_STATUS 0x42c
84 #define PCIE_IMSI_ADDR 0x430
85 #define MSI_MASK BIT(23)
86 #define MTK_MSI_IRQS_NUM 32
87
88 #define PCIE_AHB_TRANS_BASE0_L 0x438
89 #define PCIE_AHB_TRANS_BASE0_H 0x43c
90 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
91 #define PCIE_AXI_WINDOW0 0x448
92 #define WIN_ENABLE BIT(7)
93
94 /* PCIe V2 configuration transaction header */
95 #define PCIE_CFG_HEADER0 0x460
96 #define PCIE_CFG_HEADER1 0x464
97 #define PCIE_CFG_HEADER2 0x468
98 #define PCIE_CFG_WDATA 0x470
99 #define PCIE_APP_TLP_REQ 0x488
100 #define PCIE_CFG_RDATA 0x48c
101 #define APP_CFG_REQ BIT(0)
102 #define APP_CPL_STATUS GENMASK(7, 5)
103
104 #define CFG_WRRD_TYPE_0 4
105 #define CFG_WR_FMT 2
106 #define CFG_RD_FMT 0
107
108 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
109 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
110 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
111 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
112 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
113 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
114 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
115 #define CFG_HEADER_DW0(type, fmt) \
116 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
117 #define CFG_HEADER_DW1(where, size) \
118 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
119 #define CFG_HEADER_DW2(regn, fun, dev, bus) \
120 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
121 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
122
123 #define PCIE_RST_CTRL 0x510
124 #define PCIE_PHY_RSTB BIT(0)
125 #define PCIE_PIPE_SRSTB BIT(1)
126 #define PCIE_MAC_SRSTB BIT(2)
127 #define PCIE_CRSTB BIT(3)
128 #define PCIE_PERSTB BIT(8)
129 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
130 #define PCIE_LINK_STATUS_V2 0x804
131 #define PCIE_PORT_LINKUP_V2 BIT(10)
132
133 struct mtk_pcie_port;
134
135 /**
136 * struct mtk_pcie_soc - differentiate between host generations
137 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
138 * @need_fix_device_id: whether this host's device ID needed to be fixed or not
139 * @device_id: device ID which this host need to be fixed
140 * @ops: pointer to configuration access functions
141 * @startup: pointer to controller setting functions
142 * @setup_irq: pointer to initialize IRQ functions
143 */
144 struct mtk_pcie_soc {
145 bool need_fix_class_id;
146 bool need_fix_device_id;
147 unsigned int device_id;
148 struct pci_ops *ops;
149 int (*startup)(struct mtk_pcie_port *port);
150 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
151 };
152
153 /**
154 * struct mtk_pcie_port - PCIe port information
155 * @base: IO mapped register base
156 * @list: port list
157 * @pcie: pointer to PCIe host info
158 * @reset: pointer to port reset control
159 * @sys_ck: pointer to transaction/data link layer clock
160 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
161 * and RC initiated MMIO access
162 * @axi_ck: pointer to application layer MMIO channel operating clock
163 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
164 * when pcie_mac_ck/pcie_pipe_ck is turned off
165 * @obff_ck: pointer to OBFF functional block operating clock
166 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
167 * @phy: pointer to PHY control block
168 * @lane: lane count
169 * @slot: port slot
170 * @irq_domain: legacy INTx IRQ domain
171 * @inner_domain: inner IRQ domain
172 * @msi_domain: MSI IRQ domain
173 * @lock: protect the msi_irq_in_use bitmap
174 * @msi_irq_in_use: bit map for assigned MSI IRQ
175 */
176 struct mtk_pcie_port {
177 void __iomem *base;
178 struct list_head list;
179 struct mtk_pcie *pcie;
180 struct reset_control *reset;
181 struct clk *sys_ck;
182 struct clk *ahb_ck;
183 struct clk *axi_ck;
184 struct clk *aux_ck;
185 struct clk *obff_ck;
186 struct clk *pipe_ck;
187 struct phy *phy;
188 u32 lane;
189 u32 slot;
190 struct irq_domain *irq_domain;
191 struct irq_domain *inner_domain;
192 struct irq_domain *msi_domain;
193 struct mutex lock;
194 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
195 };
196
197 /**
198 * struct mtk_pcie - PCIe host information
199 * @dev: pointer to PCIe device
200 * @base: IO mapped register base
201 * @free_ck: free-run reference clock
202 * @io: IO resource
203 * @pio: PIO resource
204 * @mem: non-prefetchable memory resource
205 * @busn: bus range
206 * @offset: IO / Memory offset
207 * @ports: pointer to PCIe port information
208 * @soc: pointer to SoC-dependent operations
209 */
210 struct mtk_pcie {
211 struct device *dev;
212 void __iomem *base;
213 struct clk *free_ck;
214
215 struct resource io;
216 struct resource pio;
217 struct resource mem;
218 struct resource busn;
219 struct {
220 resource_size_t mem;
221 resource_size_t io;
222 } offset;
223 struct list_head ports;
224 const struct mtk_pcie_soc *soc;
225 };
226
227 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
228 {
229 struct device *dev = pcie->dev;
230
231 clk_disable_unprepare(pcie->free_ck);
232
233 if (dev->pm_domain) {
234 pm_runtime_put_sync(dev);
235 pm_runtime_disable(dev);
236 }
237 }
238
239 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
240 {
241 struct mtk_pcie *pcie = port->pcie;
242 struct device *dev = pcie->dev;
243
244 devm_iounmap(dev, port->base);
245 list_del(&port->list);
246 devm_kfree(dev, port);
247 }
248
249 static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
250 {
251 struct mtk_pcie_port *port, *tmp;
252
253 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
254 phy_power_off(port->phy);
255 phy_exit(port->phy);
256 clk_disable_unprepare(port->pipe_ck);
257 clk_disable_unprepare(port->obff_ck);
258 clk_disable_unprepare(port->axi_ck);
259 clk_disable_unprepare(port->aux_ck);
260 clk_disable_unprepare(port->ahb_ck);
261 clk_disable_unprepare(port->sys_ck);
262 mtk_pcie_port_free(port);
263 }
264
265 mtk_pcie_subsys_powerdown(pcie);
266 }
267
268 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
269 {
270 u32 val;
271 int err;
272
273 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
274 !(val & APP_CFG_REQ), 10,
275 100 * USEC_PER_MSEC);
276 if (err)
277 return PCIBIOS_SET_FAILED;
278
279 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
280 return PCIBIOS_SET_FAILED;
281
282 return PCIBIOS_SUCCESSFUL;
283 }
284
285 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
286 int where, int size, u32 *val)
287 {
288 u32 tmp;
289
290 /* Write PCIe configuration transaction header for Cfgrd */
291 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
292 port->base + PCIE_CFG_HEADER0);
293 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
294 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
295 port->base + PCIE_CFG_HEADER2);
296
297 /* Trigger h/w to transmit Cfgrd TLP */
298 tmp = readl(port->base + PCIE_APP_TLP_REQ);
299 tmp |= APP_CFG_REQ;
300 writel(tmp, port->base + PCIE_APP_TLP_REQ);
301
302 /* Check completion status */
303 if (mtk_pcie_check_cfg_cpld(port))
304 return PCIBIOS_SET_FAILED;
305
306 /* Read cpld payload of Cfgrd */
307 *val = readl(port->base + PCIE_CFG_RDATA);
308
309 if (size == 1)
310 *val = (*val >> (8 * (where & 3))) & 0xff;
311 else if (size == 2)
312 *val = (*val >> (8 * (where & 3))) & 0xffff;
313
314 return PCIBIOS_SUCCESSFUL;
315 }
316
317 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
318 int where, int size, u32 val)
319 {
320 /* Write PCIe configuration transaction header for Cfgwr */
321 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
322 port->base + PCIE_CFG_HEADER0);
323 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
324 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
325 port->base + PCIE_CFG_HEADER2);
326
327 /* Write Cfgwr data */
328 val = val << 8 * (where & 3);
329 writel(val, port->base + PCIE_CFG_WDATA);
330
331 /* Trigger h/w to transmit Cfgwr TLP */
332 val = readl(port->base + PCIE_APP_TLP_REQ);
333 val |= APP_CFG_REQ;
334 writel(val, port->base + PCIE_APP_TLP_REQ);
335
336 /* Check completion status */
337 return mtk_pcie_check_cfg_cpld(port);
338 }
339
340 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
341 unsigned int devfn)
342 {
343 struct mtk_pcie *pcie = bus->sysdata;
344 struct mtk_pcie_port *port;
345 struct pci_dev *dev = NULL;
346
347 /*
348 * Walk the bus hierarchy to get the devfn value
349 * of the port in the root bus.
350 */
351 while (bus && bus->number) {
352 dev = bus->self;
353 bus = dev->bus;
354 devfn = dev->devfn;
355 }
356
357 list_for_each_entry(port, &pcie->ports, list)
358 if (port->slot == PCI_SLOT(devfn))
359 return port;
360
361 return NULL;
362 }
363
364 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
365 int where, int size, u32 *val)
366 {
367 struct mtk_pcie_port *port;
368 u32 bn = bus->number;
369 int ret;
370
371 port = mtk_pcie_find_port(bus, devfn);
372 if (!port) {
373 *val = ~0;
374 return PCIBIOS_DEVICE_NOT_FOUND;
375 }
376
377 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
378 if (ret)
379 *val = ~0;
380
381 return ret;
382 }
383
384 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
385 int where, int size, u32 val)
386 {
387 struct mtk_pcie_port *port;
388 u32 bn = bus->number;
389
390 port = mtk_pcie_find_port(bus, devfn);
391 if (!port)
392 return PCIBIOS_DEVICE_NOT_FOUND;
393
394 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
395 }
396
397 static struct pci_ops mtk_pcie_ops_v2 = {
398 .read = mtk_pcie_config_read,
399 .write = mtk_pcie_config_write,
400 };
401
402 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
403 {
404 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
405 phys_addr_t addr;
406
407 /* MT2712/MT7622 only support 32-bit MSI addresses */
408 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
409 msg->address_hi = 0;
410 msg->address_lo = lower_32_bits(addr);
411
412 msg->data = data->hwirq;
413
414 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
415 (int)data->hwirq, msg->address_hi, msg->address_lo);
416 }
417
418 static int mtk_msi_set_affinity(struct irq_data *irq_data,
419 const struct cpumask *mask, bool force)
420 {
421 return -EINVAL;
422 }
423
424 static void mtk_msi_ack_irq(struct irq_data *data)
425 {
426 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
427 u32 hwirq = data->hwirq;
428
429 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
430 }
431
432 static struct irq_chip mtk_msi_bottom_irq_chip = {
433 .name = "MTK MSI",
434 .irq_compose_msi_msg = mtk_compose_msi_msg,
435 .irq_set_affinity = mtk_msi_set_affinity,
436 .irq_ack = mtk_msi_ack_irq,
437 };
438
439 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
440 unsigned int nr_irqs, void *args)
441 {
442 struct mtk_pcie_port *port = domain->host_data;
443 unsigned long bit;
444
445 WARN_ON(nr_irqs != 1);
446 mutex_lock(&port->lock);
447
448 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
449 if (bit >= MTK_MSI_IRQS_NUM) {
450 mutex_unlock(&port->lock);
451 return -ENOSPC;
452 }
453
454 __set_bit(bit, port->msi_irq_in_use);
455
456 mutex_unlock(&port->lock);
457
458 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
459 domain->host_data, handle_edge_irq,
460 NULL, NULL);
461
462 return 0;
463 }
464
465 static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
466 unsigned int virq, unsigned int nr_irqs)
467 {
468 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
469 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
470
471 mutex_lock(&port->lock);
472
473 if (!test_bit(d->hwirq, port->msi_irq_in_use))
474 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
475 d->hwirq);
476 else
477 __clear_bit(d->hwirq, port->msi_irq_in_use);
478
479 mutex_unlock(&port->lock);
480
481 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
482 }
483
484 static const struct irq_domain_ops msi_domain_ops = {
485 .alloc = mtk_pcie_irq_domain_alloc,
486 .free = mtk_pcie_irq_domain_free,
487 };
488
489 static struct irq_chip mtk_msi_irq_chip = {
490 .name = "MTK PCIe MSI",
491 .irq_ack = irq_chip_ack_parent,
492 .irq_mask = pci_msi_mask_irq,
493 .irq_unmask = pci_msi_unmask_irq,
494 };
495
496 static struct msi_domain_info mtk_msi_domain_info = {
497 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
498 MSI_FLAG_PCI_MSIX),
499 .chip = &mtk_msi_irq_chip,
500 };
501
502 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
503 {
504 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
505
506 mutex_init(&port->lock);
507
508 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
509 &msi_domain_ops, port);
510 if (!port->inner_domain) {
511 dev_err(port->pcie->dev, "failed to create IRQ domain\n");
512 return -ENOMEM;
513 }
514
515 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
516 port->inner_domain);
517 if (!port->msi_domain) {
518 dev_err(port->pcie->dev, "failed to create MSI domain\n");
519 irq_domain_remove(port->inner_domain);
520 return -ENOMEM;
521 }
522
523 return 0;
524 }
525
526 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
527 {
528 u32 val;
529 phys_addr_t msg_addr;
530
531 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
532 val = lower_32_bits(msg_addr);
533 writel(val, port->base + PCIE_IMSI_ADDR);
534
535 val = readl(port->base + PCIE_INT_MASK);
536 val &= ~MSI_MASK;
537 writel(val, port->base + PCIE_INT_MASK);
538 }
539
540 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
541 irq_hw_number_t hwirq)
542 {
543 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
544 irq_set_chip_data(irq, domain->host_data);
545
546 return 0;
547 }
548
549 static const struct irq_domain_ops intx_domain_ops = {
550 .map = mtk_pcie_intx_map,
551 };
552
553 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
554 struct device_node *node)
555 {
556 struct device *dev = port->pcie->dev;
557 struct device_node *pcie_intc_node;
558 int ret;
559
560 /* Setup INTx */
561 pcie_intc_node = of_get_next_child(node, NULL);
562 if (!pcie_intc_node) {
563 dev_err(dev, "no PCIe Intc node found\n");
564 return -ENODEV;
565 }
566
567 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
568 &intx_domain_ops, port);
569 if (!port->irq_domain) {
570 dev_err(dev, "failed to get INTx IRQ domain\n");
571 return -ENODEV;
572 }
573
574 if (IS_ENABLED(CONFIG_PCI_MSI)) {
575 ret = mtk_pcie_allocate_msi_domains(port);
576 if (ret)
577 return ret;
578 }
579
580 return 0;
581 }
582
583 static void mtk_pcie_intr_handler(struct irq_desc *desc)
584 {
585 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
586 struct irq_chip *irqchip = irq_desc_get_chip(desc);
587 unsigned long status;
588 u32 virq;
589 u32 bit = INTX_SHIFT;
590
591 chained_irq_enter(irqchip, desc);
592
593 status = readl(port->base + PCIE_INT_STATUS);
594 if (status & INTX_MASK) {
595 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
596 /* Clear the INTx */
597 writel(1 << bit, port->base + PCIE_INT_STATUS);
598 virq = irq_find_mapping(port->irq_domain,
599 bit - INTX_SHIFT);
600 generic_handle_irq(virq);
601 }
602 }
603
604 if (IS_ENABLED(CONFIG_PCI_MSI)) {
605 if (status & MSI_STATUS){
606 unsigned long imsi_status;
607
608 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
609 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
610 virq = irq_find_mapping(port->inner_domain, bit);
611 generic_handle_irq(virq);
612 }
613 }
614 /* Clear MSI interrupt status */
615 writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
616 }
617 }
618
619 chained_irq_exit(irqchip, desc);
620
621 return;
622 }
623
624 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
625 struct device_node *node)
626 {
627 struct mtk_pcie *pcie = port->pcie;
628 struct device *dev = pcie->dev;
629 struct platform_device *pdev = to_platform_device(dev);
630 int err, irq;
631
632 err = mtk_pcie_init_irq_domain(port, node);
633 if (err) {
634 dev_err(dev, "failed to init PCIe IRQ domain\n");
635 return err;
636 }
637
638 irq = platform_get_irq(pdev, port->slot);
639 irq_set_chained_handler_and_data(irq, mtk_pcie_intr_handler, port);
640
641 return 0;
642 }
643
644 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
645 {
646 struct mtk_pcie *pcie = port->pcie;
647 struct resource *mem = &pcie->mem;
648 const struct mtk_pcie_soc *soc = port->pcie->soc;
649 u32 val;
650 size_t size;
651 int err;
652
653 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
654 if (pcie->base) {
655 val = readl(pcie->base + PCIE_SYS_CFG_V2);
656 val |= PCIE_CSR_LTSSM_EN(port->slot) |
657 PCIE_CSR_ASPM_L1_EN(port->slot);
658 writel(val, pcie->base + PCIE_SYS_CFG_V2);
659 }
660
661 /* Assert all reset signals */
662 writel(0, port->base + PCIE_RST_CTRL);
663
664 /*
665 * Enable PCIe link down reset, if link status changed from link up to
666 * link down, this will reset MAC control registers and configuration
667 * space.
668 */
669 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
670
671 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
672 val = readl(port->base + PCIE_RST_CTRL);
673 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
674 PCIE_MAC_SRSTB | PCIE_CRSTB;
675 writel(val, port->base + PCIE_RST_CTRL);
676
677 /* Set up vendor ID and class code */
678 if (soc->need_fix_class_id) {
679 val = PCI_VENDOR_ID_MEDIATEK;
680 writew(val, port->base + PCIE_CONF_VEND_ID);
681
682 val = PCI_CLASS_BRIDGE_PCI;
683 writew(val, port->base + PCIE_CONF_CLASS_ID);
684 }
685
686 if (soc->need_fix_device_id)
687 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
688
689 /* 100ms timeout value should be enough for Gen1/2 training */
690 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
691 !!(val & PCIE_PORT_LINKUP_V2), 20,
692 100 * USEC_PER_MSEC);
693 if (err)
694 return -ETIMEDOUT;
695
696 /* Set INTx mask */
697 val = readl(port->base + PCIE_INT_MASK);
698 val &= ~INTX_MASK;
699 writel(val, port->base + PCIE_INT_MASK);
700
701 if (IS_ENABLED(CONFIG_PCI_MSI))
702 mtk_pcie_enable_msi(port);
703
704 /* Set AHB to PCIe translation windows */
705 size = mem->end - mem->start;
706 val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
707 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
708
709 val = upper_32_bits(mem->start);
710 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
711
712 /* Set PCIe to AXI translation memory space.*/
713 val = fls(0xffffffff) | WIN_ENABLE;
714 writel(val, port->base + PCIE_AXI_WINDOW0);
715
716 return 0;
717 }
718
719 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
720 unsigned int devfn, int where)
721 {
722 struct mtk_pcie *pcie = bus->sysdata;
723
724 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
725 bus->number), pcie->base + PCIE_CFG_ADDR);
726
727 return pcie->base + PCIE_CFG_DATA + (where & 3);
728 }
729
730 static struct pci_ops mtk_pcie_ops = {
731 .map_bus = mtk_pcie_map_bus,
732 .read = pci_generic_config_read,
733 .write = pci_generic_config_write,
734 };
735
736 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
737 {
738 struct mtk_pcie *pcie = port->pcie;
739 u32 func = PCI_FUNC(port->slot << 3);
740 u32 slot = PCI_SLOT(port->slot << 3);
741 u32 val;
742 int err;
743
744 /* assert port PERST_N */
745 val = readl(pcie->base + PCIE_SYS_CFG);
746 val |= PCIE_PORT_PERST(port->slot);
747 writel(val, pcie->base + PCIE_SYS_CFG);
748
749 /* de-assert port PERST_N */
750 val = readl(pcie->base + PCIE_SYS_CFG);
751 val &= ~PCIE_PORT_PERST(port->slot);
752 writel(val, pcie->base + PCIE_SYS_CFG);
753
754 /* 100ms timeout value should be enough for Gen1/2 training */
755 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
756 !!(val & PCIE_PORT_LINKUP), 20,
757 100 * USEC_PER_MSEC);
758 if (err)
759 return -ETIMEDOUT;
760
761 /* enable interrupt */
762 val = readl(pcie->base + PCIE_INT_ENABLE);
763 val |= PCIE_PORT_INT_EN(port->slot);
764 writel(val, pcie->base + PCIE_INT_ENABLE);
765
766 /* map to all DDR region. We need to set it before cfg operation. */
767 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
768 port->base + PCIE_BAR0_SETUP);
769
770 /* configure class code and revision ID */
771 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
772
773 /* configure FC credit */
774 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
775 pcie->base + PCIE_CFG_ADDR);
776 val = readl(pcie->base + PCIE_CFG_DATA);
777 val &= ~PCIE_FC_CREDIT_MASK;
778 val |= PCIE_FC_CREDIT_VAL(0x806c);
779 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
780 pcie->base + PCIE_CFG_ADDR);
781 writel(val, pcie->base + PCIE_CFG_DATA);
782
783 /* configure RC FTS number to 250 when it leaves L0s */
784 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
785 pcie->base + PCIE_CFG_ADDR);
786 val = readl(pcie->base + PCIE_CFG_DATA);
787 val &= ~PCIE_FTS_NUM_MASK;
788 val |= PCIE_FTS_NUM_L0(0x50);
789 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
790 pcie->base + PCIE_CFG_ADDR);
791 writel(val, pcie->base + PCIE_CFG_DATA);
792
793 return 0;
794 }
795
796 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
797 {
798 struct mtk_pcie *pcie = port->pcie;
799 struct device *dev = pcie->dev;
800 int err;
801
802 err = clk_prepare_enable(port->sys_ck);
803 if (err) {
804 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
805 goto err_sys_clk;
806 }
807
808 err = clk_prepare_enable(port->ahb_ck);
809 if (err) {
810 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
811 goto err_ahb_clk;
812 }
813
814 err = clk_prepare_enable(port->aux_ck);
815 if (err) {
816 dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
817 goto err_aux_clk;
818 }
819
820 err = clk_prepare_enable(port->axi_ck);
821 if (err) {
822 dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
823 goto err_axi_clk;
824 }
825
826 err = clk_prepare_enable(port->obff_ck);
827 if (err) {
828 dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
829 goto err_obff_clk;
830 }
831
832 err = clk_prepare_enable(port->pipe_ck);
833 if (err) {
834 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
835 goto err_pipe_clk;
836 }
837
838 reset_control_assert(port->reset);
839 reset_control_deassert(port->reset);
840
841 err = phy_init(port->phy);
842 if (err) {
843 dev_err(dev, "failed to initialize port%d phy\n", port->slot);
844 goto err_phy_init;
845 }
846
847 err = phy_power_on(port->phy);
848 if (err) {
849 dev_err(dev, "failed to power on port%d phy\n", port->slot);
850 goto err_phy_on;
851 }
852
853 if (!pcie->soc->startup(port))
854 return;
855
856 dev_info(dev, "Port%d link down\n", port->slot);
857
858 phy_power_off(port->phy);
859 err_phy_on:
860 phy_exit(port->phy);
861 err_phy_init:
862 clk_disable_unprepare(port->pipe_ck);
863 err_pipe_clk:
864 clk_disable_unprepare(port->obff_ck);
865 err_obff_clk:
866 clk_disable_unprepare(port->axi_ck);
867 err_axi_clk:
868 clk_disable_unprepare(port->aux_ck);
869 err_aux_clk:
870 clk_disable_unprepare(port->ahb_ck);
871 err_ahb_clk:
872 clk_disable_unprepare(port->sys_ck);
873 err_sys_clk:
874 mtk_pcie_port_free(port);
875 }
876
877 static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
878 struct device_node *node,
879 int slot)
880 {
881 struct mtk_pcie_port *port;
882 struct resource *regs;
883 struct device *dev = pcie->dev;
884 struct platform_device *pdev = to_platform_device(dev);
885 char name[10];
886 int err;
887
888 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
889 if (!port)
890 return -ENOMEM;
891
892 err = of_property_read_u32(node, "num-lanes", &port->lane);
893 if (err) {
894 dev_err(dev, "missing num-lanes property\n");
895 return err;
896 }
897
898 snprintf(name, sizeof(name), "port%d", slot);
899 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
900 port->base = devm_ioremap_resource(dev, regs);
901 if (IS_ERR(port->base)) {
902 dev_err(dev, "failed to map port%d base\n", slot);
903 return PTR_ERR(port->base);
904 }
905
906 snprintf(name, sizeof(name), "sys_ck%d", slot);
907 port->sys_ck = devm_clk_get(dev, name);
908 if (IS_ERR(port->sys_ck)) {
909 dev_err(dev, "failed to get sys_ck%d clock\n", slot);
910 return PTR_ERR(port->sys_ck);
911 }
912
913 /* sys_ck might be divided into the following parts in some chips */
914 snprintf(name, sizeof(name), "ahb_ck%d", slot);
915 port->ahb_ck = devm_clk_get(dev, name);
916 if (IS_ERR(port->ahb_ck)) {
917 if (PTR_ERR(port->ahb_ck) == -EPROBE_DEFER)
918 return -EPROBE_DEFER;
919
920 port->ahb_ck = NULL;
921 }
922
923 snprintf(name, sizeof(name), "axi_ck%d", slot);
924 port->axi_ck = devm_clk_get(dev, name);
925 if (IS_ERR(port->axi_ck)) {
926 if (PTR_ERR(port->axi_ck) == -EPROBE_DEFER)
927 return -EPROBE_DEFER;
928
929 port->axi_ck = NULL;
930 }
931
932 snprintf(name, sizeof(name), "aux_ck%d", slot);
933 port->aux_ck = devm_clk_get(dev, name);
934 if (IS_ERR(port->aux_ck)) {
935 if (PTR_ERR(port->aux_ck) == -EPROBE_DEFER)
936 return -EPROBE_DEFER;
937
938 port->aux_ck = NULL;
939 }
940
941 snprintf(name, sizeof(name), "obff_ck%d", slot);
942 port->obff_ck = devm_clk_get(dev, name);
943 if (IS_ERR(port->obff_ck)) {
944 if (PTR_ERR(port->obff_ck) == -EPROBE_DEFER)
945 return -EPROBE_DEFER;
946
947 port->obff_ck = NULL;
948 }
949
950 snprintf(name, sizeof(name), "pipe_ck%d", slot);
951 port->pipe_ck = devm_clk_get(dev, name);
952 if (IS_ERR(port->pipe_ck)) {
953 if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER)
954 return -EPROBE_DEFER;
955
956 port->pipe_ck = NULL;
957 }
958
959 snprintf(name, sizeof(name), "pcie-rst%d", slot);
960 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
961 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
962 return PTR_ERR(port->reset);
963
964 /* some platforms may use default PHY setting */
965 snprintf(name, sizeof(name), "pcie-phy%d", slot);
966 port->phy = devm_phy_optional_get(dev, name);
967 if (IS_ERR(port->phy))
968 return PTR_ERR(port->phy);
969
970 port->slot = slot;
971 port->pcie = pcie;
972
973 if (pcie->soc->setup_irq) {
974 err = pcie->soc->setup_irq(port, node);
975 if (err)
976 return err;
977 }
978
979 INIT_LIST_HEAD(&port->list);
980 list_add_tail(&port->list, &pcie->ports);
981
982 return 0;
983 }
984
985 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
986 {
987 struct device *dev = pcie->dev;
988 struct platform_device *pdev = to_platform_device(dev);
989 struct resource *regs;
990 int err;
991
992 /* get shared registers, which are optional */
993 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
994 if (regs) {
995 pcie->base = devm_ioremap_resource(dev, regs);
996 if (IS_ERR(pcie->base)) {
997 dev_err(dev, "failed to map shared register\n");
998 return PTR_ERR(pcie->base);
999 }
1000 }
1001
1002 pcie->free_ck = devm_clk_get(dev, "free_ck");
1003 if (IS_ERR(pcie->free_ck)) {
1004 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
1005 return -EPROBE_DEFER;
1006
1007 pcie->free_ck = NULL;
1008 }
1009
1010 if (dev->pm_domain) {
1011 pm_runtime_enable(dev);
1012 pm_runtime_get_sync(dev);
1013 }
1014
1015 /* enable top level clock */
1016 err = clk_prepare_enable(pcie->free_ck);
1017 if (err) {
1018 dev_err(dev, "failed to enable free_ck\n");
1019 goto err_free_ck;
1020 }
1021
1022 return 0;
1023
1024 err_free_ck:
1025 if (dev->pm_domain) {
1026 pm_runtime_put_sync(dev);
1027 pm_runtime_disable(dev);
1028 }
1029
1030 return err;
1031 }
1032
1033 static int mtk_pcie_setup(struct mtk_pcie *pcie)
1034 {
1035 struct device *dev = pcie->dev;
1036 struct device_node *node = dev->of_node, *child;
1037 struct of_pci_range_parser parser;
1038 struct of_pci_range range;
1039 struct resource res;
1040 struct mtk_pcie_port *port, *tmp;
1041 int err;
1042
1043 if (of_pci_range_parser_init(&parser, node)) {
1044 dev_err(dev, "missing \"ranges\" property\n");
1045 return -EINVAL;
1046 }
1047
1048 for_each_of_pci_range(&parser, &range) {
1049 err = of_pci_range_to_resource(&range, node, &res);
1050 if (err < 0)
1051 return err;
1052
1053 switch (res.flags & IORESOURCE_TYPE_BITS) {
1054 case IORESOURCE_IO:
1055 pcie->offset.io = res.start - range.pci_addr;
1056
1057 memcpy(&pcie->pio, &res, sizeof(res));
1058 pcie->pio.name = node->full_name;
1059
1060 pcie->io.start = range.cpu_addr;
1061 pcie->io.end = range.cpu_addr + range.size - 1;
1062 pcie->io.flags = IORESOURCE_MEM;
1063 pcie->io.name = "I/O";
1064
1065 memcpy(&res, &pcie->io, sizeof(res));
1066 break;
1067
1068 case IORESOURCE_MEM:
1069 pcie->offset.mem = res.start - range.pci_addr;
1070
1071 memcpy(&pcie->mem, &res, sizeof(res));
1072 pcie->mem.name = "non-prefetchable";
1073 break;
1074 }
1075 }
1076
1077 err = of_pci_parse_bus_range(node, &pcie->busn);
1078 if (err < 0) {
1079 dev_err(dev, "failed to parse bus ranges property: %d\n", err);
1080 pcie->busn.name = node->name;
1081 pcie->busn.start = 0;
1082 pcie->busn.end = 0xff;
1083 pcie->busn.flags = IORESOURCE_BUS;
1084 }
1085
1086 for_each_available_child_of_node(node, child) {
1087 int slot;
1088
1089 err = of_pci_get_devfn(child);
1090 if (err < 0) {
1091 dev_err(dev, "failed to parse devfn: %d\n", err);
1092 return err;
1093 }
1094
1095 slot = PCI_SLOT(err);
1096
1097 err = mtk_pcie_parse_port(pcie, child, slot);
1098 if (err)
1099 return err;
1100 }
1101
1102 err = mtk_pcie_subsys_powerup(pcie);
1103 if (err)
1104 return err;
1105
1106 /* enable each port, and then check link status */
1107 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1108 mtk_pcie_enable_port(port);
1109
1110 /* power down PCIe subsys if slots are all empty (link down) */
1111 if (list_empty(&pcie->ports))
1112 mtk_pcie_subsys_powerdown(pcie);
1113
1114 return 0;
1115 }
1116
1117 static int mtk_pcie_request_resources(struct mtk_pcie *pcie)
1118 {
1119 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1120 struct list_head *windows = &host->windows;
1121 struct device *dev = pcie->dev;
1122 int err;
1123
1124 pci_add_resource_offset(windows, &pcie->pio, pcie->offset.io);
1125 pci_add_resource_offset(windows, &pcie->mem, pcie->offset.mem);
1126 pci_add_resource(windows, &pcie->busn);
1127
1128 err = devm_request_pci_bus_resources(dev, windows);
1129 if (err < 0)
1130 return err;
1131
1132 err = devm_pci_remap_iospace(dev, &pcie->pio, pcie->io.start);
1133 if (err)
1134 return err;
1135
1136 return 0;
1137 }
1138
1139 static int mtk_pcie_register_host(struct pci_host_bridge *host)
1140 {
1141 struct mtk_pcie *pcie = pci_host_bridge_priv(host);
1142 struct pci_bus *child;
1143 int err;
1144
1145 host->busnr = pcie->busn.start;
1146 host->dev.parent = pcie->dev;
1147 host->ops = pcie->soc->ops;
1148 host->map_irq = of_irq_parse_and_map_pci;
1149 host->swizzle_irq = pci_common_swizzle;
1150 host->sysdata = pcie;
1151
1152 err = pci_scan_root_bus_bridge(host);
1153 if (err < 0)
1154 return err;
1155
1156 pci_bus_size_bridges(host->bus);
1157 pci_bus_assign_resources(host->bus);
1158
1159 list_for_each_entry(child, &host->bus->children, node)
1160 pcie_bus_configure_settings(child);
1161
1162 pci_bus_add_devices(host->bus);
1163
1164 return 0;
1165 }
1166
1167 static int mtk_pcie_probe(struct platform_device *pdev)
1168 {
1169 struct device *dev = &pdev->dev;
1170 struct mtk_pcie *pcie;
1171 struct pci_host_bridge *host;
1172 int err;
1173
1174 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1175 if (!host)
1176 return -ENOMEM;
1177
1178 pcie = pci_host_bridge_priv(host);
1179
1180 pcie->dev = dev;
1181 pcie->soc = of_device_get_match_data(dev);
1182 platform_set_drvdata(pdev, pcie);
1183 INIT_LIST_HEAD(&pcie->ports);
1184
1185 err = mtk_pcie_setup(pcie);
1186 if (err)
1187 return err;
1188
1189 err = mtk_pcie_request_resources(pcie);
1190 if (err)
1191 goto put_resources;
1192
1193 err = mtk_pcie_register_host(host);
1194 if (err)
1195 goto put_resources;
1196
1197 return 0;
1198
1199 put_resources:
1200 if (!list_empty(&pcie->ports))
1201 mtk_pcie_put_resources(pcie);
1202
1203 return err;
1204 }
1205
1206 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1207 .ops = &mtk_pcie_ops,
1208 .startup = mtk_pcie_startup_port,
1209 };
1210
1211 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1212 .ops = &mtk_pcie_ops_v2,
1213 .startup = mtk_pcie_startup_port_v2,
1214 .setup_irq = mtk_pcie_setup_irq,
1215 };
1216
1217 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1218 .need_fix_class_id = true,
1219 .ops = &mtk_pcie_ops_v2,
1220 .startup = mtk_pcie_startup_port_v2,
1221 .setup_irq = mtk_pcie_setup_irq,
1222 };
1223
1224 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1225 .need_fix_class_id = true,
1226 .need_fix_device_id = true,
1227 .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1228 .ops = &mtk_pcie_ops_v2,
1229 .startup = mtk_pcie_startup_port_v2,
1230 .setup_irq = mtk_pcie_setup_irq,
1231 };
1232
1233 static const struct of_device_id mtk_pcie_ids[] = {
1234 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1235 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1236 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1237 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1238 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1239 {},
1240 };
1241
1242 static struct platform_driver mtk_pcie_driver = {
1243 .probe = mtk_pcie_probe,
1244 .driver = {
1245 .name = "mtk-pcie",
1246 .of_match_table = mtk_pcie_ids,
1247 .suppress_bind_attrs = true,
1248 },
1249 };
1250 builtin_platform_driver(mtk_pcie_driver);
Linux with added FPC-III support