drivers/pci/hotplug/shpchp.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Standard Hot Plug Controller Driver
   4  *
   5  * Copyright (C) 1995,2001 Compaq Computer Corporation
   6  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   7  * Copyright (C) 2001 IBM
   8  * Copyright (C) 2003-2004 Intel Corporation
   9  *
  10  * All rights reserved.
  11  *
  12  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  13  *
  14  */
  15 #ifndef _SHPCHP_H
  16 #define _SHPCHP_H
  17
  18 #include <linux/types.h>
  19 #include <linux/pci.h>
  20 #include <linux/pci_hotplug.h>
  21 #include <linux/delay.h>
  22 #include <linux/sched/signal.h> /* signal_pending(), struct timer_list */
  23 #include <linux/mutex.h>
  24 #include <linux/workqueue.h>
  25
  26 #if !defined(MODULE)
  27         #define MY_NAME "shpchp"
  28 #else
  29         #define MY_NAME THIS_MODULE->name
  30 #endif
  31
  32 extern bool shpchp_poll_mode;
  33 extern int shpchp_poll_time;
  34 extern bool shpchp_debug;
  35
  36 #define dbg(format, arg...)                                             \
  37 do {                                                                    \
  38         if (shpchp_debug)                                               \
  39                 printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg);      \
  40 } while (0)
  41 #define err(format, arg...)                                             \
  42         printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
  43 #define info(format, arg...)                                            \
  44         printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
  45 #define warn(format, arg...)                                            \
  46         printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
  47
  48 #define ctrl_dbg(ctrl, format, arg...)                                  \
  49         do {                                                            \
  50                 if (shpchp_debug)                                       \
  51                         pci_printk(KERN_DEBUG, ctrl->pci_dev,           \
  52                                         format, ## arg);                \
  53         } while (0)
  54 #define ctrl_err(ctrl, format, arg...)                                  \
  55         pci_err(ctrl->pci_dev, format, ## arg)
  56 #define ctrl_info(ctrl, format, arg...)                                 \
  57         pci_info(ctrl->pci_dev, format, ## arg)
  58 #define ctrl_warn(ctrl, format, arg...)                                 \
  59         pci_warn(ctrl->pci_dev, format, ## arg)
  60
  61
  62 #define SLOT_NAME_SIZE 10
  63 struct slot {
  64         u8 bus;
  65         u8 device;
  66         u16 status;
  67         u32 number;
  68         u8 is_a_board;
  69         u8 state;
  70         u8 presence_save;
  71         u8 pwr_save;
  72         struct controller *ctrl;
  73         const struct hpc_ops *hpc_ops;
  74         struct hotplug_slot *hotplug_slot;
  75         struct list_head        slot_list;
  76         struct delayed_work work;       /* work for button event */
  77         struct mutex lock;
  78         struct workqueue_struct *wq;
  79         u8 hp_slot;
  80 };
  81
  82 struct event_info {
  83         u32 event_type;
  84         struct slot *p_slot;
  85         struct work_struct work;
  86 };
  87
  88 struct controller {
  89         struct mutex crit_sect;         /* critical section mutex */
  90         struct mutex cmd_lock;          /* command lock */
  91         int num_slots;                  /* Number of slots on ctlr */
  92         int slot_num_inc;               /* 1 or -1 */
  93         struct pci_dev *pci_dev;
  94         struct list_head slot_list;
  95         const struct hpc_ops *hpc_ops;
  96         wait_queue_head_t queue;        /* sleep & wake process */
  97         u8 slot_device_offset;
  98         u32 pcix_misc2_reg;     /* for amd pogo errata */
  99         u32 first_slot;         /* First physical slot number */
 100         u32 cap_offset;
 101         unsigned long mmio_base;
 102         unsigned long mmio_size;
 103         void __iomem *creg;
 104         struct timer_list poll_timer;
 105 };
 106
 107 /* Define AMD SHPC ID  */
 108 #define PCI_DEVICE_ID_AMD_POGO_7458     0x7458
 109
 110 /* AMD PCI-X bridge registers */
 111 #define PCIX_MEM_BASE_LIMIT_OFFSET      0x1C
 112 #define PCIX_MISCII_OFFSET              0x48
 113 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET  0x80
 114
 115 /* AMD PCIX_MISCII masks and offsets */
 116 #define PERRNONFATALENABLE_MASK         0x00040000
 117 #define PERRFATALENABLE_MASK            0x00080000
 118 #define PERRFLOODENABLE_MASK            0x00100000
 119 #define SERRNONFATALENABLE_MASK         0x00200000
 120 #define SERRFATALENABLE_MASK            0x00400000
 121
 122 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
 123 #define PERR_OBSERVED_MASK              0x00000001
 124
 125 /* AMD PCIX_MEM_BASE_LIMIT masks */
 126 #define RSE_MASK                        0x40000000
 127
 128 #define INT_BUTTON_IGNORE               0
 129 #define INT_PRESENCE_ON                 1
 130 #define INT_PRESENCE_OFF                2
 131 #define INT_SWITCH_CLOSE                3
 132 #define INT_SWITCH_OPEN                 4
 133 #define INT_POWER_FAULT                 5
 134 #define INT_POWER_FAULT_CLEAR           6
 135 #define INT_BUTTON_PRESS                7
 136 #define INT_BUTTON_RELEASE              8
 137 #define INT_BUTTON_CANCEL               9
 138
 139 #define STATIC_STATE                    0
 140 #define BLINKINGON_STATE                1
 141 #define BLINKINGOFF_STATE               2
 142 #define POWERON_STATE                   3
 143 #define POWEROFF_STATE                  4
 144
 145 /* Error messages */
 146 #define INTERLOCK_OPEN                  0x00000002
 147 #define ADD_NOT_SUPPORTED               0x00000003
 148 #define CARD_FUNCTIONING                0x00000005
 149 #define ADAPTER_NOT_SAME                0x00000006
 150 #define NO_ADAPTER_PRESENT              0x00000009
 151 #define NOT_ENOUGH_RESOURCES            0x0000000B
 152 #define DEVICE_TYPE_NOT_SUPPORTED       0x0000000C
 153 #define WRONG_BUS_FREQUENCY             0x0000000D
 154 #define POWER_FAILURE                   0x0000000E
 155
 156 int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
 157 void shpchp_remove_ctrl_files(struct controller *ctrl);
 158 int shpchp_sysfs_enable_slot(struct slot *slot);
 159 int shpchp_sysfs_disable_slot(struct slot *slot);
 160 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
 161 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
 162 u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
 163 u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
 164 int shpchp_configure_device(struct slot *p_slot);
 165 int shpchp_unconfigure_device(struct slot *p_slot);
 166 void cleanup_slots(struct controller *ctrl);
 167 void shpchp_queue_pushbutton_work(struct work_struct *work);
 168 int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
 169
 170 static inline const char *slot_name(struct slot *slot)
 171 {
 172         return hotplug_slot_name(slot->hotplug_slot);
 173 }
 174
 175 struct ctrl_reg {
 176         volatile u32 base_offset;
 177         volatile u32 slot_avail1;
 178         volatile u32 slot_avail2;
 179         volatile u32 slot_config;
 180         volatile u16 sec_bus_config;
 181         volatile u8  msi_ctrl;
 182         volatile u8  prog_interface;
 183         volatile u16 cmd;
 184         volatile u16 cmd_status;
 185         volatile u32 intr_loc;
 186         volatile u32 serr_loc;
 187         volatile u32 serr_intr_enable;
 188         volatile u32 slot1;
 189 } __attribute__ ((packed));
 190
 191 /* offsets to the controller registers based on the above structure layout */
 192 enum ctrl_offsets {
 193         BASE_OFFSET      = offsetof(struct ctrl_reg, base_offset),
 194         SLOT_AVAIL1      = offsetof(struct ctrl_reg, slot_avail1),
 195         SLOT_AVAIL2      = offsetof(struct ctrl_reg, slot_avail2),
 196         SLOT_CONFIG      = offsetof(struct ctrl_reg, slot_config),
 197         SEC_BUS_CONFIG   = offsetof(struct ctrl_reg, sec_bus_config),
 198         MSI_CTRL         = offsetof(struct ctrl_reg, msi_ctrl),
 199         PROG_INTERFACE   = offsetof(struct ctrl_reg, prog_interface),
 200         CMD              = offsetof(struct ctrl_reg, cmd),
 201         CMD_STATUS       = offsetof(struct ctrl_reg, cmd_status),
 202         INTR_LOC         = offsetof(struct ctrl_reg, intr_loc),
 203         SERR_LOC         = offsetof(struct ctrl_reg, serr_loc),
 204         SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
 205         SLOT1            = offsetof(struct ctrl_reg, slot1),
 206 };
 207
 208 static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
 209 {
 210         return hotplug_slot->private;
 211 }
 212
 213 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
 214 {
 215         struct slot *slot;
 216
 217         list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
 218                 if (slot->device == device)
 219                         return slot;
 220         }
 221
 222         ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
 223         return NULL;
 224 }
 225
 226 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
 227 {
 228         u32 pcix_misc2_temp;
 229
 230         /* save MiscII register */
 231         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
 232
 233         p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
 234
 235         /* clear SERR/PERR enable bits */
 236         pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
 237         pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
 238         pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
 239         pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
 240         pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
 241         pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
 242 }
 243
 244 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
 245 {
 246         u32 pcix_misc2_temp;
 247         u32 pcix_bridge_errors_reg;
 248         u32 pcix_mem_base_reg;
 249         u8  perr_set;
 250         u8  rse_set;
 251
 252         /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
 253         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
 254         perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
 255         if (perr_set) {
 256                 ctrl_dbg(p_slot->ctrl,
 257                          "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
 258                          perr_set);
 259
 260                 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
 261         }
 262
 263         /* write-one-to-clear Memory_Base_Limit[ RSE ] */
 264         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
 265         rse_set = pcix_mem_base_reg & RSE_MASK;
 266         if (rse_set) {
 267                 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
 268
 269                 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
 270         }
 271         /* restore MiscII register */
 272         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
 273
 274         if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
 275                 pcix_misc2_temp |= SERRFATALENABLE_MASK;
 276         else
 277                 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
 278
 279         if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
 280                 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
 281         else
 282                 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
 283
 284         if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
 285                 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
 286         else
 287                 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
 288
 289         if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
 290                 pcix_misc2_temp |= PERRFATALENABLE_MASK;
 291         else
 292                 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
 293
 294         if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
 295                 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
 296         else
 297                 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
 298         pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
 299 }
 300
 301 struct hpc_ops {
 302         int (*power_on_slot)(struct slot *slot);
 303         int (*slot_enable)(struct slot *slot);
 304         int (*slot_disable)(struct slot *slot);
 305         int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
 306         int (*get_power_status)(struct slot *slot, u8 *status);
 307         int (*get_attention_status)(struct slot *slot, u8 *status);
 308         int (*set_attention_status)(struct slot *slot, u8 status);
 309         int (*get_latch_status)(struct slot *slot, u8 *status);
 310         int (*get_adapter_status)(struct slot *slot, u8 *status);
 311         int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
 312         int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
 313         int (*get_prog_int)(struct slot *slot, u8 *prog_int);
 314         int (*query_power_fault)(struct slot *slot);
 315         void (*green_led_on)(struct slot *slot);
 316         void (*green_led_off)(struct slot *slot);
 317         void (*green_led_blink)(struct slot *slot);
 318         void (*release_ctlr)(struct controller *ctrl);
 319         int (*check_cmd_status)(struct controller *ctrl);
 320 };
 321
 322 #endif                          /* _SHPCHP_H */