drivers/pci/pci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef DRIVERS_PCI_H
   3 #define DRIVERS_PCI_H
   4
   5 #define PCI_FIND_CAP_TTL        48
   6
   7 #define PCI_VSEC_ID_INTEL_TBT   0x1234  /* Thunderbolt */
   8
   9 extern const unsigned char pcie_link_speed[];
  10 extern bool pci_early_dump;
  11
  12 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
  13
  14 /* Functions internal to the PCI core code */
  15
  16 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  17 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  18 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
  19 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  20 { return; }
  21 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  22 { return; }
  23 #else
  24 void pci_create_firmware_label_files(struct pci_dev *pdev);
  25 void pci_remove_firmware_label_files(struct pci_dev *pdev);
  26 #endif
  27 void pci_cleanup_rom(struct pci_dev *dev);
  28
  29 enum pci_mmap_api {
  30         PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  31         PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  32 };
  33 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
  34                   enum pci_mmap_api mmap_api);
  35
  36 int pci_probe_reset_function(struct pci_dev *dev);
  37 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
  38 int pci_bus_error_reset(struct pci_dev *dev);
  39
  40 /**
  41  * struct pci_platform_pm_ops - Firmware PM callbacks
  42  *
  43  * @is_manageable: returns 'true' if given device is power manageable by the
  44  *                 platform firmware
  45  *
  46  * @set_state: invokes the platform firmware to set the device's power state
  47  *
  48  * @get_state: queries the platform firmware for a device's current power state
  49  *
  50  * @choose_state: returns PCI power state of given device preferred by the
  51  *                platform; to be used during system-wide transitions from a
  52  *                sleeping state to the working state and vice versa
  53  *
  54  * @set_wakeup: enables/disables wakeup capability for the device
  55  *
  56  * @need_resume: returns 'true' if the given device (which is currently
  57  *               suspended) needs to be resumed to be configured for system
  58  *               wakeup.
  59  *
  60  * If given platform is generally capable of power managing PCI devices, all of
  61  * these callbacks are mandatory.
  62  */
  63 struct pci_platform_pm_ops {
  64         bool (*is_manageable)(struct pci_dev *dev);
  65         int (*set_state)(struct pci_dev *dev, pci_power_t state);
  66         pci_power_t (*get_state)(struct pci_dev *dev);
  67         pci_power_t (*choose_state)(struct pci_dev *dev);
  68         int (*set_wakeup)(struct pci_dev *dev, bool enable);
  69         bool (*need_resume)(struct pci_dev *dev);
  70 };
  71
  72 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
  73 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  74 void pci_power_up(struct pci_dev *dev);
  75 void pci_disable_enabled_device(struct pci_dev *dev);
  76 int pci_finish_runtime_suspend(struct pci_dev *dev);
  77 void pcie_clear_root_pme_status(struct pci_dev *dev);
  78 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  79 void pci_pme_restore(struct pci_dev *dev);
  80 bool pci_dev_keep_suspended(struct pci_dev *dev);
  81 void pci_dev_complete_resume(struct pci_dev *pci_dev);
  82 void pci_config_pm_runtime_get(struct pci_dev *dev);
  83 void pci_config_pm_runtime_put(struct pci_dev *dev);
  84 void pci_pm_init(struct pci_dev *dev);
  85 void pci_ea_init(struct pci_dev *dev);
  86 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
  87 void pci_free_cap_save_buffers(struct pci_dev *dev);
  88 bool pci_bridge_d3_possible(struct pci_dev *dev);
  89 void pci_bridge_d3_update(struct pci_dev *dev);
  90
  91 static inline void pci_wakeup_event(struct pci_dev *dev)
  92 {
  93         /* Wait 100 ms before the system can be put into a sleep state. */
  94         pm_wakeup_event(&dev->dev, 100);
  95 }
  96
  97 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
  98 {
  99         return !!(pci_dev->subordinate);
 100 }
 101
 102 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
 103 {
 104         /*
 105          * Currently we allow normal PCI devices and PCI bridges transition
 106          * into D3 if their bridge_d3 is set.
 107          */
 108         return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
 109 }
 110
 111 int pci_vpd_init(struct pci_dev *dev);
 112 void pci_vpd_release(struct pci_dev *dev);
 113 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
 114 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
 115
 116 /* PCI /proc functions */
 117 #ifdef CONFIG_PROC_FS
 118 int pci_proc_attach_device(struct pci_dev *dev);
 119 int pci_proc_detach_device(struct pci_dev *dev);
 120 int pci_proc_detach_bus(struct pci_bus *bus);
 121 #else
 122 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
 123 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
 124 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
 125 #endif
 126
 127 /* Functions for PCI Hotplug drivers to use */
 128 int pci_hp_add_bridge(struct pci_dev *dev);
 129
 130 #ifdef HAVE_PCI_LEGACY
 131 void pci_create_legacy_files(struct pci_bus *bus);
 132 void pci_remove_legacy_files(struct pci_bus *bus);
 133 #else
 134 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
 135 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
 136 #endif
 137
 138 /* Lock for read/write access to pci device and bus lists */
 139 extern struct rw_semaphore pci_bus_sem;
 140 extern struct mutex pci_slot_mutex;
 141
 142 extern raw_spinlock_t pci_lock;
 143
 144 extern unsigned int pci_pm_d3_delay;
 145
 146 #ifdef CONFIG_PCI_MSI
 147 void pci_no_msi(void);
 148 #else
 149 static inline void pci_no_msi(void) { }
 150 #endif
 151
 152 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
 153 {
 154         u16 control;
 155
 156         pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 157         control &= ~PCI_MSI_FLAGS_ENABLE;
 158         if (enable)
 159                 control |= PCI_MSI_FLAGS_ENABLE;
 160         pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
 161 }
 162
 163 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
 164 {
 165         u16 ctrl;
 166
 167         pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
 168         ctrl &= ~clear;
 169         ctrl |= set;
 170         pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
 171 }
 172
 173 void pci_realloc_get_opt(char *);
 174
 175 static inline int pci_no_d1d2(struct pci_dev *dev)
 176 {
 177         unsigned int parent_dstates = 0;
 178
 179         if (dev->bus->self)
 180                 parent_dstates = dev->bus->self->no_d1d2;
 181         return (dev->no_d1d2 || parent_dstates);
 182
 183 }
 184 extern const struct attribute_group *pci_dev_groups[];
 185 extern const struct attribute_group *pcibus_groups[];
 186 extern const struct device_type pci_dev_type;
 187 extern const struct attribute_group *pci_bus_groups[];
 188
 189
 190 /**
 191  * pci_match_one_device - Tell if a PCI device structure has a matching
 192  *                        PCI device id structure
 193  * @id: single PCI device id structure to match
 194  * @dev: the PCI device structure to match against
 195  *
 196  * Returns the matching pci_device_id structure or %NULL if there is no match.
 197  */
 198 static inline const struct pci_device_id *
 199 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
 200 {
 201         if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
 202             (id->device == PCI_ANY_ID || id->device == dev->device) &&
 203             (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
 204             (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
 205             !((id->class ^ dev->class) & id->class_mask))
 206                 return id;
 207         return NULL;
 208 }
 209
 210 /* PCI slot sysfs helper code */
 211 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
 212
 213 extern struct kset *pci_slots_kset;
 214
 215 struct pci_slot_attribute {
 216         struct attribute attr;
 217         ssize_t (*show)(struct pci_slot *, char *);
 218         ssize_t (*store)(struct pci_slot *, const char *, size_t);
 219 };
 220 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
 221
 222 enum pci_bar_type {
 223         pci_bar_unknown,        /* Standard PCI BAR probe */
 224         pci_bar_io,             /* An I/O port BAR */
 225         pci_bar_mem32,          /* A 32-bit memory BAR */
 226         pci_bar_mem64,          /* A 64-bit memory BAR */
 227 };
 228
 229 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
 230 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 231                                 int crs_timeout);
 232 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 233                                         int crs_timeout);
 234 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
 235
 236 int pci_setup_device(struct pci_dev *dev);
 237 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 238                     struct resource *res, unsigned int reg);
 239 void pci_configure_ari(struct pci_dev *dev);
 240 void __pci_bus_size_bridges(struct pci_bus *bus,
 241                         struct list_head *realloc_head);
 242 void __pci_bus_assign_resources(const struct pci_bus *bus,
 243                                 struct list_head *realloc_head,
 244                                 struct list_head *fail_head);
 245 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
 246
 247 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
 248 void pci_disable_bridge_window(struct pci_dev *dev);
 249
 250 /* PCIe link information */
 251 #define PCIE_SPEED2STR(speed) \
 252         ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
 253          (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
 254          (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
 255          (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
 256          "Unknown speed")
 257
 258 /* PCIe speed to Mb/s reduced by encoding overhead */
 259 #define PCIE_SPEED2MBS_ENC(speed) \
 260         ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
 261          (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
 262          (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \
 263          (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
 264          0)
 265
 266 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
 267 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
 268 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
 269                            enum pcie_link_width *width);
 270 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
 271
 272 /* Single Root I/O Virtualization */
 273 struct pci_sriov {
 274         int             pos;            /* Capability position */
 275         int             nres;           /* Number of resources */
 276         u32             cap;            /* SR-IOV Capabilities */
 277         u16             ctrl;           /* SR-IOV Control */
 278         u16             total_VFs;      /* Total VFs associated with the PF */
 279         u16             initial_VFs;    /* Initial VFs associated with the PF */
 280         u16             num_VFs;        /* Number of VFs available */
 281         u16             offset;         /* First VF Routing ID offset */
 282         u16             stride;         /* Following VF stride */
 283         u16             vf_device;      /* VF device ID */
 284         u32             pgsz;           /* Page size for BAR alignment */
 285         u8              link;           /* Function Dependency Link */
 286         u8              max_VF_buses;   /* Max buses consumed by VFs */
 287         u16             driver_max_VFs; /* Max num VFs driver supports */
 288         struct pci_dev  *dev;           /* Lowest numbered PF */
 289         struct pci_dev  *self;          /* This PF */
 290         u32             class;          /* VF device */
 291         u8              hdr_type;       /* VF header type */
 292         u16             subsystem_vendor; /* VF subsystem vendor */
 293         u16             subsystem_device; /* VF subsystem device */
 294         resource_size_t barsz[PCI_SRIOV_NUM_BARS];      /* VF BAR size */
 295         bool            drivers_autoprobe; /* Auto probing of VFs by driver */
 296 };
 297
 298 /* pci_dev priv_flags */
 299 #define PCI_DEV_DISCONNECTED 0
 300 #define PCI_DEV_ADDED 1
 301
 302 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
 303 {
 304         set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
 305         return 0;
 306 }
 307
 308 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
 309 {
 310         return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
 311 }
 312
 313 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
 314 {
 315         assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
 316 }
 317
 318 static inline bool pci_dev_is_added(const struct pci_dev *dev)
 319 {
 320         return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
 321 }
 322
 323 #ifdef CONFIG_PCIEAER
 324 #include <linux/aer.h>
 325
 326 #define AER_MAX_MULTI_ERR_DEVICES       5       /* Not likely to have more */
 327
 328 struct aer_err_info {
 329         struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
 330         int error_dev_num;
 331
 332         unsigned int id:16;
 333
 334         unsigned int severity:2;        /* 0:NONFATAL | 1:FATAL | 2:COR */
 335         unsigned int __pad1:5;
 336         unsigned int multi_error_valid:1;
 337
 338         unsigned int first_error:5;
 339         unsigned int __pad2:2;
 340         unsigned int tlp_header_valid:1;
 341
 342         unsigned int status;            /* COR/UNCOR Error Status */
 343         unsigned int mask;              /* COR/UNCOR Error Mask */
 344         struct aer_header_log_regs tlp; /* TLP Header */
 345 };
 346
 347 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
 348 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
 349 #endif  /* CONFIG_PCIEAER */
 350
 351 #ifdef CONFIG_PCI_ATS
 352 void pci_restore_ats_state(struct pci_dev *dev);
 353 #else
 354 static inline void pci_restore_ats_state(struct pci_dev *dev)
 355 {
 356 }
 357 #endif /* CONFIG_PCI_ATS */
 358
 359 #ifdef CONFIG_PCI_IOV
 360 int pci_iov_init(struct pci_dev *dev);
 361 void pci_iov_release(struct pci_dev *dev);
 362 void pci_iov_remove(struct pci_dev *dev);
 363 void pci_iov_update_resource(struct pci_dev *dev, int resno);
 364 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
 365 void pci_restore_iov_state(struct pci_dev *dev);
 366 int pci_iov_bus_range(struct pci_bus *bus);
 367
 368 #else
 369 static inline int pci_iov_init(struct pci_dev *dev)
 370 {
 371         return -ENODEV;
 372 }
 373 static inline void pci_iov_release(struct pci_dev *dev)
 374
 375 {
 376 }
 377 static inline void pci_iov_remove(struct pci_dev *dev)
 378 {
 379 }
 380 static inline void pci_restore_iov_state(struct pci_dev *dev)
 381 {
 382 }
 383 static inline int pci_iov_bus_range(struct pci_bus *bus)
 384 {
 385         return 0;
 386 }
 387
 388 #endif /* CONFIG_PCI_IOV */
 389
 390 unsigned long pci_cardbus_resource_alignment(struct resource *);
 391
 392 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
 393                                                      struct resource *res)
 394 {
 395 #ifdef CONFIG_PCI_IOV
 396         int resno = res - dev->resource;
 397
 398         if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 399                 return pci_sriov_resource_alignment(dev, resno);
 400 #endif
 401         if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
 402                 return pci_cardbus_resource_alignment(res);
 403         return resource_alignment(res);
 404 }
 405
 406 void pci_enable_acs(struct pci_dev *dev);
 407 #ifdef CONFIG_PCI_QUIRKS
 408 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
 409 int pci_dev_specific_enable_acs(struct pci_dev *dev);
 410 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
 411 #else
 412 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
 413                                                u16 acs_flags)
 414 {
 415         return -ENOTTY;
 416 }
 417 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
 418 {
 419         return -ENOTTY;
 420 }
 421 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
 422 {
 423         return -ENOTTY;
 424 }
 425 #endif
 426
 427 /* PCI error reporting and recovery */
 428 void pcie_do_fatal_recovery(struct pci_dev *dev, u32 service);
 429 void pcie_do_nonfatal_recovery(struct pci_dev *dev);
 430
 431 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
 432 #ifdef CONFIG_PCIEASPM
 433 void pcie_aspm_init_link_state(struct pci_dev *pdev);
 434 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
 435 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
 436 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 437 #else
 438 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
 439 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
 440 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
 441 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
 442 #endif
 443
 444 #ifdef CONFIG_PCIEASPM_DEBUG
 445 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
 446 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
 447 #else
 448 static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
 449 static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
 450 #endif
 451
 452 #ifdef CONFIG_PCIE_PTM
 453 void pci_ptm_init(struct pci_dev *dev);
 454 #else
 455 static inline void pci_ptm_init(struct pci_dev *dev) { }
 456 #endif
 457
 458 struct pci_dev_reset_methods {
 459         u16 vendor;
 460         u16 device;
 461         int (*reset)(struct pci_dev *dev, int probe);
 462 };
 463
 464 #ifdef CONFIG_PCI_QUIRKS
 465 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
 466 #else
 467 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
 468 {
 469         return -ENOTTY;
 470 }
 471 #endif
 472
 473 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
 474 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
 475                           struct resource *res);
 476 #endif
 477
 478 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
 479 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
 480 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
 481 static inline u64 pci_rebar_size_to_bytes(int size)
 482 {
 483         return 1ULL << (size + 20);
 484 }
 485
 486 struct device_node;
 487
 488 #ifdef CONFIG_OF
 489 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 490 int of_get_pci_domain_nr(struct device_node *node);
 491 int of_pci_get_max_link_speed(struct device_node *node);
 492
 493 #else
 494 static inline int
 495 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
 496 {
 497         return -EINVAL;
 498 }
 499
 500 static inline int
 501 of_get_pci_domain_nr(struct device_node *node)
 502 {
 503         return -1;
 504 }
 505
 506 static inline int
 507 of_pci_get_max_link_speed(struct device_node *node)
 508 {
 509         return -EINVAL;
 510 }
 511 #endif /* CONFIG_OF */
 512
 513 #if defined(CONFIG_OF_ADDRESS)
 514 int devm_of_pci_get_host_bridge_resources(struct device *dev,
 515                         unsigned char busno, unsigned char bus_max,
 516                         struct list_head *resources, resource_size_t *io_base);
 517 #else
 518 static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
 519                         unsigned char busno, unsigned char bus_max,
 520                         struct list_head *resources, resource_size_t *io_base)
 521 {
 522         return -EINVAL;
 523 }
 524 #endif
 525
 526 #ifdef CONFIG_PCIEAER
 527 void pci_no_aer(void);
 528 void pci_aer_init(struct pci_dev *dev);
 529 void pci_aer_exit(struct pci_dev *dev);
 530 extern const struct attribute_group aer_stats_attr_group;
 531 void pci_aer_clear_fatal_status(struct pci_dev *dev);
 532 void pci_aer_clear_device_status(struct pci_dev *dev);
 533 #else
 534 static inline void pci_no_aer(void) { }
 535 static inline void pci_aer_init(struct pci_dev *d) { }
 536 static inline void pci_aer_exit(struct pci_dev *d) { }
 537 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
 538 static inline void pci_aer_clear_device_status(struct pci_dev *dev) { }
 539 #endif
 540
 541 #endif /* DRIVERS_PCI_H */