Linux 4.19.133
[linux/fpc-iii.git] / drivers / pci / proc.c
blob7ac035af39f0458ac26431a0629e3d0a144939d7
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Procfs interface for the PCI bus
5 * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
6 */
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/proc_fs.h>
13 #include <linux/seq_file.h>
14 #include <linux/capability.h>
15 #include <linux/uaccess.h>
16 #include <asm/byteorder.h>
17 #include "pci.h"
19 static int proc_initialized; /* = 0 */
21 static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
23 struct pci_dev *dev = PDE_DATA(file_inode(file));
24 return fixed_size_llseek(file, off, whence, dev->cfg_size);
27 static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
28 size_t nbytes, loff_t *ppos)
30 struct pci_dev *dev = PDE_DATA(file_inode(file));
31 unsigned int pos = *ppos;
32 unsigned int cnt, size;
35 * Normal users can read only the standardized portion of the
36 * configuration space as several chips lock up when trying to read
37 * undefined locations (think of Intel PIIX4 as a typical example).
40 if (capable(CAP_SYS_ADMIN))
41 size = dev->cfg_size;
42 else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
43 size = 128;
44 else
45 size = 64;
47 if (pos >= size)
48 return 0;
49 if (nbytes >= size)
50 nbytes = size;
51 if (pos + nbytes > size)
52 nbytes = size - pos;
53 cnt = nbytes;
55 if (!access_ok(VERIFY_WRITE, buf, cnt))
56 return -EINVAL;
58 pci_config_pm_runtime_get(dev);
60 if ((pos & 1) && cnt) {
61 unsigned char val;
62 pci_user_read_config_byte(dev, pos, &val);
63 __put_user(val, buf);
64 buf++;
65 pos++;
66 cnt--;
69 if ((pos & 3) && cnt > 2) {
70 unsigned short val;
71 pci_user_read_config_word(dev, pos, &val);
72 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
73 buf += 2;
74 pos += 2;
75 cnt -= 2;
78 while (cnt >= 4) {
79 unsigned int val;
80 pci_user_read_config_dword(dev, pos, &val);
81 __put_user(cpu_to_le32(val), (__le32 __user *) buf);
82 buf += 4;
83 pos += 4;
84 cnt -= 4;
87 if (cnt >= 2) {
88 unsigned short val;
89 pci_user_read_config_word(dev, pos, &val);
90 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
91 buf += 2;
92 pos += 2;
93 cnt -= 2;
96 if (cnt) {
97 unsigned char val;
98 pci_user_read_config_byte(dev, pos, &val);
99 __put_user(val, buf);
100 buf++;
101 pos++;
102 cnt--;
105 pci_config_pm_runtime_put(dev);
107 *ppos = pos;
108 return nbytes;
111 static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
112 size_t nbytes, loff_t *ppos)
114 struct inode *ino = file_inode(file);
115 struct pci_dev *dev = PDE_DATA(ino);
116 int pos = *ppos;
117 int size = dev->cfg_size;
118 int cnt;
120 if (pos >= size)
121 return 0;
122 if (nbytes >= size)
123 nbytes = size;
124 if (pos + nbytes > size)
125 nbytes = size - pos;
126 cnt = nbytes;
128 if (!access_ok(VERIFY_READ, buf, cnt))
129 return -EINVAL;
131 pci_config_pm_runtime_get(dev);
133 if ((pos & 1) && cnt) {
134 unsigned char val;
135 __get_user(val, buf);
136 pci_user_write_config_byte(dev, pos, val);
137 buf++;
138 pos++;
139 cnt--;
142 if ((pos & 3) && cnt > 2) {
143 __le16 val;
144 __get_user(val, (__le16 __user *) buf);
145 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
146 buf += 2;
147 pos += 2;
148 cnt -= 2;
151 while (cnt >= 4) {
152 __le32 val;
153 __get_user(val, (__le32 __user *) buf);
154 pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
155 buf += 4;
156 pos += 4;
157 cnt -= 4;
160 if (cnt >= 2) {
161 __le16 val;
162 __get_user(val, (__le16 __user *) buf);
163 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
164 buf += 2;
165 pos += 2;
166 cnt -= 2;
169 if (cnt) {
170 unsigned char val;
171 __get_user(val, buf);
172 pci_user_write_config_byte(dev, pos, val);
173 buf++;
174 pos++;
175 cnt--;
178 pci_config_pm_runtime_put(dev);
180 *ppos = pos;
181 i_size_write(ino, dev->cfg_size);
182 return nbytes;
185 struct pci_filp_private {
186 enum pci_mmap_state mmap_state;
187 int write_combine;
190 static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
191 unsigned long arg)
193 struct pci_dev *dev = PDE_DATA(file_inode(file));
194 #ifdef HAVE_PCI_MMAP
195 struct pci_filp_private *fpriv = file->private_data;
196 #endif /* HAVE_PCI_MMAP */
197 int ret = 0;
199 switch (cmd) {
200 case PCIIOC_CONTROLLER:
201 ret = pci_domain_nr(dev->bus);
202 break;
204 #ifdef HAVE_PCI_MMAP
205 case PCIIOC_MMAP_IS_IO:
206 if (!arch_can_pci_mmap_io())
207 return -EINVAL;
208 fpriv->mmap_state = pci_mmap_io;
209 break;
211 case PCIIOC_MMAP_IS_MEM:
212 fpriv->mmap_state = pci_mmap_mem;
213 break;
215 case PCIIOC_WRITE_COMBINE:
216 if (arch_can_pci_mmap_wc()) {
217 if (arg)
218 fpriv->write_combine = 1;
219 else
220 fpriv->write_combine = 0;
221 break;
223 /* If arch decided it can't, fall through... */
224 #endif /* HAVE_PCI_MMAP */
225 default:
226 ret = -EINVAL;
227 break;
230 return ret;
233 #ifdef HAVE_PCI_MMAP
234 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
236 struct pci_dev *dev = PDE_DATA(file_inode(file));
237 struct pci_filp_private *fpriv = file->private_data;
238 int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM;
240 if (!capable(CAP_SYS_RAWIO))
241 return -EPERM;
243 if (fpriv->mmap_state == pci_mmap_io) {
244 if (!arch_can_pci_mmap_io())
245 return -EINVAL;
246 res_bit = IORESOURCE_IO;
249 /* Make sure the caller is mapping a real resource for this device */
250 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
251 if (dev->resource[i].flags & res_bit &&
252 pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
253 break;
256 if (i >= PCI_ROM_RESOURCE)
257 return -ENODEV;
259 if (fpriv->mmap_state == pci_mmap_mem &&
260 fpriv->write_combine) {
261 if (dev->resource[i].flags & IORESOURCE_PREFETCH)
262 write_combine = 1;
263 else
264 return -EINVAL;
266 ret = pci_mmap_page_range(dev, i, vma,
267 fpriv->mmap_state, write_combine);
268 if (ret < 0)
269 return ret;
271 return 0;
274 static int proc_bus_pci_open(struct inode *inode, struct file *file)
276 struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
278 if (!fpriv)
279 return -ENOMEM;
281 fpriv->mmap_state = pci_mmap_io;
282 fpriv->write_combine = 0;
284 file->private_data = fpriv;
286 return 0;
289 static int proc_bus_pci_release(struct inode *inode, struct file *file)
291 kfree(file->private_data);
292 file->private_data = NULL;
294 return 0;
296 #endif /* HAVE_PCI_MMAP */
298 static const struct file_operations proc_bus_pci_operations = {
299 .owner = THIS_MODULE,
300 .llseek = proc_bus_pci_lseek,
301 .read = proc_bus_pci_read,
302 .write = proc_bus_pci_write,
303 .unlocked_ioctl = proc_bus_pci_ioctl,
304 .compat_ioctl = proc_bus_pci_ioctl,
305 #ifdef HAVE_PCI_MMAP
306 .open = proc_bus_pci_open,
307 .release = proc_bus_pci_release,
308 .mmap = proc_bus_pci_mmap,
309 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
310 .get_unmapped_area = get_pci_unmapped_area,
311 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
312 #endif /* HAVE_PCI_MMAP */
315 /* iterator */
316 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
318 struct pci_dev *dev = NULL;
319 loff_t n = *pos;
321 for_each_pci_dev(dev) {
322 if (!n--)
323 break;
325 return dev;
328 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
330 struct pci_dev *dev = v;
332 (*pos)++;
333 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
334 return dev;
337 static void pci_seq_stop(struct seq_file *m, void *v)
339 if (v) {
340 struct pci_dev *dev = v;
341 pci_dev_put(dev);
345 static int show_device(struct seq_file *m, void *v)
347 const struct pci_dev *dev = v;
348 const struct pci_driver *drv;
349 int i;
351 if (dev == NULL)
352 return 0;
354 drv = pci_dev_driver(dev);
355 seq_printf(m, "%02x%02x\t%04x%04x\t%x",
356 dev->bus->number,
357 dev->devfn,
358 dev->vendor,
359 dev->device,
360 dev->irq);
362 /* only print standard and ROM resources to preserve compatibility */
363 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
364 resource_size_t start, end;
365 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
366 seq_printf(m, "\t%16llx",
367 (unsigned long long)(start |
368 (dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
370 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
371 resource_size_t start, end;
372 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
373 seq_printf(m, "\t%16llx",
374 dev->resource[i].start < dev->resource[i].end ?
375 (unsigned long long)(end - start) + 1 : 0);
377 seq_putc(m, '\t');
378 if (drv)
379 seq_printf(m, "%s", drv->name);
380 seq_putc(m, '\n');
381 return 0;
384 static const struct seq_operations proc_bus_pci_devices_op = {
385 .start = pci_seq_start,
386 .next = pci_seq_next,
387 .stop = pci_seq_stop,
388 .show = show_device
391 static struct proc_dir_entry *proc_bus_pci_dir;
393 int pci_proc_attach_device(struct pci_dev *dev)
395 struct pci_bus *bus = dev->bus;
396 struct proc_dir_entry *e;
397 char name[16];
399 if (!proc_initialized)
400 return -EACCES;
402 if (!bus->procdir) {
403 if (pci_proc_domain(bus)) {
404 sprintf(name, "%04x:%02x", pci_domain_nr(bus),
405 bus->number);
406 } else {
407 sprintf(name, "%02x", bus->number);
409 bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
410 if (!bus->procdir)
411 return -ENOMEM;
414 sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
415 e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
416 &proc_bus_pci_operations, dev);
417 if (!e)
418 return -ENOMEM;
419 proc_set_size(e, dev->cfg_size);
420 dev->procent = e;
422 return 0;
425 int pci_proc_detach_device(struct pci_dev *dev)
427 proc_remove(dev->procent);
428 dev->procent = NULL;
429 return 0;
432 int pci_proc_detach_bus(struct pci_bus *bus)
434 proc_remove(bus->procdir);
435 return 0;
438 static int __init pci_proc_init(void)
440 struct pci_dev *dev = NULL;
441 proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
442 proc_create_seq("devices", 0, proc_bus_pci_dir,
443 &proc_bus_pci_devices_op);
444 proc_initialized = 1;
445 for_each_pci_dev(dev)
446 pci_proc_attach_device(dev);
448 return 0;
450 device_initcall(pci_proc_init);