drivers/pinctrl/intel/pinctrl-broxton.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Broxton SoC pinctrl/GPIO driver
   4  *
   5  * Copyright (C) 2015, 2016 Intel Corporation
   6  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/pm.h>
  13 #include <linux/pinctrl/pinctrl.h>
  14
  15 #include "pinctrl-intel.h"
  16
  17 #define BXT_PAD_OWN     0x020
  18 #define BXT_HOSTSW_OWN  0x080
  19 #define BXT_PADCFGLOCK  0x060
  20 #define BXT_GPI_IE      0x110
  21
  22 #define BXT_COMMUNITY(s, e)                             \
  23         {                                               \
  24                 .padown_offset = BXT_PAD_OWN,           \
  25                 .padcfglock_offset = BXT_PADCFGLOCK,    \
  26                 .hostown_offset = BXT_HOSTSW_OWN,       \
  27                 .ie_offset = BXT_GPI_IE,                \
  28                 .gpp_size = 32,                         \
  29                 .pin_base = (s),                        \
  30                 .npins = ((e) - (s) + 1),               \
  31         }
  32
  33 /* BXT */
  34 static const struct pinctrl_pin_desc bxt_north_pins[] = {
  35         PINCTRL_PIN(0, "GPIO_0"),
  36         PINCTRL_PIN(1, "GPIO_1"),
  37         PINCTRL_PIN(2, "GPIO_2"),
  38         PINCTRL_PIN(3, "GPIO_3"),
  39         PINCTRL_PIN(4, "GPIO_4"),
  40         PINCTRL_PIN(5, "GPIO_5"),
  41         PINCTRL_PIN(6, "GPIO_6"),
  42         PINCTRL_PIN(7, "GPIO_7"),
  43         PINCTRL_PIN(8, "GPIO_8"),
  44         PINCTRL_PIN(9, "GPIO_9"),
  45         PINCTRL_PIN(10, "GPIO_10"),
  46         PINCTRL_PIN(11, "GPIO_11"),
  47         PINCTRL_PIN(12, "GPIO_12"),
  48         PINCTRL_PIN(13, "GPIO_13"),
  49         PINCTRL_PIN(14, "GPIO_14"),
  50         PINCTRL_PIN(15, "GPIO_15"),
  51         PINCTRL_PIN(16, "GPIO_16"),
  52         PINCTRL_PIN(17, "GPIO_17"),
  53         PINCTRL_PIN(18, "GPIO_18"),
  54         PINCTRL_PIN(19, "GPIO_19"),
  55         PINCTRL_PIN(20, "GPIO_20"),
  56         PINCTRL_PIN(21, "GPIO_21"),
  57         PINCTRL_PIN(22, "GPIO_22"),
  58         PINCTRL_PIN(23, "GPIO_23"),
  59         PINCTRL_PIN(24, "GPIO_24"),
  60         PINCTRL_PIN(25, "GPIO_25"),
  61         PINCTRL_PIN(26, "GPIO_26"),
  62         PINCTRL_PIN(27, "GPIO_27"),
  63         PINCTRL_PIN(28, "GPIO_28"),
  64         PINCTRL_PIN(29, "GPIO_29"),
  65         PINCTRL_PIN(30, "GPIO_30"),
  66         PINCTRL_PIN(31, "GPIO_31"),
  67         PINCTRL_PIN(32, "GPIO_32"),
  68         PINCTRL_PIN(33, "GPIO_33"),
  69         PINCTRL_PIN(34, "PWM0"),
  70         PINCTRL_PIN(35, "PWM1"),
  71         PINCTRL_PIN(36, "PWM2"),
  72         PINCTRL_PIN(37, "PWM3"),
  73         PINCTRL_PIN(38, "LPSS_UART0_RXD"),
  74         PINCTRL_PIN(39, "LPSS_UART0_TXD"),
  75         PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
  76         PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
  77         PINCTRL_PIN(42, "LPSS_UART1_RXD"),
  78         PINCTRL_PIN(43, "LPSS_UART1_TXD"),
  79         PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
  80         PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
  81         PINCTRL_PIN(46, "LPSS_UART2_RXD"),
  82         PINCTRL_PIN(47, "LPSS_UART2_TXD"),
  83         PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
  84         PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
  85         PINCTRL_PIN(50, "ISH_UART0_RXD"),
  86         PINCTRL_PIN(51, "ISH_UART0_TXT"),
  87         PINCTRL_PIN(52, "ISH_UART0_RTS_B"),
  88         PINCTRL_PIN(53, "ISH_UART0_CTS_B"),
  89         PINCTRL_PIN(54, "ISH_UART1_RXD"),
  90         PINCTRL_PIN(55, "ISH_UART1_TXT"),
  91         PINCTRL_PIN(56, "ISH_UART1_RTS_B"),
  92         PINCTRL_PIN(57, "ISH_UART1_CTS_B"),
  93         PINCTRL_PIN(58, "ISH_UART2_RXD"),
  94         PINCTRL_PIN(59, "ISH_UART2_TXD"),
  95         PINCTRL_PIN(60, "ISH_UART2_RTS_B"),
  96         PINCTRL_PIN(61, "ISH_UART2_CTS_B"),
  97         PINCTRL_PIN(62, "GP_CAMERASB00"),
  98         PINCTRL_PIN(63, "GP_CAMERASB01"),
  99         PINCTRL_PIN(64, "GP_CAMERASB02"),
 100         PINCTRL_PIN(65, "GP_CAMERASB03"),
 101         PINCTRL_PIN(66, "GP_CAMERASB04"),
 102         PINCTRL_PIN(67, "GP_CAMERASB05"),
 103         PINCTRL_PIN(68, "GP_CAMERASB06"),
 104         PINCTRL_PIN(69, "GP_CAMERASB07"),
 105         PINCTRL_PIN(70, "GP_CAMERASB08"),
 106         PINCTRL_PIN(71, "GP_CAMERASB09"),
 107         PINCTRL_PIN(72, "GP_CAMERASB10"),
 108         PINCTRL_PIN(73, "GP_CAMERASB11"),
 109         PINCTRL_PIN(74, "TCK"),
 110         PINCTRL_PIN(75, "TRST_B"),
 111         PINCTRL_PIN(76, "TMS"),
 112         PINCTRL_PIN(77, "TDI"),
 113         PINCTRL_PIN(78, "CX_PMODE"),
 114         PINCTRL_PIN(79, "CX_PREQ_B"),
 115         PINCTRL_PIN(80, "JTAGX"),
 116         PINCTRL_PIN(81, "CX_PRDY_B"),
 117         PINCTRL_PIN(82, "TDO"),
 118 };
 119
 120 static const unsigned bxt_north_pwm0_pins[] = { 34 };
 121 static const unsigned bxt_north_pwm1_pins[] = { 35 };
 122 static const unsigned bxt_north_pwm2_pins[] = { 36 };
 123 static const unsigned bxt_north_pwm3_pins[] = { 37 };
 124 static const unsigned bxt_north_uart0_pins[] = { 38, 39, 40, 41 };
 125 static const unsigned bxt_north_uart1_pins[] = { 42, 43, 44, 45 };
 126 static const unsigned bxt_north_uart2_pins[] = { 46, 47, 48, 49 };
 127 static const unsigned bxt_north_uart0b_pins[] = { 50, 51, 52, 53 };
 128 static const unsigned bxt_north_uart1b_pins[] = { 54, 55, 56, 57 };
 129 static const unsigned bxt_north_uart2b_pins[] = { 58, 59, 60, 61 };
 130 static const unsigned bxt_north_uart3_pins[] = { 58, 59, 60, 61 };
 131
 132 static const struct intel_pingroup bxt_north_groups[] = {
 133         PIN_GROUP("pwm0_grp", bxt_north_pwm0_pins, 1),
 134         PIN_GROUP("pwm1_grp", bxt_north_pwm1_pins, 1),
 135         PIN_GROUP("pwm2_grp", bxt_north_pwm2_pins, 1),
 136         PIN_GROUP("pwm3_grp", bxt_north_pwm3_pins, 1),
 137         PIN_GROUP("uart0_grp", bxt_north_uart0_pins, 1),
 138         PIN_GROUP("uart1_grp", bxt_north_uart1_pins, 1),
 139         PIN_GROUP("uart2_grp", bxt_north_uart2_pins, 1),
 140         PIN_GROUP("uart0b_grp", bxt_north_uart0b_pins, 2),
 141         PIN_GROUP("uart1b_grp", bxt_north_uart1b_pins, 2),
 142         PIN_GROUP("uart2b_grp", bxt_north_uart2b_pins, 2),
 143         PIN_GROUP("uart3_grp", bxt_north_uart3_pins, 3),
 144 };
 145
 146 static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" };
 147 static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" };
 148 static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" };
 149 static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" };
 150 static const char * const bxt_north_uart0_groups[] = {
 151         "uart0_grp", "uart0b_grp",
 152 };
 153 static const char * const bxt_north_uart1_groups[] = {
 154         "uart1_grp", "uart1b_grp",
 155 };
 156 static const char * const bxt_north_uart2_groups[] = {
 157         "uart2_grp", "uart2b_grp",
 158 };
 159 static const char * const bxt_north_uart3_groups[] = { "uart3_grp" };
 160
 161 static const struct intel_function bxt_north_functions[] = {
 162         FUNCTION("pwm0", bxt_north_pwm0_groups),
 163         FUNCTION("pwm1", bxt_north_pwm1_groups),
 164         FUNCTION("pwm2", bxt_north_pwm2_groups),
 165         FUNCTION("pwm3", bxt_north_pwm3_groups),
 166         FUNCTION("uart0", bxt_north_uart0_groups),
 167         FUNCTION("uart1", bxt_north_uart1_groups),
 168         FUNCTION("uart2", bxt_north_uart2_groups),
 169         FUNCTION("uart3", bxt_north_uart3_groups),
 170 };
 171
 172 static const struct intel_community bxt_north_communities[] = {
 173         BXT_COMMUNITY(0, 82),
 174 };
 175
 176 static const struct intel_pinctrl_soc_data bxt_north_soc_data = {
 177         .uid = "1",
 178         .pins = bxt_north_pins,
 179         .npins = ARRAY_SIZE(bxt_north_pins),
 180         .groups = bxt_north_groups,
 181         .ngroups = ARRAY_SIZE(bxt_north_groups),
 182         .functions = bxt_north_functions,
 183         .nfunctions = ARRAY_SIZE(bxt_north_functions),
 184         .communities = bxt_north_communities,
 185         .ncommunities = ARRAY_SIZE(bxt_north_communities),
 186 };
 187
 188 static const struct pinctrl_pin_desc bxt_northwest_pins[] = {
 189         PINCTRL_PIN(0, "PMC_SPI_FS0"),
 190         PINCTRL_PIN(1, "PMC_SPI_FS1"),
 191         PINCTRL_PIN(2, "PMC_SPI_FS2"),
 192         PINCTRL_PIN(3, "PMC_SPI_RXD"),
 193         PINCTRL_PIN(4, "PMC_SPI_TXD"),
 194         PINCTRL_PIN(5, "PMC_SPI_CLK"),
 195         PINCTRL_PIN(6, "PMC_UART_RXD"),
 196         PINCTRL_PIN(7, "PMC_UART_TXD"),
 197         PINCTRL_PIN(8, "PMIC_PWRGOOD"),
 198         PINCTRL_PIN(9, "PMIC_RESET_B"),
 199         PINCTRL_PIN(10, "RTC_CLK"),
 200         PINCTRL_PIN(11, "PMIC_SDWN_B"),
 201         PINCTRL_PIN(12, "PMIC_BCUDISW2"),
 202         PINCTRL_PIN(13, "PMIC_BCUDISCRIT"),
 203         PINCTRL_PIN(14, "PMIC_THERMTRIP_B"),
 204         PINCTRL_PIN(15, "PMIC_STDBY"),
 205         PINCTRL_PIN(16, "SVID0_ALERT_B"),
 206         PINCTRL_PIN(17, "SVID0_DATA"),
 207         PINCTRL_PIN(18, "SVID0_CLK"),
 208         PINCTRL_PIN(19, "PMIC_I2C_SCL"),
 209         PINCTRL_PIN(20, "PMIC_I2C_SDA"),
 210         PINCTRL_PIN(21, "AVS_I2S1_MCLK"),
 211         PINCTRL_PIN(22, "AVS_I2S1_BCLK"),
 212         PINCTRL_PIN(23, "AVS_I2S1_WS_SYNC"),
 213         PINCTRL_PIN(24, "AVS_I2S1_SDI"),
 214         PINCTRL_PIN(25, "AVS_I2S1_SDO"),
 215         PINCTRL_PIN(26, "AVS_M_CLK_A1"),
 216         PINCTRL_PIN(27, "AVS_M_CLK_B1"),
 217         PINCTRL_PIN(28, "AVS_M_DATA_1"),
 218         PINCTRL_PIN(29, "AVS_M_CLK_AB2"),
 219         PINCTRL_PIN(30, "AVS_M_DATA_2"),
 220         PINCTRL_PIN(31, "AVS_I2S2_MCLK"),
 221         PINCTRL_PIN(32, "AVS_I2S2_BCLK"),
 222         PINCTRL_PIN(33, "AVS_I2S2_WS_SYNC"),
 223         PINCTRL_PIN(34, "AVS_I2S2_SDI"),
 224         PINCTRL_PIN(35, "AVS_I2S2_SDOK"),
 225         PINCTRL_PIN(36, "AVS_I2S3_BCLK"),
 226         PINCTRL_PIN(37, "AVS_I2S3_WS_SYNC"),
 227         PINCTRL_PIN(38, "AVS_I2S3_SDI"),
 228         PINCTRL_PIN(39, "AVS_I2S3_SDO"),
 229         PINCTRL_PIN(40, "AVS_I2S4_BCLK"),
 230         PINCTRL_PIN(41, "AVS_I2S4_WS_SYNC"),
 231         PINCTRL_PIN(42, "AVS_I2S4_SDI"),
 232         PINCTRL_PIN(43, "AVS_I2S4_SDO"),
 233         PINCTRL_PIN(44, "PROCHOT_B"),
 234         PINCTRL_PIN(45, "FST_SPI_CS0_B"),
 235         PINCTRL_PIN(46, "FST_SPI_CS1_B"),
 236         PINCTRL_PIN(47, "FST_SPI_MOSI_IO0"),
 237         PINCTRL_PIN(48, "FST_SPI_MISO_IO1"),
 238         PINCTRL_PIN(49, "FST_SPI_IO2"),
 239         PINCTRL_PIN(50, "FST_SPI_IO3"),
 240         PINCTRL_PIN(51, "FST_SPI_CLK"),
 241         PINCTRL_PIN(52, "FST_SPI_CLK_FB"),
 242         PINCTRL_PIN(53, "GP_SSP_0_CLK"),
 243         PINCTRL_PIN(54, "GP_SSP_0_FS0"),
 244         PINCTRL_PIN(55, "GP_SSP_0_FS1"),
 245         PINCTRL_PIN(56, "GP_SSP_0_FS2"),
 246         PINCTRL_PIN(57, "GP_SSP_0_RXD"),
 247         PINCTRL_PIN(58, "GP_SSP_0_TXD"),
 248         PINCTRL_PIN(59, "GP_SSP_1_CLK"),
 249         PINCTRL_PIN(60, "GP_SSP_1_FS0"),
 250         PINCTRL_PIN(61, "GP_SSP_1_FS1"),
 251         PINCTRL_PIN(62, "GP_SSP_1_FS2"),
 252         PINCTRL_PIN(63, "GP_SSP_1_FS3"),
 253         PINCTRL_PIN(64, "GP_SSP_1_RXD"),
 254         PINCTRL_PIN(65, "GP_SSP_1_TXD"),
 255         PINCTRL_PIN(66, "GP_SSP_2_CLK"),
 256         PINCTRL_PIN(67, "GP_SSP_2_FS0"),
 257         PINCTRL_PIN(68, "GP_SSP_2_FS1"),
 258         PINCTRL_PIN(69, "GP_SSP_2_FS2"),
 259         PINCTRL_PIN(70, "GP_SSP_2_RXD"),
 260         PINCTRL_PIN(71, "GP_SSP_2_TXD"),
 261 };
 262
 263 static const unsigned bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 };
 264 static const unsigned bxt_northwest_ssp1_pins[] = {
 265         59, 60, 61, 62, 63, 64, 65
 266 };
 267 static const unsigned bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 };
 268 static const unsigned bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 };
 269
 270 static const struct intel_pingroup bxt_northwest_groups[] = {
 271         PIN_GROUP("ssp0_grp", bxt_northwest_ssp0_pins, 1),
 272         PIN_GROUP("ssp1_grp", bxt_northwest_ssp1_pins, 1),
 273         PIN_GROUP("ssp2_grp", bxt_northwest_ssp2_pins, 1),
 274         PIN_GROUP("uart3_grp", bxt_northwest_uart3_pins, 2),
 275 };
 276
 277 static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" };
 278 static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" };
 279 static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" };
 280 static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" };
 281
 282 static const struct intel_function bxt_northwest_functions[] = {
 283         FUNCTION("ssp0", bxt_northwest_ssp0_groups),
 284         FUNCTION("ssp1", bxt_northwest_ssp1_groups),
 285         FUNCTION("ssp2", bxt_northwest_ssp2_groups),
 286         FUNCTION("uart3", bxt_northwest_uart3_groups),
 287 };
 288
 289 static const struct intel_community bxt_northwest_communities[] = {
 290         BXT_COMMUNITY(0, 71),
 291 };
 292
 293 static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = {
 294         .uid = "2",
 295         .pins = bxt_northwest_pins,
 296         .npins = ARRAY_SIZE(bxt_northwest_pins),
 297         .groups = bxt_northwest_groups,
 298         .ngroups = ARRAY_SIZE(bxt_northwest_groups),
 299         .functions = bxt_northwest_functions,
 300         .nfunctions = ARRAY_SIZE(bxt_northwest_functions),
 301         .communities = bxt_northwest_communities,
 302         .ncommunities = ARRAY_SIZE(bxt_northwest_communities),
 303 };
 304
 305 static const struct pinctrl_pin_desc bxt_west_pins[] = {
 306         PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
 307         PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
 308         PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
 309         PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
 310         PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
 311         PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
 312         PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
 313         PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
 314         PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
 315         PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
 316         PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
 317         PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
 318         PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
 319         PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
 320         PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
 321         PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
 322         PINCTRL_PIN(16, "ISH_I2C0_SDA"),
 323         PINCTRL_PIN(17, "ISH_I2C0_SCL"),
 324         PINCTRL_PIN(18, "ISH_I2C1_SDA"),
 325         PINCTRL_PIN(19, "ISH_I2C1_SCL"),
 326         PINCTRL_PIN(20, "ISH_I2C2_SDA"),
 327         PINCTRL_PIN(21, "ISH_I2C2_SCL"),
 328         PINCTRL_PIN(22, "ISH_GPIO_0"),
 329         PINCTRL_PIN(23, "ISH_GPIO_1"),
 330         PINCTRL_PIN(24, "ISH_GPIO_2"),
 331         PINCTRL_PIN(25, "ISH_GPIO_3"),
 332         PINCTRL_PIN(26, "ISH_GPIO_4"),
 333         PINCTRL_PIN(27, "ISH_GPIO_5"),
 334         PINCTRL_PIN(28, "ISH_GPIO_6"),
 335         PINCTRL_PIN(29, "ISH_GPIO_7"),
 336         PINCTRL_PIN(30, "ISH_GPIO_8"),
 337         PINCTRL_PIN(31, "ISH_GPIO_9"),
 338         PINCTRL_PIN(32, "MODEM_CLKREQ"),
 339         PINCTRL_PIN(33, "DGCLKDBG_PMC_0"),
 340         PINCTRL_PIN(34, "DGCLKDBG_PMC_1"),
 341         PINCTRL_PIN(35, "DGCLKDBG_PMC_2"),
 342         PINCTRL_PIN(36, "DGCLKDBG_ICLK_0"),
 343         PINCTRL_PIN(37, "DGCLKDBG_ICLK_1"),
 344         PINCTRL_PIN(38, "OSC_CLK_OUT_0"),
 345         PINCTRL_PIN(39, "OSC_CLK_OUT_1"),
 346         PINCTRL_PIN(40, "OSC_CLK_OUT_2"),
 347         PINCTRL_PIN(41, "OSC_CLK_OUT_3"),
 348 };
 349
 350 static const unsigned bxt_west_i2c0_pins[] = { 0, 1 };
 351 static const unsigned bxt_west_i2c1_pins[] = { 2, 3 };
 352 static const unsigned bxt_west_i2c2_pins[] = { 4, 5 };
 353 static const unsigned bxt_west_i2c3_pins[] = { 6, 7 };
 354 static const unsigned bxt_west_i2c4_pins[] = { 8, 9 };
 355 static const unsigned bxt_west_i2c5_pins[] = { 10, 11 };
 356 static const unsigned bxt_west_i2c6_pins[] = { 12, 13 };
 357 static const unsigned bxt_west_i2c7_pins[] = { 14, 15 };
 358 static const unsigned bxt_west_i2c5b_pins[] = { 16, 17 };
 359 static const unsigned bxt_west_i2c6b_pins[] = { 18, 19 };
 360 static const unsigned bxt_west_i2c7b_pins[] = { 20, 21 };
 361
 362 static const struct intel_pingroup bxt_west_groups[] = {
 363         PIN_GROUP("i2c0_grp", bxt_west_i2c0_pins, 1),
 364         PIN_GROUP("i2c1_grp", bxt_west_i2c1_pins, 1),
 365         PIN_GROUP("i2c2_grp", bxt_west_i2c2_pins, 1),
 366         PIN_GROUP("i2c3_grp", bxt_west_i2c3_pins, 1),
 367         PIN_GROUP("i2c4_grp", bxt_west_i2c4_pins, 1),
 368         PIN_GROUP("i2c5_grp", bxt_west_i2c5_pins, 1),
 369         PIN_GROUP("i2c6_grp", bxt_west_i2c6_pins, 1),
 370         PIN_GROUP("i2c7_grp", bxt_west_i2c7_pins, 1),
 371         PIN_GROUP("i2c5b_grp", bxt_west_i2c5b_pins, 2),
 372         PIN_GROUP("i2c6b_grp", bxt_west_i2c6b_pins, 2),
 373         PIN_GROUP("i2c7b_grp", bxt_west_i2c7b_pins, 2),
 374 };
 375
 376 static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" };
 377 static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" };
 378 static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" };
 379 static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" };
 380 static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" };
 381 static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp", "i2c5b_grp" };
 382 static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp", "i2c6b_grp" };
 383 static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp", "i2c7b_grp" };
 384
 385 static const struct intel_function bxt_west_functions[] = {
 386         FUNCTION("i2c0", bxt_west_i2c0_groups),
 387         FUNCTION("i2c1", bxt_west_i2c1_groups),
 388         FUNCTION("i2c2", bxt_west_i2c2_groups),
 389         FUNCTION("i2c3", bxt_west_i2c3_groups),
 390         FUNCTION("i2c4", bxt_west_i2c4_groups),
 391         FUNCTION("i2c5", bxt_west_i2c5_groups),
 392         FUNCTION("i2c6", bxt_west_i2c6_groups),
 393         FUNCTION("i2c7", bxt_west_i2c7_groups),
 394 };
 395
 396 static const struct intel_community bxt_west_communities[] = {
 397         BXT_COMMUNITY(0, 41),
 398 };
 399
 400 static const struct intel_pinctrl_soc_data bxt_west_soc_data = {
 401         .uid = "3",
 402         .pins = bxt_west_pins,
 403         .npins = ARRAY_SIZE(bxt_west_pins),
 404         .groups = bxt_west_groups,
 405         .ngroups = ARRAY_SIZE(bxt_west_groups),
 406         .functions = bxt_west_functions,
 407         .nfunctions = ARRAY_SIZE(bxt_west_functions),
 408         .communities = bxt_west_communities,
 409         .ncommunities = ARRAY_SIZE(bxt_west_communities),
 410 };
 411
 412 static const struct pinctrl_pin_desc bxt_southwest_pins[] = {
 413         PINCTRL_PIN(0, "EMMC0_CLK"),
 414         PINCTRL_PIN(1, "EMMC0_D0"),
 415         PINCTRL_PIN(2, "EMMC0_D1"),
 416         PINCTRL_PIN(3, "EMMC0_D2"),
 417         PINCTRL_PIN(4, "EMMC0_D3"),
 418         PINCTRL_PIN(5, "EMMC0_D4"),
 419         PINCTRL_PIN(6, "EMMC0_D5"),
 420         PINCTRL_PIN(7, "EMMC0_D6"),
 421         PINCTRL_PIN(8, "EMMC0_D7"),
 422         PINCTRL_PIN(9, "EMMC0_CMD"),
 423         PINCTRL_PIN(10, "SDIO_CLK"),
 424         PINCTRL_PIN(11, "SDIO_D0"),
 425         PINCTRL_PIN(12, "SDIO_D1"),
 426         PINCTRL_PIN(13, "SDIO_D2"),
 427         PINCTRL_PIN(14, "SDIO_D3"),
 428         PINCTRL_PIN(15, "SDIO_CMD"),
 429         PINCTRL_PIN(16, "SDCARD_CLK"),
 430         PINCTRL_PIN(17, "SDCARD_D0"),
 431         PINCTRL_PIN(18, "SDCARD_D1"),
 432         PINCTRL_PIN(19, "SDCARD_D2"),
 433         PINCTRL_PIN(20, "SDCARD_D3"),
 434         PINCTRL_PIN(21, "SDCARD_CD_B"),
 435         PINCTRL_PIN(22, "SDCARD_CMD"),
 436         PINCTRL_PIN(23, "SDCARD_LVL_CLK_FB"),
 437         PINCTRL_PIN(24, "SDCARD_LVL_CMD_DIR"),
 438         PINCTRL_PIN(25, "SDCARD_LVL_DAT_DIR"),
 439         PINCTRL_PIN(26, "EMMC0_STROBE"),
 440         PINCTRL_PIN(27, "SDIO_PWR_DOWN_B"),
 441         PINCTRL_PIN(28, "SDCARD_PWR_DOWN_B"),
 442         PINCTRL_PIN(29, "SDCARD_LVL_SEL"),
 443         PINCTRL_PIN(30, "SDCARD_LVL_WP"),
 444 };
 445
 446 static const unsigned bxt_southwest_emmc0_pins[] = {
 447         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26,
 448 };
 449 static const unsigned bxt_southwest_sdio_pins[] = {
 450         10, 11, 12, 13, 14, 15, 27,
 451 };
 452 static const unsigned bxt_southwest_sdcard_pins[] = {
 453         16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
 454 };
 455
 456 static const struct intel_pingroup bxt_southwest_groups[] = {
 457         PIN_GROUP("emmc0_grp", bxt_southwest_emmc0_pins, 1),
 458         PIN_GROUP("sdio_grp", bxt_southwest_sdio_pins, 1),
 459         PIN_GROUP("sdcard_grp", bxt_southwest_sdcard_pins, 1),
 460 };
 461
 462 static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" };
 463 static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" };
 464 static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" };
 465
 466 static const struct intel_function bxt_southwest_functions[] = {
 467         FUNCTION("emmc0", bxt_southwest_emmc0_groups),
 468         FUNCTION("sdio", bxt_southwest_sdio_groups),
 469         FUNCTION("sdcard", bxt_southwest_sdcard_groups),
 470 };
 471
 472 static const struct intel_community bxt_southwest_communities[] = {
 473         BXT_COMMUNITY(0, 30),
 474 };
 475
 476 static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = {
 477         .uid = "4",
 478         .pins = bxt_southwest_pins,
 479         .npins = ARRAY_SIZE(bxt_southwest_pins),
 480         .groups = bxt_southwest_groups,
 481         .ngroups = ARRAY_SIZE(bxt_southwest_groups),
 482         .functions = bxt_southwest_functions,
 483         .nfunctions = ARRAY_SIZE(bxt_southwest_functions),
 484         .communities = bxt_southwest_communities,
 485         .ncommunities = ARRAY_SIZE(bxt_southwest_communities),
 486 };
 487
 488 static const struct pinctrl_pin_desc bxt_south_pins[] = {
 489         PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
 490         PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
 491         PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
 492         PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
 493         PINCTRL_PIN(4, "DBI_SDA"),
 494         PINCTRL_PIN(5, "DBI_SCL"),
 495         PINCTRL_PIN(6, "PANEL0_VDDEN"),
 496         PINCTRL_PIN(7, "PANEL0_BKLTEN"),
 497         PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
 498         PINCTRL_PIN(9, "PANEL1_VDDEN"),
 499         PINCTRL_PIN(10, "PANEL1_BKLTEN"),
 500         PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
 501         PINCTRL_PIN(12, "DBI_CSX"),
 502         PINCTRL_PIN(13, "DBI_RESX"),
 503         PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
 504         PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
 505         PINCTRL_PIN(16, "USB_OC0_B"),
 506         PINCTRL_PIN(17, "USB_OC1_B"),
 507         PINCTRL_PIN(18, "MEX_WAKE0_B"),
 508         PINCTRL_PIN(19, "MEX_WAKE1_B"),
 509 };
 510
 511 static const struct intel_community bxt_south_communities[] = {
 512         BXT_COMMUNITY(0, 19),
 513 };
 514
 515 static const struct intel_pinctrl_soc_data bxt_south_soc_data = {
 516         .uid = "5",
 517         .pins = bxt_south_pins,
 518         .npins = ARRAY_SIZE(bxt_south_pins),
 519         .communities = bxt_south_communities,
 520         .ncommunities = ARRAY_SIZE(bxt_south_communities),
 521 };
 522
 523 static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = {
 524         &bxt_north_soc_data,
 525         &bxt_northwest_soc_data,
 526         &bxt_west_soc_data,
 527         &bxt_southwest_soc_data,
 528         &bxt_south_soc_data,
 529         NULL,
 530 };
 531
 532 /* APL */
 533 static const struct pinctrl_pin_desc apl_north_pins[] = {
 534         PINCTRL_PIN(0, "GPIO_0"),
 535         PINCTRL_PIN(1, "GPIO_1"),
 536         PINCTRL_PIN(2, "GPIO_2"),
 537         PINCTRL_PIN(3, "GPIO_3"),
 538         PINCTRL_PIN(4, "GPIO_4"),
 539         PINCTRL_PIN(5, "GPIO_5"),
 540         PINCTRL_PIN(6, "GPIO_6"),
 541         PINCTRL_PIN(7, "GPIO_7"),
 542         PINCTRL_PIN(8, "GPIO_8"),
 543         PINCTRL_PIN(9, "GPIO_9"),
 544         PINCTRL_PIN(10, "GPIO_10"),
 545         PINCTRL_PIN(11, "GPIO_11"),
 546         PINCTRL_PIN(12, "GPIO_12"),
 547         PINCTRL_PIN(13, "GPIO_13"),
 548         PINCTRL_PIN(14, "GPIO_14"),
 549         PINCTRL_PIN(15, "GPIO_15"),
 550         PINCTRL_PIN(16, "GPIO_16"),
 551         PINCTRL_PIN(17, "GPIO_17"),
 552         PINCTRL_PIN(18, "GPIO_18"),
 553         PINCTRL_PIN(19, "GPIO_19"),
 554         PINCTRL_PIN(20, "GPIO_20"),
 555         PINCTRL_PIN(21, "GPIO_21"),
 556         PINCTRL_PIN(22, "GPIO_22"),
 557         PINCTRL_PIN(23, "GPIO_23"),
 558         PINCTRL_PIN(24, "GPIO_24"),
 559         PINCTRL_PIN(25, "GPIO_25"),
 560         PINCTRL_PIN(26, "GPIO_26"),
 561         PINCTRL_PIN(27, "GPIO_27"),
 562         PINCTRL_PIN(28, "GPIO_28"),
 563         PINCTRL_PIN(29, "GPIO_29"),
 564         PINCTRL_PIN(30, "GPIO_30"),
 565         PINCTRL_PIN(31, "GPIO_31"),
 566         PINCTRL_PIN(32, "GPIO_32"),
 567         PINCTRL_PIN(33, "GPIO_33"),
 568         PINCTRL_PIN(34, "PWM0"),
 569         PINCTRL_PIN(35, "PWM1"),
 570         PINCTRL_PIN(36, "PWM2"),
 571         PINCTRL_PIN(37, "PWM3"),
 572         PINCTRL_PIN(38, "LPSS_UART0_RXD"),
 573         PINCTRL_PIN(39, "LPSS_UART0_TXD"),
 574         PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
 575         PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
 576         PINCTRL_PIN(42, "LPSS_UART1_RXD"),
 577         PINCTRL_PIN(43, "LPSS_UART1_TXD"),
 578         PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
 579         PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
 580         PINCTRL_PIN(46, "LPSS_UART2_RXD"),
 581         PINCTRL_PIN(47, "LPSS_UART2_TXD"),
 582         PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
 583         PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
 584         PINCTRL_PIN(50, "GP_CAMERASB00"),
 585         PINCTRL_PIN(51, "GP_CAMERASB01"),
 586         PINCTRL_PIN(52, "GP_CAMERASB02"),
 587         PINCTRL_PIN(53, "GP_CAMERASB03"),
 588         PINCTRL_PIN(54, "GP_CAMERASB04"),
 589         PINCTRL_PIN(55, "GP_CAMERASB05"),
 590         PINCTRL_PIN(56, "GP_CAMERASB06"),
 591         PINCTRL_PIN(57, "GP_CAMERASB07"),
 592         PINCTRL_PIN(58, "GP_CAMERASB08"),
 593         PINCTRL_PIN(59, "GP_CAMERASB09"),
 594         PINCTRL_PIN(60, "GP_CAMERASB10"),
 595         PINCTRL_PIN(61, "GP_CAMERASB11"),
 596         PINCTRL_PIN(62, "TCK"),
 597         PINCTRL_PIN(63, "TRST_B"),
 598         PINCTRL_PIN(64, "TMS"),
 599         PINCTRL_PIN(65, "TDI"),
 600         PINCTRL_PIN(66, "CX_PMODE"),
 601         PINCTRL_PIN(67, "CX_PREQ_B"),
 602         PINCTRL_PIN(68, "JTAGX"),
 603         PINCTRL_PIN(69, "CX_PRDY_B"),
 604         PINCTRL_PIN(70, "TDO"),
 605         PINCTRL_PIN(71, "CNV_BRI_DT"),
 606         PINCTRL_PIN(72, "CNV_BRI_RSP"),
 607         PINCTRL_PIN(73, "CNV_RGI_DT"),
 608         PINCTRL_PIN(74, "CNV_RGI_RSP"),
 609         PINCTRL_PIN(75, "SVID0_ALERT_B"),
 610         PINCTRL_PIN(76, "SVID0_DATA"),
 611         PINCTRL_PIN(77, "SVID0_CLK"),
 612 };
 613
 614 static const unsigned apl_north_pwm0_pins[] = { 34 };
 615 static const unsigned apl_north_pwm1_pins[] = { 35 };
 616 static const unsigned apl_north_pwm2_pins[] = { 36 };
 617 static const unsigned apl_north_pwm3_pins[] = { 37 };
 618 static const unsigned apl_north_uart0_pins[] = { 38, 39, 40, 41 };
 619 static const unsigned apl_north_uart1_pins[] = { 42, 43, 44, 45 };
 620 static const unsigned apl_north_uart2_pins[] = { 46, 47, 48, 49 };
 621
 622 static const struct intel_pingroup apl_north_groups[] = {
 623         PIN_GROUP("pwm0_grp", apl_north_pwm0_pins, 1),
 624         PIN_GROUP("pwm1_grp", apl_north_pwm1_pins, 1),
 625         PIN_GROUP("pwm2_grp", apl_north_pwm2_pins, 1),
 626         PIN_GROUP("pwm3_grp", apl_north_pwm3_pins, 1),
 627         PIN_GROUP("uart0_grp", apl_north_uart0_pins, 1),
 628         PIN_GROUP("uart1_grp", apl_north_uart1_pins, 1),
 629         PIN_GROUP("uart2_grp", apl_north_uart2_pins, 1),
 630 };
 631
 632 static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" };
 633 static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" };
 634 static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" };
 635 static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" };
 636 static const char * const apl_north_uart0_groups[] = { "uart0_grp" };
 637 static const char * const apl_north_uart1_groups[] = { "uart1_grp" };
 638 static const char * const apl_north_uart2_groups[] = { "uart2_grp" };
 639
 640 static const struct intel_function apl_north_functions[] = {
 641         FUNCTION("pwm0", apl_north_pwm0_groups),
 642         FUNCTION("pwm1", apl_north_pwm1_groups),
 643         FUNCTION("pwm2", apl_north_pwm2_groups),
 644         FUNCTION("pwm3", apl_north_pwm3_groups),
 645         FUNCTION("uart0", apl_north_uart0_groups),
 646         FUNCTION("uart1", apl_north_uart1_groups),
 647         FUNCTION("uart2", apl_north_uart2_groups),
 648 };
 649
 650 static const struct intel_community apl_north_communities[] = {
 651         BXT_COMMUNITY(0, 77),
 652 };
 653
 654 static const struct intel_pinctrl_soc_data apl_north_soc_data = {
 655         .uid = "1",
 656         .pins = apl_north_pins,
 657         .npins = ARRAY_SIZE(apl_north_pins),
 658         .groups = apl_north_groups,
 659         .ngroups = ARRAY_SIZE(apl_north_groups),
 660         .functions = apl_north_functions,
 661         .nfunctions = ARRAY_SIZE(apl_north_functions),
 662         .communities = apl_north_communities,
 663         .ncommunities = ARRAY_SIZE(apl_north_communities),
 664 };
 665
 666 static const struct pinctrl_pin_desc apl_northwest_pins[] = {
 667         PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
 668         PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
 669         PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
 670         PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
 671         PINCTRL_PIN(4, "DBI_SDA"),
 672         PINCTRL_PIN(5, "DBI_SCL"),
 673         PINCTRL_PIN(6, "PANEL0_VDDEN"),
 674         PINCTRL_PIN(7, "PANEL0_BKLTEN"),
 675         PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
 676         PINCTRL_PIN(9, "PANEL1_VDDEN"),
 677         PINCTRL_PIN(10, "PANEL1_BKLTEN"),
 678         PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
 679         PINCTRL_PIN(12, "DBI_CSX"),
 680         PINCTRL_PIN(13, "DBI_RESX"),
 681         PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
 682         PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
 683         PINCTRL_PIN(16, "USB_OC0_B"),
 684         PINCTRL_PIN(17, "USB_OC1_B"),
 685         PINCTRL_PIN(18, "PMC_SPI_FS0"),
 686         PINCTRL_PIN(19, "PMC_SPI_FS1"),
 687         PINCTRL_PIN(20, "PMC_SPI_FS2"),
 688         PINCTRL_PIN(21, "PMC_SPI_RXD"),
 689         PINCTRL_PIN(22, "PMC_SPI_TXD"),
 690         PINCTRL_PIN(23, "PMC_SPI_CLK"),
 691         PINCTRL_PIN(24, "PMIC_PWRGOOD"),
 692         PINCTRL_PIN(25, "PMIC_RESET_B"),
 693         PINCTRL_PIN(26, "PMIC_SDWN_B"),
 694         PINCTRL_PIN(27, "PMIC_BCUDISW2"),
 695         PINCTRL_PIN(28, "PMIC_BCUDISCRIT"),
 696         PINCTRL_PIN(29, "PMIC_THERMTRIP_B"),
 697         PINCTRL_PIN(30, "PMIC_STDBY"),
 698         PINCTRL_PIN(31, "PROCHOT_B"),
 699         PINCTRL_PIN(32, "PMIC_I2C_SCL"),
 700         PINCTRL_PIN(33, "PMIC_I2C_SDA"),
 701         PINCTRL_PIN(34, "AVS_I2S1_MCLK"),
 702         PINCTRL_PIN(35, "AVS_I2S1_BCLK"),
 703         PINCTRL_PIN(36, "AVS_I2S1_WS_SYNC"),
 704         PINCTRL_PIN(37, "AVS_I2S1_SDI"),
 705         PINCTRL_PIN(38, "AVS_I2S1_SDO"),
 706         PINCTRL_PIN(39, "AVS_M_CLK_A1"),
 707         PINCTRL_PIN(40, "AVS_M_CLK_B1"),
 708         PINCTRL_PIN(41, "AVS_M_DATA_1"),
 709         PINCTRL_PIN(42, "AVS_M_CLK_AB2"),
 710         PINCTRL_PIN(43, "AVS_M_DATA_2"),
 711         PINCTRL_PIN(44, "AVS_I2S2_MCLK"),
 712         PINCTRL_PIN(45, "AVS_I2S2_BCLK"),
 713         PINCTRL_PIN(46, "AVS_I2S2_WS_SYNC"),
 714         PINCTRL_PIN(47, "AVS_I2S2_SDI"),
 715         PINCTRL_PIN(48, "AVS_I2S2_SDO"),
 716         PINCTRL_PIN(49, "AVS_I2S3_BCLK"),
 717         PINCTRL_PIN(50, "AVS_I2S3_WS_SYNC"),
 718         PINCTRL_PIN(51, "AVS_I2S3_SDI"),
 719         PINCTRL_PIN(52, "AVS_I2S3_SDO"),
 720         PINCTRL_PIN(53, "FST_SPI_CS0_B"),
 721         PINCTRL_PIN(54, "FST_SPI_CS1_B"),
 722         PINCTRL_PIN(55, "FST_SPI_MOSI_IO0"),
 723         PINCTRL_PIN(56, "FST_SPI_MISO_IO1"),
 724         PINCTRL_PIN(57, "FST_SPI_IO2"),
 725         PINCTRL_PIN(58, "FST_SPI_IO3"),
 726         PINCTRL_PIN(59, "FST_SPI_CLK"),
 727         PINCTRL_PIN(60, "FST_SPI_CLK_FB"),
 728         PINCTRL_PIN(61, "GP_SSP_0_CLK"),
 729         PINCTRL_PIN(62, "GP_SSP_0_FS0"),
 730         PINCTRL_PIN(63, "GP_SSP_0_FS1"),
 731         PINCTRL_PIN(64, "GP_SSP_0_RXD"),
 732         PINCTRL_PIN(65, "GP_SSP_0_TXD"),
 733         PINCTRL_PIN(66, "GP_SSP_1_CLK"),
 734         PINCTRL_PIN(67, "GP_SSP_1_FS0"),
 735         PINCTRL_PIN(68, "GP_SSP_1_FS1"),
 736         PINCTRL_PIN(69, "GP_SSP_1_RXD"),
 737         PINCTRL_PIN(70, "GP_SSP_1_TXD"),
 738         PINCTRL_PIN(71, "GP_SSP_2_CLK"),
 739         PINCTRL_PIN(72, "GP_SSP_2_FS0"),
 740         PINCTRL_PIN(73, "GP_SSP_2_FS1"),
 741         PINCTRL_PIN(74, "GP_SSP_2_FS2"),
 742         PINCTRL_PIN(75, "GP_SSP_2_RXD"),
 743         PINCTRL_PIN(76, "GP_SSP_2_TXD"),
 744 };
 745
 746 static const unsigned apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 };
 747 static const unsigned apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 };
 748 static const unsigned apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 };
 749 static const unsigned apl_northwest_uart3_pins[] = { 67, 68, 69, 70 };
 750
 751 static const struct intel_pingroup apl_northwest_groups[] = {
 752         PIN_GROUP("ssp0_grp", apl_northwest_ssp0_pins, 1),
 753         PIN_GROUP("ssp1_grp", apl_northwest_ssp1_pins, 1),
 754         PIN_GROUP("ssp2_grp", apl_northwest_ssp2_pins, 1),
 755         PIN_GROUP("uart3_grp", apl_northwest_uart3_pins, 2),
 756 };
 757
 758 static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" };
 759 static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" };
 760 static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" };
 761 static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" };
 762
 763 static const struct intel_function apl_northwest_functions[] = {
 764         FUNCTION("ssp0", apl_northwest_ssp0_groups),
 765         FUNCTION("ssp1", apl_northwest_ssp1_groups),
 766         FUNCTION("ssp2", apl_northwest_ssp2_groups),
 767         FUNCTION("uart3", apl_northwest_uart3_groups),
 768 };
 769
 770 static const struct intel_community apl_northwest_communities[] = {
 771         BXT_COMMUNITY(0, 76),
 772 };
 773
 774 static const struct intel_pinctrl_soc_data apl_northwest_soc_data = {
 775         .uid = "2",
 776         .pins = apl_northwest_pins,
 777         .npins = ARRAY_SIZE(apl_northwest_pins),
 778         .groups = apl_northwest_groups,
 779         .ngroups = ARRAY_SIZE(apl_northwest_groups),
 780         .functions = apl_northwest_functions,
 781         .nfunctions = ARRAY_SIZE(apl_northwest_functions),
 782         .communities = apl_northwest_communities,
 783         .ncommunities = ARRAY_SIZE(apl_northwest_communities),
 784 };
 785
 786 static const struct pinctrl_pin_desc apl_west_pins[] = {
 787         PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
 788         PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
 789         PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
 790         PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
 791         PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
 792         PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
 793         PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
 794         PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
 795         PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
 796         PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
 797         PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
 798         PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
 799         PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
 800         PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
 801         PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
 802         PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
 803         PINCTRL_PIN(16, "ISH_GPIO_0"),
 804         PINCTRL_PIN(17, "ISH_GPIO_1"),
 805         PINCTRL_PIN(18, "ISH_GPIO_2"),
 806         PINCTRL_PIN(19, "ISH_GPIO_3"),
 807         PINCTRL_PIN(20, "ISH_GPIO_4"),
 808         PINCTRL_PIN(21, "ISH_GPIO_5"),
 809         PINCTRL_PIN(22, "ISH_GPIO_6"),
 810         PINCTRL_PIN(23, "ISH_GPIO_7"),
 811         PINCTRL_PIN(24, "ISH_GPIO_8"),
 812         PINCTRL_PIN(25, "ISH_GPIO_9"),
 813         PINCTRL_PIN(26, "PCIE_CLKREQ0_B"),
 814         PINCTRL_PIN(27, "PCIE_CLKREQ1_B"),
 815         PINCTRL_PIN(28, "PCIE_CLKREQ2_B"),
 816         PINCTRL_PIN(29, "PCIE_CLKREQ3_B"),
 817         PINCTRL_PIN(30, "OSC_CLK_OUT_0"),
 818         PINCTRL_PIN(31, "OSC_CLK_OUT_1"),
 819         PINCTRL_PIN(32, "OSC_CLK_OUT_2"),
 820         PINCTRL_PIN(33, "OSC_CLK_OUT_3"),
 821         PINCTRL_PIN(34, "OSC_CLK_OUT_4"),
 822         PINCTRL_PIN(35, "PMU_AC_PRESENT"),
 823         PINCTRL_PIN(36, "PMU_BATLOW_B"),
 824         PINCTRL_PIN(37, "PMU_PLTRST_B"),
 825         PINCTRL_PIN(38, "PMU_PWRBTN_B"),
 826         PINCTRL_PIN(39, "PMU_RESETBUTTON_B"),
 827         PINCTRL_PIN(40, "PMU_SLP_S0_B"),
 828         PINCTRL_PIN(41, "PMU_SLP_S3_B"),
 829         PINCTRL_PIN(42, "PMU_SLP_S4_B"),
 830         PINCTRL_PIN(43, "PMU_SUSCLK"),
 831         PINCTRL_PIN(44, "PMU_WAKE_B"),
 832         PINCTRL_PIN(45, "SUS_STAT_B"),
 833         PINCTRL_PIN(46, "SUSPWRDNACK"),
 834 };
 835
 836 static const unsigned apl_west_i2c0_pins[] = { 0, 1 };
 837 static const unsigned apl_west_i2c1_pins[] = { 2, 3 };
 838 static const unsigned apl_west_i2c2_pins[] = { 4, 5 };
 839 static const unsigned apl_west_i2c3_pins[] = { 6, 7 };
 840 static const unsigned apl_west_i2c4_pins[] = { 8, 9 };
 841 static const unsigned apl_west_i2c5_pins[] = { 10, 11 };
 842 static const unsigned apl_west_i2c6_pins[] = { 12, 13 };
 843 static const unsigned apl_west_i2c7_pins[] = { 14, 15 };
 844 static const unsigned apl_west_uart2_pins[] = { 20, 21, 22, 34 };
 845
 846 static const struct intel_pingroup apl_west_groups[] = {
 847         PIN_GROUP("i2c0_grp", apl_west_i2c0_pins, 1),
 848         PIN_GROUP("i2c1_grp", apl_west_i2c1_pins, 1),
 849         PIN_GROUP("i2c2_grp", apl_west_i2c2_pins, 1),
 850         PIN_GROUP("i2c3_grp", apl_west_i2c3_pins, 1),
 851         PIN_GROUP("i2c4_grp", apl_west_i2c4_pins, 1),
 852         PIN_GROUP("i2c5_grp", apl_west_i2c5_pins, 1),
 853         PIN_GROUP("i2c6_grp", apl_west_i2c6_pins, 1),
 854         PIN_GROUP("i2c7_grp", apl_west_i2c7_pins, 1),
 855         PIN_GROUP("uart2_grp", apl_west_uart2_pins, 3),
 856 };
 857
 858 static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" };
 859 static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" };
 860 static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" };
 861 static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" };
 862 static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" };
 863 static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" };
 864 static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" };
 865 static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" };
 866 static const char * const apl_west_uart2_groups[] = { "uart2_grp" };
 867
 868 static const struct intel_function apl_west_functions[] = {
 869         FUNCTION("i2c0", apl_west_i2c0_groups),
 870         FUNCTION("i2c1", apl_west_i2c1_groups),
 871         FUNCTION("i2c2", apl_west_i2c2_groups),
 872         FUNCTION("i2c3", apl_west_i2c3_groups),
 873         FUNCTION("i2c4", apl_west_i2c4_groups),
 874         FUNCTION("i2c5", apl_west_i2c5_groups),
 875         FUNCTION("i2c6", apl_west_i2c6_groups),
 876         FUNCTION("i2c7", apl_west_i2c7_groups),
 877         FUNCTION("uart2", apl_west_uart2_groups),
 878 };
 879
 880 static const struct intel_community apl_west_communities[] = {
 881         BXT_COMMUNITY(0, 46),
 882 };
 883
 884 static const struct intel_pinctrl_soc_data apl_west_soc_data = {
 885         .uid = "3",
 886         .pins = apl_west_pins,
 887         .npins = ARRAY_SIZE(apl_west_pins),
 888         .groups = apl_west_groups,
 889         .ngroups = ARRAY_SIZE(apl_west_groups),
 890         .functions = apl_west_functions,
 891         .nfunctions = ARRAY_SIZE(apl_west_functions),
 892         .communities = apl_west_communities,
 893         .ncommunities = ARRAY_SIZE(apl_west_communities),
 894 };
 895
 896 static const struct pinctrl_pin_desc apl_southwest_pins[] = {
 897         PINCTRL_PIN(0, "PCIE_WAKE0_B"),
 898         PINCTRL_PIN(1, "PCIE_WAKE1_B"),
 899         PINCTRL_PIN(2, "PCIE_WAKE2_B"),
 900         PINCTRL_PIN(3, "PCIE_WAKE3_B"),
 901         PINCTRL_PIN(4, "EMMC0_CLK"),
 902         PINCTRL_PIN(5, "EMMC0_D0"),
 903         PINCTRL_PIN(6, "EMMC0_D1"),
 904         PINCTRL_PIN(7, "EMMC0_D2"),
 905         PINCTRL_PIN(8, "EMMC0_D3"),
 906         PINCTRL_PIN(9, "EMMC0_D4"),
 907         PINCTRL_PIN(10, "EMMC0_D5"),
 908         PINCTRL_PIN(11, "EMMC0_D6"),
 909         PINCTRL_PIN(12, "EMMC0_D7"),
 910         PINCTRL_PIN(13, "EMMC0_CMD"),
 911         PINCTRL_PIN(14, "SDIO_CLK"),
 912         PINCTRL_PIN(15, "SDIO_D0"),
 913         PINCTRL_PIN(16, "SDIO_D1"),
 914         PINCTRL_PIN(17, "SDIO_D2"),
 915         PINCTRL_PIN(18, "SDIO_D3"),
 916         PINCTRL_PIN(19, "SDIO_CMD"),
 917         PINCTRL_PIN(20, "SDCARD_CLK"),
 918         PINCTRL_PIN(21, "SDCARD_CLK_FB"),
 919         PINCTRL_PIN(22, "SDCARD_D0"),
 920         PINCTRL_PIN(23, "SDCARD_D1"),
 921         PINCTRL_PIN(24, "SDCARD_D2"),
 922         PINCTRL_PIN(25, "SDCARD_D3"),
 923         PINCTRL_PIN(26, "SDCARD_CD_B"),
 924         PINCTRL_PIN(27, "SDCARD_CMD"),
 925         PINCTRL_PIN(28, "SDCARD_LVL_WP"),
 926         PINCTRL_PIN(29, "EMMC0_STROBE"),
 927         PINCTRL_PIN(30, "SDIO_PWR_DOWN_B"),
 928         PINCTRL_PIN(31, "SMB_ALERTB"),
 929         PINCTRL_PIN(32, "SMB_CLK"),
 930         PINCTRL_PIN(33, "SMB_DATA"),
 931         PINCTRL_PIN(34, "LPC_ILB_SERIRQ"),
 932         PINCTRL_PIN(35, "LPC_CLKOUT0"),
 933         PINCTRL_PIN(36, "LPC_CLKOUT1"),
 934         PINCTRL_PIN(37, "LPC_AD0"),
 935         PINCTRL_PIN(38, "LPC_AD1"),
 936         PINCTRL_PIN(39, "LPC_AD2"),
 937         PINCTRL_PIN(40, "LPC_AD3"),
 938         PINCTRL_PIN(41, "LPC_CLKRUNB"),
 939         PINCTRL_PIN(42, "LPC_FRAMEB"),
 940 };
 941
 942 static const unsigned apl_southwest_emmc0_pins[] = {
 943         4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29,
 944 };
 945 static const unsigned apl_southwest_sdio_pins[] = {
 946         14, 15, 16, 17, 18, 19, 30,
 947 };
 948 static const unsigned apl_southwest_sdcard_pins[] = {
 949         20, 21, 22, 23, 24, 25, 26, 27, 28,
 950 };
 951 static const unsigned apl_southwest_i2c7_pins[] = { 32, 33 };
 952
 953 static const struct intel_pingroup apl_southwest_groups[] = {
 954         PIN_GROUP("emmc0_grp", apl_southwest_emmc0_pins, 1),
 955         PIN_GROUP("sdio_grp", apl_southwest_sdio_pins, 1),
 956         PIN_GROUP("sdcard_grp", apl_southwest_sdcard_pins, 1),
 957         PIN_GROUP("i2c7_grp", apl_southwest_i2c7_pins, 2),
 958 };
 959
 960 static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" };
 961 static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" };
 962 static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" };
 963 static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" };
 964
 965 static const struct intel_function apl_southwest_functions[] = {
 966         FUNCTION("emmc0", apl_southwest_emmc0_groups),
 967         FUNCTION("sdio", apl_southwest_sdio_groups),
 968         FUNCTION("sdcard", apl_southwest_sdcard_groups),
 969         FUNCTION("i2c7", apl_southwest_i2c7_groups),
 970 };
 971
 972 static const struct intel_community apl_southwest_communities[] = {
 973         BXT_COMMUNITY(0, 42),
 974 };
 975
 976 static const struct intel_pinctrl_soc_data apl_southwest_soc_data = {
 977         .uid = "4",
 978         .pins = apl_southwest_pins,
 979         .npins = ARRAY_SIZE(apl_southwest_pins),
 980         .groups = apl_southwest_groups,
 981         .ngroups = ARRAY_SIZE(apl_southwest_groups),
 982         .functions = apl_southwest_functions,
 983         .nfunctions = ARRAY_SIZE(apl_southwest_functions),
 984         .communities = apl_southwest_communities,
 985         .ncommunities = ARRAY_SIZE(apl_southwest_communities),
 986 };
 987
 988 static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = {
 989         &apl_north_soc_data,
 990         &apl_northwest_soc_data,
 991         &apl_west_soc_data,
 992         &apl_southwest_soc_data,
 993         NULL,
 994 };
 995
 996 static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {
 997         { "INT3452", (kernel_ulong_t)apl_pinctrl_soc_data },
 998         { "INT34D1", (kernel_ulong_t)bxt_pinctrl_soc_data },
 999         { }
1000 };
1001 MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);
1002
1003 static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
1004         { "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data },
1005         { "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data },
1006         { },
1007 };
1008
1009 static int bxt_pinctrl_probe(struct platform_device *pdev)
1010 {
1011         const struct intel_pinctrl_soc_data *soc_data = NULL;
1012         const struct intel_pinctrl_soc_data **soc_table;
1013         struct acpi_device *adev;
1014         int i;
1015
1016         adev = ACPI_COMPANION(&pdev->dev);
1017         if (adev) {
1018                 const struct acpi_device_id *id;
1019
1020                 id = acpi_match_device(bxt_pinctrl_acpi_match, &pdev->dev);
1021                 if (!id)
1022                         return -ENODEV;
1023
1024                 soc_table = (const struct intel_pinctrl_soc_data **)
1025                         id->driver_data;
1026
1027                 for (i = 0; soc_table[i]; i++) {
1028                         if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
1029                                 soc_data = soc_table[i];
1030                                 break;
1031                         }
1032                 }
1033         } else {
1034                 const struct platform_device_id *pid;
1035
1036                 pid = platform_get_device_id(pdev);
1037                 if (!pid)
1038                         return -ENODEV;
1039
1040                 soc_table = (const struct intel_pinctrl_soc_data **)
1041                         pid->driver_data;
1042                 soc_data = soc_table[pdev->id];
1043         }
1044
1045         if (!soc_data)
1046                 return -ENODEV;
1047
1048         return intel_pinctrl_probe(pdev, soc_data);
1049 }
1050
1051 static const struct dev_pm_ops bxt_pinctrl_pm_ops = {
1052         SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
1053                                      intel_pinctrl_resume)
1054 };
1055
1056 static struct platform_driver bxt_pinctrl_driver = {
1057         .probe = bxt_pinctrl_probe,
1058         .driver = {
1059                 .name = "broxton-pinctrl",
1060                 .acpi_match_table = bxt_pinctrl_acpi_match,
1061                 .pm = &bxt_pinctrl_pm_ops,
1062         },
1063         .id_table = bxt_pinctrl_platform_ids,
1064 };
1065
1066 static int __init bxt_pinctrl_init(void)
1067 {
1068         return platform_driver_register(&bxt_pinctrl_driver);
1069 }
1070 subsys_initcall(bxt_pinctrl_init);
1071
1072 static void __exit bxt_pinctrl_exit(void)
1073 {
1074         platform_driver_unregister(&bxt_pinctrl_driver);
1075 }
1076 module_exit(bxt_pinctrl_exit);
1077
1078 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1079 MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
1080 MODULE_LICENSE("GPL v2");
1081 MODULE_ALIAS("platform:broxton-pinctrl");