drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/gpio/driver.h>
  13 #include <linux/log2.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pinctrl/pinctrl.h>
  16 #include <linux/pinctrl/pinmux.h>
  17 #include <linux/pinctrl/pinconf.h>
  18 #include <linux/pinctrl/pinconf-generic.h>
  19
  20 #include "../core.h"
  21 #include "pinctrl-intel.h"
  22
  23 /* Offset from regs */
  24 #define REVID                           0x000
  25 #define REVID_SHIFT                     16
  26 #define REVID_MASK                      GENMASK(31, 16)
  27
  28 #define PADBAR                          0x00c
  29 #define GPI_IS                          0x100
  30
  31 #define PADOWN_BITS                     4
  32 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  33 #define PADOWN_MASK(p)                  (0xf << PADOWN_SHIFT(p))
  34 #define PADOWN_GPP(p)                   ((p) / 8)
  35
  36 /* Offset from pad_regs */
  37 #define PADCFG0                         0x000
  38 #define PADCFG0_RXEVCFG_SHIFT           25
  39 #define PADCFG0_RXEVCFG_MASK            (3 << PADCFG0_RXEVCFG_SHIFT)
  40 #define PADCFG0_RXEVCFG_LEVEL           0
  41 #define PADCFG0_RXEVCFG_EDGE            1
  42 #define PADCFG0_RXEVCFG_DISABLED        2
  43 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  44 #define PADCFG0_PREGFRXSEL              BIT(24)
  45 #define PADCFG0_RXINV                   BIT(23)
  46 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  47 #define PADCFG0_GPIROUTSCI              BIT(19)
  48 #define PADCFG0_GPIROUTSMI              BIT(18)
  49 #define PADCFG0_GPIROUTNMI              BIT(17)
  50 #define PADCFG0_PMODE_SHIFT             10
  51 #define PADCFG0_PMODE_MASK              (0xf << PADCFG0_PMODE_SHIFT)
  52 #define PADCFG0_PMODE_GPIO              0
  53 #define PADCFG0_GPIORXDIS               BIT(9)
  54 #define PADCFG0_GPIOTXDIS               BIT(8)
  55 #define PADCFG0_GPIORXSTATE             BIT(1)
  56 #define PADCFG0_GPIOTXSTATE             BIT(0)
  57
  58 #define PADCFG1                         0x004
  59 #define PADCFG1_TERM_UP                 BIT(13)
  60 #define PADCFG1_TERM_SHIFT              10
  61 #define PADCFG1_TERM_MASK               (7 << PADCFG1_TERM_SHIFT)
  62 #define PADCFG1_TERM_20K                4
  63 #define PADCFG1_TERM_2K                 3
  64 #define PADCFG1_TERM_5K                 2
  65 #define PADCFG1_TERM_1K                 1
  66
  67 #define PADCFG2                         0x008
  68 #define PADCFG2_DEBEN                   BIT(0)
  69 #define PADCFG2_DEBOUNCE_SHIFT          1
  70 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  71
  72 #define DEBOUNCE_PERIOD                 31250 /* ns */
  73
  74 struct intel_pad_context {
  75         u32 padcfg0;
  76         u32 padcfg1;
  77         u32 padcfg2;
  78 };
  79
  80 struct intel_community_context {
  81         u32 *intmask;
  82 };
  83
  84 struct intel_pinctrl_context {
  85         struct intel_pad_context *pads;
  86         struct intel_community_context *communities;
  87 };
  88
  89 /**
  90  * struct intel_pinctrl - Intel pinctrl private structure
  91  * @dev: Pointer to the device structure
  92  * @lock: Lock to serialize register access
  93  * @pctldesc: Pin controller description
  94  * @pctldev: Pointer to the pin controller device
  95  * @chip: GPIO chip in this pin controller
  96  * @soc: SoC/PCH specific pin configuration data
  97  * @communities: All communities in this pin controller
  98  * @ncommunities: Number of communities in this pin controller
  99  * @context: Configuration saved over system sleep
 100  * @irq: pinctrl/GPIO chip irq number
 101  */
 102 struct intel_pinctrl {
 103         struct device *dev;
 104         raw_spinlock_t lock;
 105         struct pinctrl_desc pctldesc;
 106         struct pinctrl_dev *pctldev;
 107         struct gpio_chip chip;
 108         const struct intel_pinctrl_soc_data *soc;
 109         struct intel_community *communities;
 110         size_t ncommunities;
 111         struct intel_pinctrl_context context;
 112         int irq;
 113 };
 114
 115 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 116 #define padgroup_offset(g, p)   ((p) - (g)->base)
 117
 118 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 119                                                    unsigned pin)
 120 {
 121         struct intel_community *community;
 122         int i;
 123
 124         for (i = 0; i < pctrl->ncommunities; i++) {
 125                 community = &pctrl->communities[i];
 126                 if (pin >= community->pin_base &&
 127                     pin < community->pin_base + community->npins)
 128                         return community;
 129         }
 130
 131         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 132         return NULL;
 133 }
 134
 135 static const struct intel_padgroup *
 136 intel_community_get_padgroup(const struct intel_community *community,
 137                              unsigned pin)
 138 {
 139         int i;
 140
 141         for (i = 0; i < community->ngpps; i++) {
 142                 const struct intel_padgroup *padgrp = &community->gpps[i];
 143
 144                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 145                         return padgrp;
 146         }
 147
 148         return NULL;
 149 }
 150
 151 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
 152                                       unsigned reg)
 153 {
 154         const struct intel_community *community;
 155         unsigned padno;
 156         size_t nregs;
 157
 158         community = intel_get_community(pctrl, pin);
 159         if (!community)
 160                 return NULL;
 161
 162         padno = pin_to_padno(community, pin);
 163         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 164
 165         if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
 166                 return NULL;
 167
 168         return community->pad_regs + reg + padno * nregs * 4;
 169 }
 170
 171 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
 172 {
 173         const struct intel_community *community;
 174         const struct intel_padgroup *padgrp;
 175         unsigned gpp, offset, gpp_offset;
 176         void __iomem *padown;
 177
 178         community = intel_get_community(pctrl, pin);
 179         if (!community)
 180                 return false;
 181         if (!community->padown_offset)
 182                 return true;
 183
 184         padgrp = intel_community_get_padgroup(community, pin);
 185         if (!padgrp)
 186                 return false;
 187
 188         gpp_offset = padgroup_offset(padgrp, pin);
 189         gpp = PADOWN_GPP(gpp_offset);
 190         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 191         padown = community->regs + offset;
 192
 193         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 194 }
 195
 196 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
 197 {
 198         const struct intel_community *community;
 199         const struct intel_padgroup *padgrp;
 200         unsigned offset, gpp_offset;
 201         void __iomem *hostown;
 202
 203         community = intel_get_community(pctrl, pin);
 204         if (!community)
 205                 return true;
 206         if (!community->hostown_offset)
 207                 return false;
 208
 209         padgrp = intel_community_get_padgroup(community, pin);
 210         if (!padgrp)
 211                 return true;
 212
 213         gpp_offset = padgroup_offset(padgrp, pin);
 214         offset = community->hostown_offset + padgrp->reg_num * 4;
 215         hostown = community->regs + offset;
 216
 217         return !(readl(hostown) & BIT(gpp_offset));
 218 }
 219
 220 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
 221 {
 222         struct intel_community *community;
 223         const struct intel_padgroup *padgrp;
 224         unsigned offset, gpp_offset;
 225         u32 value;
 226
 227         community = intel_get_community(pctrl, pin);
 228         if (!community)
 229                 return true;
 230         if (!community->padcfglock_offset)
 231                 return false;
 232
 233         padgrp = intel_community_get_padgroup(community, pin);
 234         if (!padgrp)
 235                 return true;
 236
 237         gpp_offset = padgroup_offset(padgrp, pin);
 238
 239         /*
 240          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 241          * the pad is considered unlocked. Any other case means that it is
 242          * either fully or partially locked and we don't touch it.
 243          */
 244         offset = community->padcfglock_offset + padgrp->reg_num * 8;
 245         value = readl(community->regs + offset);
 246         if (value & BIT(gpp_offset))
 247                 return true;
 248
 249         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 250         value = readl(community->regs + offset);
 251         if (value & BIT(gpp_offset))
 252                 return true;
 253
 254         return false;
 255 }
 256
 257 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
 258 {
 259         return intel_pad_owned_by_host(pctrl, pin) &&
 260                 !intel_pad_locked(pctrl, pin);
 261 }
 262
 263 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 264 {
 265         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 266
 267         return pctrl->soc->ngroups;
 268 }
 269
 270 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 271                                       unsigned group)
 272 {
 273         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 274
 275         return pctrl->soc->groups[group].name;
 276 }
 277
 278 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 279                               const unsigned **pins, unsigned *npins)
 280 {
 281         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 282
 283         *pins = pctrl->soc->groups[group].pins;
 284         *npins = pctrl->soc->groups[group].npins;
 285         return 0;
 286 }
 287
 288 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 289                                unsigned pin)
 290 {
 291         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 292         void __iomem *padcfg;
 293         u32 cfg0, cfg1, mode;
 294         bool locked, acpi;
 295
 296         if (!intel_pad_owned_by_host(pctrl, pin)) {
 297                 seq_puts(s, "not available");
 298                 return;
 299         }
 300
 301         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 302         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 303
 304         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 305         if (mode == PADCFG0_PMODE_GPIO)
 306                 seq_puts(s, "GPIO ");
 307         else
 308                 seq_printf(s, "mode %d ", mode);
 309
 310         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 311
 312         /* Dump the additional PADCFG registers if available */
 313         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 314         if (padcfg)
 315                 seq_printf(s, " 0x%08x", readl(padcfg));
 316
 317         locked = intel_pad_locked(pctrl, pin);
 318         acpi = intel_pad_acpi_mode(pctrl, pin);
 319
 320         if (locked || acpi) {
 321                 seq_puts(s, " [");
 322                 if (locked) {
 323                         seq_puts(s, "LOCKED");
 324                         if (acpi)
 325                                 seq_puts(s, ", ");
 326                 }
 327                 if (acpi)
 328                         seq_puts(s, "ACPI");
 329                 seq_puts(s, "]");
 330         }
 331 }
 332
 333 static const struct pinctrl_ops intel_pinctrl_ops = {
 334         .get_groups_count = intel_get_groups_count,
 335         .get_group_name = intel_get_group_name,
 336         .get_group_pins = intel_get_group_pins,
 337         .pin_dbg_show = intel_pin_dbg_show,
 338 };
 339
 340 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 341 {
 342         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 343
 344         return pctrl->soc->nfunctions;
 345 }
 346
 347 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 348                                            unsigned function)
 349 {
 350         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 351
 352         return pctrl->soc->functions[function].name;
 353 }
 354
 355 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 356                                      unsigned function,
 357                                      const char * const **groups,
 358                                      unsigned * const ngroups)
 359 {
 360         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 361
 362         *groups = pctrl->soc->functions[function].groups;
 363         *ngroups = pctrl->soc->functions[function].ngroups;
 364         return 0;
 365 }
 366
 367 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 368                                 unsigned group)
 369 {
 370         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 371         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 372         unsigned long flags;
 373         int i;
 374
 375         raw_spin_lock_irqsave(&pctrl->lock, flags);
 376
 377         /*
 378          * All pins in the groups needs to be accessible and writable
 379          * before we can enable the mux for this group.
 380          */
 381         for (i = 0; i < grp->npins; i++) {
 382                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 383                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 384                         return -EBUSY;
 385                 }
 386         }
 387
 388         /* Now enable the mux setting for each pin in the group */
 389         for (i = 0; i < grp->npins; i++) {
 390                 void __iomem *padcfg0;
 391                 u32 value;
 392
 393                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 394                 value = readl(padcfg0);
 395
 396                 value &= ~PADCFG0_PMODE_MASK;
 397
 398                 if (grp->modes)
 399                         value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
 400                 else
 401                         value |= grp->mode << PADCFG0_PMODE_SHIFT;
 402
 403                 writel(value, padcfg0);
 404         }
 405
 406         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 407
 408         return 0;
 409 }
 410
 411 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 412 {
 413         u32 value;
 414
 415         value = readl(padcfg0);
 416         if (input) {
 417                 value &= ~PADCFG0_GPIORXDIS;
 418                 value |= PADCFG0_GPIOTXDIS;
 419         } else {
 420                 value &= ~PADCFG0_GPIOTXDIS;
 421                 value |= PADCFG0_GPIORXDIS;
 422         }
 423         writel(value, padcfg0);
 424 }
 425
 426 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
 427 {
 428         return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 429 }
 430
 431 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 432 {
 433         u32 value;
 434
 435         /* Put the pad into GPIO mode */
 436         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 437         /* Disable SCI/SMI/NMI generation */
 438         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 439         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 440         writel(value, padcfg0);
 441 }
 442
 443 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 444                                      struct pinctrl_gpio_range *range,
 445                                      unsigned pin)
 446 {
 447         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 448         void __iomem *padcfg0;
 449         unsigned long flags;
 450
 451         raw_spin_lock_irqsave(&pctrl->lock, flags);
 452
 453         if (!intel_pad_usable(pctrl, pin)) {
 454                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 455                 return -EBUSY;
 456         }
 457
 458         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 459
 460         /*
 461          * If pin is already configured in GPIO mode, we assume that
 462          * firmware provides correct settings. In such case we avoid
 463          * potential glitches on the pin. Otherwise, for the pin in
 464          * alternative mode, consumer has to supply respective flags.
 465          */
 466         if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
 467                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 468                 return 0;
 469         }
 470
 471         intel_gpio_set_gpio_mode(padcfg0);
 472
 473         /* Disable TX buffer and enable RX (this will be input) */
 474         __intel_gpio_set_direction(padcfg0, true);
 475
 476         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 477
 478         return 0;
 479 }
 480
 481 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 482                                     struct pinctrl_gpio_range *range,
 483                                     unsigned pin, bool input)
 484 {
 485         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 486         void __iomem *padcfg0;
 487         unsigned long flags;
 488
 489         raw_spin_lock_irqsave(&pctrl->lock, flags);
 490
 491         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 492         __intel_gpio_set_direction(padcfg0, input);
 493
 494         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 495
 496         return 0;
 497 }
 498
 499 static const struct pinmux_ops intel_pinmux_ops = {
 500         .get_functions_count = intel_get_functions_count,
 501         .get_function_name = intel_get_function_name,
 502         .get_function_groups = intel_get_function_groups,
 503         .set_mux = intel_pinmux_set_mux,
 504         .gpio_request_enable = intel_gpio_request_enable,
 505         .gpio_set_direction = intel_gpio_set_direction,
 506 };
 507
 508 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
 509                             unsigned long *config)
 510 {
 511         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 512         enum pin_config_param param = pinconf_to_config_param(*config);
 513         const struct intel_community *community;
 514         u32 value, term;
 515         u32 arg = 0;
 516
 517         if (!intel_pad_owned_by_host(pctrl, pin))
 518                 return -ENOTSUPP;
 519
 520         community = intel_get_community(pctrl, pin);
 521         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 522         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 523
 524         switch (param) {
 525         case PIN_CONFIG_BIAS_DISABLE:
 526                 if (term)
 527                         return -EINVAL;
 528                 break;
 529
 530         case PIN_CONFIG_BIAS_PULL_UP:
 531                 if (!term || !(value & PADCFG1_TERM_UP))
 532                         return -EINVAL;
 533
 534                 switch (term) {
 535                 case PADCFG1_TERM_1K:
 536                         arg = 1000;
 537                         break;
 538                 case PADCFG1_TERM_2K:
 539                         arg = 2000;
 540                         break;
 541                 case PADCFG1_TERM_5K:
 542                         arg = 5000;
 543                         break;
 544                 case PADCFG1_TERM_20K:
 545                         arg = 20000;
 546                         break;
 547                 }
 548
 549                 break;
 550
 551         case PIN_CONFIG_BIAS_PULL_DOWN:
 552                 if (!term || value & PADCFG1_TERM_UP)
 553                         return -EINVAL;
 554
 555                 switch (term) {
 556                 case PADCFG1_TERM_1K:
 557                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 558                                 return -EINVAL;
 559                         arg = 1000;
 560                         break;
 561                 case PADCFG1_TERM_5K:
 562                         arg = 5000;
 563                         break;
 564                 case PADCFG1_TERM_20K:
 565                         arg = 20000;
 566                         break;
 567                 }
 568
 569                 break;
 570
 571         case PIN_CONFIG_INPUT_DEBOUNCE: {
 572                 void __iomem *padcfg2;
 573                 u32 v;
 574
 575                 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 576                 if (!padcfg2)
 577                         return -ENOTSUPP;
 578
 579                 v = readl(padcfg2);
 580                 if (!(v & PADCFG2_DEBEN))
 581                         return -EINVAL;
 582
 583                 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 584                 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
 585
 586                 break;
 587         }
 588
 589         default:
 590                 return -ENOTSUPP;
 591         }
 592
 593         *config = pinconf_to_config_packed(param, arg);
 594         return 0;
 595 }
 596
 597 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
 598                                  unsigned long config)
 599 {
 600         unsigned param = pinconf_to_config_param(config);
 601         unsigned arg = pinconf_to_config_argument(config);
 602         const struct intel_community *community;
 603         void __iomem *padcfg1;
 604         unsigned long flags;
 605         int ret = 0;
 606         u32 value;
 607
 608         raw_spin_lock_irqsave(&pctrl->lock, flags);
 609
 610         community = intel_get_community(pctrl, pin);
 611         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 612         value = readl(padcfg1);
 613
 614         switch (param) {
 615         case PIN_CONFIG_BIAS_DISABLE:
 616                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 617                 break;
 618
 619         case PIN_CONFIG_BIAS_PULL_UP:
 620                 value &= ~PADCFG1_TERM_MASK;
 621
 622                 value |= PADCFG1_TERM_UP;
 623
 624                 switch (arg) {
 625                 case 20000:
 626                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 627                         break;
 628                 case 5000:
 629                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 630                         break;
 631                 case 2000:
 632                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 633                         break;
 634                 case 1000:
 635                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 636                         break;
 637                 default:
 638                         ret = -EINVAL;
 639                 }
 640
 641                 break;
 642
 643         case PIN_CONFIG_BIAS_PULL_DOWN:
 644                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 645
 646                 switch (arg) {
 647                 case 20000:
 648                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 649                         break;
 650                 case 5000:
 651                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 652                         break;
 653                 case 1000:
 654                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 655                                 ret = -EINVAL;
 656                                 break;
 657                         }
 658                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 659                         break;
 660                 default:
 661                         ret = -EINVAL;
 662                 }
 663
 664                 break;
 665         }
 666
 667         if (!ret)
 668                 writel(value, padcfg1);
 669
 670         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 671
 672         return ret;
 673 }
 674
 675 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
 676                                      unsigned debounce)
 677 {
 678         void __iomem *padcfg0, *padcfg2;
 679         unsigned long flags;
 680         u32 value0, value2;
 681         int ret = 0;
 682
 683         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 684         if (!padcfg2)
 685                 return -ENOTSUPP;
 686
 687         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 688
 689         raw_spin_lock_irqsave(&pctrl->lock, flags);
 690
 691         value0 = readl(padcfg0);
 692         value2 = readl(padcfg2);
 693
 694         /* Disable glitch filter and debouncer */
 695         value0 &= ~PADCFG0_PREGFRXSEL;
 696         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 697
 698         if (debounce) {
 699                 unsigned long v;
 700
 701                 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
 702                 if (v < 3 || v > 15) {
 703                         ret = -EINVAL;
 704                         goto exit_unlock;
 705                 } else {
 706                         /* Enable glitch filter and debouncer */
 707                         value0 |= PADCFG0_PREGFRXSEL;
 708                         value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 709                         value2 |= PADCFG2_DEBEN;
 710                 }
 711         }
 712
 713         writel(value0, padcfg0);
 714         writel(value2, padcfg2);
 715
 716 exit_unlock:
 717         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 718
 719         return ret;
 720 }
 721
 722 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
 723                           unsigned long *configs, unsigned nconfigs)
 724 {
 725         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 726         int i, ret;
 727
 728         if (!intel_pad_usable(pctrl, pin))
 729                 return -ENOTSUPP;
 730
 731         for (i = 0; i < nconfigs; i++) {
 732                 switch (pinconf_to_config_param(configs[i])) {
 733                 case PIN_CONFIG_BIAS_DISABLE:
 734                 case PIN_CONFIG_BIAS_PULL_UP:
 735                 case PIN_CONFIG_BIAS_PULL_DOWN:
 736                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 737                         if (ret)
 738                                 return ret;
 739                         break;
 740
 741                 case PIN_CONFIG_INPUT_DEBOUNCE:
 742                         ret = intel_config_set_debounce(pctrl, pin,
 743                                 pinconf_to_config_argument(configs[i]));
 744                         if (ret)
 745                                 return ret;
 746                         break;
 747
 748                 default:
 749                         return -ENOTSUPP;
 750                 }
 751         }
 752
 753         return 0;
 754 }
 755
 756 static const struct pinconf_ops intel_pinconf_ops = {
 757         .is_generic = true,
 758         .pin_config_get = intel_config_get,
 759         .pin_config_set = intel_config_set,
 760 };
 761
 762 static const struct pinctrl_desc intel_pinctrl_desc = {
 763         .pctlops = &intel_pinctrl_ops,
 764         .pmxops = &intel_pinmux_ops,
 765         .confops = &intel_pinconf_ops,
 766         .owner = THIS_MODULE,
 767 };
 768
 769 /**
 770  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 771  * @pctrl: Pinctrl structure
 772  * @offset: GPIO offset from gpiolib
 773  * @commmunity: Community is filled here if not %NULL
 774  * @padgrp: Pad group is filled here if not %NULL
 775  *
 776  * When coming through gpiolib irqchip, the GPIO offset is not
 777  * automatically translated to pinctrl pin number. This function can be
 778  * used to find out the corresponding pinctrl pin.
 779  */
 780 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
 781                              const struct intel_community **community,
 782                              const struct intel_padgroup **padgrp)
 783 {
 784         int i;
 785
 786         for (i = 0; i < pctrl->ncommunities; i++) {
 787                 const struct intel_community *comm = &pctrl->communities[i];
 788                 int j;
 789
 790                 for (j = 0; j < comm->ngpps; j++) {
 791                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 792
 793                         if (pgrp->gpio_base < 0)
 794                                 continue;
 795
 796                         if (offset >= pgrp->gpio_base &&
 797                             offset < pgrp->gpio_base + pgrp->size) {
 798                                 int pin;
 799
 800                                 pin = pgrp->base + offset - pgrp->gpio_base;
 801                                 if (community)
 802                                         *community = comm;
 803                                 if (padgrp)
 804                                         *padgrp = pgrp;
 805
 806                                 return pin;
 807                         }
 808                 }
 809         }
 810
 811         return -EINVAL;
 812 }
 813
 814 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
 815 {
 816         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 817         void __iomem *reg;
 818         u32 padcfg0;
 819         int pin;
 820
 821         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 822         if (pin < 0)
 823                 return -EINVAL;
 824
 825         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 826         if (!reg)
 827                 return -EINVAL;
 828
 829         padcfg0 = readl(reg);
 830         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 831                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 832
 833         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 834 }
 835
 836 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 837 {
 838         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 839         unsigned long flags;
 840         void __iomem *reg;
 841         u32 padcfg0;
 842         int pin;
 843
 844         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 845         if (pin < 0)
 846                 return;
 847
 848         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 849         if (!reg)
 850                 return;
 851
 852         raw_spin_lock_irqsave(&pctrl->lock, flags);
 853         padcfg0 = readl(reg);
 854         if (value)
 855                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 856         else
 857                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 858         writel(padcfg0, reg);
 859         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 860 }
 861
 862 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 863 {
 864         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 865         void __iomem *reg;
 866         u32 padcfg0;
 867         int pin;
 868
 869         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 870         if (pin < 0)
 871                 return -EINVAL;
 872
 873         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 874         if (!reg)
 875                 return -EINVAL;
 876
 877         padcfg0 = readl(reg);
 878
 879         if (padcfg0 & PADCFG0_PMODE_MASK)
 880                 return -EINVAL;
 881
 882         return !!(padcfg0 & PADCFG0_GPIOTXDIS);
 883 }
 884
 885 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 886 {
 887         return pinctrl_gpio_direction_input(chip->base + offset);
 888 }
 889
 890 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 891                                        int value)
 892 {
 893         intel_gpio_set(chip, offset, value);
 894         return pinctrl_gpio_direction_output(chip->base + offset);
 895 }
 896
 897 static const struct gpio_chip intel_gpio_chip = {
 898         .owner = THIS_MODULE,
 899         .request = gpiochip_generic_request,
 900         .free = gpiochip_generic_free,
 901         .get_direction = intel_gpio_get_direction,
 902         .direction_input = intel_gpio_direction_input,
 903         .direction_output = intel_gpio_direction_output,
 904         .get = intel_gpio_get,
 905         .set = intel_gpio_set,
 906         .set_config = gpiochip_generic_config,
 907 };
 908
 909 static void intel_gpio_irq_ack(struct irq_data *d)
 910 {
 911         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 912         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 913         const struct intel_community *community;
 914         const struct intel_padgroup *padgrp;
 915         int pin;
 916
 917         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 918         if (pin >= 0) {
 919                 unsigned gpp, gpp_offset, is_offset;
 920
 921                 gpp = padgrp->reg_num;
 922                 gpp_offset = padgroup_offset(padgrp, pin);
 923                 is_offset = community->is_offset + gpp * 4;
 924
 925                 raw_spin_lock(&pctrl->lock);
 926                 writel(BIT(gpp_offset), community->regs + is_offset);
 927                 raw_spin_unlock(&pctrl->lock);
 928         }
 929 }
 930
 931 static void intel_gpio_irq_enable(struct irq_data *d)
 932 {
 933         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 934         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 935         const struct intel_community *community;
 936         const struct intel_padgroup *padgrp;
 937         int pin;
 938
 939         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 940         if (pin >= 0) {
 941                 unsigned gpp, gpp_offset, is_offset;
 942                 unsigned long flags;
 943                 u32 value;
 944
 945                 gpp = padgrp->reg_num;
 946                 gpp_offset = padgroup_offset(padgrp, pin);
 947                 is_offset = community->is_offset + gpp * 4;
 948
 949                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 950                 /* Clear interrupt status first to avoid unexpected interrupt */
 951                 writel(BIT(gpp_offset), community->regs + is_offset);
 952
 953                 value = readl(community->regs + community->ie_offset + gpp * 4);
 954                 value |= BIT(gpp_offset);
 955                 writel(value, community->regs + community->ie_offset + gpp * 4);
 956                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 957         }
 958 }
 959
 960 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 961 {
 962         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 963         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 964         const struct intel_community *community;
 965         const struct intel_padgroup *padgrp;
 966         int pin;
 967
 968         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 969         if (pin >= 0) {
 970                 unsigned gpp, gpp_offset;
 971                 unsigned long flags;
 972                 void __iomem *reg;
 973                 u32 value;
 974
 975                 gpp = padgrp->reg_num;
 976                 gpp_offset = padgroup_offset(padgrp, pin);
 977
 978                 reg = community->regs + community->ie_offset + gpp * 4;
 979
 980                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 981                 value = readl(reg);
 982                 if (mask)
 983                         value &= ~BIT(gpp_offset);
 984                 else
 985                         value |= BIT(gpp_offset);
 986                 writel(value, reg);
 987                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 988         }
 989 }
 990
 991 static void intel_gpio_irq_mask(struct irq_data *d)
 992 {
 993         intel_gpio_irq_mask_unmask(d, true);
 994 }
 995
 996 static void intel_gpio_irq_unmask(struct irq_data *d)
 997 {
 998         intel_gpio_irq_mask_unmask(d, false);
 999 }
1000
1001 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
1002 {
1003         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1004         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1005         unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1006         unsigned long flags;
1007         void __iomem *reg;
1008         u32 value;
1009
1010         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1011         if (!reg)
1012                 return -EINVAL;
1013
1014         /*
1015          * If the pin is in ACPI mode it is still usable as a GPIO but it
1016          * cannot be used as IRQ because GPI_IS status bit will not be
1017          * updated by the host controller hardware.
1018          */
1019         if (intel_pad_acpi_mode(pctrl, pin)) {
1020                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1021                 return -EPERM;
1022         }
1023
1024         raw_spin_lock_irqsave(&pctrl->lock, flags);
1025
1026         intel_gpio_set_gpio_mode(reg);
1027
1028         value = readl(reg);
1029
1030         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1031
1032         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1033                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1034         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1035                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1036                 value |= PADCFG0_RXINV;
1037         } else if (type & IRQ_TYPE_EDGE_RISING) {
1038                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1039         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1040                 if (type & IRQ_TYPE_LEVEL_LOW)
1041                         value |= PADCFG0_RXINV;
1042         } else {
1043                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1044         }
1045
1046         writel(value, reg);
1047
1048         if (type & IRQ_TYPE_EDGE_BOTH)
1049                 irq_set_handler_locked(d, handle_edge_irq);
1050         else if (type & IRQ_TYPE_LEVEL_MASK)
1051                 irq_set_handler_locked(d, handle_level_irq);
1052
1053         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1054
1055         return 0;
1056 }
1057
1058 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1059 {
1060         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1061         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1062         unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1063
1064         if (on)
1065                 enable_irq_wake(pctrl->irq);
1066         else
1067                 disable_irq_wake(pctrl->irq);
1068
1069         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1070         return 0;
1071 }
1072
1073 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1074         const struct intel_community *community)
1075 {
1076         struct gpio_chip *gc = &pctrl->chip;
1077         irqreturn_t ret = IRQ_NONE;
1078         int gpp;
1079
1080         for (gpp = 0; gpp < community->ngpps; gpp++) {
1081                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1082                 unsigned long pending, enabled, gpp_offset;
1083
1084                 pending = readl(community->regs + community->is_offset +
1085                                 padgrp->reg_num * 4);
1086                 enabled = readl(community->regs + community->ie_offset +
1087                                 padgrp->reg_num * 4);
1088
1089                 /* Only interrupts that are enabled */
1090                 pending &= enabled;
1091
1092                 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1093                         unsigned irq;
1094
1095                         irq = irq_find_mapping(gc->irq.domain,
1096                                                padgrp->gpio_base + gpp_offset);
1097                         generic_handle_irq(irq);
1098
1099                         ret |= IRQ_HANDLED;
1100                 }
1101         }
1102
1103         return ret;
1104 }
1105
1106 static irqreturn_t intel_gpio_irq(int irq, void *data)
1107 {
1108         const struct intel_community *community;
1109         struct intel_pinctrl *pctrl = data;
1110         irqreturn_t ret = IRQ_NONE;
1111         int i;
1112
1113         /* Need to check all communities for pending interrupts */
1114         for (i = 0; i < pctrl->ncommunities; i++) {
1115                 community = &pctrl->communities[i];
1116                 ret |= intel_gpio_community_irq_handler(pctrl, community);
1117         }
1118
1119         return ret;
1120 }
1121
1122 static struct irq_chip intel_gpio_irqchip = {
1123         .name = "intel-gpio",
1124         .irq_enable = intel_gpio_irq_enable,
1125         .irq_ack = intel_gpio_irq_ack,
1126         .irq_mask = intel_gpio_irq_mask,
1127         .irq_unmask = intel_gpio_irq_unmask,
1128         .irq_set_type = intel_gpio_irq_type,
1129         .irq_set_wake = intel_gpio_irq_wake,
1130         .flags = IRQCHIP_MASK_ON_SUSPEND,
1131 };
1132
1133 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1134                                      const struct intel_community *community)
1135 {
1136         int ret = 0, i;
1137
1138         for (i = 0; i < community->ngpps; i++) {
1139                 const struct intel_padgroup *gpp = &community->gpps[i];
1140
1141                 if (gpp->gpio_base < 0)
1142                         continue;
1143
1144                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1145                                              gpp->gpio_base, gpp->base,
1146                                              gpp->size);
1147                 if (ret)
1148                         return ret;
1149         }
1150
1151         return ret;
1152 }
1153
1154 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1155 {
1156         const struct intel_community *community;
1157         unsigned ngpio = 0;
1158         int i, j;
1159
1160         for (i = 0; i < pctrl->ncommunities; i++) {
1161                 community = &pctrl->communities[i];
1162                 for (j = 0; j < community->ngpps; j++) {
1163                         const struct intel_padgroup *gpp = &community->gpps[j];
1164
1165                         if (gpp->gpio_base < 0)
1166                                 continue;
1167
1168                         if (gpp->gpio_base + gpp->size > ngpio)
1169                                 ngpio = gpp->gpio_base + gpp->size;
1170                 }
1171         }
1172
1173         return ngpio;
1174 }
1175
1176 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1177 {
1178         int ret, i;
1179
1180         pctrl->chip = intel_gpio_chip;
1181
1182         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1183         pctrl->chip.label = dev_name(pctrl->dev);
1184         pctrl->chip.parent = pctrl->dev;
1185         pctrl->chip.base = -1;
1186         pctrl->irq = irq;
1187
1188         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1189         if (ret) {
1190                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1191                 return ret;
1192         }
1193
1194         for (i = 0; i < pctrl->ncommunities; i++) {
1195                 struct intel_community *community = &pctrl->communities[i];
1196
1197                 ret = intel_gpio_add_pin_ranges(pctrl, community);
1198                 if (ret) {
1199                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1200                         return ret;
1201                 }
1202         }
1203
1204         /*
1205          * We need to request the interrupt here (instead of providing chip
1206          * to the irq directly) because on some platforms several GPIO
1207          * controllers share the same interrupt line.
1208          */
1209         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1210                                IRQF_SHARED | IRQF_NO_THREAD,
1211                                dev_name(pctrl->dev), pctrl);
1212         if (ret) {
1213                 dev_err(pctrl->dev, "failed to request interrupt\n");
1214                 return ret;
1215         }
1216
1217         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1218                                    handle_bad_irq, IRQ_TYPE_NONE);
1219         if (ret) {
1220                 dev_err(pctrl->dev, "failed to add irqchip\n");
1221                 return ret;
1222         }
1223
1224         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1225                                      NULL);
1226         return 0;
1227 }
1228
1229 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1230                                        struct intel_community *community)
1231 {
1232         struct intel_padgroup *gpps;
1233         unsigned npins = community->npins;
1234         unsigned padown_num = 0;
1235         size_t ngpps, i;
1236
1237         if (community->gpps)
1238                 ngpps = community->ngpps;
1239         else
1240                 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1241
1242         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1243         if (!gpps)
1244                 return -ENOMEM;
1245
1246         for (i = 0; i < ngpps; i++) {
1247                 if (community->gpps) {
1248                         gpps[i] = community->gpps[i];
1249                 } else {
1250                         unsigned gpp_size = community->gpp_size;
1251
1252                         gpps[i].reg_num = i;
1253                         gpps[i].base = community->pin_base + i * gpp_size;
1254                         gpps[i].size = min(gpp_size, npins);
1255                         npins -= gpps[i].size;
1256                 }
1257
1258                 if (gpps[i].size > 32)
1259                         return -EINVAL;
1260
1261                 if (!gpps[i].gpio_base)
1262                         gpps[i].gpio_base = gpps[i].base;
1263
1264                 gpps[i].padown_num = padown_num;
1265
1266                 /*
1267                  * In older hardware the number of padown registers per
1268                  * group is fixed regardless of the group size.
1269                  */
1270                 if (community->gpp_num_padown_regs)
1271                         padown_num += community->gpp_num_padown_regs;
1272                 else
1273                         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1274         }
1275
1276         community->ngpps = ngpps;
1277         community->gpps = gpps;
1278
1279         return 0;
1280 }
1281
1282 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1283 {
1284 #ifdef CONFIG_PM_SLEEP
1285         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1286         struct intel_community_context *communities;
1287         struct intel_pad_context *pads;
1288         int i;
1289
1290         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1291         if (!pads)
1292                 return -ENOMEM;
1293
1294         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1295                                    sizeof(*communities), GFP_KERNEL);
1296         if (!communities)
1297                 return -ENOMEM;
1298
1299
1300         for (i = 0; i < pctrl->ncommunities; i++) {
1301                 struct intel_community *community = &pctrl->communities[i];
1302                 u32 *intmask;
1303
1304                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1305                                        sizeof(*intmask), GFP_KERNEL);
1306                 if (!intmask)
1307                         return -ENOMEM;
1308
1309                 communities[i].intmask = intmask;
1310         }
1311
1312         pctrl->context.pads = pads;
1313         pctrl->context.communities = communities;
1314 #endif
1315
1316         return 0;
1317 }
1318
1319 int intel_pinctrl_probe(struct platform_device *pdev,
1320                         const struct intel_pinctrl_soc_data *soc_data)
1321 {
1322         struct intel_pinctrl *pctrl;
1323         int i, ret, irq;
1324
1325         if (!soc_data)
1326                 return -EINVAL;
1327
1328         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1329         if (!pctrl)
1330                 return -ENOMEM;
1331
1332         pctrl->dev = &pdev->dev;
1333         pctrl->soc = soc_data;
1334         raw_spin_lock_init(&pctrl->lock);
1335
1336         /*
1337          * Make a copy of the communities which we can use to hold pointers
1338          * to the registers.
1339          */
1340         pctrl->ncommunities = pctrl->soc->ncommunities;
1341         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1342                                   sizeof(*pctrl->communities), GFP_KERNEL);
1343         if (!pctrl->communities)
1344                 return -ENOMEM;
1345
1346         for (i = 0; i < pctrl->ncommunities; i++) {
1347                 struct intel_community *community = &pctrl->communities[i];
1348                 struct resource *res;
1349                 void __iomem *regs;
1350                 u32 padbar;
1351
1352                 *community = pctrl->soc->communities[i];
1353
1354                 res = platform_get_resource(pdev, IORESOURCE_MEM,
1355                                             community->barno);
1356                 regs = devm_ioremap_resource(&pdev->dev, res);
1357                 if (IS_ERR(regs))
1358                         return PTR_ERR(regs);
1359
1360                 /*
1361                  * Determine community features based on the revision if
1362                  * not specified already.
1363                  */
1364                 if (!community->features) {
1365                         u32 rev;
1366
1367                         rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1368                         if (rev >= 0x94) {
1369                                 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1370                                 community->features |= PINCTRL_FEATURE_1K_PD;
1371                         }
1372                 }
1373
1374                 /* Read offset of the pad configuration registers */
1375                 padbar = readl(regs + PADBAR);
1376
1377                 community->regs = regs;
1378                 community->pad_regs = regs + padbar;
1379
1380                 if (!community->is_offset)
1381                         community->is_offset = GPI_IS;
1382
1383                 ret = intel_pinctrl_add_padgroups(pctrl, community);
1384                 if (ret)
1385                         return ret;
1386         }
1387
1388         irq = platform_get_irq(pdev, 0);
1389         if (irq < 0) {
1390                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1391                 return irq;
1392         }
1393
1394         ret = intel_pinctrl_pm_init(pctrl);
1395         if (ret)
1396                 return ret;
1397
1398         pctrl->pctldesc = intel_pinctrl_desc;
1399         pctrl->pctldesc.name = dev_name(&pdev->dev);
1400         pctrl->pctldesc.pins = pctrl->soc->pins;
1401         pctrl->pctldesc.npins = pctrl->soc->npins;
1402
1403         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1404                                                pctrl);
1405         if (IS_ERR(pctrl->pctldev)) {
1406                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1407                 return PTR_ERR(pctrl->pctldev);
1408         }
1409
1410         ret = intel_gpio_probe(pctrl, irq);
1411         if (ret)
1412                 return ret;
1413
1414         platform_set_drvdata(pdev, pctrl);
1415
1416         return 0;
1417 }
1418 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1419
1420 #ifdef CONFIG_PM_SLEEP
1421 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1422 {
1423         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1424
1425         if (!pd || !intel_pad_usable(pctrl, pin))
1426                 return false;
1427
1428         /*
1429          * Only restore the pin if it is actually in use by the kernel (or
1430          * by userspace). It is possible that some pins are used by the
1431          * BIOS during resume and those are not always locked down so leave
1432          * them alone.
1433          */
1434         if (pd->mux_owner || pd->gpio_owner ||
1435             gpiochip_line_is_irq(&pctrl->chip, pin))
1436                 return true;
1437
1438         return false;
1439 }
1440
1441 int intel_pinctrl_suspend(struct device *dev)
1442 {
1443         struct platform_device *pdev = to_platform_device(dev);
1444         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1445         struct intel_community_context *communities;
1446         struct intel_pad_context *pads;
1447         int i;
1448
1449         pads = pctrl->context.pads;
1450         for (i = 0; i < pctrl->soc->npins; i++) {
1451                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1452                 void __iomem *padcfg;
1453                 u32 val;
1454
1455                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1456                         continue;
1457
1458                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1459                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1460                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1461                 pads[i].padcfg1 = val;
1462
1463                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1464                 if (padcfg)
1465                         pads[i].padcfg2 = readl(padcfg);
1466         }
1467
1468         communities = pctrl->context.communities;
1469         for (i = 0; i < pctrl->ncommunities; i++) {
1470                 struct intel_community *community = &pctrl->communities[i];
1471                 void __iomem *base;
1472                 unsigned gpp;
1473
1474                 base = community->regs + community->ie_offset;
1475                 for (gpp = 0; gpp < community->ngpps; gpp++)
1476                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1477         }
1478
1479         return 0;
1480 }
1481 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1482
1483 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1484 {
1485         size_t i;
1486
1487         for (i = 0; i < pctrl->ncommunities; i++) {
1488                 const struct intel_community *community;
1489                 void __iomem *base;
1490                 unsigned gpp;
1491
1492                 community = &pctrl->communities[i];
1493                 base = community->regs;
1494
1495                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1496                         /* Mask and clear all interrupts */
1497                         writel(0, base + community->ie_offset + gpp * 4);
1498                         writel(0xffff, base + community->is_offset + gpp * 4);
1499                 }
1500         }
1501 }
1502
1503 int intel_pinctrl_resume(struct device *dev)
1504 {
1505         struct platform_device *pdev = to_platform_device(dev);
1506         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1507         const struct intel_community_context *communities;
1508         const struct intel_pad_context *pads;
1509         int i;
1510
1511         /* Mask all interrupts */
1512         intel_gpio_irq_init(pctrl);
1513
1514         pads = pctrl->context.pads;
1515         for (i = 0; i < pctrl->soc->npins; i++) {
1516                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1517                 void __iomem *padcfg;
1518                 u32 val;
1519
1520                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1521                         continue;
1522
1523                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1524                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1525                 if (val != pads[i].padcfg0) {
1526                         writel(pads[i].padcfg0, padcfg);
1527                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1528                                 desc->number, readl(padcfg));
1529                 }
1530
1531                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1532                 val = readl(padcfg);
1533                 if (val != pads[i].padcfg1) {
1534                         writel(pads[i].padcfg1, padcfg);
1535                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1536                                 desc->number, readl(padcfg));
1537                 }
1538
1539                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1540                 if (padcfg) {
1541                         val = readl(padcfg);
1542                         if (val != pads[i].padcfg2) {
1543                                 writel(pads[i].padcfg2, padcfg);
1544                                 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1545                                         desc->number, readl(padcfg));
1546                         }
1547                 }
1548         }
1549
1550         communities = pctrl->context.communities;
1551         for (i = 0; i < pctrl->ncommunities; i++) {
1552                 struct intel_community *community = &pctrl->communities[i];
1553                 void __iomem *base;
1554                 unsigned gpp;
1555
1556                 base = community->regs + community->ie_offset;
1557                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1558                         writel(communities[i].intmask[gpp], base + gpp * 4);
1559                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1560                                 readl(base + gpp * 4));
1561                 }
1562         }
1563
1564         return 0;
1565 }
1566 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1567 #endif
1568
1569 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1570 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1571 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1572 MODULE_LICENSE("GPL v2");