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Linux 4.19.133
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-amd.c
blobb1ffdd3f6d076ab31bb94a922f97467d4ccc5817
1 /*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
13 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
14 *
15 */
16
17 #include <linux/err.h>
18 #include <linux/bug.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/compiler.h>
23 #include <linux/types.h>
24 #include <linux/errno.h>
25 #include <linux/log2.h>
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/slab.h>
29 #include <linux/platform_device.h>
30 #include <linux/mutex.h>
31 #include <linux/acpi.h>
32 #include <linux/seq_file.h>
33 #include <linux/interrupt.h>
34 #include <linux/list.h>
35 #include <linux/bitops.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38
39 #include "core.h"
40 #include "pinctrl-utils.h"
41 #include "pinctrl-amd.h"
42
43 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
44 {
45 unsigned long flags;
46 u32 pin_reg;
47 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
48
49 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
50 pin_reg = readl(gpio_dev->base + offset * 4);
51 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
52
53 return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
54 }
55
56 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
57 {
58 unsigned long flags;
59 u32 pin_reg;
60 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
61
62 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
63 pin_reg = readl(gpio_dev->base + offset * 4);
64 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
65 writel(pin_reg, gpio_dev->base + offset * 4);
66 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
67
68 return 0;
69 }
70
71 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
72 int value)
73 {
74 u32 pin_reg;
75 unsigned long flags;
76 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
77
78 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
79 pin_reg = readl(gpio_dev->base + offset * 4);
80 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
81 if (value)
82 pin_reg |= BIT(OUTPUT_VALUE_OFF);
83 else
84 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
85 writel(pin_reg, gpio_dev->base + offset * 4);
86 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
87
88 return 0;
89 }
90
91 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
92 {
93 u32 pin_reg;
94 unsigned long flags;
95 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
96
97 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
98 pin_reg = readl(gpio_dev->base + offset * 4);
99 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
100
101 return !!(pin_reg & BIT(PIN_STS_OFF));
102 }
103
104 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
105 {
106 u32 pin_reg;
107 unsigned long flags;
108 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
109
110 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
111 pin_reg = readl(gpio_dev->base + offset * 4);
112 if (value)
113 pin_reg |= BIT(OUTPUT_VALUE_OFF);
114 else
115 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
116 writel(pin_reg, gpio_dev->base + offset * 4);
117 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
118 }
119
120 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
121 unsigned debounce)
122 {
123 u32 time;
124 u32 pin_reg;
125 int ret = 0;
126 unsigned long flags;
127 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
128
129 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
130 pin_reg = readl(gpio_dev->base + offset * 4);
131
132 if (debounce) {
133 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
134 pin_reg &= ~DB_TMR_OUT_MASK;
135 /*
136 Debounce Debounce Timer Max
137 TmrLarge TmrOutUnit Unit Debounce
138 Time
139 0 0 61 usec (2 RtcClk) 976 usec
140 0 1 244 usec (8 RtcClk) 3.9 msec
141 1 0 15.6 msec (512 RtcClk) 250 msec
142 1 1 62.5 msec (2048 RtcClk) 1 sec
143 */
144
145 if (debounce < 61) {
146 pin_reg |= 1;
147 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
148 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
149 } else if (debounce < 976) {
150 time = debounce / 61;
151 pin_reg |= time & DB_TMR_OUT_MASK;
152 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
153 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
154 } else if (debounce < 3900) {
155 time = debounce / 244;
156 pin_reg |= time & DB_TMR_OUT_MASK;
157 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
158 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
159 } else if (debounce < 250000) {
160 time = debounce / 15600;
161 pin_reg |= time & DB_TMR_OUT_MASK;
162 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
163 pin_reg |= BIT(DB_TMR_LARGE_OFF);
164 } else if (debounce < 1000000) {
165 time = debounce / 62500;
166 pin_reg |= time & DB_TMR_OUT_MASK;
167 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
168 pin_reg |= BIT(DB_TMR_LARGE_OFF);
169 } else {
170 pin_reg &= ~DB_CNTRl_MASK;
171 ret = -EINVAL;
172 }
173 } else {
174 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
175 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
176 pin_reg &= ~DB_TMR_OUT_MASK;
177 pin_reg &= ~DB_CNTRl_MASK;
178 }
179 writel(pin_reg, gpio_dev->base + offset * 4);
180 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
181
182 return ret;
183 }
184
185 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
186 unsigned long config)
187 {
188 u32 debounce;
189
190 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
191 return -ENOTSUPP;
192
193 debounce = pinconf_to_config_argument(config);
194 return amd_gpio_set_debounce(gc, offset, debounce);
195 }
196
197 #ifdef CONFIG_DEBUG_FS
198 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
199 {
200 u32 pin_reg;
201 unsigned long flags;
202 unsigned int bank, i, pin_num;
203 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
204
205 char *level_trig;
206 char *active_level;
207 char *interrupt_enable;
208 char *interrupt_mask;
209 char *wake_cntrl0;
210 char *wake_cntrl1;
211 char *wake_cntrl2;
212 char *pin_sts;
213 char *pull_up_sel;
214 char *pull_up_enable;
215 char *pull_down_enable;
216 char *output_value;
217 char *output_enable;
218
219 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
220 seq_printf(s, "GPIO bank%d\t", bank);
221
222 switch (bank) {
223 case 0:
224 i = 0;
225 pin_num = AMD_GPIO_PINS_BANK0;
226 break;
227 case 1:
228 i = 64;
229 pin_num = AMD_GPIO_PINS_BANK1 + i;
230 break;
231 case 2:
232 i = 128;
233 pin_num = AMD_GPIO_PINS_BANK2 + i;
234 break;
235 case 3:
236 i = 192;
237 pin_num = AMD_GPIO_PINS_BANK3 + i;
238 break;
239 default:
240 /* Illegal bank number, ignore */
241 continue;
242 }
243 for (; i < pin_num; i++) {
244 seq_printf(s, "pin%d\t", i);
245 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
246 pin_reg = readl(gpio_dev->base + i * 4);
247 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
248
249 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
250 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
251 ACTIVE_LEVEL_MASK;
252 interrupt_enable = "interrupt is enabled|";
253
254 if (level == ACTIVE_LEVEL_HIGH)
255 active_level = "Active high|";
256 else if (level == ACTIVE_LEVEL_LOW)
257 active_level = "Active low|";
258 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
259 level == ACTIVE_LEVEL_BOTH)
260 active_level = "Active on both|";
261 else
262 active_level = "Unknown Active level|";
263
264 if (pin_reg & BIT(LEVEL_TRIG_OFF))
265 level_trig = "Level trigger|";
266 else
267 level_trig = "Edge trigger|";
268
269 } else {
270 interrupt_enable =
271 "interrupt is disabled|";
272 active_level = " ";
273 level_trig = " ";
274 }
275
276 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
277 interrupt_mask =
278 "interrupt is unmasked|";
279 else
280 interrupt_mask =
281 "interrupt is masked|";
282
283 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
284 wake_cntrl0 = "enable wakeup in S0i3 state|";
285 else
286 wake_cntrl0 = "disable wakeup in S0i3 state|";
287
288 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
289 wake_cntrl1 = "enable wakeup in S3 state|";
290 else
291 wake_cntrl1 = "disable wakeup in S3 state|";
292
293 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
294 wake_cntrl2 = "enable wakeup in S4/S5 state|";
295 else
296 wake_cntrl2 = "disable wakeup in S4/S5 state|";
297
298 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
299 pull_up_enable = "pull-up is enabled|";
300 if (pin_reg & BIT(PULL_UP_SEL_OFF))
301 pull_up_sel = "8k pull-up|";
302 else
303 pull_up_sel = "4k pull-up|";
304 } else {
305 pull_up_enable = "pull-up is disabled|";
306 pull_up_sel = " ";
307 }
308
309 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
310 pull_down_enable = "pull-down is enabled|";
311 else
312 pull_down_enable = "Pull-down is disabled|";
313
314 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
315 pin_sts = " ";
316 output_enable = "output is enabled|";
317 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
318 output_value = "output is high|";
319 else
320 output_value = "output is low|";
321 } else {
322 output_enable = "output is disabled|";
323 output_value = " ";
324
325 if (pin_reg & BIT(PIN_STS_OFF))
326 pin_sts = "input is high|";
327 else
328 pin_sts = "input is low|";
329 }
330
331 seq_printf(s, "%s %s %s %s %s %s\n"
332 " %s %s %s %s %s %s %s 0x%x\n",
333 level_trig, active_level, interrupt_enable,
334 interrupt_mask, wake_cntrl0, wake_cntrl1,
335 wake_cntrl2, pin_sts, pull_up_sel,
336 pull_up_enable, pull_down_enable,
337 output_value, output_enable, pin_reg);
338 }
339 }
340 }
341 #else
342 #define amd_gpio_dbg_show NULL
343 #endif
344
345 static void amd_gpio_irq_enable(struct irq_data *d)
346 {
347 u32 pin_reg;
348 unsigned long flags;
349 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
350 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
351
352 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
353 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
354 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
355 pin_reg |= BIT(INTERRUPT_MASK_OFF);
356 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
357 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
358 }
359
360 static void amd_gpio_irq_disable(struct irq_data *d)
361 {
362 u32 pin_reg;
363 unsigned long flags;
364 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
365 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
366
367 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
368 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
369 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
370 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
371 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
372 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
373 }
374
375 static void amd_gpio_irq_mask(struct irq_data *d)
376 {
377 u32 pin_reg;
378 unsigned long flags;
379 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
380 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
381
382 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
383 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
384 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
385 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
386 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
387 }
388
389 static void amd_gpio_irq_unmask(struct irq_data *d)
390 {
391 u32 pin_reg;
392 unsigned long flags;
393 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
394 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
395
396 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
397 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
398 pin_reg |= BIT(INTERRUPT_MASK_OFF);
399 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
400 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
401 }
402
403 static void amd_gpio_irq_eoi(struct irq_data *d)
404 {
405 u32 reg;
406 unsigned long flags;
407 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
408 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
409
410 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
411 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
412 reg |= EOI_MASK;
413 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
414 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
415 }
416
417 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
418 {
419 int ret = 0;
420 u32 pin_reg, pin_reg_irq_en, mask;
421 unsigned long flags, irq_flags;
422 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
423 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
424
425 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
426 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
427
428 /* Ignore the settings coming from the client and
429 * read the values from the ACPI tables
430 * while setting the trigger type
431 */
432
433 irq_flags = irq_get_trigger_type(d->irq);
434 if (irq_flags != IRQ_TYPE_NONE)
435 type = irq_flags;
436
437 switch (type & IRQ_TYPE_SENSE_MASK) {
438 case IRQ_TYPE_EDGE_RISING:
439 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
440 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
441 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
442 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
443 irq_set_handler_locked(d, handle_edge_irq);
444 break;
445
446 case IRQ_TYPE_EDGE_FALLING:
447 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
448 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
449 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
450 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
451 irq_set_handler_locked(d, handle_edge_irq);
452 break;
453
454 case IRQ_TYPE_EDGE_BOTH:
455 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
456 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
457 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
458 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
459 irq_set_handler_locked(d, handle_edge_irq);
460 break;
461
462 case IRQ_TYPE_LEVEL_HIGH:
463 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
464 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
465 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
466 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
467 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
468 irq_set_handler_locked(d, handle_level_irq);
469 break;
470
471 case IRQ_TYPE_LEVEL_LOW:
472 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
473 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
474 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
475 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
476 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
477 irq_set_handler_locked(d, handle_level_irq);
478 break;
479
480 case IRQ_TYPE_NONE:
481 break;
482
483 default:
484 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
485 ret = -EINVAL;
486 }
487
488 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
489 /*
490 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
491 * debounce registers of any GPIO will block wake/interrupt status
492 * generation for *all* GPIOs for a lenght of time that depends on
493 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
494 * INTERRUPT_ENABLE bit will read as 0.
495 *
496 * We temporarily enable irq for the GPIO whose configuration is
497 * changing, and then wait for it to read back as 1 to know when
498 * debounce has settled and then disable the irq again.
499 * We do this polling with the spinlock held to ensure other GPIO
500 * access routines do not read an incorrect value for the irq enable
501 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
502 * spurious irqs, and disable the irq again after polling.
503 */
504 mask = BIT(INTERRUPT_ENABLE_OFF);
505 pin_reg_irq_en = pin_reg;
506 pin_reg_irq_en |= mask;
507 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
508 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
509 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
510 continue;
511 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
512 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
513
514 return ret;
515 }
516
517 static void amd_irq_ack(struct irq_data *d)
518 {
519 /*
520 * based on HW design,there is no need to ack HW
521 * before handle current irq. But this routine is
522 * necessary for handle_edge_irq
523 */
524 }
525
526 static struct irq_chip amd_gpio_irqchip = {
527 .name = "amd_gpio",
528 .irq_ack = amd_irq_ack,
529 .irq_enable = amd_gpio_irq_enable,
530 .irq_disable = amd_gpio_irq_disable,
531 .irq_mask = amd_gpio_irq_mask,
532 .irq_unmask = amd_gpio_irq_unmask,
533 .irq_eoi = amd_gpio_irq_eoi,
534 .irq_set_type = amd_gpio_irq_set_type,
535 .flags = IRQCHIP_SKIP_SET_WAKE,
536 };
537
538 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
539
540 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
541 {
542 struct amd_gpio *gpio_dev = dev_id;
543 struct gpio_chip *gc = &gpio_dev->gc;
544 irqreturn_t ret = IRQ_NONE;
545 unsigned int i, irqnr;
546 unsigned long flags;
547 u32 __iomem *regs;
548 u32 regval;
549 u64 status, mask;
550
551 /* Read the wake status */
552 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
553 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
554 status <<= 32;
555 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
556 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
557
558 /* Bit 0-45 contain the relevant status bits */
559 status &= (1ULL << 46) - 1;
560 regs = gpio_dev->base;
561 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
562 if (!(status & mask))
563 continue;
564 status &= ~mask;
565
566 /* Each status bit covers four pins */
567 for (i = 0; i < 4; i++) {
568 regval = readl(regs + i);
569 if (!(regval & PIN_IRQ_PENDING) ||
570 !(regval & BIT(INTERRUPT_MASK_OFF)))
571 continue;
572 irq = irq_find_mapping(gc->irq.domain, irqnr + i);
573 if (irq != 0)
574 generic_handle_irq(irq);
575
576 /* Clear interrupt.
577 * We must read the pin register again, in case the
578 * value was changed while executing
579 * generic_handle_irq() above.
580 * If we didn't find a mapping for the interrupt,
581 * disable it in order to avoid a system hang caused
582 * by an interrupt storm.
583 */
584 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
585 regval = readl(regs + i);
586 if (irq == 0) {
587 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
588 dev_dbg(&gpio_dev->pdev->dev,
589 "Disabling spurious GPIO IRQ %d\n",
590 irqnr + i);
591 }
592 writel(regval, regs + i);
593 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
594 ret = IRQ_HANDLED;
595 }
596 }
597
598 /* Signal EOI to the GPIO unit */
599 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
600 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
601 regval |= EOI_MASK;
602 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
603 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
604
605 return ret;
606 }
607
608 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
609 {
610 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
611
612 return gpio_dev->ngroups;
613 }
614
615 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
616 unsigned group)
617 {
618 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
619
620 return gpio_dev->groups[group].name;
621 }
622
623 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
624 unsigned group,
625 const unsigned **pins,
626 unsigned *num_pins)
627 {
628 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
629
630 *pins = gpio_dev->groups[group].pins;
631 *num_pins = gpio_dev->groups[group].npins;
632 return 0;
633 }
634
635 static const struct pinctrl_ops amd_pinctrl_ops = {
636 .get_groups_count = amd_get_groups_count,
637 .get_group_name = amd_get_group_name,
638 .get_group_pins = amd_get_group_pins,
639 #ifdef CONFIG_OF
640 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
641 .dt_free_map = pinctrl_utils_free_map,
642 #endif
643 };
644
645 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
646 unsigned int pin,
647 unsigned long *config)
648 {
649 u32 pin_reg;
650 unsigned arg;
651 unsigned long flags;
652 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
653 enum pin_config_param param = pinconf_to_config_param(*config);
654
655 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
656 pin_reg = readl(gpio_dev->base + pin*4);
657 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
658 switch (param) {
659 case PIN_CONFIG_INPUT_DEBOUNCE:
660 arg = pin_reg & DB_TMR_OUT_MASK;
661 break;
662
663 case PIN_CONFIG_BIAS_PULL_DOWN:
664 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
665 break;
666
667 case PIN_CONFIG_BIAS_PULL_UP:
668 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
669 break;
670
671 case PIN_CONFIG_DRIVE_STRENGTH:
672 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
673 break;
674
675 default:
676 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
677 param);
678 return -ENOTSUPP;
679 }
680
681 *config = pinconf_to_config_packed(param, arg);
682
683 return 0;
684 }
685
686 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
687 unsigned long *configs, unsigned num_configs)
688 {
689 int i;
690 u32 arg;
691 int ret = 0;
692 u32 pin_reg;
693 unsigned long flags;
694 enum pin_config_param param;
695 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
696
697 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
698 for (i = 0; i < num_configs; i++) {
699 param = pinconf_to_config_param(configs[i]);
700 arg = pinconf_to_config_argument(configs[i]);
701 pin_reg = readl(gpio_dev->base + pin*4);
702
703 switch (param) {
704 case PIN_CONFIG_INPUT_DEBOUNCE:
705 pin_reg &= ~DB_TMR_OUT_MASK;
706 pin_reg |= arg & DB_TMR_OUT_MASK;
707 break;
708
709 case PIN_CONFIG_BIAS_PULL_DOWN:
710 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
711 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
712 break;
713
714 case PIN_CONFIG_BIAS_PULL_UP:
715 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
716 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
717 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
718 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
719 break;
720
721 case PIN_CONFIG_DRIVE_STRENGTH:
722 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
723 << DRV_STRENGTH_SEL_OFF);
724 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
725 << DRV_STRENGTH_SEL_OFF;
726 break;
727
728 default:
729 dev_err(&gpio_dev->pdev->dev,
730 "Invalid config param %04x\n", param);
731 ret = -ENOTSUPP;
732 }
733
734 writel(pin_reg, gpio_dev->base + pin*4);
735 }
736 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
737
738 return ret;
739 }
740
741 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
742 unsigned int group,
743 unsigned long *config)
744 {
745 const unsigned *pins;
746 unsigned npins;
747 int ret;
748
749 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
750 if (ret)
751 return ret;
752
753 if (amd_pinconf_get(pctldev, pins[0], config))
754 return -ENOTSUPP;
755
756 return 0;
757 }
758
759 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
760 unsigned group, unsigned long *configs,
761 unsigned num_configs)
762 {
763 const unsigned *pins;
764 unsigned npins;
765 int i, ret;
766
767 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
768 if (ret)
769 return ret;
770 for (i = 0; i < npins; i++) {
771 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
772 return -ENOTSUPP;
773 }
774 return 0;
775 }
776
777 static const struct pinconf_ops amd_pinconf_ops = {
778 .pin_config_get = amd_pinconf_get,
779 .pin_config_set = amd_pinconf_set,
780 .pin_config_group_get = amd_pinconf_group_get,
781 .pin_config_group_set = amd_pinconf_group_set,
782 };
783
784 #ifdef CONFIG_PM_SLEEP
785 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
786 {
787 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
788
789 if (!pd)
790 return false;
791
792 /*
793 * Only restore the pin if it is actually in use by the kernel (or
794 * by userspace).
795 */
796 if (pd->mux_owner || pd->gpio_owner ||
797 gpiochip_line_is_irq(&gpio_dev->gc, pin))
798 return true;
799
800 return false;
801 }
802
803 static int amd_gpio_suspend(struct device *dev)
804 {
805 struct platform_device *pdev = to_platform_device(dev);
806 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
807 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
808 int i;
809
810 for (i = 0; i < desc->npins; i++) {
811 int pin = desc->pins[i].number;
812
813 if (!amd_gpio_should_save(gpio_dev, pin))
814 continue;
815
816 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
817 }
818
819 return 0;
820 }
821
822 static int amd_gpio_resume(struct device *dev)
823 {
824 struct platform_device *pdev = to_platform_device(dev);
825 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
826 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
827 int i;
828
829 for (i = 0; i < desc->npins; i++) {
830 int pin = desc->pins[i].number;
831
832 if (!amd_gpio_should_save(gpio_dev, pin))
833 continue;
834
835 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
836 }
837
838 return 0;
839 }
840
841 static const struct dev_pm_ops amd_gpio_pm_ops = {
842 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
843 amd_gpio_resume)
844 };
845 #endif
846
847 static struct pinctrl_desc amd_pinctrl_desc = {
848 .pins = kerncz_pins,
849 .npins = ARRAY_SIZE(kerncz_pins),
850 .pctlops = &amd_pinctrl_ops,
851 .confops = &amd_pinconf_ops,
852 .owner = THIS_MODULE,
853 };
854
855 static int amd_gpio_probe(struct platform_device *pdev)
856 {
857 int ret = 0;
858 int irq_base;
859 struct resource *res;
860 struct amd_gpio *gpio_dev;
861
862 gpio_dev = devm_kzalloc(&pdev->dev,
863 sizeof(struct amd_gpio), GFP_KERNEL);
864 if (!gpio_dev)
865 return -ENOMEM;
866
867 raw_spin_lock_init(&gpio_dev->lock);
868
869 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
870 if (!res) {
871 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
872 return -EINVAL;
873 }
874
875 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
876 resource_size(res));
877 if (!gpio_dev->base)
878 return -ENOMEM;
879
880 irq_base = platform_get_irq(pdev, 0);
881 if (irq_base < 0) {
882 dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base);
883 return irq_base;
884 }
885
886 #ifdef CONFIG_PM_SLEEP
887 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
888 sizeof(*gpio_dev->saved_regs),
889 GFP_KERNEL);
890 if (!gpio_dev->saved_regs)
891 return -ENOMEM;
892 #endif
893
894 gpio_dev->pdev = pdev;
895 gpio_dev->gc.get_direction = amd_gpio_get_direction;
896 gpio_dev->gc.direction_input = amd_gpio_direction_input;
897 gpio_dev->gc.direction_output = amd_gpio_direction_output;
898 gpio_dev->gc.get = amd_gpio_get_value;
899 gpio_dev->gc.set = amd_gpio_set_value;
900 gpio_dev->gc.set_config = amd_gpio_set_config;
901 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
902
903 gpio_dev->gc.base = -1;
904 gpio_dev->gc.label = pdev->name;
905 gpio_dev->gc.owner = THIS_MODULE;
906 gpio_dev->gc.parent = &pdev->dev;
907 gpio_dev->gc.ngpio = resource_size(res) / 4;
908 #if defined(CONFIG_OF_GPIO)
909 gpio_dev->gc.of_node = pdev->dev.of_node;
910 #endif
911
912 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
913 gpio_dev->groups = kerncz_groups;
914 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
915
916 amd_pinctrl_desc.name = dev_name(&pdev->dev);
917 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
918 gpio_dev);
919 if (IS_ERR(gpio_dev->pctrl)) {
920 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
921 return PTR_ERR(gpio_dev->pctrl);
922 }
923
924 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
925 if (ret)
926 return ret;
927
928 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
929 0, 0, gpio_dev->gc.ngpio);
930 if (ret) {
931 dev_err(&pdev->dev, "Failed to add pin range\n");
932 goto out2;
933 }
934
935 ret = gpiochip_irqchip_add(&gpio_dev->gc,
936 &amd_gpio_irqchip,
937 0,
938 handle_simple_irq,
939 IRQ_TYPE_NONE);
940 if (ret) {
941 dev_err(&pdev->dev, "could not add irqchip\n");
942 ret = -ENODEV;
943 goto out2;
944 }
945
946 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
947 KBUILD_MODNAME, gpio_dev);
948 if (ret)
949 goto out2;
950
951 platform_set_drvdata(pdev, gpio_dev);
952
953 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
954 return ret;
955
956 out2:
957 gpiochip_remove(&gpio_dev->gc);
958
959 return ret;
960 }
961
962 static int amd_gpio_remove(struct platform_device *pdev)
963 {
964 struct amd_gpio *gpio_dev;
965
966 gpio_dev = platform_get_drvdata(pdev);
967
968 gpiochip_remove(&gpio_dev->gc);
969
970 return 0;
971 }
972
973 static const struct acpi_device_id amd_gpio_acpi_match[] = {
974 { "AMD0030", 0 },
975 { "AMDI0030", 0},
976 { },
977 };
978 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
979
980 static struct platform_driver amd_gpio_driver = {
981 .driver = {
982 .name = "amd_gpio",
983 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
984 #ifdef CONFIG_PM_SLEEP
985 .pm = &amd_gpio_pm_ops,
986 #endif
987 },
988 .probe = amd_gpio_probe,
989 .remove = amd_gpio_remove,
990 };
991
992 module_platform_driver(amd_gpio_driver);
993
994 MODULE_LICENSE("GPL v2");
995 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
996 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux with added FPC-III support