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Linux 4.19.133
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-at91-pio4.c
blob9e2f3738bf3ecdec3314be32863b4fcc89b46739
1 /*
2 * Driver for the Atmel PIO4 controller
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <dt-bindings/pinctrl/at91.h>
18 #include <linux/clk.h>
19 #include <linux/gpio/driver.h>
20 /* FIXME: needed for gpio_to_irq(), get rid of this */
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/init.h>
25 #include <linux/of.h>
26 #include <linux/platform_device.h>
27 #include <linux/pinctrl/pinconf.h>
28 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/slab.h>
32 #include "core.h"
33 #include "pinconf.h"
34 #include "pinctrl-utils.h"
35
36 /*
37 * Warning:
38 * In order to not introduce confusion between Atmel PIO groups and pinctrl
39 * framework groups, Atmel PIO groups will be called banks, line is kept to
40 * designed the pin id into this bank.
41 */
42
43 #define ATMEL_PIO_MSKR 0x0000
44 #define ATMEL_PIO_CFGR 0x0004
45 #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
46 #define ATMEL_PIO_DIR_MASK BIT(8)
47 #define ATMEL_PIO_PUEN_MASK BIT(9)
48 #define ATMEL_PIO_PDEN_MASK BIT(10)
49 #define ATMEL_PIO_IFEN_MASK BIT(12)
50 #define ATMEL_PIO_IFSCEN_MASK BIT(13)
51 #define ATMEL_PIO_OPD_MASK BIT(14)
52 #define ATMEL_PIO_SCHMITT_MASK BIT(15)
53 #define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
54 #define ATMEL_PIO_DRVSTR_OFFSET 16
55 #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
56 #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
57 #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
58 #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
59 #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
60 #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
61 #define ATMEL_PIO_PDSR 0x0008
62 #define ATMEL_PIO_LOCKSR 0x000C
63 #define ATMEL_PIO_SODR 0x0010
64 #define ATMEL_PIO_CODR 0x0014
65 #define ATMEL_PIO_ODSR 0x0018
66 #define ATMEL_PIO_IER 0x0020
67 #define ATMEL_PIO_IDR 0x0024
68 #define ATMEL_PIO_IMR 0x0028
69 #define ATMEL_PIO_ISR 0x002C
70 #define ATMEL_PIO_IOFR 0x003C
71
72 #define ATMEL_PIO_NPINS_PER_BANK 32
73 #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
74 #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
75 #define ATMEL_PIO_BANK_OFFSET 0x40
76
77 #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
78 #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
79 #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
80
81 /* Custom pinconf parameters */
82 #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
83
84 struct atmel_pioctrl_data {
85 unsigned nbanks;
86 };
87
88 struct atmel_group {
89 const char *name;
90 u32 pin;
91 };
92
93 struct atmel_pin {
94 unsigned pin_id;
95 unsigned mux;
96 unsigned ioset;
97 unsigned bank;
98 unsigned line;
99 const char *device;
100 };
101
102 /**
103 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
104 * @reg_base: base address of the controller.
105 * @clk: clock of the controller.
106 * @nbanks: number of PIO groups, it can vary depending on the SoC.
107 * @pinctrl_dev: pinctrl device registered.
108 * @groups: groups table to provide group name and pin in the group to pinctrl.
109 * @group_names: group names table to provide all the group/pin names to
110 * pinctrl or gpio.
111 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
112 * fields are set at probe time. Other ones are set when parsing dt
113 * pinctrl.
114 * @npins: number of pins.
115 * @gpio_chip: gpio chip registered.
116 * @irq_domain: irq domain for the gpio controller.
117 * @irqs: table containing the hw irq number of the bank. The index of the
118 * table is the bank id.
119 * @dev: device entry for the Atmel PIO controller.
120 * @node: node of the Atmel PIO controller.
121 */
122 struct atmel_pioctrl {
123 void __iomem *reg_base;
124 struct clk *clk;
125 unsigned nbanks;
126 struct pinctrl_dev *pinctrl_dev;
127 struct atmel_group *groups;
128 const char * const *group_names;
129 struct atmel_pin **pins;
130 unsigned npins;
131 struct gpio_chip *gpio_chip;
132 struct irq_domain *irq_domain;
133 int *irqs;
134 unsigned *pm_wakeup_sources;
135 struct {
136 u32 imr;
137 u32 odsr;
138 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];
139 } *pm_suspend_backup;
140 struct device *dev;
141 struct device_node *node;
142 };
143
144 static const char * const atmel_functions[] = {
145 "GPIO", "A", "B", "C", "D", "E", "F", "G"
146 };
147
148 static const struct pinconf_generic_params atmel_custom_bindings[] = {
149 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
150 };
151
152 /* --- GPIO --- */
153 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
154 unsigned int bank, unsigned int reg)
155 {
156 return readl_relaxed(atmel_pioctrl->reg_base
157 + ATMEL_PIO_BANK_OFFSET * bank + reg);
158 }
159
160 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
161 unsigned int bank, unsigned int reg,
162 unsigned int val)
163 {
164 writel_relaxed(val, atmel_pioctrl->reg_base
165 + ATMEL_PIO_BANK_OFFSET * bank + reg);
166 }
167
168 static void atmel_gpio_irq_ack(struct irq_data *d)
169 {
170 /*
171 * Nothing to do, interrupt is cleared when reading the status
172 * register.
173 */
174 }
175
176 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
177 {
178 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
179 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
180 unsigned reg;
181
182 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
183 BIT(pin->line));
184 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
185 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
186
187 switch (type) {
188 case IRQ_TYPE_EDGE_RISING:
189 irq_set_handler_locked(d, handle_edge_irq);
190 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
191 break;
192 case IRQ_TYPE_EDGE_FALLING:
193 irq_set_handler_locked(d, handle_edge_irq);
194 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
195 break;
196 case IRQ_TYPE_EDGE_BOTH:
197 irq_set_handler_locked(d, handle_edge_irq);
198 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
199 break;
200 case IRQ_TYPE_LEVEL_LOW:
201 irq_set_handler_locked(d, handle_level_irq);
202 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
203 break;
204 case IRQ_TYPE_LEVEL_HIGH:
205 irq_set_handler_locked(d, handle_level_irq);
206 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
207 break;
208 case IRQ_TYPE_NONE:
209 default:
210 return -EINVAL;
211 }
212
213 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
214
215 return 0;
216 }
217
218 static void atmel_gpio_irq_mask(struct irq_data *d)
219 {
220 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
221 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
222
223 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
224 BIT(pin->line));
225 }
226
227 static void atmel_gpio_irq_unmask(struct irq_data *d)
228 {
229 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
230 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
231
232 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
233 BIT(pin->line));
234 }
235
236 #ifdef CONFIG_PM_SLEEP
237
238 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
239 {
240 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
241 int bank = ATMEL_PIO_BANK(d->hwirq);
242 int line = ATMEL_PIO_LINE(d->hwirq);
243
244 /* The gpio controller has one interrupt line per bank. */
245 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
246
247 if (on)
248 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
249 else
250 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
251
252 return 0;
253 }
254 #else
255 #define atmel_gpio_irq_set_wake NULL
256 #endif /* CONFIG_PM_SLEEP */
257
258 static struct irq_chip atmel_gpio_irq_chip = {
259 .name = "GPIO",
260 .irq_ack = atmel_gpio_irq_ack,
261 .irq_mask = atmel_gpio_irq_mask,
262 .irq_unmask = atmel_gpio_irq_unmask,
263 .irq_set_type = atmel_gpio_irq_set_type,
264 .irq_set_wake = atmel_gpio_irq_set_wake,
265 };
266
267 static void atmel_gpio_irq_handler(struct irq_desc *desc)
268 {
269 unsigned int irq = irq_desc_get_irq(desc);
270 struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
271 struct irq_chip *chip = irq_desc_get_chip(desc);
272 unsigned long isr;
273 int n, bank = -1;
274
275 /* Find from which bank is the irq received. */
276 for (n = 0; n < atmel_pioctrl->nbanks; n++) {
277 if (atmel_pioctrl->irqs[n] == irq) {
278 bank = n;
279 break;
280 }
281 }
282
283 if (bank < 0) {
284 dev_err(atmel_pioctrl->dev,
285 "no bank associated to irq %u\n", irq);
286 return;
287 }
288
289 chained_irq_enter(chip, desc);
290
291 for (;;) {
292 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
293 ATMEL_PIO_ISR);
294 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
295 ATMEL_PIO_IMR);
296 if (!isr)
297 break;
298
299 for_each_set_bit(n, &isr, BITS_PER_LONG)
300 generic_handle_irq(gpio_to_irq(bank *
301 ATMEL_PIO_NPINS_PER_BANK + n));
302 }
303
304 chained_irq_exit(chip, desc);
305 }
306
307 static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
308 {
309 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
310 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
311 unsigned reg;
312
313 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
314 BIT(pin->line));
315 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
316 reg &= ~ATMEL_PIO_DIR_MASK;
317 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
318
319 return 0;
320 }
321
322 static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
323 {
324 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
325 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
326 unsigned reg;
327
328 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
329
330 return !!(reg & BIT(pin->line));
331 }
332
333 static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
334 int value)
335 {
336 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
337 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
338 unsigned reg;
339
340 atmel_gpio_write(atmel_pioctrl, pin->bank,
341 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
342 BIT(pin->line));
343
344 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
345 BIT(pin->line));
346 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
347 reg |= ATMEL_PIO_DIR_MASK;
348 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
349
350 return 0;
351 }
352
353 static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
354 {
355 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
356 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
357
358 atmel_gpio_write(atmel_pioctrl, pin->bank,
359 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
360 BIT(pin->line));
361 }
362
363 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
364 {
365 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
366
367 return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
368 }
369
370 static struct gpio_chip atmel_gpio_chip = {
371 .direction_input = atmel_gpio_direction_input,
372 .get = atmel_gpio_get,
373 .direction_output = atmel_gpio_direction_output,
374 .set = atmel_gpio_set,
375 .to_irq = atmel_gpio_to_irq,
376 .base = 0,
377 };
378
379 /* --- PINCTRL --- */
380 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
381 unsigned pin_id)
382 {
383 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
384 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
385 unsigned line = atmel_pioctrl->pins[pin_id]->line;
386 void __iomem *addr = atmel_pioctrl->reg_base
387 + bank * ATMEL_PIO_BANK_OFFSET;
388
389 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
390 /* Have to set MSKR first, to access the right pin CFGR. */
391 wmb();
392
393 return readl_relaxed(addr + ATMEL_PIO_CFGR);
394 }
395
396 static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
397 unsigned pin_id, u32 conf)
398 {
399 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
400 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
401 unsigned line = atmel_pioctrl->pins[pin_id]->line;
402 void __iomem *addr = atmel_pioctrl->reg_base
403 + bank * ATMEL_PIO_BANK_OFFSET;
404
405 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
406 /* Have to set MSKR first, to access the right pin CFGR. */
407 wmb();
408 writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
409 }
410
411 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
412 {
413 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
414
415 return atmel_pioctrl->npins;
416 }
417
418 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
419 unsigned selector)
420 {
421 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
422
423 return atmel_pioctrl->groups[selector].name;
424 }
425
426 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
427 unsigned selector, const unsigned **pins,
428 unsigned *num_pins)
429 {
430 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
431
432 *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
433 *num_pins = 1;
434
435 return 0;
436 }
437
438 static struct atmel_group *
439 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
440 {
441 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
442 int i;
443
444 for (i = 0; i < atmel_pioctrl->npins; i++) {
445 struct atmel_group *grp = atmel_pioctrl->groups + i;
446
447 if (grp->pin == pin)
448 return grp;
449 }
450
451 return NULL;
452 }
453
454 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
455 struct device_node *np,
456 u32 pinfunc, const char **grp_name,
457 const char **func_name)
458 {
459 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
460 unsigned pin_id, func_id;
461 struct atmel_group *grp;
462
463 pin_id = ATMEL_GET_PIN_NO(pinfunc);
464 func_id = ATMEL_GET_PIN_FUNC(pinfunc);
465
466 if (func_id >= ARRAY_SIZE(atmel_functions))
467 return -EINVAL;
468
469 *func_name = atmel_functions[func_id];
470
471 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
472 if (!grp)
473 return -EINVAL;
474 *grp_name = grp->name;
475
476 atmel_pioctrl->pins[pin_id]->mux = func_id;
477 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
478 /* Want the device name not the group one. */
479 if (np->parent == atmel_pioctrl->node)
480 atmel_pioctrl->pins[pin_id]->device = np->name;
481 else
482 atmel_pioctrl->pins[pin_id]->device = np->parent->name;
483
484 return 0;
485 }
486
487 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
488 struct device_node *np,
489 struct pinctrl_map **map,
490 unsigned *reserved_maps,
491 unsigned *num_maps)
492 {
493 unsigned num_pins, num_configs, reserve;
494 unsigned long *configs;
495 struct property *pins;
496 u32 pinfunc;
497 int ret, i;
498
499 pins = of_find_property(np, "pinmux", NULL);
500 if (!pins)
501 return -EINVAL;
502
503 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
504 &num_configs);
505 if (ret < 0) {
506 dev_err(pctldev->dev, "%pOF: could not parse node property\n",
507 np);
508 return ret;
509 }
510
511 num_pins = pins->length / sizeof(u32);
512 if (!num_pins) {
513 dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
514 ret = -EINVAL;
515 goto exit;
516 }
517
518 /*
519 * Reserve maps, at least there is a mux map and an optional conf
520 * map for each pin.
521 */
522 reserve = 1;
523 if (num_configs)
524 reserve++;
525 reserve *= num_pins;
526 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
527 reserve);
528 if (ret < 0)
529 goto exit;
530
531 for (i = 0; i < num_pins; i++) {
532 const char *group, *func;
533
534 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
535 if (ret)
536 goto exit;
537
538 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
539 &func);
540 if (ret)
541 goto exit;
542
543 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
544 group, func);
545
546 if (num_configs) {
547 ret = pinctrl_utils_add_map_configs(pctldev, map,
548 reserved_maps, num_maps, group,
549 configs, num_configs,
550 PIN_MAP_TYPE_CONFIGS_GROUP);
551 if (ret < 0)
552 goto exit;
553 }
554 }
555
556 exit:
557 kfree(configs);
558 return ret;
559 }
560
561 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
562 struct device_node *np_config,
563 struct pinctrl_map **map,
564 unsigned *num_maps)
565 {
566 struct device_node *np;
567 unsigned reserved_maps;
568 int ret;
569
570 *map = NULL;
571 *num_maps = 0;
572 reserved_maps = 0;
573
574 /*
575 * If all the pins of a device have the same configuration (or no one),
576 * it is useless to add a subnode, so directly parse node referenced by
577 * phandle.
578 */
579 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
580 &reserved_maps, num_maps);
581 if (ret) {
582 for_each_child_of_node(np_config, np) {
583 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
584 &reserved_maps, num_maps);
585 if (ret < 0) {
586 of_node_put(np);
587 break;
588 }
589 }
590 }
591
592 if (ret < 0) {
593 pinctrl_utils_free_map(pctldev, *map, *num_maps);
594 dev_err(pctldev->dev, "can't create maps for node %pOF\n",
595 np_config);
596 }
597
598 return ret;
599 }
600
601 static const struct pinctrl_ops atmel_pctlops = {
602 .get_groups_count = atmel_pctl_get_groups_count,
603 .get_group_name = atmel_pctl_get_group_name,
604 .get_group_pins = atmel_pctl_get_group_pins,
605 .dt_node_to_map = atmel_pctl_dt_node_to_map,
606 .dt_free_map = pinctrl_utils_free_map,
607 };
608
609 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
610 {
611 return ARRAY_SIZE(atmel_functions);
612 }
613
614 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
615 unsigned selector)
616 {
617 return atmel_functions[selector];
618 }
619
620 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
621 unsigned selector,
622 const char * const **groups,
623 unsigned * const num_groups)
624 {
625 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
626
627 *groups = atmel_pioctrl->group_names;
628 *num_groups = atmel_pioctrl->npins;
629
630 return 0;
631 }
632
633 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
634 unsigned function,
635 unsigned group)
636 {
637 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
638 unsigned pin;
639 u32 conf;
640
641 dev_dbg(pctldev->dev, "enable function %s group %s\n",
642 atmel_functions[function], atmel_pioctrl->groups[group].name);
643
644 pin = atmel_pioctrl->groups[group].pin;
645 conf = atmel_pin_config_read(pctldev, pin);
646 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
647 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
648 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
649 atmel_pin_config_write(pctldev, pin, conf);
650
651 return 0;
652 }
653
654 static const struct pinmux_ops atmel_pmxops = {
655 .get_functions_count = atmel_pmx_get_functions_count,
656 .get_function_name = atmel_pmx_get_function_name,
657 .get_function_groups = atmel_pmx_get_function_groups,
658 .set_mux = atmel_pmx_set_mux,
659 };
660
661 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
662 unsigned group,
663 unsigned long *config)
664 {
665 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
666 unsigned param = pinconf_to_config_param(*config), arg = 0;
667 struct atmel_group *grp = atmel_pioctrl->groups + group;
668 unsigned pin_id = grp->pin;
669 u32 res;
670
671 res = atmel_pin_config_read(pctldev, pin_id);
672
673 switch (param) {
674 case PIN_CONFIG_BIAS_PULL_UP:
675 if (!(res & ATMEL_PIO_PUEN_MASK))
676 return -EINVAL;
677 arg = 1;
678 break;
679 case PIN_CONFIG_BIAS_PULL_DOWN:
680 if ((res & ATMEL_PIO_PUEN_MASK) ||
681 (!(res & ATMEL_PIO_PDEN_MASK)))
682 return -EINVAL;
683 arg = 1;
684 break;
685 case PIN_CONFIG_BIAS_DISABLE:
686 if ((res & ATMEL_PIO_PUEN_MASK) ||
687 ((res & ATMEL_PIO_PDEN_MASK)))
688 return -EINVAL;
689 arg = 1;
690 break;
691 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
692 if (!(res & ATMEL_PIO_OPD_MASK))
693 return -EINVAL;
694 arg = 1;
695 break;
696 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
697 if (!(res & ATMEL_PIO_SCHMITT_MASK))
698 return -EINVAL;
699 arg = 1;
700 break;
701 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
702 if (!(res & ATMEL_PIO_DRVSTR_MASK))
703 return -EINVAL;
704 arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
705 break;
706 default:
707 return -ENOTSUPP;
708 }
709
710 *config = pinconf_to_config_packed(param, arg);
711 return 0;
712 }
713
714 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
715 unsigned group,
716 unsigned long *configs,
717 unsigned num_configs)
718 {
719 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
720 struct atmel_group *grp = atmel_pioctrl->groups + group;
721 unsigned bank, pin, pin_id = grp->pin;
722 u32 mask, conf = 0;
723 int i;
724
725 conf = atmel_pin_config_read(pctldev, pin_id);
726
727 for (i = 0; i < num_configs; i++) {
728 unsigned param = pinconf_to_config_param(configs[i]);
729 unsigned arg = pinconf_to_config_argument(configs[i]);
730
731 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
732 __func__, pin_id, configs[i]);
733
734 switch (param) {
735 case PIN_CONFIG_BIAS_DISABLE:
736 conf &= (~ATMEL_PIO_PUEN_MASK);
737 conf &= (~ATMEL_PIO_PDEN_MASK);
738 break;
739 case PIN_CONFIG_BIAS_PULL_UP:
740 conf |= ATMEL_PIO_PUEN_MASK;
741 conf &= (~ATMEL_PIO_PDEN_MASK);
742 break;
743 case PIN_CONFIG_BIAS_PULL_DOWN:
744 conf |= ATMEL_PIO_PDEN_MASK;
745 conf &= (~ATMEL_PIO_PUEN_MASK);
746 break;
747 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
748 if (arg == 0)
749 conf &= (~ATMEL_PIO_OPD_MASK);
750 else
751 conf |= ATMEL_PIO_OPD_MASK;
752 break;
753 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
754 if (arg == 0)
755 conf |= ATMEL_PIO_SCHMITT_MASK;
756 else
757 conf &= (~ATMEL_PIO_SCHMITT_MASK);
758 break;
759 case PIN_CONFIG_INPUT_DEBOUNCE:
760 if (arg == 0) {
761 conf &= (~ATMEL_PIO_IFEN_MASK);
762 conf &= (~ATMEL_PIO_IFSCEN_MASK);
763 } else {
764 /*
765 * We don't care about the debounce value for several reasons:
766 * - can't have different debounce periods inside a same group,
767 * - the register to configure this period is a secure register.
768 * The debouncing filter can filter a pulse with a duration of less
769 * than 1/2 slow clock period.
770 */
771 conf |= ATMEL_PIO_IFEN_MASK;
772 conf |= ATMEL_PIO_IFSCEN_MASK;
773 }
774 break;
775 case PIN_CONFIG_OUTPUT:
776 conf |= ATMEL_PIO_DIR_MASK;
777 bank = ATMEL_PIO_BANK(pin_id);
778 pin = ATMEL_PIO_LINE(pin_id);
779 mask = 1 << pin;
780
781 if (arg == 0) {
782 writel_relaxed(mask, atmel_pioctrl->reg_base +
783 bank * ATMEL_PIO_BANK_OFFSET +
784 ATMEL_PIO_CODR);
785 } else {
786 writel_relaxed(mask, atmel_pioctrl->reg_base +
787 bank * ATMEL_PIO_BANK_OFFSET +
788 ATMEL_PIO_SODR);
789 }
790 break;
791 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
792 switch (arg) {
793 case ATMEL_PIO_DRVSTR_LO:
794 case ATMEL_PIO_DRVSTR_ME:
795 case ATMEL_PIO_DRVSTR_HI:
796 conf &= (~ATMEL_PIO_DRVSTR_MASK);
797 conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
798 break;
799 default:
800 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
801 }
802 break;
803 default:
804 dev_warn(pctldev->dev,
805 "unsupported configuration parameter: %u\n",
806 param);
807 continue;
808 }
809 }
810
811 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
812 atmel_pin_config_write(pctldev, pin_id, conf);
813
814 return 0;
815 }
816
817 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
818 struct seq_file *s, unsigned pin_id)
819 {
820 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
821 u32 conf;
822
823 if (!atmel_pioctrl->pins[pin_id]->device)
824 return;
825
826 if (atmel_pioctrl->pins[pin_id])
827 seq_printf(s, " (%s, ioset %u) ",
828 atmel_pioctrl->pins[pin_id]->device,
829 atmel_pioctrl->pins[pin_id]->ioset);
830
831 conf = atmel_pin_config_read(pctldev, pin_id);
832 if (conf & ATMEL_PIO_PUEN_MASK)
833 seq_printf(s, "%s ", "pull-up");
834 if (conf & ATMEL_PIO_PDEN_MASK)
835 seq_printf(s, "%s ", "pull-down");
836 if (conf & ATMEL_PIO_IFEN_MASK)
837 seq_printf(s, "%s ", "debounce");
838 if (conf & ATMEL_PIO_OPD_MASK)
839 seq_printf(s, "%s ", "open-drain");
840 if (conf & ATMEL_PIO_SCHMITT_MASK)
841 seq_printf(s, "%s ", "schmitt");
842 if (conf & ATMEL_PIO_DRVSTR_MASK) {
843 switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
844 case ATMEL_PIO_DRVSTR_ME:
845 seq_printf(s, "%s ", "medium-drive");
846 break;
847 case ATMEL_PIO_DRVSTR_HI:
848 seq_printf(s, "%s ", "high-drive");
849 break;
850 /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
851 default:
852 seq_printf(s, "%s ", "low-drive");
853 }
854 }
855 }
856
857 static const struct pinconf_ops atmel_confops = {
858 .pin_config_group_get = atmel_conf_pin_config_group_get,
859 .pin_config_group_set = atmel_conf_pin_config_group_set,
860 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
861 };
862
863 static struct pinctrl_desc atmel_pinctrl_desc = {
864 .name = "atmel_pinctrl",
865 .confops = &atmel_confops,
866 .pctlops = &atmel_pctlops,
867 .pmxops = &atmel_pmxops,
868 };
869
870 static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
871 {
872 struct platform_device *pdev = to_platform_device(dev);
873 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
874 int i, j;
875
876 /*
877 * For each bank, save IMR to restore it later and disable all GPIO
878 * interrupts excepting the ones marked as wakeup sources.
879 */
880 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
881 atmel_pioctrl->pm_suspend_backup[i].imr =
882 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
883 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
884 ~atmel_pioctrl->pm_wakeup_sources[i]);
885 atmel_pioctrl->pm_suspend_backup[i].odsr =
886 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
887 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
888 atmel_gpio_write(atmel_pioctrl, i,
889 ATMEL_PIO_MSKR, BIT(j));
890 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
891 atmel_gpio_read(atmel_pioctrl, i,
892 ATMEL_PIO_CFGR);
893 }
894 }
895
896 return 0;
897 }
898
899 static int __maybe_unused atmel_pctrl_resume(struct device *dev)
900 {
901 struct platform_device *pdev = to_platform_device(dev);
902 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
903 int i, j;
904
905 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
906 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
907 atmel_pioctrl->pm_suspend_backup[i].imr);
908 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
909 atmel_pioctrl->pm_suspend_backup[i].odsr);
910 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
911 atmel_gpio_write(atmel_pioctrl, i,
912 ATMEL_PIO_MSKR, BIT(j));
913 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
914 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
915 }
916 }
917
918 return 0;
919 }
920
921 static const struct dev_pm_ops atmel_pctrl_pm_ops = {
922 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
923 };
924
925 /*
926 * The number of banks can be different from a SoC to another one.
927 * We can have up to 16 banks.
928 */
929 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
930 .nbanks = 4,
931 };
932
933 static const struct of_device_id atmel_pctrl_of_match[] = {
934 {
935 .compatible = "atmel,sama5d2-pinctrl",
936 .data = &atmel_sama5d2_pioctrl_data,
937 }, {
938 /* sentinel */
939 }
940 };
941
942 static int atmel_pinctrl_probe(struct platform_device *pdev)
943 {
944 struct device *dev = &pdev->dev;
945 struct pinctrl_pin_desc *pin_desc;
946 const char **group_names;
947 const struct of_device_id *match;
948 int i, ret;
949 struct resource *res;
950 struct atmel_pioctrl *atmel_pioctrl;
951 const struct atmel_pioctrl_data *atmel_pioctrl_data;
952
953 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
954 if (!atmel_pioctrl)
955 return -ENOMEM;
956 atmel_pioctrl->dev = dev;
957 atmel_pioctrl->node = dev->of_node;
958 platform_set_drvdata(pdev, atmel_pioctrl);
959
960 match = of_match_node(atmel_pctrl_of_match, dev->of_node);
961 if (!match) {
962 dev_err(dev, "unknown compatible string\n");
963 return -ENODEV;
964 }
965 atmel_pioctrl_data = match->data;
966 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
967 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
968
969 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
970 atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res);
971 if (IS_ERR(atmel_pioctrl->reg_base))
972 return -EINVAL;
973
974 atmel_pioctrl->clk = devm_clk_get(dev, NULL);
975 if (IS_ERR(atmel_pioctrl->clk)) {
976 dev_err(dev, "failed to get clock\n");
977 return PTR_ERR(atmel_pioctrl->clk);
978 }
979
980 atmel_pioctrl->pins = devm_kcalloc(dev,
981 atmel_pioctrl->npins,
982 sizeof(*atmel_pioctrl->pins),
983 GFP_KERNEL);
984 if (!atmel_pioctrl->pins)
985 return -ENOMEM;
986
987 pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
988 GFP_KERNEL);
989 if (!pin_desc)
990 return -ENOMEM;
991 atmel_pinctrl_desc.pins = pin_desc;
992 atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
993 atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
994 atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
995
996 /* One pin is one group since a pin can achieve all functions. */
997 group_names = devm_kcalloc(dev,
998 atmel_pioctrl->npins, sizeof(*group_names),
999 GFP_KERNEL);
1000 if (!group_names)
1001 return -ENOMEM;
1002 atmel_pioctrl->group_names = group_names;
1003
1004 atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
1005 atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
1006 GFP_KERNEL);
1007 if (!atmel_pioctrl->groups)
1008 return -ENOMEM;
1009 for (i = 0 ; i < atmel_pioctrl->npins; i++) {
1010 struct atmel_group *group = atmel_pioctrl->groups + i;
1011 unsigned bank = ATMEL_PIO_BANK(i);
1012 unsigned line = ATMEL_PIO_LINE(i);
1013
1014 atmel_pioctrl->pins[i] = devm_kzalloc(dev,
1015 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
1016 if (!atmel_pioctrl->pins[i])
1017 return -ENOMEM;
1018
1019 atmel_pioctrl->pins[i]->pin_id = i;
1020 atmel_pioctrl->pins[i]->bank = bank;
1021 atmel_pioctrl->pins[i]->line = line;
1022
1023 pin_desc[i].number = i;
1024 /* Pin naming convention: P(bank_name)(bank_pin_number). */
1025 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
1026 bank + 'A', line);
1027
1028 group->name = group_names[i] = pin_desc[i].name;
1029 group->pin = pin_desc[i].number;
1030
1031 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
1032 }
1033
1034 atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
1035 atmel_pioctrl->gpio_chip->of_node = dev->of_node;
1036 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
1037 atmel_pioctrl->gpio_chip->label = dev_name(dev);
1038 atmel_pioctrl->gpio_chip->parent = dev;
1039 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
1040
1041 atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
1042 atmel_pioctrl->nbanks,
1043 sizeof(*atmel_pioctrl->pm_wakeup_sources),
1044 GFP_KERNEL);
1045 if (!atmel_pioctrl->pm_wakeup_sources)
1046 return -ENOMEM;
1047
1048 atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
1049 atmel_pioctrl->nbanks,
1050 sizeof(*atmel_pioctrl->pm_suspend_backup),
1051 GFP_KERNEL);
1052 if (!atmel_pioctrl->pm_suspend_backup)
1053 return -ENOMEM;
1054
1055 atmel_pioctrl->irqs = devm_kcalloc(dev,
1056 atmel_pioctrl->nbanks,
1057 sizeof(*atmel_pioctrl->irqs),
1058 GFP_KERNEL);
1059 if (!atmel_pioctrl->irqs)
1060 return -ENOMEM;
1061
1062 /* There is one controller but each bank has its own irq line. */
1063 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1064 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1065 if (!res) {
1066 dev_err(dev, "missing irq resource for group %c\n",
1067 'A' + i);
1068 return -EINVAL;
1069 }
1070 atmel_pioctrl->irqs[i] = res->start;
1071 irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
1072 irq_set_handler_data(res->start, atmel_pioctrl);
1073 dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
1074 }
1075
1076 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1077 atmel_pioctrl->gpio_chip->ngpio,
1078 &irq_domain_simple_ops, NULL);
1079 if (!atmel_pioctrl->irq_domain) {
1080 dev_err(dev, "can't add the irq domain\n");
1081 return -ENODEV;
1082 }
1083 atmel_pioctrl->irq_domain->name = "atmel gpio";
1084
1085 for (i = 0; i < atmel_pioctrl->npins; i++) {
1086 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1087
1088 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1089 handle_simple_irq);
1090 irq_set_chip_data(irq, atmel_pioctrl);
1091 dev_dbg(dev,
1092 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1093 i, irq);
1094 }
1095
1096 ret = clk_prepare_enable(atmel_pioctrl->clk);
1097 if (ret) {
1098 dev_err(dev, "failed to prepare and enable clock\n");
1099 goto clk_prepare_enable_error;
1100 }
1101
1102 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
1103 &atmel_pinctrl_desc,
1104 atmel_pioctrl);
1105 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
1106 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
1107 dev_err(dev, "pinctrl registration failed\n");
1108 goto clk_unprep;
1109 }
1110
1111 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
1112 if (ret) {
1113 dev_err(dev, "failed to add gpiochip\n");
1114 goto clk_unprep;
1115 }
1116
1117 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1118 0, 0, atmel_pioctrl->gpio_chip->ngpio);
1119 if (ret) {
1120 dev_err(dev, "failed to add gpio pin range\n");
1121 goto gpiochip_add_pin_range_error;
1122 }
1123
1124 dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1125
1126 return 0;
1127
1128 gpiochip_add_pin_range_error:
1129 gpiochip_remove(atmel_pioctrl->gpio_chip);
1130
1131 clk_unprep:
1132 clk_disable_unprepare(atmel_pioctrl->clk);
1133
1134 clk_prepare_enable_error:
1135 irq_domain_remove(atmel_pioctrl->irq_domain);
1136
1137 return ret;
1138 }
1139
1140 static struct platform_driver atmel_pinctrl_driver = {
1141 .driver = {
1142 .name = "pinctrl-at91-pio4",
1143 .of_match_table = atmel_pctrl_of_match,
1144 .pm = &atmel_pctrl_pm_ops,
1145 .suppress_bind_attrs = true,
1146 },
1147 .probe = atmel_pinctrl_probe,
1148 };
1149 builtin_platform_driver(atmel_pinctrl_driver);
Linux with added FPC-III support