| blob | 3ea133cfb241a3dfe2533ef6f04c1066bf021503 |
1 /*
2 * R8A7796 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2016-2017 Renesas Electronics Corp.
5 *
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
7 *
8 * R-Car Gen3 processor support - PFC hardware block.
9 *
10 * Copyright (C) 2015 Renesas Electronics Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 */
17 #include <linux/kernel.h>
22 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
23 SH_PFC_PIN_CFG_PULL_UP | \
24 SH_PFC_PIN_CFG_PULL_DOWN)
26 #define CPU_ALL_PORT(fn, sfx) \
27 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
36 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
39 /*
40 * F_() : just information
41 * FM() : macro for FN_xxx / xxx_MARK
42 */
44 /* GPSR0 */
45 #define GPSR0_15 F_(D15, IP7_11_8)
46 #define GPSR0_14 F_(D14, IP7_7_4)
47 #define GPSR0_13 F_(D13, IP7_3_0)
48 #define GPSR0_12 F_(D12, IP6_31_28)
49 #define GPSR0_11 F_(D11, IP6_27_24)
50 #define GPSR0_10 F_(D10, IP6_23_20)
51 #define GPSR0_9 F_(D9, IP6_19_16)
52 #define GPSR0_8 F_(D8, IP6_15_12)
53 #define GPSR0_7 F_(D7, IP6_11_8)
54 #define GPSR0_6 F_(D6, IP6_7_4)
55 #define GPSR0_5 F_(D5, IP6_3_0)
56 #define GPSR0_4 F_(D4, IP5_31_28)
57 #define GPSR0_3 F_(D3, IP5_27_24)
58 #define GPSR0_2 F_(D2, IP5_23_20)
59 #define GPSR0_1 F_(D1, IP5_19_16)
60 #define GPSR0_0 F_(D0, IP5_15_12)
62 /* GPSR1 */
63 #define GPSR1_28 FM(CLKOUT)
64 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
65 #define GPSR1_26 F_(WE1_N, IP5_7_4)
66 #define GPSR1_25 F_(WE0_N, IP5_3_0)
67 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
68 #define GPSR1_23 F_(RD_N, IP4_27_24)
69 #define GPSR1_22 F_(BS_N, IP4_23_20)
70 #define GPSR1_21 F_(CS1_N, IP4_19_16)
71 #define GPSR1_20 F_(CS0_N, IP4_15_12)
72 #define GPSR1_19 F_(A19, IP4_11_8)
73 #define GPSR1_18 F_(A18, IP4_7_4)
74 #define GPSR1_17 F_(A17, IP4_3_0)
75 #define GPSR1_16 F_(A16, IP3_31_28)
76 #define GPSR1_15 F_(A15, IP3_27_24)
77 #define GPSR1_14 F_(A14, IP3_23_20)
78 #define GPSR1_13 F_(A13, IP3_19_16)
79 #define GPSR1_12 F_(A12, IP3_15_12)
80 #define GPSR1_11 F_(A11, IP3_11_8)
81 #define GPSR1_10 F_(A10, IP3_7_4)
82 #define GPSR1_9 F_(A9, IP3_3_0)
83 #define GPSR1_8 F_(A8, IP2_31_28)
84 #define GPSR1_7 F_(A7, IP2_27_24)
85 #define GPSR1_6 F_(A6, IP2_23_20)
86 #define GPSR1_5 F_(A5, IP2_19_16)
87 #define GPSR1_4 F_(A4, IP2_15_12)
88 #define GPSR1_3 F_(A3, IP2_11_8)
89 #define GPSR1_2 F_(A2, IP2_7_4)
90 #define GPSR1_1 F_(A1, IP2_3_0)
91 #define GPSR1_0 F_(A0, IP1_31_28)
93 /* GPSR2 */
94 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
95 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
96 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
97 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
98 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
99 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
100 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
101 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
102 #define GPSR2_6 F_(PWM0, IP1_19_16)
103 #define GPSR2_5 F_(IRQ5, IP1_15_12)
104 #define GPSR2_4 F_(IRQ4, IP1_11_8)
105 #define GPSR2_3 F_(IRQ3, IP1_7_4)
106 #define GPSR2_2 F_(IRQ2, IP1_3_0)
107 #define GPSR2_1 F_(IRQ1, IP0_31_28)
108 #define GPSR2_0 F_(IRQ0, IP0_27_24)
110 /* GPSR3 */
111 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
112 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
113 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
114 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
115 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
116 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
117 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
118 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
119 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
120 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
121 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
122 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
123 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
124 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
125 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
126 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
128 /* GPSR4 */
129 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
130 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
131 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
132 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
133 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
134 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
135 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
136 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
137 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
138 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
139 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
140 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
141 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
142 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
143 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
144 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
145 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
146 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
148 /* GPSR5 */
149 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
150 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
151 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
152 #define GPSR5_22 FM(MSIOF0_RXD)
153 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
154 #define GPSR5_20 FM(MSIOF0_TXD)
155 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
156 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
157 #define GPSR5_17 FM(MSIOF0_SCK)
158 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
159 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
160 #define GPSR5_14 F_(HTX0, IP13_19_16)
161 #define GPSR5_13 F_(HRX0, IP13_15_12)
162 #define GPSR5_12 F_(HSCK0, IP13_11_8)
163 #define GPSR5_11 F_(RX2_A, IP13_7_4)
164 #define GPSR5_10 F_(TX2_A, IP13_3_0)
165 #define GPSR5_9 F_(SCK2, IP12_31_28)
166 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
167 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
168 #define GPSR5_6 F_(TX1_A, IP12_19_16)
169 #define GPSR5_5 F_(RX1_A, IP12_15_12)
170 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
171 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
172 #define GPSR5_2 F_(TX0, IP12_3_0)
173 #define GPSR5_1 F_(RX0, IP11_31_28)
174 #define GPSR5_0 F_(SCK0, IP11_27_24)
176 /* GPSR6 */
177 #define GPSR6_31 F_(GP6_31, IP18_7_4)
178 #define GPSR6_30 F_(GP6_30, IP18_3_0)
179 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
180 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
181 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
182 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
183 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
184 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
185 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
186 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
187 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
188 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
189 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
190 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
191 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
192 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
193 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
194 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
195 #define GPSR6_13 FM(SSI_SDATA5)
196 #define GPSR6_12 FM(SSI_WS5)
197 #define GPSR6_11 FM(SSI_SCK5)
198 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
199 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
200 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
201 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
202 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
203 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
204 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
205 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
206 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
207 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
208 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
210 /* GPSR7 */
211 #define GPSR7_3 FM(GP7_03)
212 #define GPSR7_2 FM(HDMI0_CEC)
213 #define GPSR7_1 FM(AVS2)
214 #define GPSR7_0 FM(AVS1)
217 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
218 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
247 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
278 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
314 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
335 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
344 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
364 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
365 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
366 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
367 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
368 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
370 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
372 #define PINMUX_GPSR \
373 \
374 GPSR6_31 \
375 GPSR6_30 \
376 GPSR6_29 \
377 GPSR1_28 GPSR6_28 \
378 GPSR1_27 GPSR6_27 \
379 GPSR1_26 GPSR6_26 \
380 GPSR1_25 GPSR5_25 GPSR6_25 \
381 GPSR1_24 GPSR5_24 GPSR6_24 \
382 GPSR1_23 GPSR5_23 GPSR6_23 \
383 GPSR1_22 GPSR5_22 GPSR6_22 \
384 GPSR1_21 GPSR5_21 GPSR6_21 \
385 GPSR1_20 GPSR5_20 GPSR6_20 \
386 GPSR1_19 GPSR5_19 GPSR6_19 \
387 GPSR1_18 GPSR5_18 GPSR6_18 \
388 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
389 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
390 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
391 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
392 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
393 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
394 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
395 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
396 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
397 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
398 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
399 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
400 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
401 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
402 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
403 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
404 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
405 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
407 #define PINMUX_IPSR \
408 \
409 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
410 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
411 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
412 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
413 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
414 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
415 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
416 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
417 \
418 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
419 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
420 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
421 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
422 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
423 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
424 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
425 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
426 \
427 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
428 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
429 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
430 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
431 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
432 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
433 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
434 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
435 \
436 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
437 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
438 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
439 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
440 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
441 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
442 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
443 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
444 \
445 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
446 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
447 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
448 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
449 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
450 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
451 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
452 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
455 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
456 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
457 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
458 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
459 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
460 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
461 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
462 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
463 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
464 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
465 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
466 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
467 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
468 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
469 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
470 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
471 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
472 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
475 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
476 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
477 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
478 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
479 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
480 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
481 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
482 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
483 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
484 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
485 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
486 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
487 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
488 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
489 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
490 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
491 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
492 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
493 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
494 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
495 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
496 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
499 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
500 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
501 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
502 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
503 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
504 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
505 #define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
506 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
507 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
508 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
509 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
510 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
511 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
513 #define PINMUX_MOD_SELS \
514 \
515 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
516 MOD_SEL2_30 \
517 MOD_SEL1_29_28_27 MOD_SEL2_29 \
518 MOD_SEL0_28_27 MOD_SEL2_28_27 \
519 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
520 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
521 MOD_SEL0_23 MOD_SEL1_23_22_21 \
522 MOD_SEL0_22 MOD_SEL2_22 \
523 MOD_SEL0_21 MOD_SEL2_21 \
524 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
525 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
526 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
527 MOD_SEL2_17 \
528 MOD_SEL0_16 MOD_SEL1_16 \
529 MOD_SEL1_15_14 \
530 MOD_SEL0_14_13 \
531 MOD_SEL1_13 \
532 MOD_SEL0_12 MOD_SEL1_12 \
533 MOD_SEL0_11 MOD_SEL1_11 \
534 MOD_SEL0_10 MOD_SEL1_10 \
535 MOD_SEL0_9_8 MOD_SEL1_9 \
536 MOD_SEL0_7_6 \
537 MOD_SEL1_6 \
538 MOD_SEL0_5 MOD_SEL1_5 \
539 MOD_SEL0_4_3 MOD_SEL1_4 \
540 MOD_SEL1_3 \
541 MOD_SEL1_2 \
542 MOD_SEL1_1 \
543 MOD_SEL1_0 MOD_SEL2_0
545 /*
546 * These pins are not able to be muxed but have other properties
547 * that can be set, such as drive-strength or pull-up/pull-down enable.
548 */
549 #define PINMUX_STATIC \
550 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
551 FM(QSPI0_IO2) FM(QSPI0_IO3) \
552 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
553 FM(QSPI1_IO2) FM(QSPI1_IO3) \
554 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
555 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
556 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
557 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
558 FM(PRESETOUT) \
559 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
560 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
565 PINMUX_DATA_BEGIN,
567 PINMUX_DATA_END,
569 #define F_(x, y)
570 #define FM(x) FN_##x,
571 PINMUX_FUNCTION_BEGIN,
573 PINMUX_GPSR
574 PINMUX_IPSR
575 PINMUX_MOD_SELS
576 PINMUX_FUNCTION_END,
577 #undef F_
578 #undef FM
580 #define F_(x, y)
581 #define FM(x) x##_MARK,
582 PINMUX_MARK_BEGIN,
583 PINMUX_GPSR
584 PINMUX_IPSR
585 PINMUX_MOD_SELS
586 PINMUX_STATIC
587 PINMUX_MARK_END,
588 #undef F_
589 #undef FM
590 };
607 /* IPSR0 */
647 /* IPSR1 */
697 /* IPSR2 */
758 /* IPSR3 */
812 /* IPSR4 */
858 /* IPSR5 */
908 /* IPSR6 */
960 /* IPSR7 */
1002 /* IPSR8 */
1051 /* IPSR9 */
1076 /* IPSR10 */
1104 /* IPSR11 */
1146 /* IPSR12 */
1207 /* IPSR13 */
1267 /* IPSR14 */
1308 /* IPSR15 */
1355 /* IPSR16 */
1407 /* IPSR17 */
1474 /* IPSR18 */
1495 /* I2C */
1500 /*
1501 * Static pins can not be muxed between different functions but
1502 * still need mark entries in the pinmux list. Add each static
1503 * pin to the list without an associated function. The sh-pfc
1504 * core will do the right thing and skip trying to mux the pin
1505 * while still applying configuration to it.
1506 */
1507 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1508 PINMUX_STATIC
1509 #undef FM
1510 };
1512 /*
1513 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1514 * Physical layout rows: A - AW, cols: 1 - 39.
1515 */
1518 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1519 #define PIN_NONE U16_MAX
1524 /*
1525 * Pins not associated with a GPIO port.
1526 *
1527 * The pin positions are different between different r8a7796
1528 * packages, all that is needed for the pfc driver is a unique
1529 * number for each pin. To this end use the pin layout from
1530 * R-Car M3SiP to calculate a unique number for each pin.
1531 */
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574 };
1576 /* - AUDIO CLOCK ------------------------------------------------------------ */
1578 /* CLK A */
1580 };
1582 AUDIO_CLKA_A_MARK,
1583 };
1585 /* CLK A */
1587 };
1589 AUDIO_CLKA_B_MARK,
1590 };
1592 /* CLK A */
1594 };
1596 AUDIO_CLKA_C_MARK,
1597 };
1599 /* CLK B */
1601 };
1603 AUDIO_CLKB_A_MARK,
1604 };
1606 /* CLK B */
1608 };
1610 AUDIO_CLKB_B_MARK,
1611 };
1613 /* CLK C */
1615 };
1617 AUDIO_CLKC_A_MARK,
1618 };
1620 /* CLK C */
1622 };
1624 AUDIO_CLKC_B_MARK,
1625 };
1627 /* CLKOUT */
1629 };
1631 AUDIO_CLKOUT_A_MARK,
1632 };
1634 /* CLKOUT */
1636 };
1638 AUDIO_CLKOUT_B_MARK,
1639 };
1641 /* CLKOUT */
1643 };
1645 AUDIO_CLKOUT_C_MARK,
1646 };
1648 /* CLKOUT */
1650 };
1652 AUDIO_CLKOUT_D_MARK,
1653 };
1655 /* CLKOUT1 */
1657 };
1659 AUDIO_CLKOUT1_A_MARK,
1660 };
1662 /* CLKOUT1 */
1664 };
1666 AUDIO_CLKOUT1_B_MARK,
1667 };
1669 /* CLKOUT2 */
1671 };
1673 AUDIO_CLKOUT2_A_MARK,
1674 };
1676 /* CLKOUT2 */
1678 };
1680 AUDIO_CLKOUT2_B_MARK,
1681 };
1684 /* CLKOUT3 */
1686 };
1688 AUDIO_CLKOUT3_A_MARK,
1689 };
1691 /* CLKOUT3 */
1693 };
1695 AUDIO_CLKOUT3_B_MARK,
1696 };
1698 /* - EtherAVB --------------------------------------------------------------- */
1700 /* AVB_LINK */
1702 };
1704 AVB_LINK_MARK,
1705 };
1707 /* AVB_MAGIC_ */
1709 };
1711 AVB_MAGIC_MARK,
1712 };
1714 /* AVB_PHY_INT */
1716 };
1718 AVB_PHY_INT_MARK,
1719 };
1721 /* AVB_MDC, AVB_MDIO */
1723 };
1726 };
1728 /*
1729 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1730 * AVB_TD1, AVB_TD2, AVB_TD3,
1731 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1732 * AVB_RD1, AVB_RD2, AVB_RD3,
1733 * AVB_TXCREFCLK
1734 */
1741 };
1747 AVB_TXCREFCLK_MARK,
1748 };
1750 /* AVB_AVTP_PPS */
1752 };
1754 AVB_AVTP_PPS_MARK,
1755 };
1757 /* AVB_AVTP_MATCH_A */
1759 };
1761 AVB_AVTP_MATCH_A_MARK,
1762 };
1764 /* AVB_AVTP_CAPTURE_A */
1766 };
1768 AVB_AVTP_CAPTURE_A_MARK,
1769 };
1771 /* AVB_AVTP_MATCH_B */
1773 };
1775 AVB_AVTP_MATCH_B_MARK,
1776 };
1778 /* AVB_AVTP_CAPTURE_B */
1780 };
1782 AVB_AVTP_CAPTURE_B_MARK,
1783 };
1785 /* - CAN ------------------------------------------------------------------ */
1787 /* TX, RX */
1789 };
1792 };
1794 /* TX, RX */
1796 };
1799 };
1801 /* TX, RX */
1803 };
1806 };
1808 /* - CAN Clock -------------------------------------------------------------- */
1810 /* CLK */
1812 };
1814 CAN_CLK_MARK,
1815 };
1817 /* - CAN FD --------------------------------------------------------------- */
1819 /* TX, RX */
1821 };
1824 };
1826 /* TX, RX */
1828 };
1831 };
1833 /* TX, RX */
1835 };
1838 };
1840 /* - DRIF0 --------------------------------------------------------------- */
1842 /* CLK, SYNC */
1844 };
1847 };
1849 /* D0 */
1851 };
1853 RIF0_D0_A_MARK,
1854 };
1856 /* D1 */
1858 };
1860 RIF0_D1_A_MARK,
1861 };
1863 /* CLK, SYNC */
1865 };
1868 };
1870 /* D0 */
1872 };
1874 RIF0_D0_B_MARK,
1875 };
1877 /* D1 */
1879 };
1881 RIF0_D1_B_MARK,
1882 };
1884 /* CLK, SYNC */
1886 };
1889 };
1891 /* D0 */
1893 };
1895 RIF0_D0_C_MARK,
1896 };
1898 /* D1 */
1900 };
1902 RIF0_D1_C_MARK,
1903 };
1904 /* - DRIF1 --------------------------------------------------------------- */
1906 /* CLK, SYNC */
1908 };
1911 };
1913 /* D0 */
1915 };
1917 RIF1_D0_A_MARK,
1918 };
1920 /* D1 */
1922 };
1924 RIF1_D1_A_MARK,
1925 };
1927 /* CLK, SYNC */
1929 };
1932 };
1934 /* D0 */
1936 };
1938 RIF1_D0_B_MARK,
1939 };
1941 /* D1 */
1943 };
1945 RIF1_D1_B_MARK,
1946 };
1948 /* CLK, SYNC */
1950 };
1953 };
1955 /* D0 */
1957 };
1959 RIF1_D0_C_MARK,
1960 };
1962 /* D1 */
1964 };
1966 RIF1_D1_C_MARK,
1967 };
1968 /* - DRIF2 --------------------------------------------------------------- */
1970 /* CLK, SYNC */
1972 };
1975 };
1977 /* D0 */
1979 };
1981 RIF2_D0_A_MARK,
1982 };
1984 /* D1 */
1986 };
1988 RIF2_D1_A_MARK,
1989 };
1991 /* CLK, SYNC */
1993 };
1996 };
1998 /* D0 */
2000 };
2002 RIF2_D0_B_MARK,
2003 };
2005 /* D1 */
2007 };
2009 RIF2_D1_B_MARK,
2010 };
2011 /* - DRIF3 --------------------------------------------------------------- */
2013 /* CLK, SYNC */
2015 };
2018 };
2020 /* D0 */
2022 };
2024 RIF3_D0_A_MARK,
2025 };
2027 /* D1 */
2029 };
2031 RIF3_D1_A_MARK,
2032 };
2034 /* CLK, SYNC */
2036 };
2039 };
2041 /* D0 */
2043 };
2045 RIF3_D0_B_MARK,
2046 };
2048 /* D1 */
2050 };
2052 RIF3_D1_B_MARK,
2053 };
2055 /* - DU --------------------------------------------------------------------- */
2057 /* R[7:2], G[7:2], B[7:2] */
2064 };
2072 };
2074 /* R[7:0], G[7:0], B[7:0] */
2084 };
2092 };
2094 /* CLKOUT */
2096 };
2098 DU_DOTCLKOUT0_MARK
2099 };
2101 /* CLKOUT */
2103 };
2105 DU_DOTCLKOUT1_MARK
2106 };
2108 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2110 };
2112 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2113 };
2115 /* EXDISP/EXODDF/EXCDE */
2117 };
2119 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2120 };
2122 /* CDE */
2124 };
2126 DU_CDE_MARK,
2127 };
2129 /* DISP */
2131 };
2133 DU_DISP_MARK,
2134 };
2136 /* - HDMI ------------------------------------------------------------------- */
2138 /* HDMI0_CEC */
2140 };
2142 HDMI0_CEC_MARK,
2143 };
2145 /* - HSCIF0 ----------------------------------------------------------------- */
2147 /* RX, TX */
2149 };
2152 };
2154 /* SCK */
2156 };
2158 HSCK0_MARK,
2159 };
2161 /* RTS, CTS */
2163 };
2166 };
2167 /* - HSCIF1 ----------------------------------------------------------------- */
2169 /* RX, TX */
2171 };
2174 };
2176 /* SCK */
2178 };
2180 HSCK1_A_MARK,
2181 };
2183 /* RTS, CTS */
2185 };
2188 };
2191 /* RX, TX */
2193 };
2196 };
2198 /* SCK */
2200 };
2202 HSCK1_B_MARK,
2203 };
2205 /* RTS, CTS */
2207 };
2210 };
2211 /* - HSCIF2 ----------------------------------------------------------------- */
2213 /* RX, TX */
2215 };
2218 };
2220 /* SCK */
2222 };
2224 HSCK2_A_MARK,
2225 };
2227 /* RTS, CTS */
2229 };
2232 };
2235 /* RX, TX */
2237 };
2240 };
2242 /* SCK */
2244 };
2246 HSCK2_B_MARK,
2247 };
2249 /* RTS, CTS */
2251 };
2254 };
2257 /* RX, TX */
2259 };
2262 };
2264 /* SCK */
2266 };
2268 HSCK2_C_MARK,
2269 };
2271 /* RTS, CTS */
2273 };
2276 };
2277 /* - HSCIF3 ----------------------------------------------------------------- */
2279 /* RX, TX */
2281 };
2284 };
2286 /* SCK */
2288 };
2290 HSCK3_MARK,
2291 };
2293 /* RTS, CTS */
2295 };
2298 };
2301 /* RX, TX */
2303 };
2306 };
2308 /* RX, TX */
2310 };
2313 };
2315 /* RX, TX */
2317 };
2320 };
2321 /* - HSCIF4 ----------------------------------------------------------------- */
2323 /* RX, TX */
2325 };
2328 };
2330 /* SCK */
2332 };
2334 HSCK4_MARK,
2335 };
2337 /* RTS, CTS */
2339 };
2342 };
2345 /* RX, TX */
2347 };
2350 };
2352 /* - I2C -------------------------------------------------------------------- */
2354 /* SDA, SCL */
2356 };
2359 };
2361 /* SDA, SCL */
2363 };
2366 };
2368 /* SDA, SCL */
2370 };
2373 };
2375 /* SDA, SCL */
2377 };
2380 };
2382 /* SDA, SCL */
2384 };
2387 };
2389 /* SDA, SCL */
2391 };
2394 };
2396 /* SDA, SCL */
2398 };
2401 };
2403 /* - INTC-EX ---------------------------------------------------------------- */
2405 /* IRQ0 */
2407 };
2409 IRQ0_MARK,
2410 };
2412 /* IRQ1 */
2414 };
2416 IRQ1_MARK,
2417 };
2419 /* IRQ2 */
2421 };
2423 IRQ2_MARK,
2424 };
2426 /* IRQ3 */
2428 };
2430 IRQ3_MARK,
2431 };
2433 /* IRQ4 */
2435 };
2437 IRQ4_MARK,
2438 };
2440 /* IRQ5 */
2442 };
2444 IRQ5_MARK,
2445 };
2447 /* - MSIOF0 ----------------------------------------------------------------- */
2449 /* SCK */
2451 };
2453 MSIOF0_SCK_MARK,
2454 };
2456 /* SYNC */
2458 };
2460 MSIOF0_SYNC_MARK,
2461 };
2463 /* SS1 */
2465 };
2467 MSIOF0_SS1_MARK,
2468 };
2470 /* SS2 */
2472 };
2474 MSIOF0_SS2_MARK,
2475 };
2477 /* TXD */
2479 };
2481 MSIOF0_TXD_MARK,
2482 };
2484 /* RXD */
2486 };
2488 MSIOF0_RXD_MARK,
2489 };
2490 /* - MSIOF1 ----------------------------------------------------------------- */
2492 /* SCK */
2494 };
2496 MSIOF1_SCK_A_MARK,
2497 };
2499 /* SYNC */
2501 };
2503 MSIOF1_SYNC_A_MARK,
2504 };
2506 /* SS1 */
2508 };
2510 MSIOF1_SS1_A_MARK,
2511 };
2513 /* SS2 */
2515 };
2517 MSIOF1_SS2_A_MARK,
2518 };
2520 /* TXD */
2522 };
2524 MSIOF1_TXD_A_MARK,
2525 };
2527 /* RXD */
2529 };
2531 MSIOF1_RXD_A_MARK,
2532 };
2534 /* SCK */
2536 };
2538 MSIOF1_SCK_B_MARK,
2539 };
2541 /* SYNC */
2543 };
2545 MSIOF1_SYNC_B_MARK,
2546 };
2548 /* SS1 */
2550 };
2552 MSIOF1_SS1_B_MARK,
2553 };
2555 /* SS2 */
2557 };
2559 MSIOF1_SS2_B_MARK,
2560 };
2562 /* TXD */
2564 };
2566 MSIOF1_TXD_B_MARK,
2567 };
2569 /* RXD */
2571 };
2573 MSIOF1_RXD_B_MARK,
2574 };
2576 /* SCK */
2578 };
2580 MSIOF1_SCK_C_MARK,
2581 };
2583 /* SYNC */
2585 };
2587 MSIOF1_SYNC_C_MARK,
2588 };
2590 /* SS1 */
2592 };
2594 MSIOF1_SS1_C_MARK,
2595 };
2597 /* SS2 */
2599 };
2601 MSIOF1_SS2_C_MARK,
2602 };
2604 /* TXD */
2606 };
2608 MSIOF1_TXD_C_MARK,
2609 };
2611 /* RXD */
2613 };
2615 MSIOF1_RXD_C_MARK,
2616 };
2618 /* SCK */
2620 };
2622 MSIOF1_SCK_D_MARK,
2623 };
2625 /* SYNC */
2627 };
2629 MSIOF1_SYNC_D_MARK,
2630 };
2632 /* SS1 */
2634 };
2636 MSIOF1_SS1_D_MARK,
2637 };
2639 /* SS2 */
2641 };
2643 MSIOF1_SS2_D_MARK,
2644 };
2646 /* TXD */
2648 };
2650 MSIOF1_TXD_D_MARK,
2651 };
2653 /* RXD */
2655 };
2657 MSIOF1_RXD_D_MARK,
2658 };
2660 /* SCK */
2662 };
2664 MSIOF1_SCK_E_MARK,
2665 };
2667 /* SYNC */
2669 };
2671 MSIOF1_SYNC_E_MARK,
2672 };
2674 /* SS1 */
2676 };
2678 MSIOF1_SS1_E_MARK,
2679 };
2681 /* SS2 */
2683 };
2685 MSIOF1_SS2_E_MARK,
2686 };
2688 /* TXD */
2690 };
2692 MSIOF1_TXD_E_MARK,
2693 };
2695 /* RXD */
2697 };
2699 MSIOF1_RXD_E_MARK,
2700 };
2702 /* SCK */
2704 };
2706 MSIOF1_SCK_F_MARK,
2707 };
2709 /* SYNC */
2711 };
2713 MSIOF1_SYNC_F_MARK,
2714 };
2716 /* SS1 */
2718 };
2720 MSIOF1_SS1_F_MARK,
2721 };
2723 /* SS2 */
2725 };
2727 MSIOF1_SS2_F_MARK,
2728 };
2730 /* TXD */
2732 };
2734 MSIOF1_TXD_F_MARK,
2735 };
2737 /* RXD */
2739 };
2741 MSIOF1_RXD_F_MARK,
2742 };
2744 /* SCK */
2746 };
2748 MSIOF1_SCK_G_MARK,
2749 };
2751 /* SYNC */
2753 };
2755 MSIOF1_SYNC_G_MARK,
2756 };
2758 /* SS1 */
2760 };
2762 MSIOF1_SS1_G_MARK,
2763 };
2765 /* SS2 */
2767 };
2769 MSIOF1_SS2_G_MARK,
2770 };
2772 /* TXD */
2774 };
2776 MSIOF1_TXD_G_MARK,
2777 };
2779 /* RXD */
2781 };
2783 MSIOF1_RXD_G_MARK,
2784 };
2785 /* - MSIOF2 ----------------------------------------------------------------- */
2787 /* SCK */
2789 };
2791 MSIOF2_SCK_A_MARK,
2792 };
2794 /* SYNC */
2796 };
2798 MSIOF2_SYNC_A_MARK,
2799 };
2801 /* SS1 */
2803 };
2805 MSIOF2_SS1_A_MARK,
2806 };
2808 /* SS2 */
2810 };
2812 MSIOF2_SS2_A_MARK,
2813 };
2815 /* TXD */
2817 };
2819 MSIOF2_TXD_A_MARK,
2820 };
2822 /* RXD */
2824 };
2826 MSIOF2_RXD_A_MARK,
2827 };
2829 /* SCK */
2831 };
2833 MSIOF2_SCK_B_MARK,
2834 };
2836 /* SYNC */
2838 };
2840 MSIOF2_SYNC_B_MARK,
2841 };
2843 /* SS1 */
2845 };
2847 MSIOF2_SS1_B_MARK,
2848 };
2850 /* SS2 */
2852 };
2854 MSIOF2_SS2_B_MARK,
2855 };
2857 /* TXD */
2859 };
2861 MSIOF2_TXD_B_MARK,
2862 };
2864 /* RXD */
2866 };
2868 MSIOF2_RXD_B_MARK,
2869 };
2871 /* SCK */
2873 };
2875 MSIOF2_SCK_C_MARK,
2876 };
2878 /* SYNC */
2880 };
2882 MSIOF2_SYNC_C_MARK,
2883 };
2885 /* SS1 */
2887 };
2889 MSIOF2_SS1_C_MARK,
2890 };
2892 /* SS2 */
2894 };
2896 MSIOF2_SS2_C_MARK,
2897 };
2899 /* TXD */
2901 };
2903 MSIOF2_TXD_C_MARK,
2904 };
2906 /* RXD */
2908 };
2910 MSIOF2_RXD_C_MARK,
2911 };
2913 /* SCK */
2915 };
2917 MSIOF2_SCK_D_MARK,
2918 };
2920 /* SYNC */
2922 };
2924 MSIOF2_SYNC_D_MARK,
2925 };
2927 /* SS1 */
2929 };
2931 MSIOF2_SS1_D_MARK,
2932 };
2934 /* SS2 */
2936 };
2938 MSIOF2_SS2_D_MARK,
2939 };
2941 /* TXD */
2943 };
2945 MSIOF2_TXD_D_MARK,
2946 };
2948 /* RXD */
2950 };
2952 MSIOF2_RXD_D_MARK,
2953 };
2954 /* - MSIOF3 ----------------------------------------------------------------- */
2956 /* SCK */
2958 };
2960 MSIOF3_SCK_A_MARK,
2961 };
2963 /* SYNC */
2965 };
2967 MSIOF3_SYNC_A_MARK,
2968 };
2970 /* SS1 */
2972 };
2974 MSIOF3_SS1_A_MARK,
2975 };
2977 /* SS2 */
2979 };
2981 MSIOF3_SS2_A_MARK,
2982 };
2984 /* TXD */
2986 };
2988 MSIOF3_TXD_A_MARK,
2989 };
2991 /* RXD */
2993 };
2995 MSIOF3_RXD_A_MARK,
2996 };
2998 /* SCK */
3000 };
3002 MSIOF3_SCK_B_MARK,
3003 };
3005 /* SYNC */
3007 };
3009 MSIOF3_SYNC_B_MARK,
3010 };
3012 /* SS1 */
3014 };
3016 MSIOF3_SS1_B_MARK,
3017 };
3019 /* SS2 */
3021 };
3023 MSIOF3_SS2_B_MARK,
3024 };
3026 /* TXD */
3028 };
3030 MSIOF3_TXD_B_MARK,
3031 };
3033 /* RXD */
3035 };
3037 MSIOF3_RXD_B_MARK,
3038 };
3040 /* SCK */
3042 };
3044 MSIOF3_SCK_C_MARK,
3045 };
3047 /* SYNC */
3049 };
3051 MSIOF3_SYNC_C_MARK,
3052 };
3054 /* TXD */
3056 };
3058 MSIOF3_TXD_C_MARK,
3059 };
3061 /* RXD */
3063 };
3065 MSIOF3_RXD_C_MARK,
3066 };
3068 /* SCK */
3070 };
3072 MSIOF3_SCK_D_MARK,
3073 };
3075 /* SYNC */
3077 };
3079 MSIOF3_SYNC_D_MARK,
3080 };
3082 /* SS1 */
3084 };
3086 MSIOF3_SS1_D_MARK,
3087 };
3089 /* TXD */
3091 };
3093 MSIOF3_TXD_D_MARK,
3094 };
3096 /* RXD */
3098 };
3100 MSIOF3_RXD_D_MARK,
3101 };
3104 /* SCK */
3106 };
3108 MSIOF3_SCK_E_MARK,
3109 };
3111 /* SYNC */
3113 };
3115 MSIOF3_SYNC_E_MARK,
3116 };
3118 /* SS1 */
3120 };
3122 MSIOF3_SS1_E_MARK,
3123 };
3125 /* SS2 */
3127 };
3129 MSIOF3_SS2_E_MARK,
3130 };
3132 /* TXD */
3134 };
3136 MSIOF3_TXD_E_MARK,
3137 };
3139 /* RXD */
3141 };
3143 MSIOF3_RXD_E_MARK,
3144 };
3146 /* - PWM0 --------------------------------------------------------------------*/
3148 /* PWM */
3150 };
3152 PWM0_MARK,
3153 };
3154 /* - PWM1 --------------------------------------------------------------------*/
3156 /* PWM */
3158 };
3160 PWM1_A_MARK,
3161 };
3163 /* PWM */
3165 };
3167 PWM1_B_MARK,
3168 };
3169 /* - PWM2 --------------------------------------------------------------------*/
3171 /* PWM */
3173 };
3175 PWM2_A_MARK,
3176 };
3178 /* PWM */
3180 };
3182 PWM2_B_MARK,
3183 };
3184 /* - PWM3 --------------------------------------------------------------------*/
3186 /* PWM */
3188 };
3190 PWM3_A_MARK,
3191 };
3193 /* PWM */
3195 };
3197 PWM3_B_MARK,
3198 };
3199 /* - PWM4 --------------------------------------------------------------------*/
3201 /* PWM */
3203 };
3205 PWM4_A_MARK,
3206 };
3208 /* PWM */
3210 };
3212 PWM4_B_MARK,
3213 };
3214 /* - PWM5 --------------------------------------------------------------------*/
3216 /* PWM */
3218 };
3220 PWM5_A_MARK,
3221 };
3223 /* PWM */
3225 };
3227 PWM5_B_MARK,
3228 };
3229 /* - PWM6 --------------------------------------------------------------------*/
3231 /* PWM */
3233 };
3235 PWM6_A_MARK,
3236 };
3238 /* PWM */
3240 };
3242 PWM6_B_MARK,
3243 };
3245 /* - SCIF0 ------------------------------------------------------------------ */
3247 /* RX, TX */
3249 };
3252 };
3254 /* SCK */
3256 };
3258 SCK0_MARK,
3259 };
3261 /* RTS, CTS */
3263 };
3266 };
3267 /* - SCIF1 ------------------------------------------------------------------ */
3269 /* RX, TX */
3271 };
3274 };
3276 /* SCK */
3278 };
3280 SCK1_MARK,
3281 };
3283 /* RTS, CTS */
3285 };
3288 };
3291 /* RX, TX */
3293 };
3296 };
3297 /* - SCIF2 ------------------------------------------------------------------ */
3299 /* RX, TX */
3301 };
3304 };
3306 /* SCK */
3308 };
3310 SCK2_MARK,
3311 };
3313 /* RX, TX */
3315 };
3318 };
3319 /* - SCIF3 ------------------------------------------------------------------ */
3321 /* RX, TX */
3323 };
3326 };
3328 /* SCK */
3330 };
3332 SCK3_MARK,
3333 };
3335 /* RTS, CTS */
3337 };
3340 };
3342 /* RX, TX */
3344 };
3347 };
3348 /* - SCIF4 ------------------------------------------------------------------ */
3350 /* RX, TX */
3352 };
3355 };
3357 /* SCK */
3359 };
3361 SCK4_A_MARK,
3362 };
3364 /* RTS, CTS */
3366 };
3369 };
3371 /* RX, TX */
3373 };
3376 };
3378 /* SCK */
3380 };
3382 SCK4_B_MARK,
3383 };
3385 /* RTS, CTS */
3387 };
3390 };
3392 /* RX, TX */
3394 };
3397 };
3399 /* SCK */
3401 };
3403 SCK4_C_MARK,
3404 };
3406 /* RTS, CTS */
3408 };
3411 };
3412 /* - SCIF5 ------------------------------------------------------------------ */
3414 /* RX, TX */
3416 };
3419 };
3421 /* SCK */
3423 };
3425 SCK5_A_MARK,
3426 };
3429 /* RX, TX */
3431 };
3434 };
3436 /* SCK */
3438 };
3440 SCK5_B_MARK,
3441 };
3443 /* - SCIF Clock ------------------------------------------------------------- */
3445 /* SCIF_CLK */
3447 };
3449 SCIF_CLK_A_MARK,
3450 };
3452 /* SCIF_CLK */
3454 };
3456 SCIF_CLK_B_MARK,
3457 };
3459 /* - SDHI0 ------------------------------------------------------------------ */
3461 /* D0 */
3463 };
3465 SD0_DAT0_MARK,
3466 };
3468 /* D[0:3] */
3471 };
3475 };
3477 /* CLK, CMD */
3479 };
3482 };
3484 /* CD */
3486 };
3488 SD0_CD_MARK,
3489 };
3491 /* WP */
3493 };
3495 SD0_WP_MARK,
3496 };
3497 /* - SDHI1 ------------------------------------------------------------------ */
3499 /* D0 */
3501 };
3503 SD1_DAT0_MARK,
3504 };
3506 /* D[0:3] */
3509 };
3513 };
3515 /* CLK, CMD */
3517 };
3520 };
3522 /* CD */
3524 };
3526 SD1_CD_MARK,
3527 };
3529 /* WP */
3531 };
3533 SD1_WP_MARK,
3534 };
3535 /* - SDHI2 ------------------------------------------------------------------ */
3537 /* D0 */
3539 };
3541 SD2_DAT0_MARK,
3542 };
3544 /* D[0:3] */
3547 };
3551 };
3553 /* D[0:7] */
3558 };
3564 };
3566 /* CLK, CMD */
3568 };
3571 };
3573 /* CD */
3575 };
3577 SD2_CD_A_MARK,
3578 };
3580 /* CD */
3582 };
3584 SD2_CD_B_MARK,
3585 };
3587 /* WP */
3589 };
3591 SD2_WP_A_MARK,
3592 };
3594 /* WP */
3596 };
3598 SD2_WP_B_MARK,
3599 };
3601 /* DS */
3603 };
3605 SD2_DS_MARK,
3606 };
3607 /* - SDHI3 ------------------------------------------------------------------ */
3609 /* D0 */
3611 };
3613 SD3_DAT0_MARK,
3614 };
3616 /* D[0:3] */
3619 };
3623 };
3625 /* D[0:7] */
3630 };
3636 };
3638 /* CLK, CMD */
3640 };
3643 };
3645 /* CD */
3647 };
3649 SD3_CD_MARK,
3650 };
3652 /* WP */
3654 };
3656 SD3_WP_MARK,
3657 };
3659 /* DS */
3661 };
3663 SD3_DS_MARK,
3664 };
3666 /* - SSI -------------------------------------------------------------------- */
3668 /* SDATA */
3670 };
3672 SSI_SDATA0_MARK,
3673 };
3675 /* SCK, WS */
3677 };
3680 };
3682 /* SDATA */
3684 };
3686 SSI_SDATA1_A_MARK,
3687 };
3689 /* SDATA */
3691 };
3693 SSI_SDATA1_B_MARK,
3694 };
3696 /* SCK, WS */
3698 };
3701 };
3703 /* SCK, WS */
3705 };
3708 };
3710 /* SDATA */
3712 };
3714 SSI_SDATA2_A_MARK,
3715 };
3717 /* SDATA */
3719 };
3721 SSI_SDATA2_B_MARK,
3722 };
3724 /* SCK, WS */
3726 };
3729 };
3731 /* SCK, WS */
3733 };
3736 };
3738 /* SDATA */
3740 };
3742 SSI_SDATA3_MARK,
3743 };
3745 /* SCK, WS */
3747 };
3750 };
3752 /* SDATA */
3754 };
3756 SSI_SDATA4_MARK,
3757 };
3759 /* SCK, WS */
3761 };
3764 };
3766 /* SDATA */
3768 };
3770 SSI_SDATA5_MARK,
3771 };
3773 /* SCK, WS */
3775 };
3778 };
3780 /* SDATA */
3782 };
3784 SSI_SDATA6_MARK,
3785 };
3787 /* SCK, WS */
3789 };
3792 };
3794 /* SDATA */
3796 };
3798 SSI_SDATA7_MARK,
3799 };
3801 /* SCK, WS */
3803 };
3806 };
3808 /* SDATA */
3810 };
3812 SSI_SDATA8_MARK,
3813 };
3815 /* SDATA */
3817 };
3819 SSI_SDATA9_A_MARK,
3820 };
3822 /* SDATA */
3824 };
3826 SSI_SDATA9_B_MARK,
3827 };
3829 /* SCK, WS */
3831 };
3834 };
3836 /* SCK, WS */
3838 };
3841 };
3843 /* - TMU -------------------------------------------------------------------- */
3845 /* TCLK */
3847 };
3849 TCLK1_A_MARK,
3850 };
3852 /* TCLK */
3854 };
3856 TCLK1_B_MARK,
3857 };
3859 /* TCLK */
3861 };
3863 TCLK2_A_MARK,
3864 };
3866 /* TCLK */
3868 };
3870 TCLK2_B_MARK,
3871 };
3873 /* - USB0 ------------------------------------------------------------------- */
3875 /* PWEN, OVC */
3877 };
3880 };
3881 /* - USB1 ------------------------------------------------------------------- */
3883 /* PWEN, OVC */
3885 };
3888 };
3890 /* - USB30 ------------------------------------------------------------------ */
3892 /* PWEN, OVC */
3894 };
3897 };
3899 /* - VIN4 ------------------------------------------------------------------- */
3910 };
3921 };
3932 };
3943 };
3958 },
3959 };
3974 },
3975 };
3990 },
3991 };
4006 },
4007 };
4009 /* HSYNC#, VSYNC# */
4011 };
4014 };
4016 /* FIELD */
4018 };
4020 VI4_FIELD_MARK,
4021 };
4023 /* CLKENB */
4025 };
4027 VI4_CLKENB_MARK,
4028 };
4030 /* CLK */
4032 };
4034 VI4_CLK_MARK,
4035 };
4037 /* - VIN5 ------------------------------------------------------------------- */
4043 };
4049 };
4056 };
4063 };
4071 };
4079 };
4089 };
4099 };
4101 /* HSYNC#, VSYNC# */
4103 };
4106 };
4109 };
4111 /* FIELD */
4112 VI5_FIELD_MARK,
4113 };
4116 };
4118 /* CLKENB */
4119 VI5_CLKENB_MARK,
4120 };
4123 };
4125 /* CLK */
4126 VI5_CLK_MARK,
4127 };
4470 };
4490 };
4504 };
4509 };
4513 };
4517 };
4522 };
4526 };
4538 };
4550 };
4559 };
4568 };
4579 };
4583 };
4589 };
4598 };
4610 };
4619 };
4626 };
4631 };
4636 };
4642 };
4651 };
4660 };
4705 };
4732 };
4762 };
4766 };
4771 };
4776 };
4781 };
4786 };
4791 };
4796 };
4802 };
4809 };
4815 };
4822 };
4834 };
4841 };
4846 };
4854 };
4862 };
4874 };
4884 };
4912 };
4919 };
4923 };
4927 };
4931 };
4952 };
4963 };
5017 };
5020 #define F_(x, y) FN_##y
5021 #define FM(x) FN_##x
5055 },
5089 },
5123 },
5157 },
5191 },
5225 },
5259 },
5293 },
5294 #undef F_
5295 #undef FM
5297 #define F_(x, y) x,
5298 #define FM(x) FN_##x,
5300 IP0_31_28
5301 IP0_27_24
5302 IP0_23_20
5303 IP0_19_16
5304 IP0_15_12
5305 IP0_11_8
5306 IP0_7_4
5307 IP0_3_0 }
5308 },
5310 IP1_31_28
5311 IP1_27_24
5312 IP1_23_20
5313 IP1_19_16
5314 IP1_15_12
5315 IP1_11_8
5316 IP1_7_4
5317 IP1_3_0 }
5318 },
5320 IP2_31_28
5321 IP2_27_24
5322 IP2_23_20
5323 IP2_19_16
5324 IP2_15_12
5325 IP2_11_8
5326 IP2_7_4
5327 IP2_3_0 }
5328 },
5330 IP3_31_28
5331 IP3_27_24
5332 IP3_23_20
5333 IP3_19_16
5334 IP3_15_12
5335 IP3_11_8
5336 IP3_7_4
5337 IP3_3_0 }
5338 },
5340 IP4_31_28
5341 IP4_27_24
5342 IP4_23_20
5343 IP4_19_16
5344 IP4_15_12
5345 IP4_11_8
5346 IP4_7_4
5347 IP4_3_0 }
5348 },
5350 IP5_31_28
5351 IP5_27_24
5352 IP5_23_20
5353 IP5_19_16
5354 IP5_15_12
5355 IP5_11_8
5356 IP5_7_4
5357 IP5_3_0 }
5358 },
5360 IP6_31_28
5361 IP6_27_24
5362 IP6_23_20
5363 IP6_19_16
5364 IP6_15_12
5365 IP6_11_8
5366 IP6_7_4
5367 IP6_3_0 }
5368 },
5370 IP7_31_28
5371 IP7_27_24
5372 IP7_23_20
5373 IP7_19_16
5375 IP7_11_8
5376 IP7_7_4
5377 IP7_3_0 }
5378 },
5380 IP8_31_28
5381 IP8_27_24
5382 IP8_23_20
5383 IP8_19_16
5384 IP8_15_12
5385 IP8_11_8
5386 IP8_7_4
5387 IP8_3_0 }
5388 },
5390 IP9_31_28
5391 IP9_27_24
5392 IP9_23_20
5393 IP9_19_16
5394 IP9_15_12
5395 IP9_11_8
5396 IP9_7_4
5397 IP9_3_0 }
5398 },
5400 IP10_31_28
5401 IP10_27_24
5402 IP10_23_20
5403 IP10_19_16
5404 IP10_15_12
5405 IP10_11_8
5406 IP10_7_4
5407 IP10_3_0 }
5408 },
5410 IP11_31_28
5411 IP11_27_24
5412 IP11_23_20
5413 IP11_19_16
5414 IP11_15_12
5415 IP11_11_8
5416 IP11_7_4
5417 IP11_3_0 }
5418 },
5420 IP12_31_28
5421 IP12_27_24
5422 IP12_23_20
5423 IP12_19_16
5424 IP12_15_12
5425 IP12_11_8
5426 IP12_7_4
5427 IP12_3_0 }
5428 },
5430 IP13_31_28
5431 IP13_27_24
5432 IP13_23_20
5433 IP13_19_16
5434 IP13_15_12
5435 IP13_11_8
5436 IP13_7_4
5437 IP13_3_0 }
5438 },
5440 IP14_31_28
5441 IP14_27_24
5442 IP14_23_20
5443 IP14_19_16
5444 IP14_15_12
5445 IP14_11_8
5446 IP14_7_4
5447 IP14_3_0 }
5448 },
5450 IP15_31_28
5451 IP15_27_24
5452 IP15_23_20
5453 IP15_19_16
5454 IP15_15_12
5455 IP15_11_8
5456 IP15_7_4
5457 IP15_3_0 }
5458 },
5460 IP16_31_28
5461 IP16_27_24
5462 IP16_23_20
5463 IP16_19_16
5464 IP16_15_12
5465 IP16_11_8
5466 IP16_7_4
5467 IP16_3_0 }
5468 },
5470 IP17_31_28
5471 IP17_27_24
5472 IP17_23_20
5473 IP17_19_16
5474 IP17_15_12
5475 IP17_11_8
5476 IP17_7_4
5477 IP17_3_0 }
5478 },
5486 IP18_7_4
5487 IP18_3_0 }
5488 },
5489 #undef F_
5490 #undef FM
5492 #define F_(x, y) x,
5493 #define FM(x) FN_##x,
5497 MOD_SEL0_31_30_29
5498 MOD_SEL0_28_27
5499 MOD_SEL0_26_25_24
5500 MOD_SEL0_23
5501 MOD_SEL0_22
5502 MOD_SEL0_21
5503 MOD_SEL0_20
5504 MOD_SEL0_19
5505 MOD_SEL0_18_17
5506 MOD_SEL0_16
5508 MOD_SEL0_14_13
5509 MOD_SEL0_12
5510 MOD_SEL0_11
5511 MOD_SEL0_10
5512 MOD_SEL0_9_8
5513 MOD_SEL0_7_6
5514 MOD_SEL0_5
5515 MOD_SEL0_4_3
5516 /* RESERVED 2, 1, 0 */
5518 },
5522 MOD_SEL1_31_30
5523 MOD_SEL1_29_28_27
5524 MOD_SEL1_26
5525 MOD_SEL1_25_24
5526 MOD_SEL1_23_22_21
5527 MOD_SEL1_20
5528 MOD_SEL1_19
5529 MOD_SEL1_18_17
5530 MOD_SEL1_16
5531 MOD_SEL1_15_14
5532 MOD_SEL1_13
5533 MOD_SEL1_12
5534 MOD_SEL1_11
5535 MOD_SEL1_10
5536 MOD_SEL1_9
5538 MOD_SEL1_6
5539 MOD_SEL1_5
5540 MOD_SEL1_4
5541 MOD_SEL1_3
5542 MOD_SEL1_2
5543 MOD_SEL1_1
5544 MOD_SEL1_0 }
5545 },
5549 MOD_SEL2_31
5550 MOD_SEL2_30
5551 MOD_SEL2_29
5552 MOD_SEL2_28_27
5553 MOD_SEL2_26
5554 MOD_SEL2_25_24_23
5555 MOD_SEL2_22
5556 MOD_SEL2_21
5557 MOD_SEL2_20
5558 MOD_SEL2_19
5559 MOD_SEL2_18
5560 MOD_SEL2_17
5561 /* RESERVED 16 */
5563 /* RESERVED 15, 14, 13, 12 */
5566 /* RESERVED 11, 10, 9, 8 */
5569 /* RESERVED 7, 6, 5, 4 */
5572 /* RESERVED 3, 2, 1 */
5574 MOD_SEL2_0 }
5575 },
5576 { },
5577 };
5589 } },
5599 } },
5609 } },
5619 } },
5629 } },
5639 } },
5649 } },
5659 } },
5669 } },
5679 } },
5689 } },
5699 } },
5704 } },
5714 } },
5724 } },
5734 } },
5744 } },
5754 } },
5764 } },
5774 } },
5784 } },
5794 } },
5804 } },
5814 } },
5823 } },
5824 { },
5825 };
5828 POCCTRL,
5829 };
5834 };
5837 {
5849 }
5885 } },
5919 } },
5953 } },
5987 } },
6021 } },
6055 } },
6089 } },
6091 };
6095 {
6107 else
6109 }
6113 {
6132 }
6138 };
6161 };