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Linux 4.19.133
[linux/fpc-iii.git] / drivers / pinctrl / sh-pfc / pfc-r8a77990.c
blobd2fcf7f7b966829d78e329327c85029f05dbb805
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77990 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
8 *
9 * R8A7796 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2016-2017 Renesas Electronics Corp.
12 */
13
14 #include <linux/kernel.h>
15
16 #include "core.h"
17 #include "sh_pfc.h"
18
19 #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
20 SH_PFC_PIN_CFG_PULL_DOWN)
21
22 #define CPU_ALL_PORT(fn, sfx) \
23 PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_16(3, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS)
30 /*
31 * F_() : just information
32 * FM() : macro for FN_xxx / xxx_MARK
33 */
34
35 /* GPSR0 */
36 #define GPSR0_17 F_(SDA4, IP7_27_24)
37 #define GPSR0_16 F_(SCL4, IP7_23_20)
38 #define GPSR0_15 F_(D15, IP7_19_16)
39 #define GPSR0_14 F_(D14, IP7_15_12)
40 #define GPSR0_13 F_(D13, IP7_11_8)
41 #define GPSR0_12 F_(D12, IP7_7_4)
42 #define GPSR0_11 F_(D11, IP7_3_0)
43 #define GPSR0_10 F_(D10, IP6_31_28)
44 #define GPSR0_9 F_(D9, IP6_27_24)
45 #define GPSR0_8 F_(D8, IP6_23_20)
46 #define GPSR0_7 F_(D7, IP6_19_16)
47 #define GPSR0_6 F_(D6, IP6_15_12)
48 #define GPSR0_5 F_(D5, IP6_11_8)
49 #define GPSR0_4 F_(D4, IP6_7_4)
50 #define GPSR0_3 F_(D3, IP6_3_0)
51 #define GPSR0_2 F_(D2, IP5_31_28)
52 #define GPSR0_1 F_(D1, IP5_27_24)
53 #define GPSR0_0 F_(D0, IP5_23_20)
54
55 /* GPSR1 */
56 #define GPSR1_22 F_(WE0_N, IP5_19_16)
57 #define GPSR1_21 F_(CS0_N, IP5_15_12)
58 #define GPSR1_20 FM(CLKOUT)
59 #define GPSR1_19 F_(A19, IP5_11_8)
60 #define GPSR1_18 F_(A18, IP5_7_4)
61 #define GPSR1_17 F_(A17, IP5_3_0)
62 #define GPSR1_16 F_(A16, IP4_31_28)
63 #define GPSR1_15 F_(A15, IP4_27_24)
64 #define GPSR1_14 F_(A14, IP4_23_20)
65 #define GPSR1_13 F_(A13, IP4_19_16)
66 #define GPSR1_12 F_(A12, IP4_15_12)
67 #define GPSR1_11 F_(A11, IP4_11_8)
68 #define GPSR1_10 F_(A10, IP4_7_4)
69 #define GPSR1_9 F_(A9, IP4_3_0)
70 #define GPSR1_8 F_(A8, IP3_31_28)
71 #define GPSR1_7 F_(A7, IP3_27_24)
72 #define GPSR1_6 F_(A6, IP3_23_20)
73 #define GPSR1_5 F_(A5, IP3_19_16)
74 #define GPSR1_4 F_(A4, IP3_15_12)
75 #define GPSR1_3 F_(A3, IP3_11_8)
76 #define GPSR1_2 F_(A2, IP3_7_4)
77 #define GPSR1_1 F_(A1, IP3_3_0)
78 #define GPSR1_0 F_(A0, IP2_31_28)
79
80 /* GPSR2 */
81 #define GPSR2_25 F_(EX_WAIT0, IP2_27_24)
82 #define GPSR2_24 F_(RD_WR_N, IP2_23_20)
83 #define GPSR2_23 F_(RD_N, IP2_19_16)
84 #define GPSR2_22 F_(BS_N, IP2_15_12)
85 #define GPSR2_21 FM(AVB_PHY_INT)
86 #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0)
87 #define GPSR2_19 FM(AVB_RD3)
88 #define GPSR2_18 F_(AVB_RD2, IP1_31_28)
89 #define GPSR2_17 F_(AVB_RD1, IP1_27_24)
90 #define GPSR2_16 F_(AVB_RD0, IP1_23_20)
91 #define GPSR2_15 FM(AVB_RXC)
92 #define GPSR2_14 FM(AVB_RX_CTL)
93 #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16)
94 #define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
95 #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8)
96 #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4)
97 #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
98 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
99 #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24)
100 #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20)
101 #define GPSR2_5 FM(QSPI0_SSL)
102 #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16)
103 #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12)
104 #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8)
105 #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4)
106 #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0)
107
108 /* GPSR3 */
109 #define GPSR3_15 F_(SD1_WP, IP11_7_4)
110 #define GPSR3_14 F_(SD1_CD, IP11_3_0)
111 #define GPSR3_13 F_(SD0_WP, IP10_31_28)
112 #define GPSR3_12 F_(SD0_CD, IP10_27_24)
113 #define GPSR3_11 F_(SD1_DAT3, IP9_11_8)
114 #define GPSR3_10 F_(SD1_DAT2, IP9_7_4)
115 #define GPSR3_9 F_(SD1_DAT1, IP9_3_0)
116 #define GPSR3_8 F_(SD1_DAT0, IP8_31_28)
117 #define GPSR3_7 F_(SD1_CMD, IP8_27_24)
118 #define GPSR3_6 F_(SD1_CLK, IP8_23_20)
119 #define GPSR3_5 F_(SD0_DAT3, IP8_19_16)
120 #define GPSR3_4 F_(SD0_DAT2, IP8_15_12)
121 #define GPSR3_3 F_(SD0_DAT1, IP8_11_8)
122 #define GPSR3_2 F_(SD0_DAT0, IP8_7_4)
123 #define GPSR3_1 F_(SD0_CMD, IP8_3_0)
124 #define GPSR3_0 F_(SD0_CLK, IP7_31_28)
125
126 /* GPSR4 */
127 #define GPSR4_10 F_(SD3_DS, IP10_23_20)
128 #define GPSR4_9 F_(SD3_DAT7, IP10_19_16)
129 #define GPSR4_8 F_(SD3_DAT6, IP10_15_12)
130 #define GPSR4_7 F_(SD3_DAT5, IP10_11_8)
131 #define GPSR4_6 F_(SD3_DAT4, IP10_7_4)
132 #define GPSR4_5 F_(SD3_DAT3, IP10_3_0)
133 #define GPSR4_4 F_(SD3_DAT2, IP9_31_28)
134 #define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
135 #define GPSR4_2 F_(SD3_DAT0, IP9_23_20)
136 #define GPSR4_1 F_(SD3_CMD, IP9_19_16)
137 #define GPSR4_0 F_(SD3_CLK, IP9_15_12)
138
139 /* GPSR5 */
140 #define GPSR5_19 F_(MLB_DAT, IP13_23_20)
141 #define GPSR5_18 F_(MLB_SIG, IP13_19_16)
142 #define GPSR5_17 F_(MLB_CLK, IP13_15_12)
143 #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8)
144 #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4)
145 #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0)
146 #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28)
147 #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24)
148 #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20)
149 #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16)
150 #define GPSR5_9 F_(RX2_A, IP12_15_12)
151 #define GPSR5_8 F_(TX2_A, IP12_11_8)
152 #define GPSR5_7 F_(SCK2_A, IP12_7_4)
153 #define GPSR5_6 F_(TX1, IP12_3_0)
154 #define GPSR5_5 F_(RX1, IP11_31_28)
155 #define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20)
156 #define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
157 #define GPSR5_2 F_(TX0_A, IP11_15_12)
158 #define GPSR5_1 F_(RX0_A, IP11_11_8)
159 #define GPSR5_0 F_(SCK0_A, IP11_27_24)
160
161 /* GPSR6 */
162 #define GPSR6_17 F_(USB30_PWEN, IP15_27_24)
163 #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16)
164 #define GPSR6_15 F_(SSI_WS6, IP15_15_12)
165 #define GPSR6_14 F_(SSI_SCK6, IP15_11_8)
166 #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4)
167 #define GPSR6_12 F_(SSI_WS5, IP15_3_0)
168 #define GPSR6_11 F_(SSI_SCK5, IP14_31_28)
169 #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24)
170 #define GPSR6_9 F_(USB30_OVC, IP15_31_28)
171 #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20)
172 #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20)
173 #define GPSR6_6 F_(SSI_WS349, IP14_19_16)
174 #define GPSR6_5 F_(SSI_SCK349, IP14_15_12)
175 #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8)
176 #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4)
177 #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0)
178 #define GPSR6_1 F_(SSI_WS01239, IP13_31_28)
179 #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24)
180
181 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
182 #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
183 #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
184 #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
185 #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
186 #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187 #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188 #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190 #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191 #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192 #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193 #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194 #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195 #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196 #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197 #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198 #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214
215 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
216 #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248
249 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
250 #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282
283 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
284 #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316
317 #define PINMUX_GPSR \
318 \
319 \
320 \
321 \
322 \
323 \
324 \
325 GPSR2_25 \
326 GPSR2_24 \
327 GPSR2_23 \
328 GPSR1_22 GPSR2_22 \
329 GPSR1_21 GPSR2_21 \
330 GPSR1_20 GPSR2_20 \
331 GPSR1_19 GPSR2_19 GPSR5_19 \
332 GPSR1_18 GPSR2_18 GPSR5_18 \
333 GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \
334 GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \
335 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \
336 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \
337 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \
338 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \
339 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \
340 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
341 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
342 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
343 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
344 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
345 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
346 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
347 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
348 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
349 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
350 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
351
352 #define PINMUX_IPSR \
353 \
354 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
355 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
356 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
357 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
358 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
359 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
360 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
361 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
362 \
363 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
364 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
365 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
366 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
367 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
368 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
369 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
370 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
371 \
372 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
373 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
374 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
375 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
376 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
377 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
378 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
379 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
380 \
381 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
382 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
383 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
384 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
385 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
386 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
387 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
388 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28
389
390 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
391 #define MOD_SEL0_30_29 FM(SEL_ADGB_0) FM(SEL_ADGB_1) FM(SEL_ADGB_2) F_(0, 0)
392 #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1)
393 #define MOD_SEL0_27_26 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) F_(0, 0)
394 #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1)
395 #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
396 #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
397 #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
398 #define MOD_SEL0_21_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) FM(SEL_I2C1_2) FM(SEL_I2C1_3)
399 #define MOD_SEL0_19_18_17 FM(SEL_I2C2_0) FM(SEL_I2C2_1) FM(SEL_I2C2_2) FM(SEL_I2C2_3) FM(SEL_I2C2_4) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
401 #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
402 #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
403 #define MOD_SEL0_13_12 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) F_(0, 0)
404 #define MOD_SEL0_11_10 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) F_(0, 0)
405 #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
406 #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
407 #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
408 #define MOD_SEL0_6_5 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) FM(SEL_REMOCON_2) F_(0, 0)
409 #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
410 #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
411 #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
412 #define MOD_SEL0_1_0 FM(SEL_SPEED_PULSE_IF_0) FM(SEL_SPEED_PULSE_IF_1) FM(SEL_SPEED_PULSE_IF_2) F_(0, 0)
413
414 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
415 #define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
416 #define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
417 #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
418 #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
419 #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
420 #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
421 #define MOD_SEL1_24_23_22 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) FM(SEL_HSCIF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
422 #define MOD_SEL1_21_20_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) FM(SEL_HSCIF4_2) FM(SEL_HSCIF4_3) FM(SEL_HSCIF4_4) F_(0, 0) F_(0, 0) F_(0, 0)
423 #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1)
424 #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1)
425 #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
426 #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
427 #define MOD_SEL1_14_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) FM(SEL_SCIF3_2) F_(0, 0)
428 #define MOD_SEL1_12_11 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
429 #define MOD_SEL1_10_9 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) FM(SEL_SCIF5_2) F_(0, 0)
430 #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
431 #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1)
432 #define MOD_SEL1_6_5 FM(SEL_ADGC_0) FM(SEL_ADGC_1) FM(SEL_ADGC_2) F_(0, 0)
433 #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
434
435 #define PINMUX_MOD_SELS \
436 \
437 MOD_SEL1_31 \
438 MOD_SEL0_30_29 MOD_SEL1_30 \
439 MOD_SEL1_29 \
440 MOD_SEL0_28 MOD_SEL1_28 \
441 MOD_SEL0_27_26 \
442 MOD_SEL1_26 \
443 MOD_SEL0_25 MOD_SEL1_25 \
444 MOD_SEL0_24 MOD_SEL1_24_23_22 \
445 MOD_SEL0_23 \
446 MOD_SEL0_22 \
447 MOD_SEL0_21_20 MOD_SEL1_21_20_19 \
448 MOD_SEL0_19_18_17 MOD_SEL1_18 \
449 MOD_SEL1_17 \
450 MOD_SEL0_16 MOD_SEL1_16 \
451 MOD_SEL0_15 MOD_SEL1_15 \
452 MOD_SEL0_14 MOD_SEL1_14_13 \
453 MOD_SEL0_13_12 \
454 MOD_SEL1_12_11 \
455 MOD_SEL0_11_10 \
456 MOD_SEL1_10_9 \
457 MOD_SEL0_9 \
458 MOD_SEL0_8 MOD_SEL1_8 \
459 MOD_SEL0_7 MOD_SEL1_7 \
460 MOD_SEL0_6_5 MOD_SEL1_6_5 \
461 MOD_SEL0_4 MOD_SEL1_4 \
462 MOD_SEL0_3 \
463 MOD_SEL0_2 \
464 MOD_SEL0_1_0
465
466 /*
467 * These pins are not able to be muxed but have other properties
468 * that can be set, such as pull-up/pull-down enable.
469 */
470 #define PINMUX_STATIC \
471 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
472 FM(AVB_TD3) \
473 FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
474 FM(ASEBRK) \
475 FM(MLB_REF)
476
477 enum {
478 PINMUX_RESERVED = 0,
479
480 PINMUX_DATA_BEGIN,
481 GP_ALL(DATA),
482 PINMUX_DATA_END,
483
484 #define F_(x, y)
485 #define FM(x) FN_##x,
486 PINMUX_FUNCTION_BEGIN,
487 GP_ALL(FN),
488 PINMUX_GPSR
489 PINMUX_IPSR
490 PINMUX_MOD_SELS
491 PINMUX_FUNCTION_END,
492 #undef F_
493 #undef FM
494
495 #define F_(x, y)
496 #define FM(x) x##_MARK,
497 PINMUX_MARK_BEGIN,
498 PINMUX_GPSR
499 PINMUX_IPSR
500 PINMUX_MOD_SELS
501 PINMUX_STATIC
502 PINMUX_MARK_END,
503 #undef F_
504 #undef FM
505 };
506
507 static const u16 pinmux_data[] = {
508 PINMUX_DATA_GP_ALL(),
509
510 PINMUX_SINGLE(CLKOUT),
511 PINMUX_SINGLE(AVB_PHY_INT),
512 PINMUX_SINGLE(AVB_RD3),
513 PINMUX_SINGLE(AVB_RXC),
514 PINMUX_SINGLE(AVB_RX_CTL),
515 PINMUX_SINGLE(QSPI0_SSL),
516
517 /* IPSR0 */
518 PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK),
519 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0),
520
521 PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0),
522 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0),
523
524 PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1),
525 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0),
526
527 PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2),
528 PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A),
529
530 PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3),
531 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0),
532
533 PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK),
534 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0),
535 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1),
536 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0),
537
538 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0),
539 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
540 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B),
541 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
542
543 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
544 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
545 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
546 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
547
548 /* IPSR1 */
549 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
550 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
551 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
552 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
553
554 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3),
555 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0),
556 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2),
557 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0),
558
559 PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL),
560 PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0),
561 PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2),
562 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0),
563
564 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
565 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
566 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
567 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
568
569 PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N),
570 PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0),
571 PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2),
572 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0),
573
574 PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0),
575
576 PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1),
577
578 PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2),
579
580 /* IPSR2 */
581 PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK),
582
583 PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO),
584
585 PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC),
586
587 PINMUX_IPSR_GPSR(IP2_15_12, BS_N),
588 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0),
589 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC),
590 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK),
591 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C),
592 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1),
593
594 PINMUX_IPSR_GPSR(IP2_19_16, RD_N),
595 PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0),
596 PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK),
597 PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD),
598 PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2),
599 PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A),
600 PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1),
601
602 PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
603 PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
604 PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A),
605 PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
606 PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
607 PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
608 PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0),
609
610 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
611 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
612 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A),
613 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
614 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
615 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
616
617 PINMUX_IPSR_GPSR(IP2_31_28, A0),
618 PINMUX_IPSR_GPSR(IP2_31_28, IRQ0),
619 PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0),
620 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1),
621 PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0),
622 PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE),
623 PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3),
624 PINMUX_IPSR_GPSR(IP2_31_28, IERX),
625 PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE),
626
627 /* IPSR3 */
628 PINMUX_IPSR_GPSR(IP3_3_0, A1),
629 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
630 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
631 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
632 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
633 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
634 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
635 PINMUX_IPSR_GPSR(IP3_3_0, IETX),
636 PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE),
637
638 PINMUX_IPSR_GPSR(IP3_7_4, A2),
639 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
640 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
641 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
642 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
643 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
644 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
645 PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE),
646
647 PINMUX_IPSR_GPSR(IP3_11_8, A3),
648 PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0),
649 PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0),
650 PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12),
651 PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0),
652 PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D),
653 PINMUX_IPSR_GPSR(IP3_11_8, IECLK),
654 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
655
656 PINMUX_IPSR_GPSR(IP3_15_12, A4),
657 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0),
658 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
659 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
660 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
661 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
662 PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1),
663
664 PINMUX_IPSR_GPSR(IP3_19_16, A5),
665 PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0),
666 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1),
667 PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9),
668 PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1),
669 PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1),
670 PINMUX_IPSR_GPSR(IP3_19_16, QPOLA),
671
672 PINMUX_IPSR_GPSR(IP3_23_20, A6),
673 PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0),
674 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1),
675 PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10),
676 PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1),
677
678 PINMUX_IPSR_GPSR(IP3_27_24, A7),
679 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A),
680 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B),
681 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11),
682 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1),
683
684 PINMUX_IPSR_GPSR(IP3_31_28, A8),
685 PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0),
686 PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1),
687 PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2),
688 PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0),
689 PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC),
690 PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1),
691 PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS),
692
693 /* IPSR4 */
694 PINMUX_IPSR_GPSR(IP4_3_0, A9),
695 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
696 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
697 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
698 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
699 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7),
700 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15),
701
702 PINMUX_IPSR_GPSR(IP4_7_4, A10),
703 PINMUX_IPSR_GPSR(IP4_7_4, IRQ4),
704 PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1),
705 PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13),
706 PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0),
707 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5),
708 PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B),
709 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13),
710
711 PINMUX_IPSR_GPSR(IP4_11_8, A11),
712 PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0),
713 PINMUX_IPSR_GPSR(IP4_11_8, TX3_B),
714 PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C),
715 PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC),
716 PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1),
717 PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS),
718
719 PINMUX_IPSR_GPSR(IP4_15_12, A12),
720 PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0),
721 PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B),
722 PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17),
723 PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0),
724 PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6),
725 PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14),
726
727 PINMUX_IPSR_GPSR(IP4_19_16, A13),
728 PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0),
729 PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1),
730 PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14),
731 PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3),
732 PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2),
733 PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2),
734
735 PINMUX_IPSR_GPSR(IP4_23_20, A14),
736 PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1),
737 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1),
738 PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15),
739 PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D),
740 PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3),
741 PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3),
742
743 PINMUX_IPSR_GPSR(IP4_27_24, A15),
744 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2),
745 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B),
746 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18),
747 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0),
748 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4),
749 PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4),
750
751 PINMUX_IPSR_GPSR(IP4_31_28, A16),
752 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC),
753 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B),
754 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19),
755 PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0),
756 PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5),
757 PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5),
758
759 /* IPSR5 */
760 PINMUX_IPSR_GPSR(IP5_3_0, A17),
761 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
762 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20),
763 PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0),
764 PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6),
765 PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6),
766
767 PINMUX_IPSR_GPSR(IP5_7_4, A18),
768 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
769 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21),
770 PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0),
771 PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0),
772 PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4),
773 PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0),
774
775 PINMUX_IPSR_GPSR(IP5_11_8, A19),
776 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
777 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22),
778 PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0),
779 PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1),
780 PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E),
781 PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1),
782
783 PINMUX_IPSR_GPSR(IP5_15_12, CS0_N),
784 PINMUX_IPSR_GPSR(IP5_15_12, SCL5),
785 PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0),
786 PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1),
787 PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16),
788
789 PINMUX_IPSR_GPSR(IP5_19_16, WE0_N),
790 PINMUX_IPSR_GPSR(IP5_19_16, SDA5),
791 PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1),
792 PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1),
793 PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17),
794
795 PINMUX_IPSR_GPSR(IP5_23_20, D0),
796 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
797 PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2),
798 PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2),
799 PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18),
800
801 PINMUX_IPSR_GPSR(IP5_27_24, D1),
802 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
803 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
804 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
805 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
806 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
807 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
808 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
809
810 PINMUX_IPSR_GPSR(IP5_31_28, D2),
811 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0),
812 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2),
813 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0),
814 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3),
815 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2),
816 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19),
817
818 /* IPSR6 */
819 PINMUX_IPSR_GPSR(IP6_3_0, D3),
820 PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A),
821 PINMUX_IPSR_GPSR(IP6_3_0, TX5_C),
822 PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0),
823 PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4),
824 PINMUX_IPSR_GPSR(IP6_3_0, TX4_C),
825 PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20),
826
827 PINMUX_IPSR_GPSR(IP6_7_4, D4),
828 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
829 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
830 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
831 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0),
832 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
833 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
834
835 PINMUX_IPSR_GPSR(IP6_11_8, D5),
836 PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0),
837 PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1),
838 PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5),
839 PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1),
840 PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21),
841
842 PINMUX_IPSR_GPSR(IP6_15_12, D6),
843 PINMUX_IPSR_GPSR(IP6_15_12, TX3_A),
844 PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B),
845 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6),
846 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1),
847 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22),
848
849 PINMUX_IPSR_GPSR(IP6_19_16, D7),
850 PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX),
851 PINMUX_IPSR_GPSR(IP6_19_16, IRQ5),
852 PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX),
853 PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0),
854 PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1),
855
856 PINMUX_IPSR_GPSR(IP6_23_20, D8),
857 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0),
858 PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1),
859 PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0),
860 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7),
861 PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1),
862 PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4),
863 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23),
864
865 PINMUX_IPSR_GPSR(IP6_27_24, D9),
866 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0),
867 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0),
868 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0),
869 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1),
870 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4),
871 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8),
872
873 PINMUX_IPSR_GPSR(IP6_31_28, D10),
874 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0),
875 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0),
876 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1),
877 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1),
878 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E),
879 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9),
880
881 /* IPSR7 */
882 PINMUX_IPSR_GPSR(IP7_3_0, D11),
883 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A),
884 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0),
885 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2),
886 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1),
887 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4),
888 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10),
889
890 PINMUX_IPSR_GPSR(IP7_7_4, D12),
891 PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX),
892 PINMUX_IPSR_GPSR(IP7_7_4, TX4_B),
893 PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX),
894 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0),
895 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1),
896
897 PINMUX_IPSR_GPSR(IP7_11_8, D13),
898 PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX),
899 PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1),
900 PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX),
901 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0),
902 PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1),
903 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1),
904
905 PINMUX_IPSR_GPSR(IP7_15_12, D14),
906 PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK),
907 PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0),
908 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A),
909 PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1),
910 PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1),
911
912 PINMUX_IPSR_GPSR(IP7_19_16, D15),
913 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A),
914 PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A),
915 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A),
916 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3),
917 PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11),
918
919 PINMUX_IPSR_GPSR(IP7_23_20, SCL4),
920 PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26),
921 PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0),
922 PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1),
923 PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1),
924 PINMUX_IPSR_GPSR(IP7_23_20, QCLK),
925
926 PINMUX_IPSR_GPSR(IP7_27_24, SDA4),
927 PINMUX_IPSR_GPSR(IP7_27_24, WE1_N),
928 PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1),
929 PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1),
930 PINMUX_IPSR_GPSR(IP7_27_24, QPOLB),
931
932 PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK),
933 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8),
934 PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2),
935 PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1),
936 PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4),
937 PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1),
938
939 /* IPSR8 */
940 PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD),
941 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9),
942 PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1),
943 PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1),
944
945 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0),
946 PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10),
947 PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B),
948 PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1),
949
950 PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1),
951 PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11),
952 PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2),
953 PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1),
954 PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1),
955
956 PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2),
957 PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12),
958 PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2),
959 PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1),
960 PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B),
961
962 PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3),
963 PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13),
964 PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2),
965 PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4),
966 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2),
967 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
968
969 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
970 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
971
972 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
973 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
974
975 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
976 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1),
977
978 /* IPSR9 */
979 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
980 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1),
981
982 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
983 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1),
984
985 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
986 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1),
987
988 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
989 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
990
991 PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD),
992 PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N),
993
994 PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0),
995 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0),
996
997 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
998 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1),
999
1000 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2),
1001 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2),
1002
1003 /* IPSR10 */
1004 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3),
1005 PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3),
1006
1007 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4),
1008 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4),
1009
1010 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5),
1011 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5),
1012
1013 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6),
1014 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6),
1015
1016 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7),
1017 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7),
1018
1019 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS),
1020 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
1021
1022 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
1023 PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A),
1024 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
1025 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1026 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
1027 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
1028 PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
1029 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
1030
1031 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
1032 PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A),
1033 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
1034 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1035 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
1036 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
1037 PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
1038 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
1039
1040 /* IPSR11 */
1041 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
1042 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0),
1043 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
1044 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1045 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
1046
1047 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
1048 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0),
1049 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
1050 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
1051 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
1052
1053 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
1054 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
1055 PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
1056 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
1057 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
1058
1059 PINMUX_IPSR_GPSR(IP11_15_12, TX0_A),
1060 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
1061 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
1062 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
1063 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
1064
1065 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
1066 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0),
1067 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
1068 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
1069 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
1070 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
1071
1072 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0),
1073 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0),
1074 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
1075 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
1076 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
1077 PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0),
1078
1079 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
1080 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
1081 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
1082 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
1083 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1084 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
1085 PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
1086
1087 PINMUX_IPSR_GPSR(IP11_31_28, RX1),
1088 PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1),
1089 PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1),
1090 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B),
1091
1092 /* IPSR12 */
1093 PINMUX_IPSR_GPSR(IP12_3_0, TX1),
1094 PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B),
1095 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1),
1096 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B),
1097
1098 PINMUX_IPSR_GPSR(IP12_7_4, SCK2_A),
1099 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0),
1100 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0),
1101 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N),
1102 PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0),
1103 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0),
1104 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1),
1105
1106 PINMUX_IPSR_GPSR(IP12_11_8, TX2_A),
1107 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0),
1108 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A),
1109 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0),
1110 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0),
1111 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1),
1112
1113 PINMUX_IPSR_GPSR(IP12_15_12, RX2_A),
1114 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A),
1115 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A),
1116 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0),
1117 PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0),
1118 PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1),
1119
1120 PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK),
1121 PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78),
1122
1123 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD),
1124 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78),
1125 PINMUX_IPSR_GPSR(IP12_23_20, TX2_B),
1126
1127 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD),
1128 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7),
1129 PINMUX_IPSR_GPSR(IP12_27_24, RX2_B),
1130
1131 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1132 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B),
1133 PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8),
1134
1135 /* IPSR13 */
1136 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1137 PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0),
1138 PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4),
1139 PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0),
1140 PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C),
1141 PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0),
1142
1143 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1144 PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A),
1145 PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4),
1146 PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0),
1147 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2),
1148 PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A),
1149
1150 PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9),
1151 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0),
1152 PINMUX_IPSR_GPSR(IP13_11_8, SCK1),
1153
1154 PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK),
1155 PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1),
1156 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0),
1157 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1),
1158 PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1),
1159 PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A),
1160
1161 PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG),
1162 PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1),
1163 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
1164 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
1165 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
1166 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
1167
1168 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
1169 PINMUX_IPSR_GPSR(IP13_23_20, TX0_B),
1170 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0),
1171 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A),
1172
1173 PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239),
1174
1175 PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239),
1176
1177 /* IPSR14 */
1178 PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0),
1179
1180 PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1),
1181 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1),
1182 PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1),
1183
1184 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2),
1185 PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B),
1186 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0),
1187 PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1),
1188
1189 PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349),
1190 PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2),
1191
1192 PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349),
1193 PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2),
1194
1195 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3),
1196 PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C),
1197 PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1),
1198 PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1),
1199
1200 PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4),
1201 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0),
1202 PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1),
1203
1204 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5),
1205 PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1),
1206 PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B),
1207 PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3),
1208 PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1),
1209
1210 /* IPSR15 */
1211 PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5),
1212 PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B),
1213 PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1),
1214 PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3),
1215
1216 PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5),
1217 PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1),
1218 PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2),
1219 PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0),
1220
1221 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6),
1222 PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0),
1223 PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2),
1224 PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1),
1225 PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1),
1226 PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B),
1227
1228 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6),
1229 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1230 PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C),
1231 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
1232 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
1233 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
1234 PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
1235
1236 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
1237 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1238 PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C),
1239 PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3),
1240 PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3),
1241 PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1),
1242 PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B),
1243
1244 PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA),
1245
1246 PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN),
1247 PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A),
1248
1249 PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC),
1250 PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0),
1251
1252 /*
1253 * Static pins can not be muxed between different functions but
1254 * still need mark entries in the pinmux list. Add each static
1255 * pin to the list without an associated function. The sh-pfc
1256 * core will do the right thing and skip trying to mux the pin
1257 * while still applying configuration to it.
1258 */
1259 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1260 PINMUX_STATIC
1261 #undef FM
1262 };
1263
1264 /*
1265 * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
1266 * Physical layout rows: A - AE, cols: 1 - 25.
1267 */
1268 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1269 #define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
1270 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1271 #define PIN_NONE U16_MAX
1272
1273 static const struct sh_pfc_pin pinmux_pins[] = {
1274 PINMUX_GPIO_GP_ALL(),
1275
1276 /*
1277 * Pins not associated with a GPIO port.
1278 *
1279 * The pin positions are different between different R8A77990
1280 * packages, all that is needed for the pfc driver is a unique
1281 * number for each pin. To this end use the pin layout from
1282 * R8A77990 to calculate a unique number for each pin.
1283 */
1284 SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS),
1285 SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS),
1286 SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS),
1287 SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS),
1288 SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS),
1289 SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS),
1290 SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS),
1291 SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS),
1292 SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS),
1293 SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS),
1294 SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS),
1295 SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS),
1296 SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS),
1297 SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS),
1298 SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS),
1299 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
1300 };
1301
1302 /* - EtherAVB --------------------------------------------------------------- */
1303 static const unsigned int avb_link_pins[] = {
1304 /* AVB_LINK */
1305 RCAR_GP_PIN(2, 23),
1306 };
1307
1308 static const unsigned int avb_link_mux[] = {
1309 AVB_LINK_MARK,
1310 };
1311
1312 static const unsigned int avb_magic_pins[] = {
1313 /* AVB_MAGIC */
1314 RCAR_GP_PIN(2, 22),
1315 };
1316
1317 static const unsigned int avb_magic_mux[] = {
1318 AVB_MAGIC_MARK,
1319 };
1320
1321 static const unsigned int avb_phy_int_pins[] = {
1322 /* AVB_PHY_INT */
1323 RCAR_GP_PIN(2, 21),
1324 };
1325
1326 static const unsigned int avb_phy_int_mux[] = {
1327 AVB_PHY_INT_MARK,
1328 };
1329
1330 static const unsigned int avb_mii_pins[] = {
1331 /*
1332 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1333 * AVB_RD1, AVB_RD2, AVB_RD3,
1334 * AVB_TXCREFCLK
1335 */
1336 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1337 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1338 RCAR_GP_PIN(2, 20),
1339 };
1340
1341 static const unsigned int avb_mii_mux[] = {
1342 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1343 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1344 AVB_TXCREFCLK_MARK,
1345 };
1346
1347 static const unsigned int avb_avtp_pps_pins[] = {
1348 /* AVB_AVTP_PPS */
1349 RCAR_GP_PIN(1, 2),
1350 };
1351
1352 static const unsigned int avb_avtp_pps_mux[] = {
1353 AVB_AVTP_PPS_MARK,
1354 };
1355
1356 static const unsigned int avb_avtp_match_a_pins[] = {
1357 /* AVB_AVTP_MATCH_A */
1358 RCAR_GP_PIN(2, 24),
1359 };
1360
1361 static const unsigned int avb_avtp_match_a_mux[] = {
1362 AVB_AVTP_MATCH_A_MARK,
1363 };
1364
1365 static const unsigned int avb_avtp_capture_a_pins[] = {
1366 /* AVB_AVTP_CAPTURE_A */
1367 RCAR_GP_PIN(2, 25),
1368 };
1369
1370 static const unsigned int avb_avtp_capture_a_mux[] = {
1371 AVB_AVTP_CAPTURE_A_MARK,
1372 };
1373
1374 /* - I2C -------------------------------------------------------------------- */
1375 static const unsigned int i2c1_a_pins[] = {
1376 /* SCL, SDA */
1377 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1378 };
1379
1380 static const unsigned int i2c1_a_mux[] = {
1381 SCL1_A_MARK, SDA1_A_MARK,
1382 };
1383
1384 static const unsigned int i2c1_b_pins[] = {
1385 /* SCL, SDA */
1386 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1387 };
1388
1389 static const unsigned int i2c1_b_mux[] = {
1390 SCL1_B_MARK, SDA1_B_MARK,
1391 };
1392
1393 static const unsigned int i2c1_c_pins[] = {
1394 /* SCL, SDA */
1395 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
1396 };
1397
1398 static const unsigned int i2c1_c_mux[] = {
1399 SCL1_C_MARK, SDA1_C_MARK,
1400 };
1401
1402 static const unsigned int i2c1_d_pins[] = {
1403 /* SCL, SDA */
1404 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
1405 };
1406
1407 static const unsigned int i2c1_d_mux[] = {
1408 SCL1_D_MARK, SDA1_D_MARK,
1409 };
1410
1411 static const unsigned int i2c2_a_pins[] = {
1412 /* SCL, SDA */
1413 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
1414 };
1415
1416 static const unsigned int i2c2_a_mux[] = {
1417 SCL2_A_MARK, SDA2_A_MARK,
1418 };
1419
1420 static const unsigned int i2c2_b_pins[] = {
1421 /* SCL, SDA */
1422 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1423 };
1424
1425 static const unsigned int i2c2_b_mux[] = {
1426 SCL2_B_MARK, SDA2_B_MARK,
1427 };
1428
1429 static const unsigned int i2c2_c_pins[] = {
1430 /* SCL, SDA */
1431 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
1432 };
1433
1434 static const unsigned int i2c2_c_mux[] = {
1435 SCL2_C_MARK, SDA2_C_MARK,
1436 };
1437
1438 static const unsigned int i2c2_d_pins[] = {
1439 /* SCL, SDA */
1440 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1441 };
1442
1443 static const unsigned int i2c2_d_mux[] = {
1444 SCL2_D_MARK, SDA2_D_MARK,
1445 };
1446
1447 static const unsigned int i2c2_e_pins[] = {
1448 /* SCL, SDA */
1449 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
1450 };
1451
1452 static const unsigned int i2c2_e_mux[] = {
1453 SCL2_E_MARK, SDA2_E_MARK,
1454 };
1455
1456 static const unsigned int i2c4_pins[] = {
1457 /* SCL, SDA */
1458 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
1459 };
1460
1461 static const unsigned int i2c4_mux[] = {
1462 SCL4_MARK, SDA4_MARK,
1463 };
1464
1465 static const unsigned int i2c5_pins[] = {
1466 /* SCL, SDA */
1467 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
1468 };
1469
1470 static const unsigned int i2c5_mux[] = {
1471 SCL5_MARK, SDA5_MARK,
1472 };
1473
1474 static const unsigned int i2c6_a_pins[] = {
1475 /* SCL, SDA */
1476 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
1477 };
1478
1479 static const unsigned int i2c6_a_mux[] = {
1480 SCL6_A_MARK, SDA6_A_MARK,
1481 };
1482
1483 static const unsigned int i2c6_b_pins[] = {
1484 /* SCL, SDA */
1485 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1486 };
1487
1488 static const unsigned int i2c6_b_mux[] = {
1489 SCL6_B_MARK, SDA6_B_MARK,
1490 };
1491
1492 static const unsigned int i2c7_a_pins[] = {
1493 /* SCL, SDA */
1494 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
1495 };
1496
1497 static const unsigned int i2c7_a_mux[] = {
1498 SCL7_A_MARK, SDA7_A_MARK,
1499 };
1500
1501 static const unsigned int i2c7_b_pins[] = {
1502 /* SCL, SDA */
1503 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1504 };
1505
1506 static const unsigned int i2c7_b_mux[] = {
1507 SCL7_B_MARK, SDA7_B_MARK,
1508 };
1509
1510 /* - SCIF0 ------------------------------------------------------------------ */
1511 static const unsigned int scif0_data_a_pins[] = {
1512 /* RX, TX */
1513 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1514 };
1515
1516 static const unsigned int scif0_data_a_mux[] = {
1517 RX0_A_MARK, TX0_A_MARK,
1518 };
1519
1520 static const unsigned int scif0_clk_a_pins[] = {
1521 /* SCK */
1522 RCAR_GP_PIN(5, 0),
1523 };
1524
1525 static const unsigned int scif0_clk_a_mux[] = {
1526 SCK0_A_MARK,
1527 };
1528
1529 static const unsigned int scif0_ctrl_a_pins[] = {
1530 /* RTS, CTS */
1531 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1532 };
1533
1534 static const unsigned int scif0_ctrl_a_mux[] = {
1535 RTS0_N_TANS_A_MARK, CTS0_N_A_MARK,
1536 };
1537
1538 static const unsigned int scif0_data_b_pins[] = {
1539 /* RX, TX */
1540 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
1541 };
1542
1543 static const unsigned int scif0_data_b_mux[] = {
1544 RX0_B_MARK, TX0_B_MARK,
1545 };
1546
1547 static const unsigned int scif0_clk_b_pins[] = {
1548 /* SCK */
1549 RCAR_GP_PIN(5, 18),
1550 };
1551
1552 static const unsigned int scif0_clk_b_mux[] = {
1553 SCK0_B_MARK,
1554 };
1555
1556 /* - SCIF1 ------------------------------------------------------------------ */
1557 static const unsigned int scif1_data_pins[] = {
1558 /* RX, TX */
1559 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1560 };
1561
1562 static const unsigned int scif1_data_mux[] = {
1563 RX1_MARK, TX1_MARK,
1564 };
1565
1566 static const unsigned int scif1_clk_pins[] = {
1567 /* SCK */
1568 RCAR_GP_PIN(5, 16),
1569 };
1570
1571 static const unsigned int scif1_clk_mux[] = {
1572 SCK1_MARK,
1573 };
1574
1575 static const unsigned int scif1_ctrl_pins[] = {
1576 /* RTS, CTS */
1577 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
1578 };
1579
1580 static const unsigned int scif1_ctrl_mux[] = {
1581 RTS1_N_TANS_MARK, CTS1_N_MARK,
1582 };
1583
1584 /* - SCIF2 ------------------------------------------------------------------ */
1585 static const unsigned int scif2_data_a_pins[] = {
1586 /* RX, TX */
1587 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
1588 };
1589
1590 static const unsigned int scif2_data_a_mux[] = {
1591 RX2_A_MARK, TX2_A_MARK,
1592 };
1593
1594 static const unsigned int scif2_clk_a_pins[] = {
1595 /* SCK */
1596 RCAR_GP_PIN(5, 7),
1597 };
1598
1599 static const unsigned int scif2_clk_a_mux[] = {
1600 SCK2_A_MARK,
1601 };
1602
1603 static const unsigned int scif2_data_b_pins[] = {
1604 /* RX, TX */
1605 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1606 };
1607
1608 static const unsigned int scif2_data_b_mux[] = {
1609 RX2_B_MARK, TX2_B_MARK,
1610 };
1611
1612 /* - SCIF3 ------------------------------------------------------------------ */
1613 static const unsigned int scif3_data_a_pins[] = {
1614 /* RX, TX */
1615 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1616 };
1617
1618 static const unsigned int scif3_data_a_mux[] = {
1619 RX3_A_MARK, TX3_A_MARK,
1620 };
1621
1622 static const unsigned int scif3_clk_a_pins[] = {
1623 /* SCK */
1624 RCAR_GP_PIN(0, 1),
1625 };
1626
1627 static const unsigned int scif3_clk_a_mux[] = {
1628 SCK3_A_MARK,
1629 };
1630
1631 static const unsigned int scif3_ctrl_a_pins[] = {
1632 /* RTS, CTS */
1633 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1634 };
1635
1636 static const unsigned int scif3_ctrl_a_mux[] = {
1637 RTS3_N_TANS_A_MARK, CTS3_N_A_MARK,
1638 };
1639
1640 static const unsigned int scif3_data_b_pins[] = {
1641 /* RX, TX */
1642 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1643 };
1644
1645 static const unsigned int scif3_data_b_mux[] = {
1646 RX3_B_MARK, TX3_B_MARK,
1647 };
1648
1649 static const unsigned int scif3_data_c_pins[] = {
1650 /* RX, TX */
1651 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
1652 };
1653
1654 static const unsigned int scif3_data_c_mux[] = {
1655 RX3_C_MARK, TX3_C_MARK,
1656 };
1657
1658 static const unsigned int scif3_clk_c_pins[] = {
1659 /* SCK */
1660 RCAR_GP_PIN(2, 24),
1661 };
1662
1663 static const unsigned int scif3_clk_c_mux[] = {
1664 SCK3_C_MARK,
1665 };
1666
1667 /* - SCIF4 ------------------------------------------------------------------ */
1668 static const unsigned int scif4_data_a_pins[] = {
1669 /* RX, TX */
1670 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1671 };
1672
1673 static const unsigned int scif4_data_a_mux[] = {
1674 RX4_A_MARK, TX4_A_MARK,
1675 };
1676
1677 static const unsigned int scif4_clk_a_pins[] = {
1678 /* SCK */
1679 RCAR_GP_PIN(1, 5),
1680 };
1681
1682 static const unsigned int scif4_clk_a_mux[] = {
1683 SCK4_A_MARK,
1684 };
1685
1686 static const unsigned int scif4_ctrl_a_pins[] = {
1687 /* RTS, CTS */
1688 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
1689 };
1690
1691 static const unsigned int scif4_ctrl_a_mux[] = {
1692 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
1693 };
1694
1695 static const unsigned int scif4_data_b_pins[] = {
1696 /* RX, TX */
1697 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
1698 };
1699
1700 static const unsigned int scif4_data_b_mux[] = {
1701 RX4_B_MARK, TX4_B_MARK,
1702 };
1703
1704 static const unsigned int scif4_clk_b_pins[] = {
1705 /* SCK */
1706 RCAR_GP_PIN(0, 8),
1707 };
1708
1709 static const unsigned int scif4_clk_b_mux[] = {
1710 SCK4_B_MARK,
1711 };
1712
1713 static const unsigned int scif4_data_c_pins[] = {
1714 /* RX, TX */
1715 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1716 };
1717
1718 static const unsigned int scif4_data_c_mux[] = {
1719 RX4_C_MARK, TX4_C_MARK,
1720 };
1721
1722 static const unsigned int scif4_ctrl_c_pins[] = {
1723 /* RTS, CTS */
1724 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
1725 };
1726
1727 static const unsigned int scif4_ctrl_c_mux[] = {
1728 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
1729 };
1730
1731 /* - SCIF5 ------------------------------------------------------------------ */
1732 static const unsigned int scif5_data_a_pins[] = {
1733 /* RX, TX */
1734 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
1735 };
1736
1737 static const unsigned int scif5_data_a_mux[] = {
1738 RX5_A_MARK, TX5_A_MARK,
1739 };
1740
1741 static const unsigned int scif5_clk_a_pins[] = {
1742 /* SCK */
1743 RCAR_GP_PIN(1, 13),
1744 };
1745
1746 static const unsigned int scif5_clk_a_mux[] = {
1747 SCK5_A_MARK,
1748 };
1749
1750 static const unsigned int scif5_data_b_pins[] = {
1751 /* RX, TX */
1752 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
1753 };
1754
1755 static const unsigned int scif5_data_b_mux[] = {
1756 RX5_B_MARK, TX5_B_MARK,
1757 };
1758
1759 static const unsigned int scif5_data_c_pins[] = {
1760 /* RX, TX */
1761 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1762 };
1763
1764 static const unsigned int scif5_data_c_mux[] = {
1765 RX5_C_MARK, TX5_C_MARK,
1766 };
1767
1768 /* - SCIF Clock ------------------------------------------------------------- */
1769 static const unsigned int scif_clk_a_pins[] = {
1770 /* SCIF_CLK */
1771 RCAR_GP_PIN(5, 3),
1772 };
1773
1774 static const unsigned int scif_clk_a_mux[] = {
1775 SCIF_CLK_A_MARK,
1776 };
1777
1778 static const unsigned int scif_clk_b_pins[] = {
1779 /* SCIF_CLK */
1780 RCAR_GP_PIN(5, 7),
1781 };
1782
1783 static const unsigned int scif_clk_b_mux[] = {
1784 SCIF_CLK_B_MARK,
1785 };
1786
1787 /* - USB0 ------------------------------------------------------------------- */
1788 static const unsigned int usb0_a_pins[] = {
1789 /* PWEN, OVC */
1790 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
1791 };
1792
1793 static const unsigned int usb0_a_mux[] = {
1794 USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
1795 };
1796
1797 static const unsigned int usb0_b_pins[] = {
1798 /* PWEN, OVC */
1799 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1800 };
1801
1802 static const unsigned int usb0_b_mux[] = {
1803 USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
1804 };
1805
1806 static const unsigned int usb0_id_pins[] = {
1807 /* ID */
1808 RCAR_GP_PIN(5, 0)
1809 };
1810
1811 static const unsigned int usb0_id_mux[] = {
1812 USB0_ID_MARK,
1813 };
1814
1815 /* - USB30 ------------------------------------------------------------------ */
1816 static const unsigned int usb30_pins[] = {
1817 /* PWEN, OVC */
1818 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
1819 };
1820
1821 static const unsigned int usb30_mux[] = {
1822 USB30_PWEN_MARK, USB30_OVC_MARK,
1823 };
1824
1825 static const unsigned int usb30_id_pins[] = {
1826 /* ID */
1827 RCAR_GP_PIN(5, 0),
1828 };
1829
1830 static const unsigned int usb30_id_mux[] = {
1831 USB3HS0_ID_MARK,
1832 };
1833
1834 static const struct sh_pfc_pin_group pinmux_groups[] = {
1835 SH_PFC_PIN_GROUP(avb_link),
1836 SH_PFC_PIN_GROUP(avb_magic),
1837 SH_PFC_PIN_GROUP(avb_phy_int),
1838 SH_PFC_PIN_GROUP(avb_mii),
1839 SH_PFC_PIN_GROUP(avb_avtp_pps),
1840 SH_PFC_PIN_GROUP(avb_avtp_match_a),
1841 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
1842 SH_PFC_PIN_GROUP(i2c1_a),
1843 SH_PFC_PIN_GROUP(i2c1_b),
1844 SH_PFC_PIN_GROUP(i2c1_c),
1845 SH_PFC_PIN_GROUP(i2c1_d),
1846 SH_PFC_PIN_GROUP(i2c2_a),
1847 SH_PFC_PIN_GROUP(i2c2_b),
1848 SH_PFC_PIN_GROUP(i2c2_c),
1849 SH_PFC_PIN_GROUP(i2c2_d),
1850 SH_PFC_PIN_GROUP(i2c2_e),
1851 SH_PFC_PIN_GROUP(i2c4),
1852 SH_PFC_PIN_GROUP(i2c5),
1853 SH_PFC_PIN_GROUP(i2c6_a),
1854 SH_PFC_PIN_GROUP(i2c6_b),
1855 SH_PFC_PIN_GROUP(i2c7_a),
1856 SH_PFC_PIN_GROUP(i2c7_b),
1857 SH_PFC_PIN_GROUP(scif0_data_a),
1858 SH_PFC_PIN_GROUP(scif0_clk_a),
1859 SH_PFC_PIN_GROUP(scif0_ctrl_a),
1860 SH_PFC_PIN_GROUP(scif0_data_b),
1861 SH_PFC_PIN_GROUP(scif0_clk_b),
1862 SH_PFC_PIN_GROUP(scif1_data),
1863 SH_PFC_PIN_GROUP(scif1_clk),
1864 SH_PFC_PIN_GROUP(scif1_ctrl),
1865 SH_PFC_PIN_GROUP(scif2_data_a),
1866 SH_PFC_PIN_GROUP(scif2_clk_a),
1867 SH_PFC_PIN_GROUP(scif2_data_b),
1868 SH_PFC_PIN_GROUP(scif3_data_a),
1869 SH_PFC_PIN_GROUP(scif3_clk_a),
1870 SH_PFC_PIN_GROUP(scif3_ctrl_a),
1871 SH_PFC_PIN_GROUP(scif3_data_b),
1872 SH_PFC_PIN_GROUP(scif3_data_c),
1873 SH_PFC_PIN_GROUP(scif3_clk_c),
1874 SH_PFC_PIN_GROUP(scif4_data_a),
1875 SH_PFC_PIN_GROUP(scif4_clk_a),
1876 SH_PFC_PIN_GROUP(scif4_ctrl_a),
1877 SH_PFC_PIN_GROUP(scif4_data_b),
1878 SH_PFC_PIN_GROUP(scif4_clk_b),
1879 SH_PFC_PIN_GROUP(scif4_data_c),
1880 SH_PFC_PIN_GROUP(scif4_ctrl_c),
1881 SH_PFC_PIN_GROUP(scif5_data_a),
1882 SH_PFC_PIN_GROUP(scif5_clk_a),
1883 SH_PFC_PIN_GROUP(scif5_data_b),
1884 SH_PFC_PIN_GROUP(scif5_data_c),
1885 SH_PFC_PIN_GROUP(scif_clk_a),
1886 SH_PFC_PIN_GROUP(scif_clk_b),
1887 SH_PFC_PIN_GROUP(usb0_a),
1888 SH_PFC_PIN_GROUP(usb0_b),
1889 SH_PFC_PIN_GROUP(usb0_id),
1890 SH_PFC_PIN_GROUP(usb30),
1891 SH_PFC_PIN_GROUP(usb30_id),
1892 };
1893
1894 static const char * const avb_groups[] = {
1895 "avb_link",
1896 "avb_magic",
1897 "avb_phy_int",
1898 "avb_mii",
1899 "avb_avtp_pps",
1900 "avb_avtp_match_a",
1901 "avb_avtp_capture_a",
1902 };
1903
1904 static const char * const i2c1_groups[] = {
1905 "i2c1_a",
1906 "i2c1_b",
1907 "i2c1_c",
1908 "i2c1_d",
1909 };
1910
1911 static const char * const i2c2_groups[] = {
1912 "i2c2_a",
1913 "i2c2_b",
1914 "i2c2_c",
1915 "i2c2_d",
1916 "i2c2_e",
1917 };
1918
1919 static const char * const i2c4_groups[] = {
1920 "i2c4",
1921 };
1922
1923 static const char * const i2c5_groups[] = {
1924 "i2c5",
1925 };
1926
1927 static const char * const i2c6_groups[] = {
1928 "i2c6_a",
1929 "i2c6_b",
1930 };
1931
1932 static const char * const i2c7_groups[] = {
1933 "i2c7_a",
1934 "i2c7_b",
1935 };
1936
1937 static const char * const scif0_groups[] = {
1938 "scif0_data_a",
1939 "scif0_clk_a",
1940 "scif0_ctrl_a",
1941 "scif0_data_b",
1942 "scif0_clk_b",
1943 };
1944
1945 static const char * const scif1_groups[] = {
1946 "scif1_data",
1947 "scif1_clk",
1948 "scif1_ctrl",
1949 };
1950
1951 static const char * const scif2_groups[] = {
1952 "scif2_data_a",
1953 "scif2_clk_a",
1954 "scif2_data_b",
1955 };
1956
1957 static const char * const scif3_groups[] = {
1958 "scif3_data_a",
1959 "scif3_clk_a",
1960 "scif3_ctrl_a",
1961 "scif3_data_b",
1962 "scif3_data_c",
1963 "scif3_clk_c",
1964 };
1965
1966 static const char * const scif4_groups[] = {
1967 "scif4_data_a",
1968 "scif4_clk_a",
1969 "scif4_ctrl_a",
1970 "scif4_data_b",
1971 "scif4_clk_b",
1972 "scif4_data_c",
1973 "scif4_ctrl_c",
1974 };
1975
1976 static const char * const scif5_groups[] = {
1977 "scif5_data_a",
1978 "scif5_clk_a",
1979 "scif5_data_b",
1980 "scif5_data_c",
1981 };
1982
1983 static const char * const scif_clk_groups[] = {
1984 "scif_clk_a",
1985 "scif_clk_b",
1986 };
1987
1988 static const char * const usb0_groups[] = {
1989 "usb0_a",
1990 "usb0_b",
1991 "usb0_id",
1992 };
1993
1994 static const char * const usb30_groups[] = {
1995 "usb30",
1996 "usb30_id",
1997 };
1998
1999 static const struct sh_pfc_function pinmux_functions[] = {
2000 SH_PFC_FUNCTION(avb),
2001 SH_PFC_FUNCTION(i2c1),
2002 SH_PFC_FUNCTION(i2c2),
2003 SH_PFC_FUNCTION(i2c4),
2004 SH_PFC_FUNCTION(i2c5),
2005 SH_PFC_FUNCTION(i2c6),
2006 SH_PFC_FUNCTION(i2c7),
2007 SH_PFC_FUNCTION(scif0),
2008 SH_PFC_FUNCTION(scif1),
2009 SH_PFC_FUNCTION(scif2),
2010 SH_PFC_FUNCTION(scif3),
2011 SH_PFC_FUNCTION(scif4),
2012 SH_PFC_FUNCTION(scif5),
2013 SH_PFC_FUNCTION(scif_clk),
2014 SH_PFC_FUNCTION(usb0),
2015 SH_PFC_FUNCTION(usb30),
2016 };
2017
2018 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2019 #define F_(x, y) FN_##y
2020 #define FM(x) FN_##x
2021 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2022 0, 0,
2023 0, 0,
2024 0, 0,
2025 0, 0,
2026 0, 0,
2027 0, 0,
2028 0, 0,
2029 0, 0,
2030 0, 0,
2031 0, 0,
2032 0, 0,
2033 0, 0,
2034 0, 0,
2035 0, 0,
2036 GP_0_17_FN, GPSR0_17,
2037 GP_0_16_FN, GPSR0_16,
2038 GP_0_15_FN, GPSR0_15,
2039 GP_0_14_FN, GPSR0_14,
2040 GP_0_13_FN, GPSR0_13,
2041 GP_0_12_FN, GPSR0_12,
2042 GP_0_11_FN, GPSR0_11,
2043 GP_0_10_FN, GPSR0_10,
2044 GP_0_9_FN, GPSR0_9,
2045 GP_0_8_FN, GPSR0_8,
2046 GP_0_7_FN, GPSR0_7,
2047 GP_0_6_FN, GPSR0_6,
2048 GP_0_5_FN, GPSR0_5,
2049 GP_0_4_FN, GPSR0_4,
2050 GP_0_3_FN, GPSR0_3,
2051 GP_0_2_FN, GPSR0_2,
2052 GP_0_1_FN, GPSR0_1,
2053 GP_0_0_FN, GPSR0_0, }
2054 },
2055 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2056 0, 0,
2057 0, 0,
2058 0, 0,
2059 0, 0,
2060 0, 0,
2061 0, 0,
2062 0, 0,
2063 0, 0,
2064 0, 0,
2065 GP_1_22_FN, GPSR1_22,
2066 GP_1_21_FN, GPSR1_21,
2067 GP_1_20_FN, GPSR1_20,
2068 GP_1_19_FN, GPSR1_19,
2069 GP_1_18_FN, GPSR1_18,
2070 GP_1_17_FN, GPSR1_17,
2071 GP_1_16_FN, GPSR1_16,
2072 GP_1_15_FN, GPSR1_15,
2073 GP_1_14_FN, GPSR1_14,
2074 GP_1_13_FN, GPSR1_13,
2075 GP_1_12_FN, GPSR1_12,
2076 GP_1_11_FN, GPSR1_11,
2077 GP_1_10_FN, GPSR1_10,
2078 GP_1_9_FN, GPSR1_9,
2079 GP_1_8_FN, GPSR1_8,
2080 GP_1_7_FN, GPSR1_7,
2081 GP_1_6_FN, GPSR1_6,
2082 GP_1_5_FN, GPSR1_5,
2083 GP_1_4_FN, GPSR1_4,
2084 GP_1_3_FN, GPSR1_3,
2085 GP_1_2_FN, GPSR1_2,
2086 GP_1_1_FN, GPSR1_1,
2087 GP_1_0_FN, GPSR1_0, }
2088 },
2089 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2090 0, 0,
2091 0, 0,
2092 0, 0,
2093 0, 0,
2094 0, 0,
2095 0, 0,
2096 GP_2_25_FN, GPSR2_25,
2097 GP_2_24_FN, GPSR2_24,
2098 GP_2_23_FN, GPSR2_23,
2099 GP_2_22_FN, GPSR2_22,
2100 GP_2_21_FN, GPSR2_21,
2101 GP_2_20_FN, GPSR2_20,
2102 GP_2_19_FN, GPSR2_19,
2103 GP_2_18_FN, GPSR2_18,
2104 GP_2_17_FN, GPSR2_17,
2105 GP_2_16_FN, GPSR2_16,
2106 GP_2_15_FN, GPSR2_15,
2107 GP_2_14_FN, GPSR2_14,
2108 GP_2_13_FN, GPSR2_13,
2109 GP_2_12_FN, GPSR2_12,
2110 GP_2_11_FN, GPSR2_11,
2111 GP_2_10_FN, GPSR2_10,
2112 GP_2_9_FN, GPSR2_9,
2113 GP_2_8_FN, GPSR2_8,
2114 GP_2_7_FN, GPSR2_7,
2115 GP_2_6_FN, GPSR2_6,
2116 GP_2_5_FN, GPSR2_5,
2117 GP_2_4_FN, GPSR2_4,
2118 GP_2_3_FN, GPSR2_3,
2119 GP_2_2_FN, GPSR2_2,
2120 GP_2_1_FN, GPSR2_1,
2121 GP_2_0_FN, GPSR2_0, }
2122 },
2123 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2124 0, 0,
2125 0, 0,
2126 0, 0,
2127 0, 0,
2128 0, 0,
2129 0, 0,
2130 0, 0,
2131 0, 0,
2132 0, 0,
2133 0, 0,
2134 0, 0,
2135 0, 0,
2136 0, 0,
2137 0, 0,
2138 0, 0,
2139 0, 0,
2140 GP_3_15_FN, GPSR3_15,
2141 GP_3_14_FN, GPSR3_14,
2142 GP_3_13_FN, GPSR3_13,
2143 GP_3_12_FN, GPSR3_12,
2144 GP_3_11_FN, GPSR3_11,
2145 GP_3_10_FN, GPSR3_10,
2146 GP_3_9_FN, GPSR3_9,
2147 GP_3_8_FN, GPSR3_8,
2148 GP_3_7_FN, GPSR3_7,
2149 GP_3_6_FN, GPSR3_6,
2150 GP_3_5_FN, GPSR3_5,
2151 GP_3_4_FN, GPSR3_4,
2152 GP_3_3_FN, GPSR3_3,
2153 GP_3_2_FN, GPSR3_2,
2154 GP_3_1_FN, GPSR3_1,
2155 GP_3_0_FN, GPSR3_0, }
2156 },
2157 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2158 0, 0,
2159 0, 0,
2160 0, 0,
2161 0, 0,
2162 0, 0,
2163 0, 0,
2164 0, 0,
2165 0, 0,
2166 0, 0,
2167 0, 0,
2168 0, 0,
2169 0, 0,
2170 0, 0,
2171 0, 0,
2172 0, 0,
2173 0, 0,
2174 0, 0,
2175 0, 0,
2176 0, 0,
2177 0, 0,
2178 0, 0,
2179 GP_4_10_FN, GPSR4_10,
2180 GP_4_9_FN, GPSR4_9,
2181 GP_4_8_FN, GPSR4_8,
2182 GP_4_7_FN, GPSR4_7,
2183 GP_4_6_FN, GPSR4_6,
2184 GP_4_5_FN, GPSR4_5,
2185 GP_4_4_FN, GPSR4_4,
2186 GP_4_3_FN, GPSR4_3,
2187 GP_4_2_FN, GPSR4_2,
2188 GP_4_1_FN, GPSR4_1,
2189 GP_4_0_FN, GPSR4_0, }
2190 },
2191 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2192 0, 0,
2193 0, 0,
2194 0, 0,
2195 0, 0,
2196 0, 0,
2197 0, 0,
2198 0, 0,
2199 0, 0,
2200 0, 0,
2201 0, 0,
2202 0, 0,
2203 0, 0,
2204 GP_5_19_FN, GPSR5_19,
2205 GP_5_18_FN, GPSR5_18,
2206 GP_5_17_FN, GPSR5_17,
2207 GP_5_16_FN, GPSR5_16,
2208 GP_5_15_FN, GPSR5_15,
2209 GP_5_14_FN, GPSR5_14,
2210 GP_5_13_FN, GPSR5_13,
2211 GP_5_12_FN, GPSR5_12,
2212 GP_5_11_FN, GPSR5_11,
2213 GP_5_10_FN, GPSR5_10,
2214 GP_5_9_FN, GPSR5_9,
2215 GP_5_8_FN, GPSR5_8,
2216 GP_5_7_FN, GPSR5_7,
2217 GP_5_6_FN, GPSR5_6,
2218 GP_5_5_FN, GPSR5_5,
2219 GP_5_4_FN, GPSR5_4,
2220 GP_5_3_FN, GPSR5_3,
2221 GP_5_2_FN, GPSR5_2,
2222 GP_5_1_FN, GPSR5_1,
2223 GP_5_0_FN, GPSR5_0, }
2224 },
2225 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
2226 0, 0,
2227 0, 0,
2228 0, 0,
2229 0, 0,
2230 0, 0,
2231 0, 0,
2232 0, 0,
2233 0, 0,
2234 0, 0,
2235 0, 0,
2236 0, 0,
2237 0, 0,
2238 0, 0,
2239 0, 0,
2240 GP_6_17_FN, GPSR6_17,
2241 GP_6_16_FN, GPSR6_16,
2242 GP_6_15_FN, GPSR6_15,
2243 GP_6_14_FN, GPSR6_14,
2244 GP_6_13_FN, GPSR6_13,
2245 GP_6_12_FN, GPSR6_12,
2246 GP_6_11_FN, GPSR6_11,
2247 GP_6_10_FN, GPSR6_10,
2248 GP_6_9_FN, GPSR6_9,
2249 GP_6_8_FN, GPSR6_8,
2250 GP_6_7_FN, GPSR6_7,
2251 GP_6_6_FN, GPSR6_6,
2252 GP_6_5_FN, GPSR6_5,
2253 GP_6_4_FN, GPSR6_4,
2254 GP_6_3_FN, GPSR6_3,
2255 GP_6_2_FN, GPSR6_2,
2256 GP_6_1_FN, GPSR6_1,
2257 GP_6_0_FN, GPSR6_0, }
2258 },
2259 #undef F_
2260 #undef FM
2261
2262 #define F_(x, y) x,
2263 #define FM(x) FN_##x,
2264 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2265 IP0_31_28
2266 IP0_27_24
2267 IP0_23_20
2268 IP0_19_16
2269 IP0_15_12
2270 IP0_11_8
2271 IP0_7_4
2272 IP0_3_0 }
2273 },
2274 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2275 IP1_31_28
2276 IP1_27_24
2277 IP1_23_20
2278 IP1_19_16
2279 IP1_15_12
2280 IP1_11_8
2281 IP1_7_4
2282 IP1_3_0 }
2283 },
2284 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2285 IP2_31_28
2286 IP2_27_24
2287 IP2_23_20
2288 IP2_19_16
2289 IP2_15_12
2290 IP2_11_8
2291 IP2_7_4
2292 IP2_3_0 }
2293 },
2294 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2295 IP3_31_28
2296 IP3_27_24
2297 IP3_23_20
2298 IP3_19_16
2299 IP3_15_12
2300 IP3_11_8
2301 IP3_7_4
2302 IP3_3_0 }
2303 },
2304 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2305 IP4_31_28
2306 IP4_27_24
2307 IP4_23_20
2308 IP4_19_16
2309 IP4_15_12
2310 IP4_11_8
2311 IP4_7_4
2312 IP4_3_0 }
2313 },
2314 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2315 IP5_31_28
2316 IP5_27_24
2317 IP5_23_20
2318 IP5_19_16
2319 IP5_15_12
2320 IP5_11_8
2321 IP5_7_4
2322 IP5_3_0 }
2323 },
2324 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2325 IP6_31_28
2326 IP6_27_24
2327 IP6_23_20
2328 IP6_19_16
2329 IP6_15_12
2330 IP6_11_8
2331 IP6_7_4
2332 IP6_3_0 }
2333 },
2334 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2335 IP7_31_28
2336 IP7_27_24
2337 IP7_23_20
2338 IP7_19_16
2339 IP7_15_12
2340 IP7_11_8
2341 IP7_7_4
2342 IP7_3_0 }
2343 },
2344 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2345 IP8_31_28
2346 IP8_27_24
2347 IP8_23_20
2348 IP8_19_16
2349 IP8_15_12
2350 IP8_11_8
2351 IP8_7_4
2352 IP8_3_0 }
2353 },
2354 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
2355 IP9_31_28
2356 IP9_27_24
2357 IP9_23_20
2358 IP9_19_16
2359 IP9_15_12
2360 IP9_11_8
2361 IP9_7_4
2362 IP9_3_0 }
2363 },
2364 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
2365 IP10_31_28
2366 IP10_27_24
2367 IP10_23_20
2368 IP10_19_16
2369 IP10_15_12
2370 IP10_11_8
2371 IP10_7_4
2372 IP10_3_0 }
2373 },
2374 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
2375 IP11_31_28
2376 IP11_27_24
2377 IP11_23_20
2378 IP11_19_16
2379 IP11_15_12
2380 IP11_11_8
2381 IP11_7_4
2382 IP11_3_0 }
2383 },
2384 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
2385 IP12_31_28
2386 IP12_27_24
2387 IP12_23_20
2388 IP12_19_16
2389 IP12_15_12
2390 IP12_11_8
2391 IP12_7_4
2392 IP12_3_0 }
2393 },
2394 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
2395 IP13_31_28
2396 IP13_27_24
2397 IP13_23_20
2398 IP13_19_16
2399 IP13_15_12
2400 IP13_11_8
2401 IP13_7_4
2402 IP13_3_0 }
2403 },
2404 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
2405 IP14_31_28
2406 IP14_27_24
2407 IP14_23_20
2408 IP14_19_16
2409 IP14_15_12
2410 IP14_11_8
2411 IP14_7_4
2412 IP14_3_0 }
2413 },
2414 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
2415 IP15_31_28
2416 IP15_27_24
2417 IP15_23_20
2418 IP15_19_16
2419 IP15_15_12
2420 IP15_11_8
2421 IP15_7_4
2422 IP15_3_0 }
2423 },
2424 #undef F_
2425 #undef FM
2426
2427 #define F_(x, y) x,
2428 #define FM(x) FN_##x,
2429 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2430 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1,
2431 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) {
2432 /* RESERVED 31 */
2433 0, 0,
2434 MOD_SEL0_30_29
2435 MOD_SEL0_28
2436 MOD_SEL0_27_26
2437 MOD_SEL0_25
2438 MOD_SEL0_24
2439 MOD_SEL0_23
2440 MOD_SEL0_22
2441 MOD_SEL0_21_20
2442 MOD_SEL0_19_18_17
2443 MOD_SEL0_16
2444 MOD_SEL0_15
2445 MOD_SEL0_14
2446 MOD_SEL0_13_12
2447 MOD_SEL0_11_10
2448 MOD_SEL0_9
2449 MOD_SEL0_8
2450 MOD_SEL0_7
2451 MOD_SEL0_6_5
2452 MOD_SEL0_4
2453 MOD_SEL0_3
2454 MOD_SEL0_2
2455 MOD_SEL0_1_0 }
2456 },
2457 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2458 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
2459 1, 2, 2, 2, 1, 1, 2, 1, 4) {
2460 MOD_SEL1_31
2461 MOD_SEL1_30
2462 MOD_SEL1_29
2463 MOD_SEL1_28
2464 /* RESERVED 27 */
2465 0, 0,
2466 MOD_SEL1_26
2467 MOD_SEL1_25
2468 MOD_SEL1_24_23_22
2469 MOD_SEL1_21_20_19
2470 MOD_SEL1_18
2471 MOD_SEL1_17
2472 MOD_SEL1_16
2473 MOD_SEL1_15
2474 MOD_SEL1_14_13
2475 MOD_SEL1_12_11
2476 MOD_SEL1_10_9
2477 MOD_SEL1_8
2478 MOD_SEL1_7
2479 MOD_SEL1_6_5
2480 MOD_SEL1_4
2481 /* RESERVED 3, 2, 1, 0 */
2482 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
2483 },
2484 { },
2485 };
2486
2487 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2488 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2489 [0] = RCAR_GP_PIN(2, 23), /* RD# */
2490 [1] = RCAR_GP_PIN(2, 22), /* BS# */
2491 [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */
2492 [3] = PIN_NUMBER('P', 5), /* AVB_MDC */
2493 [4] = PIN_NUMBER('P', 4), /* AVB_MDIO */
2494 [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */
2495 [6] = PIN_NUMBER('N', 6), /* AVB_TD3 */
2496 [7] = PIN_NUMBER('N', 5), /* AVB_TD2 */
2497 [8] = PIN_NUMBER('N', 3), /* AVB_TD1 */
2498 [9] = PIN_NUMBER('N', 2), /* AVB_TD0 */
2499 [10] = PIN_NUMBER('N', 1), /* AVB_TXC */
2500 [11] = PIN_NUMBER('P', 3), /* AVB_TX_CTL */
2501 [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */
2502 [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */
2503 [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */
2504 [15] = RCAR_GP_PIN(2, 16), /* AVB_RD0 */
2505 [16] = RCAR_GP_PIN(2, 15), /* AVB_RXC */
2506 [17] = RCAR_GP_PIN(2, 14), /* AVB_RX_CTL */
2507 [18] = RCAR_GP_PIN(2, 13), /* RPC_RESET# */
2508 [19] = RCAR_GP_PIN(2, 12), /* RPC_INT# */
2509 [20] = RCAR_GP_PIN(2, 11), /* QSPI1_SSL */
2510 [21] = RCAR_GP_PIN(2, 10), /* QSPI1_IO3 */
2511 [22] = RCAR_GP_PIN(2, 9), /* QSPI1_IO2 */
2512 [23] = RCAR_GP_PIN(2, 8), /* QSPI1_MISO/IO1 */
2513 [24] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI/IO0 */
2514 [25] = RCAR_GP_PIN(2, 6), /* QSPI1_SPCLK */
2515 [26] = RCAR_GP_PIN(2, 5), /* QSPI0_SSL */
2516 [27] = RCAR_GP_PIN(2, 4), /* QSPI0_IO3 */
2517 [28] = RCAR_GP_PIN(2, 3), /* QSPI0_IO2 */
2518 [29] = RCAR_GP_PIN(2, 2), /* QSPI0_MISO/IO1 */
2519 [30] = RCAR_GP_PIN(2, 1), /* QSPI0_MOSI/IO0 */
2520 [31] = RCAR_GP_PIN(2, 0), /* QSPI0_SPCLK */
2521 } },
2522 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2523 [0] = RCAR_GP_PIN(0, 4), /* D4 */
2524 [1] = RCAR_GP_PIN(0, 3), /* D3 */
2525 [2] = RCAR_GP_PIN(0, 2), /* D2 */
2526 [3] = RCAR_GP_PIN(0, 1), /* D1 */
2527 [4] = RCAR_GP_PIN(0, 0), /* D0 */
2528 [5] = RCAR_GP_PIN(1, 22), /* WE0# */
2529 [6] = RCAR_GP_PIN(1, 21), /* CS0# */
2530 [7] = RCAR_GP_PIN(1, 20), /* CLKOUT */
2531 [8] = RCAR_GP_PIN(1, 19), /* A19 */
2532 [9] = RCAR_GP_PIN(1, 18), /* A18 */
2533 [10] = RCAR_GP_PIN(1, 17), /* A17 */
2534 [11] = RCAR_GP_PIN(1, 16), /* A16 */
2535 [12] = RCAR_GP_PIN(1, 15), /* A15 */
2536 [13] = RCAR_GP_PIN(1, 14), /* A14 */
2537 [14] = RCAR_GP_PIN(1, 13), /* A13 */
2538 [15] = RCAR_GP_PIN(1, 12), /* A12 */
2539 [16] = RCAR_GP_PIN(1, 11), /* A11 */
2540 [17] = RCAR_GP_PIN(1, 10), /* A10 */
2541 [18] = RCAR_GP_PIN(1, 9), /* A9 */
2542 [19] = RCAR_GP_PIN(1, 8), /* A8 */
2543 [20] = RCAR_GP_PIN(1, 7), /* A7 */
2544 [21] = RCAR_GP_PIN(1, 6), /* A6 */
2545 [22] = RCAR_GP_PIN(1, 5), /* A5 */
2546 [23] = RCAR_GP_PIN(1, 4), /* A4 */
2547 [24] = RCAR_GP_PIN(1, 3), /* A3 */
2548 [25] = RCAR_GP_PIN(1, 2), /* A2 */
2549 [26] = RCAR_GP_PIN(1, 1), /* A1 */
2550 [27] = RCAR_GP_PIN(1, 0), /* A0 */
2551 [28] = PIN_NONE,
2552 [29] = PIN_NONE,
2553 [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
2554 [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
2555 } },
2556 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2557 [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
2558 [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
2559 [2] = PIN_NUMBER('H', 1), /* ASEBRK */
2560 [3] = PIN_NONE,
2561 [4] = PIN_NUMBER('G', 2), /* TDI */
2562 [5] = PIN_NUMBER('F', 3), /* TMS */
2563 [6] = PIN_NUMBER('F', 4), /* TCK */
2564 [7] = PIN_NUMBER('F', 1), /* TRST# */
2565 [8] = PIN_NONE,
2566 [9] = PIN_NONE,
2567 [10] = PIN_NONE,
2568 [11] = PIN_NONE,
2569 [12] = PIN_NONE,
2570 [13] = PIN_NONE,
2571 [14] = PIN_NONE,
2572 [15] = PIN_NUMBER('G', 3), /* FSCLKST# */
2573 [16] = RCAR_GP_PIN(0, 17), /* SDA4 */
2574 [17] = RCAR_GP_PIN(0, 16), /* SCL4 */
2575 [18] = PIN_NONE,
2576 [19] = PIN_NONE,
2577 [20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */
2578 [21] = RCAR_GP_PIN(0, 15), /* D15 */
2579 [22] = RCAR_GP_PIN(0, 14), /* D14 */
2580 [23] = RCAR_GP_PIN(0, 13), /* D13 */
2581 [24] = RCAR_GP_PIN(0, 12), /* D12 */
2582 [25] = RCAR_GP_PIN(0, 11), /* D11 */
2583 [26] = RCAR_GP_PIN(0, 10), /* D10 */
2584 [27] = RCAR_GP_PIN(0, 9), /* D9 */
2585 [28] = RCAR_GP_PIN(0, 8), /* D8 */
2586 [29] = RCAR_GP_PIN(0, 7), /* D7 */
2587 [30] = RCAR_GP_PIN(0, 6), /* D6 */
2588 [31] = RCAR_GP_PIN(0, 5), /* D5 */
2589 } },
2590 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2591 [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
2592 [1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */
2593 [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
2594 [3] = RCAR_GP_PIN(5, 2), /* TX0_A */
2595 [4] = RCAR_GP_PIN(5, 1), /* RX0_A */
2596 [5] = PIN_NONE,
2597 [6] = PIN_NONE,
2598 [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */
2599 [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */
2600 [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
2601 [10] = RCAR_GP_PIN(3, 12), /* SD0_CD */
2602 [11] = RCAR_GP_PIN(4, 10), /* SD3_DS */
2603 [12] = RCAR_GP_PIN(4, 9), /* SD3_DAT7 */
2604 [13] = RCAR_GP_PIN(4, 8), /* SD3_DAT6 */
2605 [14] = RCAR_GP_PIN(4, 7), /* SD3_DAT5 */
2606 [15] = RCAR_GP_PIN(4, 6), /* SD3_DAT4 */
2607 [16] = RCAR_GP_PIN(4, 5), /* SD3_DAT3 */
2608 [17] = RCAR_GP_PIN(4, 4), /* SD3_DAT2 */
2609 [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */
2610 [19] = RCAR_GP_PIN(4, 2), /* SD3_DAT0 */
2611 [20] = RCAR_GP_PIN(4, 1), /* SD3_CMD */
2612 [21] = RCAR_GP_PIN(4, 0), /* SD3_CLK */
2613 [22] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
2614 [23] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
2615 [24] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
2616 [25] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
2617 [26] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
2618 [27] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
2619 [28] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
2620 [29] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
2621 [30] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
2622 [31] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
2623 } },
2624 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
2625 [0] = RCAR_GP_PIN(6, 8), /* AUDIO_CLKA */
2626 [1] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
2627 [2] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
2628 [3] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
2629 [4] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
2630 [5] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
2631 [6] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
2632 [7] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
2633 [8] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
2634 [9] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
2635 [10] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
2636 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2 */
2637 [12] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1 */
2638 [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
2639 [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
2640 [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
2641 [16] = PIN_NUMBER('T', 21), /* MLB_REF */
2642 [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */
2643 [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */
2644 [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */
2645 [20] = RCAR_GP_PIN(5, 16), /* SSI_SDATA9 */
2646 [21] = RCAR_GP_PIN(5, 15), /* MSIOF0_SS2 */
2647 [22] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */
2648 [23] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */
2649 [24] = RCAR_GP_PIN(5, 12), /* MSIOF0_TXD */
2650 [25] = RCAR_GP_PIN(5, 11), /* MSIOF0_RXD */
2651 [26] = RCAR_GP_PIN(5, 10), /* MSIOF0_SCK */
2652 [27] = RCAR_GP_PIN(5, 9), /* RX2_A */
2653 [28] = RCAR_GP_PIN(5, 8), /* TX2_A */
2654 [29] = RCAR_GP_PIN(5, 7), /* SCK2_A */
2655 [30] = RCAR_GP_PIN(5, 6), /* TX1 */
2656 [31] = RCAR_GP_PIN(5, 5), /* RX1 */
2657 } },
2658 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
2659 [0] = PIN_NONE,
2660 [1] = PIN_NONE,
2661 [2] = PIN_NONE,
2662 [3] = PIN_NONE,
2663 [4] = PIN_NONE,
2664 [5] = PIN_NONE,
2665 [6] = PIN_NONE,
2666 [7] = PIN_NONE,
2667 [8] = PIN_NONE,
2668 [9] = PIN_NONE,
2669 [10] = PIN_NONE,
2670 [11] = PIN_NONE,
2671 [12] = PIN_NONE,
2672 [13] = PIN_NONE,
2673 [14] = PIN_NONE,
2674 [15] = PIN_NONE,
2675 [16] = PIN_NONE,
2676 [17] = PIN_NONE,
2677 [18] = PIN_NONE,
2678 [19] = PIN_NONE,
2679 [20] = PIN_NONE,
2680 [21] = PIN_NONE,
2681 [22] = PIN_NONE,
2682 [23] = PIN_NONE,
2683 [24] = PIN_NONE,
2684 [25] = PIN_NONE,
2685 [26] = PIN_NONE,
2686 [27] = PIN_NONE,
2687 [28] = PIN_NONE,
2688 [29] = PIN_NONE,
2689 [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
2690 [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
2691 } },
2692 { /* sentinel */ },
2693 };
2694
2695 static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
2696 unsigned int pin)
2697 {
2698 const struct pinmux_bias_reg *reg;
2699 unsigned int bit;
2700
2701 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
2702 if (!reg)
2703 return PIN_CONFIG_BIAS_DISABLE;
2704
2705 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
2706 return PIN_CONFIG_BIAS_DISABLE;
2707 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
2708 return PIN_CONFIG_BIAS_PULL_UP;
2709 else
2710 return PIN_CONFIG_BIAS_PULL_DOWN;
2711 }
2712
2713 static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2714 unsigned int bias)
2715 {
2716 const struct pinmux_bias_reg *reg;
2717 u32 enable, updown;
2718 unsigned int bit;
2719
2720 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
2721 if (!reg)
2722 return;
2723
2724 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
2725 if (bias != PIN_CONFIG_BIAS_DISABLE)
2726 enable |= BIT(bit);
2727
2728 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
2729 if (bias == PIN_CONFIG_BIAS_PULL_UP)
2730 updown |= BIT(bit);
2731
2732 sh_pfc_write(pfc, reg->pud, updown);
2733 sh_pfc_write(pfc, reg->puen, enable);
2734 }
2735
2736 static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
2737 .get_bias = r8a77990_pinmux_get_bias,
2738 .set_bias = r8a77990_pinmux_set_bias,
2739 };
2740
2741 const struct sh_pfc_soc_info r8a77990_pinmux_info = {
2742 .name = "r8a77990_pfc",
2743 .ops = &r8a77990_pinmux_ops,
2744 .unlock_reg = 0xe6060000, /* PMMR */
2745
2746 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2747
2748 .pins = pinmux_pins,
2749 .nr_pins = ARRAY_SIZE(pinmux_pins),
2750 .groups = pinmux_groups,
2751 .nr_groups = ARRAY_SIZE(pinmux_groups),
2752 .functions = pinmux_functions,
2753 .nr_functions = ARRAY_SIZE(pinmux_functions),
2754
2755 .cfg_regs = pinmux_config_regs,
2756 .bias_regs = pinmux_bias_regs,
2757
2758 .pinmux_data = pinmux_data,
2759 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2760 };
Linux with added FPC-III support